18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * Copyright (C) 1996-1998 Linus Torvalds & authors (see below) 48c2ecf20Sopenharmony_ci */ 58c2ecf20Sopenharmony_ci 68c2ecf20Sopenharmony_ci/* 78c2ecf20Sopenharmony_ci * Authors: 88c2ecf20Sopenharmony_ci * Jaromir Koutek <miri@punknet.cz>, 98c2ecf20Sopenharmony_ci * Jan Harkes <jaharkes@cwi.nl>, 108c2ecf20Sopenharmony_ci * Mark Lord <mlord@pobox.com> 118c2ecf20Sopenharmony_ci * Some parts of code are from ali14xx.c and from rz1000.c. 128c2ecf20Sopenharmony_ci */ 138c2ecf20Sopenharmony_ci 148c2ecf20Sopenharmony_ci#include <linux/types.h> 158c2ecf20Sopenharmony_ci#include <linux/module.h> 168c2ecf20Sopenharmony_ci#include <linux/kernel.h> 178c2ecf20Sopenharmony_ci#include <linux/pci.h> 188c2ecf20Sopenharmony_ci#include <linux/ide.h> 198c2ecf20Sopenharmony_ci 208c2ecf20Sopenharmony_ci#include <asm/io.h> 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci#define DRV_NAME "opti621" 238c2ecf20Sopenharmony_ci 248c2ecf20Sopenharmony_ci#define READ_REG 0 /* index of Read cycle timing register */ 258c2ecf20Sopenharmony_ci#define WRITE_REG 1 /* index of Write cycle timing register */ 268c2ecf20Sopenharmony_ci#define CNTRL_REG 3 /* index of Control register */ 278c2ecf20Sopenharmony_ci#define STRAP_REG 5 /* index of Strap register */ 288c2ecf20Sopenharmony_ci#define MISC_REG 6 /* index of Miscellaneous register */ 298c2ecf20Sopenharmony_ci 308c2ecf20Sopenharmony_cistatic int reg_base; 318c2ecf20Sopenharmony_ci 328c2ecf20Sopenharmony_cistatic DEFINE_SPINLOCK(opti621_lock); 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci/* Write value to register reg, base of register 358c2ecf20Sopenharmony_ci * is at reg_base (0x1f0 primary, 0x170 secondary, 368c2ecf20Sopenharmony_ci * if not changed by PCI configuration). 378c2ecf20Sopenharmony_ci * This is from setupvic.exe program. 388c2ecf20Sopenharmony_ci */ 398c2ecf20Sopenharmony_cistatic void write_reg(u8 value, int reg) 408c2ecf20Sopenharmony_ci{ 418c2ecf20Sopenharmony_ci inw(reg_base + 1); 428c2ecf20Sopenharmony_ci inw(reg_base + 1); 438c2ecf20Sopenharmony_ci outb(3, reg_base + 2); 448c2ecf20Sopenharmony_ci outb(value, reg_base + reg); 458c2ecf20Sopenharmony_ci outb(0x83, reg_base + 2); 468c2ecf20Sopenharmony_ci} 478c2ecf20Sopenharmony_ci 488c2ecf20Sopenharmony_ci/* Read value from register reg, base of register 498c2ecf20Sopenharmony_ci * is at reg_base (0x1f0 primary, 0x170 secondary, 508c2ecf20Sopenharmony_ci * if not changed by PCI configuration). 518c2ecf20Sopenharmony_ci * This is from setupvic.exe program. 528c2ecf20Sopenharmony_ci */ 538c2ecf20Sopenharmony_cistatic u8 read_reg(int reg) 548c2ecf20Sopenharmony_ci{ 558c2ecf20Sopenharmony_ci u8 ret = 0; 568c2ecf20Sopenharmony_ci 578c2ecf20Sopenharmony_ci inw(reg_base + 1); 588c2ecf20Sopenharmony_ci inw(reg_base + 1); 598c2ecf20Sopenharmony_ci outb(3, reg_base + 2); 608c2ecf20Sopenharmony_ci ret = inb(reg_base + reg); 618c2ecf20Sopenharmony_ci outb(0x83, reg_base + 2); 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci return ret; 648c2ecf20Sopenharmony_ci} 658c2ecf20Sopenharmony_ci 668c2ecf20Sopenharmony_cistatic void opti621_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 678c2ecf20Sopenharmony_ci{ 688c2ecf20Sopenharmony_ci ide_drive_t *pair = ide_get_pair_dev(drive); 698c2ecf20Sopenharmony_ci unsigned long flags; 708c2ecf20Sopenharmony_ci unsigned long mode = drive->pio_mode, pair_mode; 718c2ecf20Sopenharmony_ci const u8 pio = mode - XFER_PIO_0; 728c2ecf20Sopenharmony_ci u8 tim, misc, addr_pio = pio, clk; 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_ci /* DRDY is default 2 (by OPTi Databook) */ 758c2ecf20Sopenharmony_ci static const u8 addr_timings[2][5] = { 768c2ecf20Sopenharmony_ci { 0x20, 0x10, 0x00, 0x00, 0x00 }, /* 33 MHz */ 778c2ecf20Sopenharmony_ci { 0x10, 0x10, 0x00, 0x00, 0x00 }, /* 25 MHz */ 788c2ecf20Sopenharmony_ci }; 798c2ecf20Sopenharmony_ci static const u8 data_rec_timings[2][5] = { 808c2ecf20Sopenharmony_ci { 0x5b, 0x45, 0x32, 0x21, 0x20 }, /* 33 MHz */ 818c2ecf20Sopenharmony_ci { 0x48, 0x34, 0x21, 0x10, 0x10 } /* 25 MHz */ 828c2ecf20Sopenharmony_ci }; 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ci ide_set_drivedata(drive, (void *)mode); 858c2ecf20Sopenharmony_ci 868c2ecf20Sopenharmony_ci if (pair) { 878c2ecf20Sopenharmony_ci pair_mode = (unsigned long)ide_get_drivedata(pair); 888c2ecf20Sopenharmony_ci if (pair_mode && pair_mode < mode) 898c2ecf20Sopenharmony_ci addr_pio = pair_mode - XFER_PIO_0; 908c2ecf20Sopenharmony_ci } 918c2ecf20Sopenharmony_ci 928c2ecf20Sopenharmony_ci spin_lock_irqsave(&opti621_lock, flags); 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_ci reg_base = hwif->io_ports.data_addr; 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci /* allow Register-B */ 978c2ecf20Sopenharmony_ci outb(0xc0, reg_base + CNTRL_REG); 988c2ecf20Sopenharmony_ci /* hmm, setupvic.exe does this ;-) */ 998c2ecf20Sopenharmony_ci outb(0xff, reg_base + 5); 1008c2ecf20Sopenharmony_ci /* if reads 0xff, adapter not exist? */ 1018c2ecf20Sopenharmony_ci (void)inb(reg_base + CNTRL_REG); 1028c2ecf20Sopenharmony_ci /* if reads 0xc0, no interface exist? */ 1038c2ecf20Sopenharmony_ci read_reg(CNTRL_REG); 1048c2ecf20Sopenharmony_ci 1058c2ecf20Sopenharmony_ci /* check CLK speed */ 1068c2ecf20Sopenharmony_ci clk = read_reg(STRAP_REG) & 1; 1078c2ecf20Sopenharmony_ci 1088c2ecf20Sopenharmony_ci printk(KERN_INFO "%s: CLK = %d MHz\n", hwif->name, clk ? 25 : 33); 1098c2ecf20Sopenharmony_ci 1108c2ecf20Sopenharmony_ci tim = data_rec_timings[clk][pio]; 1118c2ecf20Sopenharmony_ci misc = addr_timings[clk][addr_pio]; 1128c2ecf20Sopenharmony_ci 1138c2ecf20Sopenharmony_ci /* select Index-0/1 for Register-A/B */ 1148c2ecf20Sopenharmony_ci write_reg(drive->dn & 1, MISC_REG); 1158c2ecf20Sopenharmony_ci /* set read cycle timings */ 1168c2ecf20Sopenharmony_ci write_reg(tim, READ_REG); 1178c2ecf20Sopenharmony_ci /* set write cycle timings */ 1188c2ecf20Sopenharmony_ci write_reg(tim, WRITE_REG); 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci /* use Register-A for drive 0 */ 1218c2ecf20Sopenharmony_ci /* use Register-B for drive 1 */ 1228c2ecf20Sopenharmony_ci write_reg(0x85, CNTRL_REG); 1238c2ecf20Sopenharmony_ci 1248c2ecf20Sopenharmony_ci /* set address setup, DRDY timings, */ 1258c2ecf20Sopenharmony_ci /* and read prefetch for both drives */ 1268c2ecf20Sopenharmony_ci write_reg(misc, MISC_REG); 1278c2ecf20Sopenharmony_ci 1288c2ecf20Sopenharmony_ci spin_unlock_irqrestore(&opti621_lock, flags); 1298c2ecf20Sopenharmony_ci} 1308c2ecf20Sopenharmony_ci 1318c2ecf20Sopenharmony_cistatic const struct ide_port_ops opti621_port_ops = { 1328c2ecf20Sopenharmony_ci .set_pio_mode = opti621_set_pio_mode, 1338c2ecf20Sopenharmony_ci}; 1348c2ecf20Sopenharmony_ci 1358c2ecf20Sopenharmony_cistatic const struct ide_port_info opti621_chipset = { 1368c2ecf20Sopenharmony_ci .name = DRV_NAME, 1378c2ecf20Sopenharmony_ci .enablebits = { {0x45, 0x80, 0x00}, {0x40, 0x08, 0x00} }, 1388c2ecf20Sopenharmony_ci .port_ops = &opti621_port_ops, 1398c2ecf20Sopenharmony_ci .host_flags = IDE_HFLAG_NO_DMA, 1408c2ecf20Sopenharmony_ci .pio_mask = ATA_PIO4, 1418c2ecf20Sopenharmony_ci}; 1428c2ecf20Sopenharmony_ci 1438c2ecf20Sopenharmony_cistatic int opti621_init_one(struct pci_dev *dev, const struct pci_device_id *id) 1448c2ecf20Sopenharmony_ci{ 1458c2ecf20Sopenharmony_ci return ide_pci_init_one(dev, &opti621_chipset, NULL); 1468c2ecf20Sopenharmony_ci} 1478c2ecf20Sopenharmony_ci 1488c2ecf20Sopenharmony_cistatic const struct pci_device_id opti621_pci_tbl[] = { 1498c2ecf20Sopenharmony_ci { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C621), 0 }, 1508c2ecf20Sopenharmony_ci { PCI_VDEVICE(OPTI, PCI_DEVICE_ID_OPTI_82C825), 0 }, 1518c2ecf20Sopenharmony_ci { 0, }, 1528c2ecf20Sopenharmony_ci}; 1538c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(pci, opti621_pci_tbl); 1548c2ecf20Sopenharmony_ci 1558c2ecf20Sopenharmony_cistatic struct pci_driver opti621_pci_driver = { 1568c2ecf20Sopenharmony_ci .name = "Opti621_IDE", 1578c2ecf20Sopenharmony_ci .id_table = opti621_pci_tbl, 1588c2ecf20Sopenharmony_ci .probe = opti621_init_one, 1598c2ecf20Sopenharmony_ci .remove = ide_pci_remove, 1608c2ecf20Sopenharmony_ci .suspend = ide_pci_suspend, 1618c2ecf20Sopenharmony_ci .resume = ide_pci_resume, 1628c2ecf20Sopenharmony_ci}; 1638c2ecf20Sopenharmony_ci 1648c2ecf20Sopenharmony_cistatic int __init opti621_ide_init(void) 1658c2ecf20Sopenharmony_ci{ 1668c2ecf20Sopenharmony_ci return ide_pci_register_driver(&opti621_pci_driver); 1678c2ecf20Sopenharmony_ci} 1688c2ecf20Sopenharmony_ci 1698c2ecf20Sopenharmony_cistatic void __exit opti621_ide_exit(void) 1708c2ecf20Sopenharmony_ci{ 1718c2ecf20Sopenharmony_ci pci_unregister_driver(&opti621_pci_driver); 1728c2ecf20Sopenharmony_ci} 1738c2ecf20Sopenharmony_ci 1748c2ecf20Sopenharmony_cimodule_init(opti621_ide_init); 1758c2ecf20Sopenharmony_cimodule_exit(opti621_ide_exit); 1768c2ecf20Sopenharmony_ci 1778c2ecf20Sopenharmony_ciMODULE_AUTHOR("Jaromir Koutek, Jan Harkes, Mark Lord"); 1788c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("PCI driver module for Opti621 IDE"); 1798c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL"); 180