1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Copyright (c) 1999-2001 Vojtech Pavlik 4 * Copyright (c) 2007-2008 Bartlomiej Zolnierkiewicz 5 * 6 * Should you need to contact me, the author, you can do so either by 7 * e-mail - mail your message to <vojtech@ucw.cz>, or by paper mail: 8 * Vojtech Pavlik, Simunkova 1594, Prague 8, 182 00 Czech Republic 9 */ 10 11#include <linux/kernel.h> 12#include <linux/ide.h> 13#include <linux/module.h> 14 15/* 16 * PIO 0-5, MWDMA 0-2 and UDMA 0-6 timings (in nanoseconds). 17 * These were taken from ATA/ATAPI-6 standard, rev 0a, except 18 * for PIO 5, which is a nonstandard extension and UDMA6, which 19 * is currently supported only by Maxtor drives. 20 */ 21 22static struct ide_timing ide_timing[] = { 23 24 { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, 25 { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, 26 { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, 27 { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, 28 29 { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, 30 { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, 31 { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, 32 33 { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 }, 34 { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 }, 35 { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, 36 { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, 37 { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, 38 39 { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, 40 { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, 41 { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, 42 43 { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 }, 44 { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 }, 45 { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, 46 { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, 47 48 { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, 49 { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, 50 { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, 51 52 { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, 53 54 { 0xff } 55}; 56 57struct ide_timing *ide_timing_find_mode(u8 speed) 58{ 59 struct ide_timing *t; 60 61 for (t = ide_timing; t->mode != speed; t++) 62 if (t->mode == 0xff) 63 return NULL; 64 return t; 65} 66EXPORT_SYMBOL_GPL(ide_timing_find_mode); 67 68u16 ide_pio_cycle_time(ide_drive_t *drive, u8 pio) 69{ 70 u16 *id = drive->id; 71 struct ide_timing *t = ide_timing_find_mode(XFER_PIO_0 + pio); 72 u16 cycle = 0; 73 74 if (id[ATA_ID_FIELD_VALID] & 2) { 75 if (ata_id_has_iordy(drive->id)) 76 cycle = id[ATA_ID_EIDE_PIO_IORDY]; 77 else 78 cycle = id[ATA_ID_EIDE_PIO]; 79 80 /* conservative "downgrade" for all pre-ATA2 drives */ 81 if (pio < 3 && cycle < t->cycle) 82 cycle = 0; /* use standard timing */ 83 84 /* Use the standard timing for the CF specific modes too */ 85 if (pio > 4 && ata_id_is_cfa(id)) 86 cycle = 0; 87 } 88 89 return cycle ? cycle : t->cycle; 90} 91EXPORT_SYMBOL_GPL(ide_pio_cycle_time); 92 93#define ENOUGH(v, unit) (((v) - 1) / (unit) + 1) 94#define EZ(v, unit) ((v) ? ENOUGH((v) * 1000, unit) : 0) 95 96static void ide_timing_quantize(struct ide_timing *t, struct ide_timing *q, 97 int T, int UT) 98{ 99 q->setup = EZ(t->setup, T); 100 q->act8b = EZ(t->act8b, T); 101 q->rec8b = EZ(t->rec8b, T); 102 q->cyc8b = EZ(t->cyc8b, T); 103 q->active = EZ(t->active, T); 104 q->recover = EZ(t->recover, T); 105 q->cycle = EZ(t->cycle, T); 106 q->udma = EZ(t->udma, UT); 107} 108 109void ide_timing_merge(struct ide_timing *a, struct ide_timing *b, 110 struct ide_timing *m, unsigned int what) 111{ 112 if (what & IDE_TIMING_SETUP) 113 m->setup = max(a->setup, b->setup); 114 if (what & IDE_TIMING_ACT8B) 115 m->act8b = max(a->act8b, b->act8b); 116 if (what & IDE_TIMING_REC8B) 117 m->rec8b = max(a->rec8b, b->rec8b); 118 if (what & IDE_TIMING_CYC8B) 119 m->cyc8b = max(a->cyc8b, b->cyc8b); 120 if (what & IDE_TIMING_ACTIVE) 121 m->active = max(a->active, b->active); 122 if (what & IDE_TIMING_RECOVER) 123 m->recover = max(a->recover, b->recover); 124 if (what & IDE_TIMING_CYCLE) 125 m->cycle = max(a->cycle, b->cycle); 126 if (what & IDE_TIMING_UDMA) 127 m->udma = max(a->udma, b->udma); 128} 129EXPORT_SYMBOL_GPL(ide_timing_merge); 130 131int ide_timing_compute(ide_drive_t *drive, u8 speed, 132 struct ide_timing *t, int T, int UT) 133{ 134 u16 *id = drive->id; 135 struct ide_timing *s, p; 136 137 /* 138 * Find the mode. 139 */ 140 s = ide_timing_find_mode(speed); 141 if (s == NULL) 142 return -EINVAL; 143 144 /* 145 * Copy the timing from the table. 146 */ 147 *t = *s; 148 149 /* 150 * If the drive is an EIDE drive, it can tell us it needs extended 151 * PIO/MWDMA cycle timing. 152 */ 153 if (id[ATA_ID_FIELD_VALID] & 2) { /* EIDE drive */ 154 memset(&p, 0, sizeof(p)); 155 156 if (speed >= XFER_PIO_0 && speed < XFER_SW_DMA_0) { 157 if (speed <= XFER_PIO_2) 158 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO]; 159 else if ((speed <= XFER_PIO_4) || 160 (speed == XFER_PIO_5 && !ata_id_is_cfa(id))) 161 p.cycle = p.cyc8b = id[ATA_ID_EIDE_PIO_IORDY]; 162 } else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) 163 p.cycle = id[ATA_ID_EIDE_DMA_MIN]; 164 165 ide_timing_merge(&p, t, t, IDE_TIMING_CYCLE | IDE_TIMING_CYC8B); 166 } 167 168 /* 169 * Convert the timing to bus clock counts. 170 */ 171 ide_timing_quantize(t, t, T, UT); 172 173 /* 174 * Even in DMA/UDMA modes we still use PIO access for IDENTIFY, 175 * S.M.A.R.T and some other commands. We have to ensure that the 176 * DMA cycle timing is slower/equal than the current PIO timing. 177 */ 178 if (speed >= XFER_SW_DMA_0) { 179 ide_timing_compute(drive, drive->pio_mode, &p, T, UT); 180 ide_timing_merge(&p, t, t, IDE_TIMING_ALL); 181 } 182 183 /* 184 * Lengthen active & recovery time so that cycle time is correct. 185 */ 186 if (t->act8b + t->rec8b < t->cyc8b) { 187 t->act8b += (t->cyc8b - (t->act8b + t->rec8b)) / 2; 188 t->rec8b = t->cyc8b - t->act8b; 189 } 190 191 if (t->active + t->recover < t->cycle) { 192 t->active += (t->cycle - (t->active + t->recover)) / 2; 193 t->recover = t->cycle - t->active; 194 } 195 196 return 0; 197} 198EXPORT_SYMBOL_GPL(ide_timing_compute); 199