1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/types.h>
3#include <linux/kernel.h>
4#include <linux/export.h>
5#include <linux/ide.h>
6#include <linux/scatterlist.h>
7#include <linux/dma-mapping.h>
8#include <linux/io.h>
9
10/**
11 *	config_drive_for_dma	-	attempt to activate IDE DMA
12 *	@drive: the drive to place in DMA mode
13 *
14 *	If the drive supports at least mode 2 DMA or UDMA of any kind
15 *	then attempt to place it into DMA mode. Drives that are known to
16 *	support DMA but predate the DMA properties or that are known
17 *	to have DMA handling bugs are also set up appropriately based
18 *	on the good/bad drive lists.
19 */
20
21int config_drive_for_dma(ide_drive_t *drive)
22{
23	ide_hwif_t *hwif = drive->hwif;
24	u16 *id = drive->id;
25
26	if (drive->media != ide_disk) {
27		if (hwif->host_flags & IDE_HFLAG_NO_ATAPI_DMA)
28			return 0;
29	}
30
31	/*
32	 * Enable DMA on any drive that has
33	 * UltraDMA (mode 0/1/2/3/4/5/6) enabled
34	 */
35	if ((id[ATA_ID_FIELD_VALID] & 4) &&
36	    ((id[ATA_ID_UDMA_MODES] >> 8) & 0x7f))
37		return 1;
38
39	/*
40	 * Enable DMA on any drive that has mode2 DMA
41	 * (multi or single) enabled
42	 */
43	if ((id[ATA_ID_MWDMA_MODES] & 0x404) == 0x404 ||
44	    (id[ATA_ID_SWDMA_MODES] & 0x404) == 0x404)
45		return 1;
46
47	/* Consult the list of known "good" drives */
48	if (ide_dma_good_drive(drive))
49		return 1;
50
51	return 0;
52}
53
54u8 ide_dma_sff_read_status(ide_hwif_t *hwif)
55{
56	unsigned long addr = hwif->dma_base + ATA_DMA_STATUS;
57
58	if (hwif->host_flags & IDE_HFLAG_MMIO)
59		return readb((void __iomem *)addr);
60	else
61		return inb(addr);
62}
63EXPORT_SYMBOL_GPL(ide_dma_sff_read_status);
64
65static void ide_dma_sff_write_status(ide_hwif_t *hwif, u8 val)
66{
67	unsigned long addr = hwif->dma_base + ATA_DMA_STATUS;
68
69	if (hwif->host_flags & IDE_HFLAG_MMIO)
70		writeb(val, (void __iomem *)addr);
71	else
72		outb(val, addr);
73}
74
75/**
76 *	ide_dma_host_set	-	Enable/disable DMA on a host
77 *	@drive: drive to control
78 *
79 *	Enable/disable DMA on an IDE controller following generic
80 *	bus-mastering IDE controller behaviour.
81 */
82
83void ide_dma_host_set(ide_drive_t *drive, int on)
84{
85	ide_hwif_t *hwif = drive->hwif;
86	u8 unit = drive->dn & 1;
87	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
88
89	if (on)
90		dma_stat |= (1 << (5 + unit));
91	else
92		dma_stat &= ~(1 << (5 + unit));
93
94	ide_dma_sff_write_status(hwif, dma_stat);
95}
96EXPORT_SYMBOL_GPL(ide_dma_host_set);
97
98/**
99 *	ide_build_dmatable	-	build IDE DMA table
100 *
101 *	ide_build_dmatable() prepares a dma request. We map the command
102 *	to get the pci bus addresses of the buffers and then build up
103 *	the PRD table that the IDE layer wants to be fed.
104 *
105 *	Most chipsets correctly interpret a length of 0x0000 as 64KB,
106 *	but at least one (e.g. CS5530) misinterprets it as zero (!).
107 *	So we break the 64KB entry into two 32KB entries instead.
108 *
109 *	Returns the number of built PRD entries if all went okay,
110 *	returns 0 otherwise.
111 *
112 *	May also be invoked from trm290.c
113 */
114
115int ide_build_dmatable(ide_drive_t *drive, struct ide_cmd *cmd)
116{
117	ide_hwif_t *hwif = drive->hwif;
118	__le32 *table = (__le32 *)hwif->dmatable_cpu;
119	unsigned int count = 0;
120	int i;
121	struct scatterlist *sg;
122	u8 is_trm290 = !!(hwif->host_flags & IDE_HFLAG_TRM290);
123
124	for_each_sg(hwif->sg_table, sg, cmd->sg_nents, i) {
125		u32 cur_addr, cur_len, xcount, bcount;
126
127		cur_addr = sg_dma_address(sg);
128		cur_len = sg_dma_len(sg);
129
130		/*
131		 * Fill in the dma table, without crossing any 64kB boundaries.
132		 * Most hardware requires 16-bit alignment of all blocks,
133		 * but the trm290 requires 32-bit alignment.
134		 */
135
136		while (cur_len) {
137			if (count++ >= PRD_ENTRIES)
138				goto use_pio_instead;
139
140			bcount = 0x10000 - (cur_addr & 0xffff);
141			if (bcount > cur_len)
142				bcount = cur_len;
143			*table++ = cpu_to_le32(cur_addr);
144			xcount = bcount & 0xffff;
145			if (is_trm290)
146				xcount = ((xcount >> 2) - 1) << 16;
147			else if (xcount == 0x0000) {
148				if (count++ >= PRD_ENTRIES)
149					goto use_pio_instead;
150				*table++ = cpu_to_le32(0x8000);
151				*table++ = cpu_to_le32(cur_addr + 0x8000);
152				xcount = 0x8000;
153			}
154			*table++ = cpu_to_le32(xcount);
155			cur_addr += bcount;
156			cur_len -= bcount;
157		}
158	}
159
160	if (count) {
161		if (!is_trm290)
162			*--table |= cpu_to_le32(0x80000000);
163		return count;
164	}
165
166use_pio_instead:
167	printk(KERN_ERR "%s: %s\n", drive->name,
168		count ? "DMA table too small" : "empty DMA table?");
169
170	return 0; /* revert to PIO for this request */
171}
172EXPORT_SYMBOL_GPL(ide_build_dmatable);
173
174/**
175 *	ide_dma_setup	-	begin a DMA phase
176 *	@drive: target device
177 *	@cmd: command
178 *
179 *	Build an IDE DMA PRD (IDE speak for scatter gather table)
180 *	and then set up the DMA transfer registers for a device
181 *	that follows generic IDE PCI DMA behaviour. Controllers can
182 *	override this function if they need to
183 *
184 *	Returns 0 on success. If a PIO fallback is required then 1
185 *	is returned.
186 */
187
188int ide_dma_setup(ide_drive_t *drive, struct ide_cmd *cmd)
189{
190	ide_hwif_t *hwif = drive->hwif;
191	u8 mmio = (hwif->host_flags & IDE_HFLAG_MMIO) ? 1 : 0;
192	u8 rw = (cmd->tf_flags & IDE_TFLAG_WRITE) ? 0 : ATA_DMA_WR;
193	u8 dma_stat;
194
195	/* fall back to pio! */
196	if (ide_build_dmatable(drive, cmd) == 0) {
197		ide_map_sg(drive, cmd);
198		return 1;
199	}
200
201	/* PRD table */
202	if (mmio)
203		writel(hwif->dmatable_dma,
204		       (void __iomem *)(hwif->dma_base + ATA_DMA_TABLE_OFS));
205	else
206		outl(hwif->dmatable_dma, hwif->dma_base + ATA_DMA_TABLE_OFS);
207
208	/* specify r/w */
209	if (mmio)
210		writeb(rw, (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
211	else
212		outb(rw, hwif->dma_base + ATA_DMA_CMD);
213
214	/* read DMA status for INTR & ERROR flags */
215	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
216
217	/* clear INTR & ERROR flags */
218	ide_dma_sff_write_status(hwif, dma_stat | ATA_DMA_ERR | ATA_DMA_INTR);
219
220	return 0;
221}
222EXPORT_SYMBOL_GPL(ide_dma_setup);
223
224/**
225 *	ide_dma_sff_timer_expiry	-	handle a DMA timeout
226 *	@drive: Drive that timed out
227 *
228 *	An IDE DMA transfer timed out. In the event of an error we ask
229 *	the driver to resolve the problem, if a DMA transfer is still
230 *	in progress we continue to wait (arguably we need to add a
231 *	secondary 'I don't care what the drive thinks' timeout here)
232 *	Finally if we have an interrupt we let it complete the I/O.
233 *	But only one time - we clear expiry and if it's still not
234 *	completed after WAIT_CMD, we error and retry in PIO.
235 *	This can occur if an interrupt is lost or due to hang or bugs.
236 */
237
238int ide_dma_sff_timer_expiry(ide_drive_t *drive)
239{
240	ide_hwif_t *hwif = drive->hwif;
241	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
242
243	printk(KERN_WARNING "%s: %s: DMA status (0x%02x)\n",
244		drive->name, __func__, dma_stat);
245
246	if ((dma_stat & 0x18) == 0x18)	/* BUSY Stupid Early Timer !! */
247		return WAIT_CMD;
248
249	hwif->expiry = NULL;	/* one free ride for now */
250
251	if (dma_stat & ATA_DMA_ERR)	/* ERROR */
252		return -1;
253
254	if (dma_stat & ATA_DMA_ACTIVE)	/* DMAing */
255		return WAIT_CMD;
256
257	if (dma_stat & ATA_DMA_INTR)	/* Got an Interrupt */
258		return WAIT_CMD;
259
260	return 0;	/* Status is unknown -- reset the bus */
261}
262EXPORT_SYMBOL_GPL(ide_dma_sff_timer_expiry);
263
264void ide_dma_start(ide_drive_t *drive)
265{
266	ide_hwif_t *hwif = drive->hwif;
267	u8 dma_cmd;
268
269	/* Note that this is done *after* the cmd has
270	 * been issued to the drive, as per the BM-IDE spec.
271	 * The Promise Ultra33 doesn't work correctly when
272	 * we do this part before issuing the drive cmd.
273	 */
274	if (hwif->host_flags & IDE_HFLAG_MMIO) {
275		dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
276		writeb(dma_cmd | ATA_DMA_START,
277		       (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
278	} else {
279		dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
280		outb(dma_cmd | ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
281	}
282}
283EXPORT_SYMBOL_GPL(ide_dma_start);
284
285/* returns 1 on error, 0 otherwise */
286int ide_dma_end(ide_drive_t *drive)
287{
288	ide_hwif_t *hwif = drive->hwif;
289	u8 dma_stat = 0, dma_cmd = 0;
290
291	/* stop DMA */
292	if (hwif->host_flags & IDE_HFLAG_MMIO) {
293		dma_cmd = readb((void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
294		writeb(dma_cmd & ~ATA_DMA_START,
295		       (void __iomem *)(hwif->dma_base + ATA_DMA_CMD));
296	} else {
297		dma_cmd = inb(hwif->dma_base + ATA_DMA_CMD);
298		outb(dma_cmd & ~ATA_DMA_START, hwif->dma_base + ATA_DMA_CMD);
299	}
300
301	/* get DMA status */
302	dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
303
304	/* clear INTR & ERROR bits */
305	ide_dma_sff_write_status(hwif, dma_stat | ATA_DMA_ERR | ATA_DMA_INTR);
306
307#define CHECK_DMA_MASK (ATA_DMA_ACTIVE | ATA_DMA_ERR | ATA_DMA_INTR)
308
309	/* verify good DMA status */
310	if ((dma_stat & CHECK_DMA_MASK) != ATA_DMA_INTR)
311		return 0x10 | dma_stat;
312	return 0;
313}
314EXPORT_SYMBOL_GPL(ide_dma_end);
315
316/* returns 1 if dma irq issued, 0 otherwise */
317int ide_dma_test_irq(ide_drive_t *drive)
318{
319	ide_hwif_t *hwif = drive->hwif;
320	u8 dma_stat = hwif->dma_ops->dma_sff_read_status(hwif);
321
322	return (dma_stat & ATA_DMA_INTR) ? 1 : 0;
323}
324EXPORT_SYMBOL_GPL(ide_dma_test_irq);
325
326const struct ide_dma_ops sff_dma_ops = {
327	.dma_host_set		= ide_dma_host_set,
328	.dma_setup		= ide_dma_setup,
329	.dma_start		= ide_dma_start,
330	.dma_end		= ide_dma_end,
331	.dma_test_irq		= ide_dma_test_irq,
332	.dma_lost_irq		= ide_dma_lost_irq,
333	.dma_timer_expiry	= ide_dma_sff_timer_expiry,
334	.dma_sff_read_status	= ide_dma_sff_read_status,
335};
336EXPORT_SYMBOL_GPL(sff_dma_ops);
337