1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2004-2005 Advanced Micro Devices, Inc. 4 * Copyright (C) 2007 Bartlomiej Zolnierkiewicz 5 * 6 * History: 7 * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com> 8 * - Reworked tuneproc, set_drive, misc mods to prep for mainline 9 * - Work was sponsored by CIS (M) Sdn Bhd. 10 * Ported to Kernel 2.6.11 on June 26, 2005 by 11 * Wolfgang Zuleger <wolfgang.zuleger@gmx.de> 12 * Alexander Kiausch <alex.kiausch@t-online.de> 13 * Originally developed by AMD for 2.4/2.6 14 * 15 * Development of this chipset driver was funded 16 * by the nice folks at National Semiconductor/AMD. 17 * 18 * Documentation: 19 * CS5535 documentation available from AMD 20 */ 21 22#include <linux/module.h> 23#include <linux/pci.h> 24#include <linux/ide.h> 25 26#define DRV_NAME "cs5535" 27 28#define MSR_ATAC_BASE 0x51300000 29#define ATAC_GLD_MSR_CAP (MSR_ATAC_BASE+0) 30#define ATAC_GLD_MSR_CONFIG (MSR_ATAC_BASE+0x01) 31#define ATAC_GLD_MSR_SMI (MSR_ATAC_BASE+0x02) 32#define ATAC_GLD_MSR_ERROR (MSR_ATAC_BASE+0x03) 33#define ATAC_GLD_MSR_PM (MSR_ATAC_BASE+0x04) 34#define ATAC_GLD_MSR_DIAG (MSR_ATAC_BASE+0x05) 35#define ATAC_IO_BAR (MSR_ATAC_BASE+0x08) 36#define ATAC_RESET (MSR_ATAC_BASE+0x10) 37#define ATAC_CH0D0_PIO (MSR_ATAC_BASE+0x20) 38#define ATAC_CH0D0_DMA (MSR_ATAC_BASE+0x21) 39#define ATAC_CH0D1_PIO (MSR_ATAC_BASE+0x22) 40#define ATAC_CH0D1_DMA (MSR_ATAC_BASE+0x23) 41#define ATAC_PCI_ABRTERR (MSR_ATAC_BASE+0x24) 42#define ATAC_BM0_CMD_PRIM 0x00 43#define ATAC_BM0_STS_PRIM 0x02 44#define ATAC_BM0_PRD 0x04 45#define CS5535_CABLE_DETECT 0x48 46 47/* Format I PIO settings. We separate out cmd and data for safer timings */ 48 49static unsigned int cs5535_pio_cmd_timings[5] = 50{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 }; 51static unsigned int cs5535_pio_dta_timings[5] = 52{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 }; 53 54static unsigned int cs5535_mwdma_timings[3] = 55{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 }; 56 57static unsigned int cs5535_udma_timings[5] = 58{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 }; 59 60/* Macros to check if the register is the reset value - reset value is an 61 invalid timing and indicates the register has not been set previously */ 62 63#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 ) 64#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 ) 65 66/**** 67 * cs5535_set_speed - Configure the chipset to the new speed 68 * @drive: Drive to set up 69 * @speed: desired speed 70 * 71 * cs5535_set_speed() configures the chipset to a new speed. 72 */ 73static void cs5535_set_speed(ide_drive_t *drive, const u8 speed) 74{ 75 u32 reg = 0, dummy; 76 u8 unit = drive->dn & 1; 77 78 /* Set the PIO timings */ 79 if (speed < XFER_SW_DMA_0) { 80 ide_drive_t *pair = ide_get_pair_dev(drive); 81 u8 cmd, pioa; 82 83 cmd = pioa = speed - XFER_PIO_0; 84 85 if (pair) { 86 u8 piob = pair->pio_mode - XFER_PIO_0; 87 88 if (piob < cmd) 89 cmd = piob; 90 } 91 92 /* Write the speed of the current drive */ 93 reg = (cs5535_pio_cmd_timings[cmd] << 16) | 94 cs5535_pio_dta_timings[pioa]; 95 wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0); 96 97 /* And if nessesary - change the speed of the other drive */ 98 rdmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy); 99 100 if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) != 101 cs5535_pio_cmd_timings[cmd]) { 102 reg &= 0x0000FFFF; 103 reg |= cs5535_pio_cmd_timings[cmd] << 16; 104 wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0); 105 } 106 107 /* Set bit 31 of the DMA register for PIO format 1 timings */ 108 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); 109 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, 110 reg | 0x80000000UL, 0); 111 } else { 112 rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy); 113 114 reg &= 0x80000000UL; /* Preserve the PIO format bit */ 115 116 if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4) 117 reg |= cs5535_udma_timings[speed - XFER_UDMA_0]; 118 else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2) 119 reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0]; 120 else 121 return; 122 123 wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0); 124 } 125} 126 127/** 128 * cs5535_set_dma_mode - set host controller for DMA mode 129 * @hwif: port 130 * @drive: drive 131 * 132 * Programs the chipset for DMA mode. 133 */ 134 135static void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive) 136{ 137 cs5535_set_speed(drive, drive->dma_mode); 138} 139 140/** 141 * cs5535_set_pio_mode - set host controller for PIO mode 142 * @hwif: port 143 * @drive: drive 144 * 145 * A callback from the upper layers for PIO-only tuning. 146 */ 147 148static void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 149{ 150 cs5535_set_speed(drive, drive->pio_mode); 151} 152 153static u8 cs5535_cable_detect(ide_hwif_t *hwif) 154{ 155 struct pci_dev *dev = to_pci_dev(hwif->dev); 156 u8 bit; 157 158 /* if a 80 wire cable was detected */ 159 pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit); 160 161 return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40; 162} 163 164static const struct ide_port_ops cs5535_port_ops = { 165 .set_pio_mode = cs5535_set_pio_mode, 166 .set_dma_mode = cs5535_set_dma_mode, 167 .cable_detect = cs5535_cable_detect, 168}; 169 170static const struct ide_port_info cs5535_chipset = { 171 .name = DRV_NAME, 172 .port_ops = &cs5535_port_ops, 173 .host_flags = IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE, 174 .pio_mask = ATA_PIO4, 175 .mwdma_mask = ATA_MWDMA2, 176 .udma_mask = ATA_UDMA4, 177}; 178 179static int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id) 180{ 181 return ide_pci_init_one(dev, &cs5535_chipset, NULL); 182} 183 184static const struct pci_device_id cs5535_pci_tbl[] = { 185 { PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 }, 186 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), }, 187 { 0, }, 188}; 189 190MODULE_DEVICE_TABLE(pci, cs5535_pci_tbl); 191 192static struct pci_driver cs5535_pci_driver = { 193 .name = "CS5535_IDE", 194 .id_table = cs5535_pci_tbl, 195 .probe = cs5535_init_one, 196 .remove = ide_pci_remove, 197 .suspend = ide_pci_suspend, 198 .resume = ide_pci_resume, 199}; 200 201static int __init cs5535_ide_init(void) 202{ 203 return ide_pci_register_driver(&cs5535_pci_driver); 204} 205 206static void __exit cs5535_ide_exit(void) 207{ 208 pci_unregister_driver(&cs5535_pci_driver); 209} 210 211module_init(cs5535_ide_init); 212module_exit(cs5535_ide_exit); 213 214MODULE_AUTHOR("AMD"); 215MODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE"); 216MODULE_LICENSE("GPL"); 217