18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0-only
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (C) 2004-2005 Advanced Micro Devices, Inc.
48c2ecf20Sopenharmony_ci * Copyright (C)      2007 Bartlomiej Zolnierkiewicz
58c2ecf20Sopenharmony_ci *
68c2ecf20Sopenharmony_ci * History:
78c2ecf20Sopenharmony_ci * 09/20/2005 - Jaya Kumar <jayakumar.ide@gmail.com>
88c2ecf20Sopenharmony_ci * - Reworked tuneproc, set_drive, misc mods to prep for mainline
98c2ecf20Sopenharmony_ci * - Work was sponsored by CIS (M) Sdn Bhd.
108c2ecf20Sopenharmony_ci * Ported to Kernel 2.6.11 on June 26, 2005 by
118c2ecf20Sopenharmony_ci *   Wolfgang Zuleger <wolfgang.zuleger@gmx.de>
128c2ecf20Sopenharmony_ci *   Alexander Kiausch <alex.kiausch@t-online.de>
138c2ecf20Sopenharmony_ci * Originally developed by AMD for 2.4/2.6
148c2ecf20Sopenharmony_ci *
158c2ecf20Sopenharmony_ci * Development of this chipset driver was funded
168c2ecf20Sopenharmony_ci * by the nice folks at National Semiconductor/AMD.
178c2ecf20Sopenharmony_ci *
188c2ecf20Sopenharmony_ci * Documentation:
198c2ecf20Sopenharmony_ci *  CS5535 documentation available from AMD
208c2ecf20Sopenharmony_ci */
218c2ecf20Sopenharmony_ci
228c2ecf20Sopenharmony_ci#include <linux/module.h>
238c2ecf20Sopenharmony_ci#include <linux/pci.h>
248c2ecf20Sopenharmony_ci#include <linux/ide.h>
258c2ecf20Sopenharmony_ci
268c2ecf20Sopenharmony_ci#define DRV_NAME "cs5535"
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci#define MSR_ATAC_BASE		0x51300000
298c2ecf20Sopenharmony_ci#define ATAC_GLD_MSR_CAP	(MSR_ATAC_BASE+0)
308c2ecf20Sopenharmony_ci#define ATAC_GLD_MSR_CONFIG	(MSR_ATAC_BASE+0x01)
318c2ecf20Sopenharmony_ci#define ATAC_GLD_MSR_SMI	(MSR_ATAC_BASE+0x02)
328c2ecf20Sopenharmony_ci#define ATAC_GLD_MSR_ERROR	(MSR_ATAC_BASE+0x03)
338c2ecf20Sopenharmony_ci#define ATAC_GLD_MSR_PM		(MSR_ATAC_BASE+0x04)
348c2ecf20Sopenharmony_ci#define ATAC_GLD_MSR_DIAG	(MSR_ATAC_BASE+0x05)
358c2ecf20Sopenharmony_ci#define ATAC_IO_BAR		(MSR_ATAC_BASE+0x08)
368c2ecf20Sopenharmony_ci#define ATAC_RESET		(MSR_ATAC_BASE+0x10)
378c2ecf20Sopenharmony_ci#define ATAC_CH0D0_PIO		(MSR_ATAC_BASE+0x20)
388c2ecf20Sopenharmony_ci#define ATAC_CH0D0_DMA		(MSR_ATAC_BASE+0x21)
398c2ecf20Sopenharmony_ci#define ATAC_CH0D1_PIO		(MSR_ATAC_BASE+0x22)
408c2ecf20Sopenharmony_ci#define ATAC_CH0D1_DMA		(MSR_ATAC_BASE+0x23)
418c2ecf20Sopenharmony_ci#define ATAC_PCI_ABRTERR	(MSR_ATAC_BASE+0x24)
428c2ecf20Sopenharmony_ci#define ATAC_BM0_CMD_PRIM	0x00
438c2ecf20Sopenharmony_ci#define ATAC_BM0_STS_PRIM	0x02
448c2ecf20Sopenharmony_ci#define ATAC_BM0_PRD		0x04
458c2ecf20Sopenharmony_ci#define CS5535_CABLE_DETECT	0x48
468c2ecf20Sopenharmony_ci
478c2ecf20Sopenharmony_ci/* Format I PIO settings. We separate out cmd and data for safer timings */
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_cistatic unsigned int cs5535_pio_cmd_timings[5] =
508c2ecf20Sopenharmony_ci{ 0xF7F4, 0x53F3, 0x13F1, 0x5131, 0x1131 };
518c2ecf20Sopenharmony_cistatic unsigned int cs5535_pio_dta_timings[5] =
528c2ecf20Sopenharmony_ci{ 0xF7F4, 0xF173, 0x8141, 0x5131, 0x1131 };
538c2ecf20Sopenharmony_ci
548c2ecf20Sopenharmony_cistatic unsigned int cs5535_mwdma_timings[3] =
558c2ecf20Sopenharmony_ci{ 0x7F0FFFF3, 0x7F035352, 0x7f024241 };
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_cistatic unsigned int cs5535_udma_timings[5] =
588c2ecf20Sopenharmony_ci{ 0x7F7436A1, 0x7F733481, 0x7F723261, 0x7F713161, 0x7F703061 };
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci/* Macros to check if the register is the reset value -  reset value is an
618c2ecf20Sopenharmony_ci   invalid timing and indicates the register has not been set previously */
628c2ecf20Sopenharmony_ci
638c2ecf20Sopenharmony_ci#define CS5535_BAD_PIO(timings) ( (timings&~0x80000000UL) == 0x00009172 )
648c2ecf20Sopenharmony_ci#define CS5535_BAD_DMA(timings) ( (timings & 0x000FFFFF) == 0x00077771 )
658c2ecf20Sopenharmony_ci
668c2ecf20Sopenharmony_ci/****
678c2ecf20Sopenharmony_ci *	cs5535_set_speed         -     Configure the chipset to the new speed
688c2ecf20Sopenharmony_ci *	@drive: Drive to set up
698c2ecf20Sopenharmony_ci *	@speed: desired speed
708c2ecf20Sopenharmony_ci *
718c2ecf20Sopenharmony_ci *	cs5535_set_speed() configures the chipset to a new speed.
728c2ecf20Sopenharmony_ci */
738c2ecf20Sopenharmony_cistatic void cs5535_set_speed(ide_drive_t *drive, const u8 speed)
748c2ecf20Sopenharmony_ci{
758c2ecf20Sopenharmony_ci	u32 reg = 0, dummy;
768c2ecf20Sopenharmony_ci	u8 unit = drive->dn & 1;
778c2ecf20Sopenharmony_ci
788c2ecf20Sopenharmony_ci	/* Set the PIO timings */
798c2ecf20Sopenharmony_ci	if (speed < XFER_SW_DMA_0) {
808c2ecf20Sopenharmony_ci		ide_drive_t *pair = ide_get_pair_dev(drive);
818c2ecf20Sopenharmony_ci		u8 cmd, pioa;
828c2ecf20Sopenharmony_ci
838c2ecf20Sopenharmony_ci		cmd = pioa = speed - XFER_PIO_0;
848c2ecf20Sopenharmony_ci
858c2ecf20Sopenharmony_ci		if (pair) {
868c2ecf20Sopenharmony_ci			u8 piob = pair->pio_mode - XFER_PIO_0;
878c2ecf20Sopenharmony_ci
888c2ecf20Sopenharmony_ci			if (piob < cmd)
898c2ecf20Sopenharmony_ci				cmd = piob;
908c2ecf20Sopenharmony_ci		}
918c2ecf20Sopenharmony_ci
928c2ecf20Sopenharmony_ci		/* Write the speed of the current drive */
938c2ecf20Sopenharmony_ci		reg = (cs5535_pio_cmd_timings[cmd] << 16) |
948c2ecf20Sopenharmony_ci			cs5535_pio_dta_timings[pioa];
958c2ecf20Sopenharmony_ci		wrmsr(unit ? ATAC_CH0D1_PIO : ATAC_CH0D0_PIO, reg, 0);
968c2ecf20Sopenharmony_ci
978c2ecf20Sopenharmony_ci		/* And if nessesary - change the speed of the other drive */
988c2ecf20Sopenharmony_ci		rdmsr(unit ?  ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, dummy);
998c2ecf20Sopenharmony_ci
1008c2ecf20Sopenharmony_ci		if (((reg >> 16) & cs5535_pio_cmd_timings[cmd]) !=
1018c2ecf20Sopenharmony_ci			cs5535_pio_cmd_timings[cmd]) {
1028c2ecf20Sopenharmony_ci			reg &= 0x0000FFFF;
1038c2ecf20Sopenharmony_ci			reg |= cs5535_pio_cmd_timings[cmd] << 16;
1048c2ecf20Sopenharmony_ci			wrmsr(unit ? ATAC_CH0D0_PIO : ATAC_CH0D1_PIO, reg, 0);
1058c2ecf20Sopenharmony_ci		}
1068c2ecf20Sopenharmony_ci
1078c2ecf20Sopenharmony_ci		/* Set bit 31 of the DMA register for PIO format 1 timings */
1088c2ecf20Sopenharmony_ci		rdmsr(unit ?  ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
1098c2ecf20Sopenharmony_ci		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA,
1108c2ecf20Sopenharmony_ci					reg | 0x80000000UL, 0);
1118c2ecf20Sopenharmony_ci	} else {
1128c2ecf20Sopenharmony_ci		rdmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, dummy);
1138c2ecf20Sopenharmony_ci
1148c2ecf20Sopenharmony_ci		reg &= 0x80000000UL;  /* Preserve the PIO format bit */
1158c2ecf20Sopenharmony_ci
1168c2ecf20Sopenharmony_ci		if (speed >= XFER_UDMA_0 && speed <= XFER_UDMA_4)
1178c2ecf20Sopenharmony_ci			reg |= cs5535_udma_timings[speed - XFER_UDMA_0];
1188c2ecf20Sopenharmony_ci		else if (speed >= XFER_MW_DMA_0 && speed <= XFER_MW_DMA_2)
1198c2ecf20Sopenharmony_ci			reg |= cs5535_mwdma_timings[speed - XFER_MW_DMA_0];
1208c2ecf20Sopenharmony_ci		else
1218c2ecf20Sopenharmony_ci			return;
1228c2ecf20Sopenharmony_ci
1238c2ecf20Sopenharmony_ci		wrmsr(unit ? ATAC_CH0D1_DMA : ATAC_CH0D0_DMA, reg, 0);
1248c2ecf20Sopenharmony_ci	}
1258c2ecf20Sopenharmony_ci}
1268c2ecf20Sopenharmony_ci
1278c2ecf20Sopenharmony_ci/**
1288c2ecf20Sopenharmony_ci *	cs5535_set_dma_mode	-	set host controller for DMA mode
1298c2ecf20Sopenharmony_ci *	@hwif: port
1308c2ecf20Sopenharmony_ci *	@drive: drive
1318c2ecf20Sopenharmony_ci *
1328c2ecf20Sopenharmony_ci *	Programs the chipset for DMA mode.
1338c2ecf20Sopenharmony_ci */
1348c2ecf20Sopenharmony_ci
1358c2ecf20Sopenharmony_cistatic void cs5535_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
1368c2ecf20Sopenharmony_ci{
1378c2ecf20Sopenharmony_ci	cs5535_set_speed(drive, drive->dma_mode);
1388c2ecf20Sopenharmony_ci}
1398c2ecf20Sopenharmony_ci
1408c2ecf20Sopenharmony_ci/**
1418c2ecf20Sopenharmony_ci *	cs5535_set_pio_mode	-	set host controller for PIO mode
1428c2ecf20Sopenharmony_ci *	@hwif: port
1438c2ecf20Sopenharmony_ci *	@drive: drive
1448c2ecf20Sopenharmony_ci *
1458c2ecf20Sopenharmony_ci *	A callback from the upper layers for PIO-only tuning.
1468c2ecf20Sopenharmony_ci */
1478c2ecf20Sopenharmony_ci
1488c2ecf20Sopenharmony_cistatic void cs5535_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
1498c2ecf20Sopenharmony_ci{
1508c2ecf20Sopenharmony_ci	cs5535_set_speed(drive, drive->pio_mode);
1518c2ecf20Sopenharmony_ci}
1528c2ecf20Sopenharmony_ci
1538c2ecf20Sopenharmony_cistatic u8 cs5535_cable_detect(ide_hwif_t *hwif)
1548c2ecf20Sopenharmony_ci{
1558c2ecf20Sopenharmony_ci	struct pci_dev *dev = to_pci_dev(hwif->dev);
1568c2ecf20Sopenharmony_ci	u8 bit;
1578c2ecf20Sopenharmony_ci
1588c2ecf20Sopenharmony_ci	/* if a 80 wire cable was detected */
1598c2ecf20Sopenharmony_ci	pci_read_config_byte(dev, CS5535_CABLE_DETECT, &bit);
1608c2ecf20Sopenharmony_ci
1618c2ecf20Sopenharmony_ci	return (bit & 1) ? ATA_CBL_PATA80 : ATA_CBL_PATA40;
1628c2ecf20Sopenharmony_ci}
1638c2ecf20Sopenharmony_ci
1648c2ecf20Sopenharmony_cistatic const struct ide_port_ops cs5535_port_ops = {
1658c2ecf20Sopenharmony_ci	.set_pio_mode		= cs5535_set_pio_mode,
1668c2ecf20Sopenharmony_ci	.set_dma_mode		= cs5535_set_dma_mode,
1678c2ecf20Sopenharmony_ci	.cable_detect		= cs5535_cable_detect,
1688c2ecf20Sopenharmony_ci};
1698c2ecf20Sopenharmony_ci
1708c2ecf20Sopenharmony_cistatic const struct ide_port_info cs5535_chipset = {
1718c2ecf20Sopenharmony_ci	.name		= DRV_NAME,
1728c2ecf20Sopenharmony_ci	.port_ops	= &cs5535_port_ops,
1738c2ecf20Sopenharmony_ci	.host_flags	= IDE_HFLAG_SINGLE | IDE_HFLAG_POST_SET_MODE,
1748c2ecf20Sopenharmony_ci	.pio_mask	= ATA_PIO4,
1758c2ecf20Sopenharmony_ci	.mwdma_mask	= ATA_MWDMA2,
1768c2ecf20Sopenharmony_ci	.udma_mask	= ATA_UDMA4,
1778c2ecf20Sopenharmony_ci};
1788c2ecf20Sopenharmony_ci
1798c2ecf20Sopenharmony_cistatic int cs5535_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1808c2ecf20Sopenharmony_ci{
1818c2ecf20Sopenharmony_ci	return ide_pci_init_one(dev, &cs5535_chipset, NULL);
1828c2ecf20Sopenharmony_ci}
1838c2ecf20Sopenharmony_ci
1848c2ecf20Sopenharmony_cistatic const struct pci_device_id cs5535_pci_tbl[] = {
1858c2ecf20Sopenharmony_ci	{ PCI_VDEVICE(NS, PCI_DEVICE_ID_NS_CS5535_IDE), 0 },
1868c2ecf20Sopenharmony_ci	{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5535_IDE), },
1878c2ecf20Sopenharmony_ci	{ 0, },
1888c2ecf20Sopenharmony_ci};
1898c2ecf20Sopenharmony_ci
1908c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(pci, cs5535_pci_tbl);
1918c2ecf20Sopenharmony_ci
1928c2ecf20Sopenharmony_cistatic struct pci_driver cs5535_pci_driver = {
1938c2ecf20Sopenharmony_ci	.name		= "CS5535_IDE",
1948c2ecf20Sopenharmony_ci	.id_table	= cs5535_pci_tbl,
1958c2ecf20Sopenharmony_ci	.probe		= cs5535_init_one,
1968c2ecf20Sopenharmony_ci	.remove		= ide_pci_remove,
1978c2ecf20Sopenharmony_ci	.suspend	= ide_pci_suspend,
1988c2ecf20Sopenharmony_ci	.resume		= ide_pci_resume,
1998c2ecf20Sopenharmony_ci};
2008c2ecf20Sopenharmony_ci
2018c2ecf20Sopenharmony_cistatic int __init cs5535_ide_init(void)
2028c2ecf20Sopenharmony_ci{
2038c2ecf20Sopenharmony_ci	return ide_pci_register_driver(&cs5535_pci_driver);
2048c2ecf20Sopenharmony_ci}
2058c2ecf20Sopenharmony_ci
2068c2ecf20Sopenharmony_cistatic void __exit cs5535_ide_exit(void)
2078c2ecf20Sopenharmony_ci{
2088c2ecf20Sopenharmony_ci	pci_unregister_driver(&cs5535_pci_driver);
2098c2ecf20Sopenharmony_ci}
2108c2ecf20Sopenharmony_ci
2118c2ecf20Sopenharmony_cimodule_init(cs5535_ide_init);
2128c2ecf20Sopenharmony_cimodule_exit(cs5535_ide_exit);
2138c2ecf20Sopenharmony_ci
2148c2ecf20Sopenharmony_ciMODULE_AUTHOR("AMD");
2158c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("PCI driver module for AMD/NS CS5535 IDE");
2168c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL");
217