1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * AMD 755/756/766/8111 and nVidia nForce/2/2s/3/3s/CK804/MCP04 4 * IDE driver for Linux. 5 * 6 * Copyright (c) 2000-2002 Vojtech Pavlik 7 * Copyright (c) 2007-2010 Bartlomiej Zolnierkiewicz 8 * 9 * Based on the work of: 10 * Andre Hedrick 11 */ 12 13 14#include <linux/module.h> 15#include <linux/kernel.h> 16#include <linux/pci.h> 17#include <linux/init.h> 18#include <linux/ide.h> 19 20#define DRV_NAME "amd74xx" 21 22enum { 23 AMD_IDE_CONFIG = 0x41, 24 AMD_CABLE_DETECT = 0x42, 25 AMD_DRIVE_TIMING = 0x48, 26 AMD_8BIT_TIMING = 0x4e, 27 AMD_ADDRESS_SETUP = 0x4c, 28 AMD_UDMA_TIMING = 0x50, 29}; 30 31static unsigned int amd_80w; 32static unsigned int amd_clock; 33 34static char *amd_dma[] = { "16", "25", "33", "44", "66", "100", "133" }; 35static unsigned char amd_cyc2udma[] = { 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7 }; 36 37static inline u8 amd_offset(struct pci_dev *dev) 38{ 39 return (dev->vendor == PCI_VENDOR_ID_NVIDIA) ? 0x10 : 0; 40} 41 42/* 43 * amd_set_speed() writes timing values to the chipset registers 44 */ 45 46static void amd_set_speed(struct pci_dev *dev, u8 dn, u8 udma_mask, 47 struct ide_timing *timing) 48{ 49 u8 t = 0, offset = amd_offset(dev); 50 51 pci_read_config_byte(dev, AMD_ADDRESS_SETUP + offset, &t); 52 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); 53 pci_write_config_byte(dev, AMD_ADDRESS_SETUP + offset, t); 54 55 pci_write_config_byte(dev, AMD_8BIT_TIMING + offset + (1 - (dn >> 1)), 56 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); 57 58 pci_write_config_byte(dev, AMD_DRIVE_TIMING + offset + (3 - dn), 59 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); 60 61 switch (udma_mask) { 62 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; 63 case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; break; 64 case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; break; 65 case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; break; 66 default: return; 67 } 68 69 if (timing->udma) 70 pci_write_config_byte(dev, AMD_UDMA_TIMING + offset + 3 - dn, t); 71} 72 73/* 74 * amd_set_drive() computes timing values and configures the chipset 75 * to a desired transfer mode. It also can be called by upper layers. 76 */ 77 78static void amd_set_drive(ide_hwif_t *hwif, ide_drive_t *drive) 79{ 80 struct pci_dev *dev = to_pci_dev(hwif->dev); 81 ide_drive_t *peer = ide_get_pair_dev(drive); 82 struct ide_timing t, p; 83 int T, UT; 84 u8 udma_mask = hwif->ultra_mask; 85 const u8 speed = drive->dma_mode; 86 87 T = 1000000000 / amd_clock; 88 UT = (udma_mask == ATA_UDMA2) ? T : (T / 2); 89 90 ide_timing_compute(drive, speed, &t, T, UT); 91 92 if (peer) { 93 ide_timing_compute(peer, peer->pio_mode, &p, T, UT); 94 ide_timing_merge(&p, &t, &t, IDE_TIMING_8BIT); 95 } 96 97 if (speed == XFER_UDMA_5 && amd_clock <= 33333) t.udma = 1; 98 if (speed == XFER_UDMA_6 && amd_clock <= 33333) t.udma = 15; 99 100 amd_set_speed(dev, drive->dn, udma_mask, &t); 101} 102 103/* 104 * amd_set_pio_mode() is a callback from upper layers for PIO-only tuning. 105 */ 106 107static void amd_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive) 108{ 109 drive->dma_mode = drive->pio_mode; 110 amd_set_drive(hwif, drive); 111} 112 113static void amd7409_cable_detect(struct pci_dev *dev) 114{ 115 /* no host side cable detection */ 116 amd_80w = 0x03; 117} 118 119static void amd7411_cable_detect(struct pci_dev *dev) 120{ 121 int i; 122 u32 u = 0; 123 u8 t = 0, offset = amd_offset(dev); 124 125 pci_read_config_byte(dev, AMD_CABLE_DETECT + offset, &t); 126 pci_read_config_dword(dev, AMD_UDMA_TIMING + offset, &u); 127 amd_80w = ((t & 0x3) ? 1 : 0) | ((t & 0xc) ? 2 : 0); 128 for (i = 24; i >= 0; i -= 8) 129 if (((u >> i) & 4) && !(amd_80w & (1 << (1 - (i >> 4))))) { 130 printk(KERN_WARNING DRV_NAME " %s: BIOS didn't set " 131 "cable bits correctly. Enabling workaround.\n", 132 pci_name(dev)); 133 amd_80w |= (1 << (1 - (i >> 4))); 134 } 135} 136 137/* 138 * The initialization callback. Initialize drive independent registers. 139 */ 140 141static int init_chipset_amd74xx(struct pci_dev *dev) 142{ 143 u8 t = 0, offset = amd_offset(dev); 144 145/* 146 * Check 80-wire cable presence. 147 */ 148 149 if (dev->vendor == PCI_VENDOR_ID_AMD && 150 dev->device == PCI_DEVICE_ID_AMD_COBRA_7401) 151 ; /* no UDMA > 2 */ 152 else if (dev->vendor == PCI_VENDOR_ID_AMD && 153 dev->device == PCI_DEVICE_ID_AMD_VIPER_7409) 154 amd7409_cable_detect(dev); 155 else 156 amd7411_cable_detect(dev); 157 158/* 159 * Take care of prefetch & postwrite. 160 */ 161 162 pci_read_config_byte(dev, AMD_IDE_CONFIG + offset, &t); 163 /* 164 * Check for broken FIFO support. 165 */ 166 if (dev->vendor == PCI_VENDOR_ID_AMD && 167 dev->device == PCI_DEVICE_ID_AMD_VIPER_7411) 168 t &= 0x0f; 169 else 170 t |= 0xf0; 171 pci_write_config_byte(dev, AMD_IDE_CONFIG + offset, t); 172 173 return 0; 174} 175 176static u8 amd_cable_detect(ide_hwif_t *hwif) 177{ 178 if ((amd_80w >> hwif->channel) & 1) 179 return ATA_CBL_PATA80; 180 else 181 return ATA_CBL_PATA40; 182} 183 184static const struct ide_port_ops amd_port_ops = { 185 .set_pio_mode = amd_set_pio_mode, 186 .set_dma_mode = amd_set_drive, 187 .cable_detect = amd_cable_detect, 188}; 189 190#define IDE_HFLAGS_AMD \ 191 (IDE_HFLAG_PIO_NO_BLACKLIST | \ 192 IDE_HFLAG_POST_SET_MODE | \ 193 IDE_HFLAG_IO_32BIT | \ 194 IDE_HFLAG_UNMASK_IRQS) 195 196#define DECLARE_AMD_DEV(swdma, udma) \ 197 { \ 198 .name = DRV_NAME, \ 199 .init_chipset = init_chipset_amd74xx, \ 200 .enablebits = {{0x40,0x02,0x02}, {0x40,0x01,0x01}}, \ 201 .port_ops = &amd_port_ops, \ 202 .host_flags = IDE_HFLAGS_AMD, \ 203 .pio_mask = ATA_PIO5, \ 204 .swdma_mask = swdma, \ 205 .mwdma_mask = ATA_MWDMA2, \ 206 .udma_mask = udma, \ 207 } 208 209#define DECLARE_NV_DEV(udma) \ 210 { \ 211 .name = DRV_NAME, \ 212 .init_chipset = init_chipset_amd74xx, \ 213 .enablebits = {{0x50,0x02,0x02}, {0x50,0x01,0x01}}, \ 214 .port_ops = &amd_port_ops, \ 215 .host_flags = IDE_HFLAGS_AMD, \ 216 .pio_mask = ATA_PIO5, \ 217 .swdma_mask = ATA_SWDMA2, \ 218 .mwdma_mask = ATA_MWDMA2, \ 219 .udma_mask = udma, \ 220 } 221 222static const struct ide_port_info amd74xx_chipsets[] = { 223 /* 0: AMD7401 */ DECLARE_AMD_DEV(0x00, ATA_UDMA2), 224 /* 1: AMD7409 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA4), 225 /* 2: AMD7411/7441 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5), 226 /* 3: AMD8111 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA6), 227 228 /* 4: NFORCE */ DECLARE_NV_DEV(ATA_UDMA5), 229 /* 5: >= NFORCE2 */ DECLARE_NV_DEV(ATA_UDMA6), 230 231 /* 6: AMD5536 */ DECLARE_AMD_DEV(ATA_SWDMA2, ATA_UDMA5), 232}; 233 234static int amd74xx_probe(struct pci_dev *dev, const struct pci_device_id *id) 235{ 236 struct ide_port_info d; 237 u8 idx = id->driver_data; 238 239 d = amd74xx_chipsets[idx]; 240 241 /* 242 * Check for bad SWDMA and incorrectly wired Serenade mainboards. 243 */ 244 if (idx == 1) { 245 if (dev->revision <= 7) 246 d.swdma_mask = 0; 247 d.host_flags |= IDE_HFLAG_CLEAR_SIMPLEX; 248 } else if (idx == 3) { 249 if (dev->subsystem_vendor == PCI_VENDOR_ID_AMD && 250 dev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE) 251 d.udma_mask = ATA_UDMA5; 252 } 253 254 /* 255 * It seems that on some nVidia controllers using AltStatus 256 * register can be unreliable so default to Status register 257 * if the device is in Compatibility Mode. 258 */ 259 if (dev->vendor == PCI_VENDOR_ID_NVIDIA && 260 ide_pci_is_in_compatibility_mode(dev)) 261 d.host_flags |= IDE_HFLAG_BROKEN_ALTSTATUS; 262 263 printk(KERN_INFO "%s %s: UDMA%s controller\n", 264 d.name, pci_name(dev), amd_dma[fls(d.udma_mask) - 1]); 265 266 /* 267 * Determine the system bus clock. 268 */ 269 amd_clock = (ide_pci_clk ? ide_pci_clk : 33) * 1000; 270 271 switch (amd_clock) { 272 case 33000: amd_clock = 33333; break; 273 case 37000: amd_clock = 37500; break; 274 case 41000: amd_clock = 41666; break; 275 } 276 277 if (amd_clock < 20000 || amd_clock > 50000) { 278 printk(KERN_WARNING "%s: User given PCI clock speed impossible" 279 " (%d), using 33 MHz instead.\n", 280 d.name, amd_clock); 281 amd_clock = 33333; 282 } 283 284 return ide_pci_init_one(dev, &d, NULL); 285} 286 287static const struct pci_device_id amd74xx_pci_tbl[] = { 288 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 }, 289 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 }, 290 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 2 }, 291 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 2 }, 292 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 3 }, 293 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 4 }, 294 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 5 }, 295 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 5 }, 296#ifdef CONFIG_BLK_DEV_IDE_SATA 297 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), 5 }, 298#endif 299 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 5 }, 300 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 5 }, 301#ifdef CONFIG_BLK_DEV_IDE_SATA 302 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), 5 }, 303 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), 5 }, 304#endif 305 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 5 }, 306 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 5 }, 307 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 5 }, 308 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 5 }, 309 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 5 }, 310 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 5 }, 311 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 5 }, 312 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 5 }, 313 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 5 }, 314 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 6 }, 315 { 0, }, 316}; 317MODULE_DEVICE_TABLE(pci, amd74xx_pci_tbl); 318 319static struct pci_driver amd74xx_pci_driver = { 320 .name = "AMD_IDE", 321 .id_table = amd74xx_pci_tbl, 322 .probe = amd74xx_probe, 323 .remove = ide_pci_remove, 324 .suspend = ide_pci_suspend, 325 .resume = ide_pci_resume, 326}; 327 328static int __init amd74xx_ide_init(void) 329{ 330 return ide_pci_register_driver(&amd74xx_pci_driver); 331} 332 333static void __exit amd74xx_ide_exit(void) 334{ 335 pci_unregister_driver(&amd74xx_pci_driver); 336} 337 338module_init(amd74xx_ide_init); 339module_exit(amd74xx_ide_exit); 340 341MODULE_AUTHOR("Vojtech Pavlik, Bartlomiej Zolnierkiewicz"); 342MODULE_DESCRIPTION("AMD PCI IDE driver"); 343MODULE_LICENSE("GPL"); 344