1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2017 Sanechips Technology Co., Ltd.
4 * Copyright 2017 Linaro Ltd.
5 *
6 * Author: Baoyou Xie <baoyou.xie@linaro.org>
7 */
8
9#include <linux/clk.h>
10#include <linux/i2c.h>
11#include <linux/interrupt.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/platform_device.h>
15
16#define REG_CMD				0x04
17#define REG_DEVADDR_H			0x0C
18#define REG_DEVADDR_L			0x10
19#define REG_CLK_DIV_FS			0x14
20#define REG_CLK_DIV_HS			0x18
21#define REG_WRCONF			0x1C
22#define REG_RDCONF			0x20
23#define REG_DATA			0x24
24#define REG_STAT			0x28
25
26#define I2C_STOP			0
27#define I2C_MASTER			BIT(0)
28#define I2C_ADDR_MODE_TEN		BIT(1)
29#define I2C_IRQ_MSK_ENABLE		BIT(3)
30#define I2C_RW_READ			BIT(4)
31#define I2C_CMB_RW_EN			BIT(5)
32#define I2C_START			BIT(6)
33
34#define I2C_ADDR_LOW_MASK		GENMASK(6, 0)
35#define I2C_ADDR_LOW_SHIFT		0
36#define I2C_ADDR_HI_MASK		GENMASK(2, 0)
37#define I2C_ADDR_HI_SHIFT		7
38
39#define I2C_WFIFO_RESET			BIT(7)
40#define I2C_RFIFO_RESET			BIT(7)
41
42#define I2C_IRQ_ACK_CLEAR		BIT(7)
43#define I2C_INT_MASK			GENMASK(6, 0)
44
45#define I2C_TRANS_DONE			BIT(0)
46#define I2C_SR_EDEVICE			BIT(1)
47#define I2C_SR_EDATA			BIT(2)
48
49#define I2C_FIFO_MAX			16
50
51#define I2C_TIMEOUT			msecs_to_jiffies(1000)
52
53#define DEV(i2c)			((i2c)->adap.dev.parent)
54
55struct zx2967_i2c {
56	struct i2c_adapter	adap;
57	struct clk		*clk;
58	struct completion	complete;
59	u32			clk_freq;
60	void __iomem		*reg_base;
61	size_t			residue;
62	int			irq;
63	int			msg_rd;
64	u8			*cur_trans;
65	u8			access_cnt;
66	int			error;
67};
68
69static void zx2967_i2c_writel(struct zx2967_i2c *i2c,
70			      u32 val, unsigned long reg)
71{
72	writel_relaxed(val, i2c->reg_base + reg);
73}
74
75static u32 zx2967_i2c_readl(struct zx2967_i2c *i2c, unsigned long reg)
76{
77	return readl_relaxed(i2c->reg_base + reg);
78}
79
80static void zx2967_i2c_writesb(struct zx2967_i2c *i2c,
81			       void *data, unsigned long reg, int len)
82{
83	writesb(i2c->reg_base + reg, data, len);
84}
85
86static void zx2967_i2c_readsb(struct zx2967_i2c *i2c,
87			      void *data, unsigned long reg, int len)
88{
89	readsb(i2c->reg_base + reg, data, len);
90}
91
92static void zx2967_i2c_start_ctrl(struct zx2967_i2c *i2c)
93{
94	u32 status;
95	u32 ctl;
96
97	status = zx2967_i2c_readl(i2c, REG_STAT);
98	status |= I2C_IRQ_ACK_CLEAR;
99	zx2967_i2c_writel(i2c, status, REG_STAT);
100
101	ctl = zx2967_i2c_readl(i2c, REG_CMD);
102	if (i2c->msg_rd)
103		ctl |= I2C_RW_READ;
104	else
105		ctl &= ~I2C_RW_READ;
106	ctl &= ~I2C_CMB_RW_EN;
107	ctl |= I2C_START;
108	zx2967_i2c_writel(i2c, ctl, REG_CMD);
109}
110
111static void zx2967_i2c_flush_fifos(struct zx2967_i2c *i2c)
112{
113	u32 offset;
114	u32 val;
115
116	if (i2c->msg_rd) {
117		offset = REG_RDCONF;
118		val = I2C_RFIFO_RESET;
119	} else {
120		offset = REG_WRCONF;
121		val = I2C_WFIFO_RESET;
122	}
123
124	val |= zx2967_i2c_readl(i2c, offset);
125	zx2967_i2c_writel(i2c, val, offset);
126}
127
128static int zx2967_i2c_empty_rx_fifo(struct zx2967_i2c *i2c, u32 size)
129{
130	u8 val[I2C_FIFO_MAX] = {0};
131	int i;
132
133	if (size > I2C_FIFO_MAX) {
134		dev_err(DEV(i2c), "fifo size %d over the max value %d\n",
135			size, I2C_FIFO_MAX);
136		return -EINVAL;
137	}
138
139	zx2967_i2c_readsb(i2c, val, REG_DATA, size);
140	for (i = 0; i < size; i++) {
141		*i2c->cur_trans++ = val[i];
142		i2c->residue--;
143	}
144
145	barrier();
146
147	return 0;
148}
149
150static int zx2967_i2c_fill_tx_fifo(struct zx2967_i2c *i2c)
151{
152	size_t residue = i2c->residue;
153	u8 *buf = i2c->cur_trans;
154
155	if (residue == 0) {
156		dev_err(DEV(i2c), "residue is %d\n", (int)residue);
157		return -EINVAL;
158	}
159
160	if (residue <= I2C_FIFO_MAX) {
161		zx2967_i2c_writesb(i2c, buf, REG_DATA, residue);
162
163		/* Again update before writing to FIFO to make sure isr sees. */
164		i2c->residue = 0;
165		i2c->cur_trans = NULL;
166	} else {
167		zx2967_i2c_writesb(i2c, buf, REG_DATA, I2C_FIFO_MAX);
168		i2c->residue -= I2C_FIFO_MAX;
169		i2c->cur_trans += I2C_FIFO_MAX;
170	}
171
172	barrier();
173
174	return 0;
175}
176
177static int zx2967_i2c_reset_hardware(struct zx2967_i2c *i2c)
178{
179	u32 val;
180	u32 clk_div;
181
182	val = I2C_MASTER | I2C_IRQ_MSK_ENABLE;
183	zx2967_i2c_writel(i2c, val, REG_CMD);
184
185	clk_div = clk_get_rate(i2c->clk) / i2c->clk_freq - 1;
186	zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_FS);
187	zx2967_i2c_writel(i2c, clk_div, REG_CLK_DIV_HS);
188
189	zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_WRCONF);
190	zx2967_i2c_writel(i2c, I2C_FIFO_MAX - 1, REG_RDCONF);
191	zx2967_i2c_writel(i2c, 1, REG_RDCONF);
192
193	zx2967_i2c_flush_fifos(i2c);
194
195	return 0;
196}
197
198static void zx2967_i2c_isr_clr(struct zx2967_i2c *i2c)
199{
200	u32 status;
201
202	status = zx2967_i2c_readl(i2c, REG_STAT);
203	status |= I2C_IRQ_ACK_CLEAR;
204	zx2967_i2c_writel(i2c, status, REG_STAT);
205}
206
207static irqreturn_t zx2967_i2c_isr(int irq, void *dev_id)
208{
209	u32 status;
210	struct zx2967_i2c *i2c = (struct zx2967_i2c *)dev_id;
211
212	status = zx2967_i2c_readl(i2c, REG_STAT) & I2C_INT_MASK;
213	zx2967_i2c_isr_clr(i2c);
214
215	if (status & I2C_SR_EDEVICE)
216		i2c->error = -ENXIO;
217	else if (status & I2C_SR_EDATA)
218		i2c->error = -EIO;
219	else if (status & I2C_TRANS_DONE)
220		i2c->error = 0;
221	else
222		goto done;
223
224	complete(&i2c->complete);
225done:
226	return IRQ_HANDLED;
227}
228
229static void zx2967_set_addr(struct zx2967_i2c *i2c, u16 addr)
230{
231	u16 val;
232
233	val = (addr >> I2C_ADDR_LOW_SHIFT) & I2C_ADDR_LOW_MASK;
234	zx2967_i2c_writel(i2c, val, REG_DEVADDR_L);
235
236	val = (addr >> I2C_ADDR_HI_SHIFT) & I2C_ADDR_HI_MASK;
237	zx2967_i2c_writel(i2c, val, REG_DEVADDR_H);
238	if (val)
239		val = zx2967_i2c_readl(i2c, REG_CMD) | I2C_ADDR_MODE_TEN;
240	else
241		val = zx2967_i2c_readl(i2c, REG_CMD) & ~I2C_ADDR_MODE_TEN;
242	zx2967_i2c_writel(i2c, val, REG_CMD);
243}
244
245static int zx2967_i2c_xfer_bytes(struct zx2967_i2c *i2c, u32 bytes)
246{
247	unsigned long time_left;
248	int rd = i2c->msg_rd;
249	int ret;
250
251	reinit_completion(&i2c->complete);
252
253	if (rd) {
254		zx2967_i2c_writel(i2c, bytes - 1, REG_RDCONF);
255	} else {
256		ret = zx2967_i2c_fill_tx_fifo(i2c);
257		if (ret)
258			return ret;
259	}
260
261	zx2967_i2c_start_ctrl(i2c);
262
263	time_left = wait_for_completion_timeout(&i2c->complete,
264						I2C_TIMEOUT);
265	if (time_left == 0)
266		return -ETIMEDOUT;
267
268	if (i2c->error)
269		return i2c->error;
270
271	return rd ? zx2967_i2c_empty_rx_fifo(i2c, bytes) : 0;
272}
273
274static int zx2967_i2c_xfer_msg(struct zx2967_i2c *i2c,
275			       struct i2c_msg *msg)
276{
277	int ret;
278	int i;
279
280	zx2967_i2c_flush_fifos(i2c);
281
282	i2c->cur_trans = msg->buf;
283	i2c->residue = msg->len;
284	i2c->access_cnt = msg->len / I2C_FIFO_MAX;
285	i2c->msg_rd = msg->flags & I2C_M_RD;
286
287	for (i = 0; i < i2c->access_cnt; i++) {
288		ret = zx2967_i2c_xfer_bytes(i2c, I2C_FIFO_MAX);
289		if (ret)
290			return ret;
291	}
292
293	if (i2c->residue > 0) {
294		ret = zx2967_i2c_xfer_bytes(i2c, i2c->residue);
295		if (ret)
296			return ret;
297	}
298
299	i2c->residue = 0;
300	i2c->access_cnt = 0;
301
302	return 0;
303}
304
305static int zx2967_i2c_xfer(struct i2c_adapter *adap,
306			   struct i2c_msg *msgs, int num)
307{
308	struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
309	int ret;
310	int i;
311
312	zx2967_set_addr(i2c, msgs->addr);
313
314	for (i = 0; i < num; i++) {
315		ret = zx2967_i2c_xfer_msg(i2c, &msgs[i]);
316		if (ret)
317			return ret;
318	}
319
320	return num;
321}
322
323static void
324zx2967_smbus_xfer_prepare(struct zx2967_i2c *i2c, u16 addr,
325			  char read_write, u8 command, int size,
326			  union i2c_smbus_data *data)
327{
328	u32 val;
329
330	val = zx2967_i2c_readl(i2c, REG_RDCONF);
331	val |= I2C_RFIFO_RESET;
332	zx2967_i2c_writel(i2c, val, REG_RDCONF);
333	zx2967_set_addr(i2c, addr);
334	val = zx2967_i2c_readl(i2c, REG_CMD);
335	val &= ~I2C_RW_READ;
336	zx2967_i2c_writel(i2c, val, REG_CMD);
337
338	switch (size) {
339	case I2C_SMBUS_BYTE:
340		zx2967_i2c_writel(i2c, command, REG_DATA);
341		break;
342	case I2C_SMBUS_BYTE_DATA:
343		zx2967_i2c_writel(i2c, command, REG_DATA);
344		if (read_write == I2C_SMBUS_WRITE)
345			zx2967_i2c_writel(i2c, data->byte, REG_DATA);
346		break;
347	case I2C_SMBUS_WORD_DATA:
348		zx2967_i2c_writel(i2c, command, REG_DATA);
349		if (read_write == I2C_SMBUS_WRITE) {
350			zx2967_i2c_writel(i2c, (data->word >> 8), REG_DATA);
351			zx2967_i2c_writel(i2c, (data->word & 0xff),
352					  REG_DATA);
353		}
354		break;
355	}
356}
357
358static int zx2967_smbus_xfer_read(struct zx2967_i2c *i2c, int size,
359				  union i2c_smbus_data *data)
360{
361	unsigned long time_left;
362	u8 buf[2];
363	u32 val;
364
365	reinit_completion(&i2c->complete);
366
367	val = zx2967_i2c_readl(i2c, REG_CMD);
368	val |= I2C_CMB_RW_EN;
369	zx2967_i2c_writel(i2c, val, REG_CMD);
370
371	val = zx2967_i2c_readl(i2c, REG_CMD);
372	val |= I2C_START;
373	zx2967_i2c_writel(i2c, val, REG_CMD);
374
375	time_left = wait_for_completion_timeout(&i2c->complete,
376						I2C_TIMEOUT);
377	if (time_left == 0)
378		return -ETIMEDOUT;
379
380	if (i2c->error)
381		return i2c->error;
382
383	switch (size) {
384	case I2C_SMBUS_BYTE:
385	case I2C_SMBUS_BYTE_DATA:
386		val = zx2967_i2c_readl(i2c, REG_DATA);
387		data->byte = val;
388		break;
389	case I2C_SMBUS_WORD_DATA:
390	case I2C_SMBUS_PROC_CALL:
391		buf[0] = zx2967_i2c_readl(i2c, REG_DATA);
392		buf[1] = zx2967_i2c_readl(i2c, REG_DATA);
393		data->word = (buf[0] << 8) | buf[1];
394		break;
395	default:
396		return -EOPNOTSUPP;
397	}
398
399	return 0;
400}
401
402static int zx2967_smbus_xfer_write(struct zx2967_i2c *i2c)
403{
404	unsigned long time_left;
405	u32 val;
406
407	reinit_completion(&i2c->complete);
408	val = zx2967_i2c_readl(i2c, REG_CMD);
409	val |= I2C_START;
410	zx2967_i2c_writel(i2c, val, REG_CMD);
411
412	time_left = wait_for_completion_timeout(&i2c->complete,
413						I2C_TIMEOUT);
414	if (time_left == 0)
415		return -ETIMEDOUT;
416
417	if (i2c->error)
418		return i2c->error;
419
420	return 0;
421}
422
423static int zx2967_smbus_xfer(struct i2c_adapter *adap, u16 addr,
424			     unsigned short flags, char read_write,
425			     u8 command, int size, union i2c_smbus_data *data)
426{
427	struct zx2967_i2c *i2c = i2c_get_adapdata(adap);
428
429	if (size == I2C_SMBUS_QUICK)
430		read_write = I2C_SMBUS_WRITE;
431
432	switch (size) {
433	case I2C_SMBUS_QUICK:
434	case I2C_SMBUS_BYTE:
435	case I2C_SMBUS_BYTE_DATA:
436	case I2C_SMBUS_WORD_DATA:
437		zx2967_smbus_xfer_prepare(i2c, addr, read_write,
438					  command, size, data);
439		break;
440	default:
441		return -EOPNOTSUPP;
442	}
443
444	if (read_write == I2C_SMBUS_READ)
445		return zx2967_smbus_xfer_read(i2c, size, data);
446
447	return zx2967_smbus_xfer_write(i2c);
448}
449
450static u32 zx2967_i2c_func(struct i2c_adapter *adap)
451{
452	return I2C_FUNC_I2C |
453	       I2C_FUNC_SMBUS_QUICK |
454	       I2C_FUNC_SMBUS_BYTE |
455	       I2C_FUNC_SMBUS_BYTE_DATA |
456	       I2C_FUNC_SMBUS_WORD_DATA |
457	       I2C_FUNC_SMBUS_BLOCK_DATA |
458	       I2C_FUNC_SMBUS_PROC_CALL |
459	       I2C_FUNC_SMBUS_I2C_BLOCK;
460}
461
462static int __maybe_unused zx2967_i2c_suspend(struct device *dev)
463{
464	struct zx2967_i2c *i2c = dev_get_drvdata(dev);
465
466	i2c_mark_adapter_suspended(&i2c->adap);
467	clk_disable_unprepare(i2c->clk);
468
469	return 0;
470}
471
472static int __maybe_unused zx2967_i2c_resume(struct device *dev)
473{
474	struct zx2967_i2c *i2c = dev_get_drvdata(dev);
475
476	clk_prepare_enable(i2c->clk);
477	i2c_mark_adapter_resumed(&i2c->adap);
478
479	return 0;
480}
481
482static SIMPLE_DEV_PM_OPS(zx2967_i2c_dev_pm_ops,
483			 zx2967_i2c_suspend, zx2967_i2c_resume);
484
485static const struct i2c_algorithm zx2967_i2c_algo = {
486	.master_xfer = zx2967_i2c_xfer,
487	.smbus_xfer = zx2967_smbus_xfer,
488	.functionality = zx2967_i2c_func,
489};
490
491static const struct i2c_adapter_quirks zx2967_i2c_quirks = {
492	.flags = I2C_AQ_NO_ZERO_LEN,
493};
494
495static const struct of_device_id zx2967_i2c_of_match[] = {
496	{ .compatible = "zte,zx296718-i2c", },
497	{ },
498};
499MODULE_DEVICE_TABLE(of, zx2967_i2c_of_match);
500
501static int zx2967_i2c_probe(struct platform_device *pdev)
502{
503	struct zx2967_i2c *i2c;
504	void __iomem *reg_base;
505	struct clk *clk;
506	int ret;
507
508	i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
509	if (!i2c)
510		return -ENOMEM;
511
512	reg_base = devm_platform_ioremap_resource(pdev, 0);
513	if (IS_ERR(reg_base))
514		return PTR_ERR(reg_base);
515
516	clk = devm_clk_get(&pdev->dev, NULL);
517	if (IS_ERR(clk)) {
518		dev_err(&pdev->dev, "missing controller clock");
519		return PTR_ERR(clk);
520	}
521
522	ret = clk_prepare_enable(clk);
523	if (ret) {
524		dev_err(&pdev->dev, "failed to enable i2c_clk\n");
525		return ret;
526	}
527
528	ret = device_property_read_u32(&pdev->dev, "clock-frequency",
529				       &i2c->clk_freq);
530	if (ret) {
531		dev_err(&pdev->dev, "missing clock-frequency");
532		return ret;
533	}
534
535	ret = platform_get_irq(pdev, 0);
536	if (ret < 0)
537		return ret;
538
539	i2c->irq = ret;
540	i2c->reg_base = reg_base;
541	i2c->clk = clk;
542
543	init_completion(&i2c->complete);
544	platform_set_drvdata(pdev, i2c);
545
546	ret = zx2967_i2c_reset_hardware(i2c);
547	if (ret) {
548		dev_err(&pdev->dev, "failed to initialize i2c controller\n");
549		goto err_clk_unprepare;
550	}
551
552	ret = devm_request_irq(&pdev->dev, i2c->irq,
553			zx2967_i2c_isr, 0, dev_name(&pdev->dev), i2c);
554	if (ret) {
555		dev_err(&pdev->dev, "failed to request irq %i\n", i2c->irq);
556		goto err_clk_unprepare;
557	}
558
559	i2c_set_adapdata(&i2c->adap, i2c);
560	strlcpy(i2c->adap.name, "zx2967 i2c adapter",
561		sizeof(i2c->adap.name));
562	i2c->adap.algo = &zx2967_i2c_algo;
563	i2c->adap.quirks = &zx2967_i2c_quirks;
564	i2c->adap.nr = pdev->id;
565	i2c->adap.dev.parent = &pdev->dev;
566	i2c->adap.dev.of_node = pdev->dev.of_node;
567
568	ret = i2c_add_numbered_adapter(&i2c->adap);
569	if (ret)
570		goto err_clk_unprepare;
571
572	return 0;
573
574err_clk_unprepare:
575	clk_disable_unprepare(i2c->clk);
576	return ret;
577}
578
579static int zx2967_i2c_remove(struct platform_device *pdev)
580{
581	struct zx2967_i2c *i2c = platform_get_drvdata(pdev);
582
583	i2c_del_adapter(&i2c->adap);
584	clk_disable_unprepare(i2c->clk);
585
586	return 0;
587}
588
589static struct platform_driver zx2967_i2c_driver = {
590	.probe	= zx2967_i2c_probe,
591	.remove	= zx2967_i2c_remove,
592	.driver	= {
593		.name  = "zx2967_i2c",
594		.of_match_table = zx2967_i2c_of_match,
595		.pm = &zx2967_i2c_dev_pm_ops,
596	},
597};
598module_platform_driver(zx2967_i2c_driver);
599
600MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
601MODULE_DESCRIPTION("ZTE ZX2967 I2C Bus Controller driver");
602MODULE_LICENSE("GPL v2");
603