1/*
2 * Copyright 2011, Netlogic Microsystems Inc.
3 * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
4 *
5 * This file is licensed under the terms of the GNU General Public
6 * License version 2.  This program is licensed "as is" without any
7 * warranty of any kind, whether express or implied.
8 */
9
10#include <linux/err.h>
11#include <linux/kernel.h>
12#include <linux/module.h>
13#include <linux/slab.h>
14#include <linux/ioport.h>
15#include <linux/delay.h>
16#include <linux/errno.h>
17#include <linux/i2c.h>
18#include <linux/io.h>
19#include <linux/platform_device.h>
20#include <linux/of_device.h>
21#include <linux/clk.h>
22#include <linux/interrupt.h>
23#include <linux/wait.h>
24
25/* XLR I2C REGISTERS */
26#define XLR_I2C_CFG		0x00
27#define XLR_I2C_CLKDIV		0x01
28#define XLR_I2C_DEVADDR		0x02
29#define XLR_I2C_ADDR		0x03
30#define XLR_I2C_DATAOUT		0x04
31#define XLR_I2C_DATAIN		0x05
32#define XLR_I2C_STATUS		0x06
33#define XLR_I2C_STARTXFR	0x07
34#define XLR_I2C_BYTECNT		0x08
35#define XLR_I2C_HDSTATIM	0x09
36
37/* Sigma Designs additional registers */
38#define XLR_I2C_INT_EN		0x09
39#define XLR_I2C_INT_STAT	0x0a
40
41/* XLR I2C REGISTERS FLAGS */
42#define XLR_I2C_BUS_BUSY	0x01
43#define XLR_I2C_SDOEMPTY	0x02
44#define XLR_I2C_RXRDY		0x04
45#define XLR_I2C_ACK_ERR		0x08
46#define XLR_I2C_ARB_STARTERR	0x30
47
48/* Register Values */
49#define XLR_I2C_CFG_ADDR	0xF8
50#define XLR_I2C_CFG_NOADDR	0xFA
51#define XLR_I2C_STARTXFR_ND	0x02    /* No Data */
52#define XLR_I2C_STARTXFR_RD	0x01    /* Read */
53#define XLR_I2C_STARTXFR_WR	0x00    /* Write */
54
55#define XLR_I2C_TIMEOUT		10	/* timeout per byte in msec */
56
57/*
58 * On XLR/XLS, we need to use __raw_ IO to read the I2C registers
59 * because they are in the big-endian MMIO area on the SoC.
60 *
61 * The readl/writel implementation on XLR/XLS byteswaps, because
62 * those are for its little-endian PCI space (see arch/mips/Kconfig).
63 */
64static inline void xlr_i2c_wreg(u32 __iomem *base, unsigned int reg, u32 val)
65{
66	__raw_writel(val, base + reg);
67}
68
69static inline u32 xlr_i2c_rdreg(u32 __iomem *base, unsigned int reg)
70{
71	return __raw_readl(base + reg);
72}
73
74#define XLR_I2C_FLAG_IRQ	1
75
76struct xlr_i2c_config {
77	u32 flags;		/* optional feature support */
78	u32 status_busy;	/* value of STATUS[0] when busy */
79	u32 cfg_extra;		/* extra CFG bits to set */
80};
81
82struct xlr_i2c_private {
83	struct i2c_adapter adap;
84	u32 __iomem *iobase;
85	int irq;
86	int pos;
87	struct i2c_msg *msg;
88	const struct xlr_i2c_config *cfg;
89	wait_queue_head_t wait;
90	struct clk *clk;
91};
92
93static int xlr_i2c_busy(struct xlr_i2c_private *priv, u32 status)
94{
95	return (status & XLR_I2C_BUS_BUSY) == priv->cfg->status_busy;
96}
97
98static int xlr_i2c_idle(struct xlr_i2c_private *priv)
99{
100	return !xlr_i2c_busy(priv, xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS));
101}
102
103static int xlr_i2c_wait(struct xlr_i2c_private *priv, unsigned long timeout)
104{
105	int status;
106	int t;
107
108	t = wait_event_timeout(priv->wait, xlr_i2c_idle(priv),
109				msecs_to_jiffies(timeout));
110	if (!t)
111		return -ETIMEDOUT;
112
113	status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
114
115	return status & XLR_I2C_ACK_ERR ? -EIO : 0;
116}
117
118static void xlr_i2c_tx_irq(struct xlr_i2c_private *priv, u32 status)
119{
120	struct i2c_msg *msg = priv->msg;
121
122	if (status & XLR_I2C_SDOEMPTY)
123		xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT,
124				msg->buf[priv->pos++]);
125}
126
127static void xlr_i2c_rx_irq(struct xlr_i2c_private *priv, u32 status)
128{
129	struct i2c_msg *msg = priv->msg;
130
131	if (status & XLR_I2C_RXRDY)
132		msg->buf[priv->pos++] =
133			xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN);
134}
135
136static irqreturn_t xlr_i2c_irq(int irq, void *dev_id)
137{
138	struct xlr_i2c_private *priv = dev_id;
139	struct i2c_msg *msg = priv->msg;
140	u32 int_stat, status;
141
142	int_stat = xlr_i2c_rdreg(priv->iobase, XLR_I2C_INT_STAT);
143	if (!int_stat)
144		return IRQ_NONE;
145
146	xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, int_stat);
147
148	if (!msg)
149		return IRQ_HANDLED;
150
151	status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
152
153	if (priv->pos < msg->len) {
154		if (msg->flags & I2C_M_RD)
155			xlr_i2c_rx_irq(priv, status);
156		else
157			xlr_i2c_tx_irq(priv, status);
158	}
159
160	if (!xlr_i2c_busy(priv, status))
161		wake_up(&priv->wait);
162
163	return IRQ_HANDLED;
164}
165
166static int xlr_i2c_tx(struct xlr_i2c_private *priv,  u16 len,
167	u8 *buf, u16 addr)
168{
169	struct i2c_adapter *adap = &priv->adap;
170	unsigned long timeout, stoptime, checktime;
171	u32 i2c_status;
172	int pos, timedout;
173	u8 offset;
174	u32 xfer;
175
176	offset = buf[0];
177	xlr_i2c_wreg(priv->iobase, XLR_I2C_ADDR, offset);
178	xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
179	xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG,
180			XLR_I2C_CFG_ADDR | priv->cfg->cfg_extra);
181
182	timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
183	stoptime = jiffies + timeout;
184	timedout = 0;
185
186	if (len == 1) {
187		xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1);
188		xfer = XLR_I2C_STARTXFR_ND;
189		pos = 1;
190	} else {
191		xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 2);
192		xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[1]);
193		xfer = XLR_I2C_STARTXFR_WR;
194		pos = 2;
195	}
196
197	priv->pos = pos;
198
199retry:
200	/* retry can only happen on the first byte */
201	xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, xfer);
202
203	if (priv->irq > 0)
204		return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len);
205
206	while (!timedout) {
207		checktime = jiffies;
208		i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
209
210		if ((i2c_status & XLR_I2C_SDOEMPTY) && pos < len) {
211			xlr_i2c_wreg(priv->iobase, XLR_I2C_DATAOUT, buf[pos++]);
212
213			/* reset timeout on successful xmit */
214			stoptime = jiffies + timeout;
215		}
216		timedout = time_after(checktime, stoptime);
217
218		if (i2c_status & XLR_I2C_ARB_STARTERR) {
219			if (timedout)
220				break;
221			goto retry;
222		}
223
224		if (i2c_status & XLR_I2C_ACK_ERR)
225			return -EIO;
226
227		if (!xlr_i2c_busy(priv, i2c_status) && pos >= len)
228			return 0;
229	}
230	dev_err(&adap->dev, "I2C transmit timeout\n");
231	return -ETIMEDOUT;
232}
233
234static int xlr_i2c_rx(struct xlr_i2c_private *priv, u16 len, u8 *buf, u16 addr)
235{
236	struct i2c_adapter *adap = &priv->adap;
237	u32 i2c_status;
238	unsigned long timeout, stoptime, checktime;
239	int nbytes, timedout;
240
241	xlr_i2c_wreg(priv->iobase, XLR_I2C_CFG,
242			XLR_I2C_CFG_NOADDR | priv->cfg->cfg_extra);
243	xlr_i2c_wreg(priv->iobase, XLR_I2C_BYTECNT, len - 1);
244	xlr_i2c_wreg(priv->iobase, XLR_I2C_DEVADDR, addr);
245
246	priv->pos = 0;
247
248	timeout = msecs_to_jiffies(XLR_I2C_TIMEOUT);
249	stoptime = jiffies + timeout;
250	timedout = 0;
251	nbytes = 0;
252retry:
253	xlr_i2c_wreg(priv->iobase, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD);
254
255	if (priv->irq > 0)
256		return xlr_i2c_wait(priv, XLR_I2C_TIMEOUT * len);
257
258	while (!timedout) {
259		checktime = jiffies;
260		i2c_status = xlr_i2c_rdreg(priv->iobase, XLR_I2C_STATUS);
261		if (i2c_status & XLR_I2C_RXRDY) {
262			if (nbytes >= len)
263				return -EIO;	/* should not happen */
264
265			buf[nbytes++] =
266				xlr_i2c_rdreg(priv->iobase, XLR_I2C_DATAIN);
267
268			/* reset timeout on successful read */
269			stoptime = jiffies + timeout;
270		}
271
272		timedout = time_after(checktime, stoptime);
273		if (i2c_status & XLR_I2C_ARB_STARTERR) {
274			if (timedout)
275				break;
276			goto retry;
277		}
278
279		if (i2c_status & XLR_I2C_ACK_ERR)
280			return -EIO;
281
282		if (!xlr_i2c_busy(priv, i2c_status))
283			return 0;
284	}
285
286	dev_err(&adap->dev, "I2C receive timeout\n");
287	return -ETIMEDOUT;
288}
289
290static int xlr_i2c_xfer(struct i2c_adapter *adap,
291	struct i2c_msg *msgs, int num)
292{
293	struct i2c_msg *msg;
294	int i;
295	int ret = 0;
296	struct xlr_i2c_private *priv = i2c_get_adapdata(adap);
297
298	ret = clk_enable(priv->clk);
299	if (ret)
300		return ret;
301
302	if (priv->irq)
303		xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0xf);
304
305
306	for (i = 0; ret == 0 && i < num; i++) {
307		msg = &msgs[i];
308		priv->msg = msg;
309		if (msg->flags & I2C_M_RD)
310			ret = xlr_i2c_rx(priv, msg->len, &msg->buf[0],
311					msg->addr);
312		else
313			ret = xlr_i2c_tx(priv, msg->len, &msg->buf[0],
314					msg->addr);
315	}
316
317	if (priv->irq)
318		xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0);
319
320	clk_disable(priv->clk);
321	priv->msg = NULL;
322
323	return (ret != 0) ? ret : num;
324}
325
326static u32 xlr_func(struct i2c_adapter *adap)
327{
328	/* Emulate SMBUS over I2C */
329	return (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) | I2C_FUNC_I2C;
330}
331
332static const struct i2c_algorithm xlr_i2c_algo = {
333	.master_xfer	= xlr_i2c_xfer,
334	.functionality	= xlr_func,
335};
336
337static const struct i2c_adapter_quirks xlr_i2c_quirks = {
338	.flags = I2C_AQ_NO_ZERO_LEN,
339};
340
341static const struct xlr_i2c_config xlr_i2c_config_default = {
342	.status_busy	= XLR_I2C_BUS_BUSY,
343	.cfg_extra	= 0,
344};
345
346static const struct xlr_i2c_config xlr_i2c_config_tangox = {
347	.flags		= XLR_I2C_FLAG_IRQ,
348	.status_busy	= 0,
349	.cfg_extra	= 1 << 8,
350};
351
352static const struct of_device_id xlr_i2c_dt_ids[] = {
353	{
354		.compatible	= "sigma,smp8642-i2c",
355		.data		= &xlr_i2c_config_tangox,
356	},
357	{ }
358};
359MODULE_DEVICE_TABLE(of, xlr_i2c_dt_ids);
360
361static int xlr_i2c_probe(struct platform_device *pdev)
362{
363	const struct of_device_id *match;
364	struct xlr_i2c_private  *priv;
365	struct clk *clk;
366	unsigned long clk_rate;
367	unsigned long clk_div;
368	u32 busfreq;
369	int irq;
370	int ret;
371
372	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
373	if (!priv)
374		return -ENOMEM;
375
376	match = of_match_device(xlr_i2c_dt_ids, &pdev->dev);
377	if (match)
378		priv->cfg = match->data;
379	else
380		priv->cfg = &xlr_i2c_config_default;
381
382	priv->iobase = devm_platform_ioremap_resource(pdev, 0);
383	if (IS_ERR(priv->iobase))
384		return PTR_ERR(priv->iobase);
385
386	irq = platform_get_irq(pdev, 0);
387
388	if (irq > 0 && (priv->cfg->flags & XLR_I2C_FLAG_IRQ)) {
389		priv->irq = irq;
390
391		xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_EN, 0);
392		xlr_i2c_wreg(priv->iobase, XLR_I2C_INT_STAT, 0xf);
393
394		ret = devm_request_irq(&pdev->dev, priv->irq, xlr_i2c_irq,
395					IRQF_SHARED, dev_name(&pdev->dev),
396					priv);
397		if (ret)
398			return ret;
399
400		init_waitqueue_head(&priv->wait);
401	}
402
403	if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
404				 &busfreq))
405		busfreq = I2C_MAX_STANDARD_MODE_FREQ;
406
407	clk = devm_clk_get(&pdev->dev, NULL);
408	if (!IS_ERR(clk)) {
409		ret = clk_prepare_enable(clk);
410		if (ret)
411			return ret;
412
413		clk_rate = clk_get_rate(clk);
414		clk_div = DIV_ROUND_UP(clk_rate, 2 * busfreq);
415		xlr_i2c_wreg(priv->iobase, XLR_I2C_CLKDIV, clk_div);
416
417		clk_disable(clk);
418		priv->clk = clk;
419	}
420
421	priv->adap.dev.parent = &pdev->dev;
422	priv->adap.dev.of_node	= pdev->dev.of_node;
423	priv->adap.owner	= THIS_MODULE;
424	priv->adap.algo_data	= priv;
425	priv->adap.algo		= &xlr_i2c_algo;
426	priv->adap.quirks	= &xlr_i2c_quirks;
427	priv->adap.nr		= pdev->id;
428	priv->adap.class	= I2C_CLASS_HWMON;
429	snprintf(priv->adap.name, sizeof(priv->adap.name), "xlr-i2c");
430
431	i2c_set_adapdata(&priv->adap, priv);
432	ret = i2c_add_numbered_adapter(&priv->adap);
433	if (ret < 0)
434		goto err_unprepare_clk;
435
436	platform_set_drvdata(pdev, priv);
437	dev_info(&priv->adap.dev, "Added I2C Bus.\n");
438	return 0;
439
440err_unprepare_clk:
441	clk_unprepare(clk);
442	return ret;
443}
444
445static int xlr_i2c_remove(struct platform_device *pdev)
446{
447	struct xlr_i2c_private *priv;
448
449	priv = platform_get_drvdata(pdev);
450	i2c_del_adapter(&priv->adap);
451	clk_unprepare(priv->clk);
452
453	return 0;
454}
455
456static struct platform_driver xlr_i2c_driver = {
457	.probe  = xlr_i2c_probe,
458	.remove = xlr_i2c_remove,
459	.driver = {
460		.name   = "xlr-i2cbus",
461		.of_match_table	= xlr_i2c_dt_ids,
462	},
463};
464
465module_platform_driver(xlr_i2c_driver);
466
467MODULE_AUTHOR("Ganesan Ramalingam <ganesanr@netlogicmicro.com>");
468MODULE_DESCRIPTION("XLR/XLS SoC I2C Controller driver");
469MODULE_LICENSE("GPL v2");
470MODULE_ALIAS("platform:xlr-i2cbus");
471