1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * i2c-xiic.c 4 * Copyright (c) 2002-2007 Xilinx Inc. 5 * Copyright (c) 2009-2010 Intel Corporation 6 * 7 * This code was implemented by Mocean Laboratories AB when porting linux 8 * to the automotive development board Russellville. The copyright holder 9 * as seen in the header is Intel corporation. 10 * Mocean Laboratories forked off the GNU/Linux platform work into a 11 * separate company called Pelagicore AB, which committed the code to the 12 * kernel. 13 */ 14 15/* Supports: 16 * Xilinx IIC 17 */ 18#include <linux/kernel.h> 19#include <linux/module.h> 20#include <linux/errno.h> 21#include <linux/err.h> 22#include <linux/delay.h> 23#include <linux/platform_device.h> 24#include <linux/i2c.h> 25#include <linux/interrupt.h> 26#include <linux/wait.h> 27#include <linux/platform_data/i2c-xiic.h> 28#include <linux/io.h> 29#include <linux/slab.h> 30#include <linux/of.h> 31#include <linux/clk.h> 32#include <linux/pm_runtime.h> 33 34#define DRIVER_NAME "xiic-i2c" 35 36enum xilinx_i2c_state { 37 STATE_DONE, 38 STATE_ERROR, 39 STATE_START 40}; 41 42enum xiic_endian { 43 LITTLE, 44 BIG 45}; 46 47/** 48 * struct xiic_i2c - Internal representation of the XIIC I2C bus 49 * @dev: Pointer to device structure 50 * @base: Memory base of the HW registers 51 * @wait: Wait queue for callers 52 * @adap: Kernel adapter representation 53 * @tx_msg: Messages from above to be sent 54 * @lock: Mutual exclusion 55 * @tx_pos: Current pos in TX message 56 * @nmsgs: Number of messages in tx_msg 57 * @rx_msg: Current RX message 58 * @rx_pos: Position within current RX message 59 * @endianness: big/little-endian byte order 60 * @clk: Pointer to AXI4-lite input clock 61 * @state: See STATE_ 62 * @singlemaster: Indicates bus is single master 63 */ 64struct xiic_i2c { 65 struct device *dev; 66 void __iomem *base; 67 wait_queue_head_t wait; 68 struct i2c_adapter adap; 69 struct i2c_msg *tx_msg; 70 struct mutex lock; 71 unsigned int tx_pos; 72 unsigned int nmsgs; 73 struct i2c_msg *rx_msg; 74 int rx_pos; 75 enum xiic_endian endianness; 76 struct clk *clk; 77 enum xilinx_i2c_state state; 78 bool singlemaster; 79}; 80 81 82#define XIIC_MSB_OFFSET 0 83#define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 84 85/* 86 * Register offsets in bytes from RegisterBase. Three is added to the 87 * base offset to access LSB (IBM style) of the word 88 */ 89#define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 90#define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 91#define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 92#define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 93#define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 94#define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 95#define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 96#define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 97#define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 98#define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 99 100/* Control Register masks */ 101#define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 102#define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 103#define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 104#define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 105#define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 106#define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 107#define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 108 109/* Status Register masks */ 110#define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 111#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 112#define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 113#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 114#define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 115#define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 116#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 117#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 118 119/* Interrupt Status Register masks Interrupt occurs when... */ 120#define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 121#define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 122#define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 123#define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 124#define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 125#define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 126#define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 127#define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 128 129/* The following constants specify the depth of the FIFOs */ 130#define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 131#define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 132 133/* The following constants specify groups of interrupts that are typically 134 * enabled or disables at the same time 135 */ 136#define XIIC_TX_INTERRUPTS \ 137(XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 138 139#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 140 141/* 142 * Tx Fifo upper bit masks. 143 */ 144#define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 145#define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 146 147/* 148 * The following constants define the register offsets for the Interrupt 149 * registers. There are some holes in the memory map for reserved addresses 150 * to allow other registers to be added and still match the memory map of the 151 * interrupt controller registers 152 */ 153#define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 154#define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 155#define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 156#define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 157 158#define XIIC_RESET_MASK 0xAUL 159 160#define XIIC_PM_TIMEOUT 1000 /* ms */ 161/* timeout waiting for the controller to respond */ 162#define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 163/* 164 * The following constant is used for the device global interrupt enable 165 * register, to enable all interrupts for the device, this is the only bit 166 * in the register 167 */ 168#define XIIC_GINTR_ENABLE_MASK 0x80000000UL 169 170#define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 171#define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 172 173static int xiic_start_xfer(struct xiic_i2c *i2c); 174static void __xiic_start_xfer(struct xiic_i2c *i2c); 175 176/* 177 * For the register read and write functions, a little-endian and big-endian 178 * version are necessary. Endianness is detected during the probe function. 179 * Only the least significant byte [doublet] of the register are ever 180 * accessed. This requires an offset of 3 [2] from the base address for 181 * big-endian systems. 182 */ 183 184static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 185{ 186 if (i2c->endianness == LITTLE) 187 iowrite8(value, i2c->base + reg); 188 else 189 iowrite8(value, i2c->base + reg + 3); 190} 191 192static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 193{ 194 u8 ret; 195 196 if (i2c->endianness == LITTLE) 197 ret = ioread8(i2c->base + reg); 198 else 199 ret = ioread8(i2c->base + reg + 3); 200 return ret; 201} 202 203static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 204{ 205 if (i2c->endianness == LITTLE) 206 iowrite16(value, i2c->base + reg); 207 else 208 iowrite16be(value, i2c->base + reg + 2); 209} 210 211static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 212{ 213 if (i2c->endianness == LITTLE) 214 iowrite32(value, i2c->base + reg); 215 else 216 iowrite32be(value, i2c->base + reg); 217} 218 219static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 220{ 221 u32 ret; 222 223 if (i2c->endianness == LITTLE) 224 ret = ioread32(i2c->base + reg); 225 else 226 ret = ioread32be(i2c->base + reg); 227 return ret; 228} 229 230static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 231{ 232 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 233 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 234} 235 236static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 237{ 238 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 239 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 240} 241 242static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 243{ 244 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 245 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 246} 247 248static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 249{ 250 xiic_irq_clr(i2c, mask); 251 xiic_irq_en(i2c, mask); 252} 253 254static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 255{ 256 u8 sr; 257 unsigned long timeout; 258 259 timeout = jiffies + XIIC_I2C_TIMEOUT; 260 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 261 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 262 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 263 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 264 if (time_after(jiffies, timeout)) { 265 dev_err(i2c->dev, "Failed to clear rx fifo\n"); 266 return -ETIMEDOUT; 267 } 268 } 269 270 return 0; 271} 272 273static int xiic_reinit(struct xiic_i2c *i2c) 274{ 275 int ret; 276 277 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 278 279 /* Set receive Fifo depth to maximum (zero based). */ 280 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 281 282 /* Reset Tx Fifo. */ 283 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 284 285 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 286 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 287 288 /* make sure RX fifo is empty */ 289 ret = xiic_clear_rx_fifo(i2c); 290 if (ret) 291 return ret; 292 293 /* Enable interrupts */ 294 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 295 296 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 297 298 return 0; 299} 300 301static void xiic_deinit(struct xiic_i2c *i2c) 302{ 303 u8 cr; 304 305 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 306 307 /* Disable IIC Device. */ 308 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 309 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 310} 311 312static void xiic_read_rx(struct xiic_i2c *i2c) 313{ 314 u8 bytes_in_fifo; 315 int i; 316 317 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 318 319 dev_dbg(i2c->adap.dev.parent, 320 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 321 __func__, bytes_in_fifo, xiic_rx_space(i2c), 322 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 323 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 324 325 if (bytes_in_fifo > xiic_rx_space(i2c)) 326 bytes_in_fifo = xiic_rx_space(i2c); 327 328 for (i = 0; i < bytes_in_fifo; i++) 329 i2c->rx_msg->buf[i2c->rx_pos++] = 330 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 331 332 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 333 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 334 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 335} 336 337static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 338{ 339 /* return the actual space left in the FIFO */ 340 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 341} 342 343static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 344{ 345 u8 fifo_space = xiic_tx_fifo_space(i2c); 346 int len = xiic_tx_space(i2c); 347 348 len = (len > fifo_space) ? fifo_space : len; 349 350 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 351 __func__, len, fifo_space); 352 353 while (len--) { 354 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 355 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 356 /* last message in transfer -> STOP */ 357 data |= XIIC_TX_DYN_STOP_MASK; 358 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 359 } 360 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 361 } 362} 363 364static void xiic_wakeup(struct xiic_i2c *i2c, int code) 365{ 366 i2c->tx_msg = NULL; 367 i2c->rx_msg = NULL; 368 i2c->nmsgs = 0; 369 i2c->state = code; 370 wake_up(&i2c->wait); 371} 372 373static irqreturn_t xiic_process(int irq, void *dev_id) 374{ 375 struct xiic_i2c *i2c = dev_id; 376 u32 pend, isr, ier; 377 u32 clr = 0; 378 int xfer_more = 0; 379 int wakeup_req = 0; 380 int wakeup_code = 0; 381 382 /* Get the interrupt Status from the IPIF. There is no clearing of 383 * interrupts in the IPIF. Interrupts must be cleared at the source. 384 * To find which interrupts are pending; AND interrupts pending with 385 * interrupts masked. 386 */ 387 mutex_lock(&i2c->lock); 388 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 389 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 390 pend = isr & ier; 391 392 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 393 __func__, ier, isr, pend); 394 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 395 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 396 i2c->tx_msg, i2c->nmsgs); 397 398 399 /* Service requesting interrupt */ 400 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 401 ((pend & XIIC_INTR_TX_ERROR_MASK) && 402 !(pend & XIIC_INTR_RX_FULL_MASK))) { 403 /* bus arbritration lost, or... 404 * Transmit error _OR_ RX completed 405 * if this happens when RX_FULL is not set 406 * this is probably a TX error 407 */ 408 409 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 410 411 /* dynamic mode seem to suffer from problems if we just flushes 412 * fifos and the next message is a TX with len 0 (only addr) 413 * reset the IP instead of just flush fifos 414 */ 415 xiic_reinit(i2c); 416 417 if (i2c->rx_msg) { 418 wakeup_req = 1; 419 wakeup_code = STATE_ERROR; 420 } 421 if (i2c->tx_msg) { 422 wakeup_req = 1; 423 wakeup_code = STATE_ERROR; 424 } 425 /* don't try to handle other events */ 426 goto out; 427 } 428 if (pend & XIIC_INTR_RX_FULL_MASK) { 429 /* Receive register/FIFO is full */ 430 431 clr |= XIIC_INTR_RX_FULL_MASK; 432 if (!i2c->rx_msg) { 433 dev_dbg(i2c->adap.dev.parent, 434 "%s unexpected RX IRQ\n", __func__); 435 xiic_clear_rx_fifo(i2c); 436 goto out; 437 } 438 439 xiic_read_rx(i2c); 440 if (xiic_rx_space(i2c) == 0) { 441 /* this is the last part of the message */ 442 i2c->rx_msg = NULL; 443 444 /* also clear TX error if there (RX complete) */ 445 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 446 447 dev_dbg(i2c->adap.dev.parent, 448 "%s end of message, nmsgs: %d\n", 449 __func__, i2c->nmsgs); 450 451 /* send next message if this wasn't the last, 452 * otherwise the transfer will be finialise when 453 * receiving the bus not busy interrupt 454 */ 455 if (i2c->nmsgs > 1) { 456 i2c->nmsgs--; 457 i2c->tx_msg++; 458 dev_dbg(i2c->adap.dev.parent, 459 "%s will start next...\n", __func__); 460 xfer_more = 1; 461 } 462 } 463 } 464 if (pend & XIIC_INTR_BNB_MASK) { 465 /* IIC bus has transitioned to not busy */ 466 clr |= XIIC_INTR_BNB_MASK; 467 468 /* The bus is not busy, disable BusNotBusy interrupt */ 469 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 470 471 if (!i2c->tx_msg) 472 goto out; 473 474 wakeup_req = 1; 475 476 if (i2c->nmsgs == 1 && !i2c->rx_msg && 477 xiic_tx_space(i2c) == 0) 478 wakeup_code = STATE_DONE; 479 else 480 wakeup_code = STATE_ERROR; 481 } 482 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 483 /* Transmit register/FIFO is empty or ½ empty */ 484 485 clr |= (pend & 486 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 487 488 if (!i2c->tx_msg) { 489 dev_dbg(i2c->adap.dev.parent, 490 "%s unexpected TX IRQ\n", __func__); 491 goto out; 492 } 493 494 xiic_fill_tx_fifo(i2c); 495 496 /* current message sent and there is space in the fifo */ 497 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 498 dev_dbg(i2c->adap.dev.parent, 499 "%s end of message sent, nmsgs: %d\n", 500 __func__, i2c->nmsgs); 501 if (i2c->nmsgs > 1) { 502 i2c->nmsgs--; 503 i2c->tx_msg++; 504 xfer_more = 1; 505 } else { 506 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 507 508 dev_dbg(i2c->adap.dev.parent, 509 "%s Got TX IRQ but no more to do...\n", 510 __func__); 511 } 512 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 513 /* current frame is sent and is last, 514 * make sure to disable tx half 515 */ 516 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 517 } 518out: 519 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 520 521 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 522 if (xfer_more) 523 __xiic_start_xfer(i2c); 524 if (wakeup_req) 525 xiic_wakeup(i2c, wakeup_code); 526 527 WARN_ON(xfer_more && wakeup_req); 528 529 mutex_unlock(&i2c->lock); 530 return IRQ_HANDLED; 531} 532 533static int xiic_bus_busy(struct xiic_i2c *i2c) 534{ 535 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 536 537 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 538} 539 540static int xiic_busy(struct xiic_i2c *i2c) 541{ 542 int tries = 3; 543 int err; 544 545 if (i2c->tx_msg) 546 return -EBUSY; 547 548 /* In single master mode bus can only be busy, when in use by this 549 * driver. If the register indicates bus being busy for some reason we 550 * should ignore it, since bus will never be released and i2c will be 551 * stuck forever. 552 */ 553 if (i2c->singlemaster) { 554 return 0; 555 } 556 557 /* for instance if previous transfer was terminated due to TX error 558 * it might be that the bus is on it's way to become available 559 * give it at most 3 ms to wake 560 */ 561 err = xiic_bus_busy(i2c); 562 while (err && tries--) { 563 msleep(1); 564 err = xiic_bus_busy(i2c); 565 } 566 567 return err; 568} 569 570static void xiic_start_recv(struct xiic_i2c *i2c) 571{ 572 u8 rx_watermark; 573 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 574 unsigned long flags; 575 576 /* Clear and enable Rx full interrupt. */ 577 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 578 579 /* we want to get all but last byte, because the TX_ERROR IRQ is used 580 * to inidicate error ACK on the address, and negative ack on the last 581 * received byte, so to not mix them receive all but last. 582 * In the case where there is only one byte to receive 583 * we can check if ERROR and RX full is set at the same time 584 */ 585 rx_watermark = msg->len; 586 if (rx_watermark > IIC_RX_FIFO_DEPTH) 587 rx_watermark = IIC_RX_FIFO_DEPTH; 588 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 589 590 local_irq_save(flags); 591 if (!(msg->flags & I2C_M_NOSTART)) 592 /* write the address */ 593 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 594 i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); 595 596 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 597 598 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 599 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 600 local_irq_restore(flags); 601 602 if (i2c->nmsgs == 1) 603 /* very last, enable bus not busy as well */ 604 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 605 606 /* the message is tx:ed */ 607 i2c->tx_pos = msg->len; 608} 609 610static void xiic_start_send(struct xiic_i2c *i2c) 611{ 612 struct i2c_msg *msg = i2c->tx_msg; 613 614 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 615 616 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 617 __func__, msg, msg->len); 618 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 619 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 620 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 621 622 if (!(msg->flags & I2C_M_NOSTART)) { 623 /* write the address */ 624 u16 data = i2c_8bit_addr_from_msg(msg) | 625 XIIC_TX_DYN_START_MASK; 626 if ((i2c->nmsgs == 1) && msg->len == 0) 627 /* no data and last message -> add STOP */ 628 data |= XIIC_TX_DYN_STOP_MASK; 629 630 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 631 } 632 633 xiic_fill_tx_fifo(i2c); 634 635 /* Clear any pending Tx empty, Tx Error and then enable them. */ 636 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 637 XIIC_INTR_BNB_MASK); 638} 639 640static irqreturn_t xiic_isr(int irq, void *dev_id) 641{ 642 struct xiic_i2c *i2c = dev_id; 643 u32 pend, isr, ier; 644 irqreturn_t ret = IRQ_NONE; 645 /* Do not processes a devices interrupts if the device has no 646 * interrupts pending 647 */ 648 649 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 650 651 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 652 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 653 pend = isr & ier; 654 if (pend) 655 ret = IRQ_WAKE_THREAD; 656 657 return ret; 658} 659 660static void __xiic_start_xfer(struct xiic_i2c *i2c) 661{ 662 int first = 1; 663 int fifo_space = xiic_tx_fifo_space(i2c); 664 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 665 __func__, i2c->tx_msg, fifo_space); 666 667 if (!i2c->tx_msg) 668 return; 669 670 i2c->rx_pos = 0; 671 i2c->tx_pos = 0; 672 i2c->state = STATE_START; 673 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 674 if (!first) { 675 i2c->nmsgs--; 676 i2c->tx_msg++; 677 i2c->tx_pos = 0; 678 } else 679 first = 0; 680 681 if (i2c->tx_msg->flags & I2C_M_RD) { 682 /* we dont date putting several reads in the FIFO */ 683 xiic_start_recv(i2c); 684 return; 685 } else { 686 xiic_start_send(i2c); 687 if (xiic_tx_space(i2c) != 0) { 688 /* the message could not be completely sent */ 689 break; 690 } 691 } 692 693 fifo_space = xiic_tx_fifo_space(i2c); 694 } 695 696 /* there are more messages or the current one could not be completely 697 * put into the FIFO, also enable the half empty interrupt 698 */ 699 if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 700 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 701 702} 703 704static int xiic_start_xfer(struct xiic_i2c *i2c) 705{ 706 int ret; 707 mutex_lock(&i2c->lock); 708 709 ret = xiic_reinit(i2c); 710 if (!ret) 711 __xiic_start_xfer(i2c); 712 713 mutex_unlock(&i2c->lock); 714 715 return ret; 716} 717 718static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 719{ 720 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 721 int err; 722 723 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 724 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 725 726 err = pm_runtime_resume_and_get(i2c->dev); 727 if (err < 0) 728 return err; 729 730 err = xiic_busy(i2c); 731 if (err) 732 goto out; 733 734 i2c->tx_msg = msgs; 735 i2c->nmsgs = num; 736 737 err = xiic_start_xfer(i2c); 738 if (err < 0) { 739 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 740 goto out; 741 } 742 743 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 744 (i2c->state == STATE_DONE), HZ)) { 745 err = (i2c->state == STATE_DONE) ? num : -EIO; 746 goto out; 747 } else { 748 i2c->tx_msg = NULL; 749 i2c->rx_msg = NULL; 750 i2c->nmsgs = 0; 751 err = -ETIMEDOUT; 752 goto out; 753 } 754out: 755 pm_runtime_mark_last_busy(i2c->dev); 756 pm_runtime_put_autosuspend(i2c->dev); 757 return err; 758} 759 760static u32 xiic_func(struct i2c_adapter *adap) 761{ 762 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 763} 764 765static const struct i2c_algorithm xiic_algorithm = { 766 .master_xfer = xiic_xfer, 767 .functionality = xiic_func, 768}; 769 770static const struct i2c_adapter_quirks xiic_quirks = { 771 .max_read_len = 255, 772}; 773 774static const struct i2c_adapter xiic_adapter = { 775 .owner = THIS_MODULE, 776 .class = I2C_CLASS_DEPRECATED, 777 .algo = &xiic_algorithm, 778 .quirks = &xiic_quirks, 779}; 780 781 782static int xiic_i2c_probe(struct platform_device *pdev) 783{ 784 struct xiic_i2c *i2c; 785 struct xiic_i2c_platform_data *pdata; 786 struct resource *res; 787 int ret, irq; 788 u8 i; 789 u32 sr; 790 791 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 792 if (!i2c) 793 return -ENOMEM; 794 795 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 796 i2c->base = devm_ioremap_resource(&pdev->dev, res); 797 if (IS_ERR(i2c->base)) 798 return PTR_ERR(i2c->base); 799 800 irq = platform_get_irq(pdev, 0); 801 if (irq < 0) 802 return irq; 803 804 pdata = dev_get_platdata(&pdev->dev); 805 806 /* hook up driver to tree */ 807 platform_set_drvdata(pdev, i2c); 808 i2c->adap = xiic_adapter; 809 i2c_set_adapdata(&i2c->adap, i2c); 810 i2c->adap.dev.parent = &pdev->dev; 811 i2c->adap.dev.of_node = pdev->dev.of_node; 812 snprintf(i2c->adap.name, sizeof(i2c->adap.name), 813 DRIVER_NAME " %s", pdev->name); 814 815 mutex_init(&i2c->lock); 816 init_waitqueue_head(&i2c->wait); 817 818 i2c->clk = devm_clk_get(&pdev->dev, NULL); 819 if (IS_ERR(i2c->clk)) { 820 if (PTR_ERR(i2c->clk) != -EPROBE_DEFER) 821 dev_err(&pdev->dev, "input clock not found.\n"); 822 return PTR_ERR(i2c->clk); 823 } 824 ret = clk_prepare_enable(i2c->clk); 825 if (ret) { 826 dev_err(&pdev->dev, "Unable to enable clock.\n"); 827 return ret; 828 } 829 i2c->dev = &pdev->dev; 830 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 831 pm_runtime_use_autosuspend(i2c->dev); 832 pm_runtime_set_active(i2c->dev); 833 pm_runtime_enable(i2c->dev); 834 ret = devm_request_threaded_irq(&pdev->dev, irq, xiic_isr, 835 xiic_process, IRQF_ONESHOT, 836 pdev->name, i2c); 837 838 if (ret < 0) { 839 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 840 goto err_clk_dis; 841 } 842 843 i2c->singlemaster = 844 of_property_read_bool(pdev->dev.of_node, "single-master"); 845 846 /* 847 * Detect endianness 848 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 849 * set, assume that the endianness was wrong and swap. 850 */ 851 i2c->endianness = LITTLE; 852 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 853 /* Reset is cleared in xiic_reinit */ 854 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 855 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 856 i2c->endianness = BIG; 857 858 ret = xiic_reinit(i2c); 859 if (ret < 0) { 860 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 861 goto err_clk_dis; 862 } 863 864 /* add i2c adapter to i2c tree */ 865 ret = i2c_add_adapter(&i2c->adap); 866 if (ret) { 867 xiic_deinit(i2c); 868 goto err_clk_dis; 869 } 870 871 if (pdata) { 872 /* add in known devices to the bus */ 873 for (i = 0; i < pdata->num_devices; i++) 874 i2c_new_client_device(&i2c->adap, pdata->devices + i); 875 } 876 877 return 0; 878 879err_clk_dis: 880 pm_runtime_set_suspended(&pdev->dev); 881 pm_runtime_disable(&pdev->dev); 882 clk_disable_unprepare(i2c->clk); 883 return ret; 884} 885 886static int xiic_i2c_remove(struct platform_device *pdev) 887{ 888 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 889 int ret; 890 891 /* remove adapter & data */ 892 i2c_del_adapter(&i2c->adap); 893 894 ret = pm_runtime_resume_and_get(i2c->dev); 895 if (ret < 0) 896 return ret; 897 898 xiic_deinit(i2c); 899 pm_runtime_put_sync(i2c->dev); 900 clk_disable_unprepare(i2c->clk); 901 pm_runtime_disable(&pdev->dev); 902 pm_runtime_set_suspended(&pdev->dev); 903 pm_runtime_dont_use_autosuspend(&pdev->dev); 904 905 return 0; 906} 907 908#if defined(CONFIG_OF) 909static const struct of_device_id xiic_of_match[] = { 910 { .compatible = "xlnx,xps-iic-2.00.a", }, 911 {}, 912}; 913MODULE_DEVICE_TABLE(of, xiic_of_match); 914#endif 915 916static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 917{ 918 struct xiic_i2c *i2c = dev_get_drvdata(dev); 919 920 clk_disable(i2c->clk); 921 922 return 0; 923} 924 925static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 926{ 927 struct xiic_i2c *i2c = dev_get_drvdata(dev); 928 int ret; 929 930 ret = clk_enable(i2c->clk); 931 if (ret) { 932 dev_err(dev, "Cannot enable clock.\n"); 933 return ret; 934 } 935 936 return 0; 937} 938 939static const struct dev_pm_ops xiic_dev_pm_ops = { 940 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 941 xiic_i2c_runtime_resume, NULL) 942}; 943static struct platform_driver xiic_i2c_driver = { 944 .probe = xiic_i2c_probe, 945 .remove = xiic_i2c_remove, 946 .driver = { 947 .name = DRIVER_NAME, 948 .of_match_table = of_match_ptr(xiic_of_match), 949 .pm = &xiic_dev_pm_ops, 950 }, 951}; 952 953module_platform_driver(xiic_i2c_driver); 954 955MODULE_ALIAS("platform:" DRIVER_NAME); 956MODULE_AUTHOR("info@mocean-labs.com"); 957MODULE_DESCRIPTION("Xilinx I2C bus driver"); 958MODULE_LICENSE("GPL v2"); 959MODULE_ALIAS("platform:"DRIVER_NAME); 960