1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. 3 4#include <linux/acpi.h> 5#include <linux/clk.h> 6#include <linux/dma-mapping.h> 7#include <linux/err.h> 8#include <linux/i2c.h> 9#include <linux/interrupt.h> 10#include <linux/io.h> 11#include <linux/module.h> 12#include <linux/of.h> 13#include <linux/platform_device.h> 14#include <linux/pm_runtime.h> 15#include <linux/qcom-geni-se.h> 16#include <linux/spinlock.h> 17 18#define SE_I2C_TX_TRANS_LEN 0x26c 19#define SE_I2C_RX_TRANS_LEN 0x270 20#define SE_I2C_SCL_COUNTERS 0x278 21 22#define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\ 23 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN) 24#define SE_I2C_ABORT BIT(1) 25 26/* M_CMD OP codes for I2C */ 27#define I2C_WRITE 0x1 28#define I2C_READ 0x2 29#define I2C_WRITE_READ 0x3 30#define I2C_ADDR_ONLY 0x4 31#define I2C_BUS_CLEAR 0x6 32#define I2C_STOP_ON_BUS 0x7 33/* M_CMD params for I2C */ 34#define PRE_CMD_DELAY BIT(0) 35#define TIMESTAMP_BEFORE BIT(1) 36#define STOP_STRETCH BIT(2) 37#define TIMESTAMP_AFTER BIT(3) 38#define POST_COMMAND_DELAY BIT(4) 39#define IGNORE_ADD_NACK BIT(6) 40#define READ_FINISHED_WITH_ACK BIT(7) 41#define BYPASS_ADDR_PHASE BIT(8) 42#define SLV_ADDR_MSK GENMASK(15, 9) 43#define SLV_ADDR_SHFT 9 44/* I2C SCL COUNTER fields */ 45#define HIGH_COUNTER_MSK GENMASK(29, 20) 46#define HIGH_COUNTER_SHFT 20 47#define LOW_COUNTER_MSK GENMASK(19, 10) 48#define LOW_COUNTER_SHFT 10 49#define CYCLE_COUNTER_MSK GENMASK(9, 0) 50 51enum geni_i2c_err_code { 52 GP_IRQ0, 53 NACK, 54 GP_IRQ2, 55 BUS_PROTO, 56 ARB_LOST, 57 GP_IRQ5, 58 GENI_OVERRUN, 59 GENI_ILLEGAL_CMD, 60 GENI_ABORT_DONE, 61 GENI_TIMEOUT, 62}; 63 64#define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \ 65 << 5) 66 67#define I2C_AUTO_SUSPEND_DELAY 250 68#define KHZ(freq) (1000 * freq) 69#define PACKING_BYTES_PW 4 70 71#define ABORT_TIMEOUT HZ 72#define XFER_TIMEOUT HZ 73#define RST_TIMEOUT HZ 74 75struct geni_i2c_dev { 76 struct geni_se se; 77 u32 tx_wm; 78 int irq; 79 int err; 80 struct i2c_adapter adap; 81 struct completion done; 82 struct i2c_msg *cur; 83 int cur_wr; 84 int cur_rd; 85 spinlock_t lock; 86 u32 clk_freq_out; 87 const struct geni_i2c_clk_fld *clk_fld; 88 int suspended; 89 void *dma_buf; 90 size_t xfer_len; 91 dma_addr_t dma_addr; 92}; 93 94struct geni_i2c_err_log { 95 int err; 96 const char *msg; 97}; 98 99static const struct geni_i2c_err_log gi2c_log[] = { 100 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"}, 101 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"}, 102 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"}, 103 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"}, 104 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"}, 105 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"}, 106 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"}, 107 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"}, 108 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"}, 109 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"}, 110}; 111 112struct geni_i2c_clk_fld { 113 u32 clk_freq_out; 114 u8 clk_div; 115 u8 t_high_cnt; 116 u8 t_low_cnt; 117 u8 t_cycle_cnt; 118}; 119 120/* 121 * Hardware uses the underlying formula to calculate time periods of 122 * SCL clock cycle. Firmware uses some additional cycles excluded from the 123 * below formula and it is confirmed that the time periods are within 124 * specification limits. 125 * 126 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock 127 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock 128 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock 129 * clk_freq_out = t / t_cycle 130 * source_clock = 19.2 MHz 131 */ 132static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = { 133 {KHZ(100), 7, 10, 11, 26}, 134 {KHZ(400), 2, 5, 12, 24}, 135 {KHZ(1000), 1, 3, 9, 18}, 136}; 137 138static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) 139{ 140 int i; 141 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map; 142 143 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) { 144 if (itr->clk_freq_out == gi2c->clk_freq_out) { 145 gi2c->clk_fld = itr; 146 return 0; 147 } 148 } 149 return -EINVAL; 150} 151 152static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c) 153{ 154 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld; 155 u32 val; 156 157 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); 158 159 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN; 160 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG); 161 162 val = itr->t_high_cnt << HIGH_COUNTER_SHFT; 163 val |= itr->t_low_cnt << LOW_COUNTER_SHFT; 164 val |= itr->t_cycle_cnt; 165 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS); 166} 167 168static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c) 169{ 170 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0); 171 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 172 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS); 173 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS); 174 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN); 175 u32 rx_st, tx_st; 176 177 if (dma) { 178 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 179 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 180 } else { 181 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS); 182 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS); 183 } 184 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n", 185 dma, tx_st, rx_st, m_stat); 186 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n", 187 m_cmd, geni_s, geni_ios); 188} 189 190static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err) 191{ 192 if (!gi2c->err) 193 gi2c->err = gi2c_log[err].err; 194 if (gi2c->cur) 195 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n", 196 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags); 197 198 if (err != NACK && err != GENI_ABORT_DONE) { 199 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg); 200 geni_i2c_err_misc(gi2c); 201 } 202} 203 204static irqreturn_t geni_i2c_irq(int irq, void *dev) 205{ 206 struct geni_i2c_dev *gi2c = dev; 207 void __iomem *base = gi2c->se.base; 208 int j, p; 209 u32 m_stat; 210 u32 rx_st; 211 u32 dm_tx_st; 212 u32 dm_rx_st; 213 u32 dma; 214 u32 val; 215 struct i2c_msg *cur; 216 217 spin_lock(&gi2c->lock); 218 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS); 219 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS); 220 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT); 221 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT); 222 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN); 223 cur = gi2c->cur; 224 225 if (!cur || 226 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) || 227 dm_rx_st & (DM_I2C_CB_ERR)) { 228 if (m_stat & M_GP_IRQ_1_EN) 229 geni_i2c_err(gi2c, NACK); 230 if (m_stat & M_GP_IRQ_3_EN) 231 geni_i2c_err(gi2c, BUS_PROTO); 232 if (m_stat & M_GP_IRQ_4_EN) 233 geni_i2c_err(gi2c, ARB_LOST); 234 if (m_stat & M_CMD_OVERRUN_EN) 235 geni_i2c_err(gi2c, GENI_OVERRUN); 236 if (m_stat & M_ILLEGAL_CMD_EN) 237 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD); 238 if (m_stat & M_CMD_ABORT_EN) 239 geni_i2c_err(gi2c, GENI_ABORT_DONE); 240 if (m_stat & M_GP_IRQ_0_EN) 241 geni_i2c_err(gi2c, GP_IRQ0); 242 243 /* Disable the TX Watermark interrupt to stop TX */ 244 if (!dma) 245 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 246 } else if (dma) { 247 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n", 248 dm_tx_st, dm_rx_st); 249 } else if (cur->flags & I2C_M_RD && 250 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) { 251 u32 rxcnt = rx_st & RX_FIFO_WC_MSK; 252 253 for (j = 0; j < rxcnt; j++) { 254 p = 0; 255 val = readl_relaxed(base + SE_GENI_RX_FIFOn); 256 while (gi2c->cur_rd < cur->len && p < sizeof(val)) { 257 cur->buf[gi2c->cur_rd++] = val & 0xff; 258 val >>= 8; 259 p++; 260 } 261 if (gi2c->cur_rd == cur->len) 262 break; 263 } 264 } else if (!(cur->flags & I2C_M_RD) && 265 m_stat & M_TX_FIFO_WATERMARK_EN) { 266 for (j = 0; j < gi2c->tx_wm; j++) { 267 u32 temp; 268 269 val = 0; 270 p = 0; 271 while (gi2c->cur_wr < cur->len && p < sizeof(val)) { 272 temp = cur->buf[gi2c->cur_wr++]; 273 val |= temp << (p * 8); 274 p++; 275 } 276 writel_relaxed(val, base + SE_GENI_TX_FIFOn); 277 /* TX Complete, Disable the TX Watermark interrupt */ 278 if (gi2c->cur_wr == cur->len) { 279 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG); 280 break; 281 } 282 } 283 } 284 285 if (m_stat) 286 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR); 287 288 if (dma && dm_tx_st) 289 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR); 290 if (dma && dm_rx_st) 291 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR); 292 293 /* if this is err with done-bit not set, handle that through timeout. */ 294 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || 295 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE || 296 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE) 297 complete(&gi2c->done); 298 299 spin_unlock(&gi2c->lock); 300 301 return IRQ_HANDLED; 302} 303 304static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c) 305{ 306 u32 val; 307 unsigned long time_left = ABORT_TIMEOUT; 308 unsigned long flags; 309 310 spin_lock_irqsave(&gi2c->lock, flags); 311 geni_i2c_err(gi2c, GENI_TIMEOUT); 312 gi2c->cur = NULL; 313 geni_se_abort_m_cmd(&gi2c->se); 314 spin_unlock_irqrestore(&gi2c->lock, flags); 315 do { 316 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 317 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS); 318 } while (!(val & M_CMD_ABORT_EN) && time_left); 319 320 if (!(val & M_CMD_ABORT_EN)) 321 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n"); 322} 323 324static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c) 325{ 326 u32 val; 327 unsigned long time_left = RST_TIMEOUT; 328 329 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST); 330 do { 331 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 332 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT); 333 } while (!(val & RX_RESET_DONE) && time_left); 334 335 if (!(val & RX_RESET_DONE)) 336 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n"); 337} 338 339static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c) 340{ 341 u32 val; 342 unsigned long time_left = RST_TIMEOUT; 343 344 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST); 345 do { 346 time_left = wait_for_completion_timeout(&gi2c->done, time_left); 347 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT); 348 } while (!(val & TX_RESET_DONE) && time_left); 349 350 if (!(val & TX_RESET_DONE)) 351 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n"); 352} 353 354static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c, 355 struct i2c_msg *cur) 356{ 357 gi2c->cur_rd = 0; 358 if (gi2c->dma_buf) { 359 if (gi2c->err) 360 geni_i2c_rx_fsm_rst(gi2c); 361 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 362 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 363 } 364} 365 366static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c, 367 struct i2c_msg *cur) 368{ 369 gi2c->cur_wr = 0; 370 if (gi2c->dma_buf) { 371 if (gi2c->err) 372 geni_i2c_tx_fsm_rst(gi2c); 373 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len); 374 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err); 375 } 376} 377 378static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 379 u32 m_param) 380{ 381 dma_addr_t rx_dma = 0; 382 unsigned long time_left; 383 void *dma_buf = NULL; 384 struct geni_se *se = &gi2c->se; 385 size_t len = msg->len; 386 struct i2c_msg *cur; 387 388 if (!of_machine_is_compatible("lenovo,yoga-c630")) 389 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 390 391 if (dma_buf) 392 geni_se_select_mode(se, GENI_SE_DMA); 393 else 394 geni_se_select_mode(se, GENI_SE_FIFO); 395 396 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN); 397 geni_se_setup_m_cmd(se, I2C_READ, m_param); 398 399 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) { 400 geni_se_select_mode(se, GENI_SE_FIFO); 401 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 402 dma_buf = NULL; 403 } else { 404 gi2c->xfer_len = len; 405 gi2c->dma_addr = rx_dma; 406 gi2c->dma_buf = dma_buf; 407 } 408 409 cur = gi2c->cur; 410 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 411 if (!time_left) 412 geni_i2c_abort_xfer(gi2c); 413 414 geni_i2c_rx_msg_cleanup(gi2c, cur); 415 416 return gi2c->err; 417} 418 419static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg, 420 u32 m_param) 421{ 422 dma_addr_t tx_dma = 0; 423 unsigned long time_left; 424 void *dma_buf = NULL; 425 struct geni_se *se = &gi2c->se; 426 size_t len = msg->len; 427 struct i2c_msg *cur; 428 429 if (!of_machine_is_compatible("lenovo,yoga-c630")) 430 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32); 431 432 if (dma_buf) 433 geni_se_select_mode(se, GENI_SE_DMA); 434 else 435 geni_se_select_mode(se, GENI_SE_FIFO); 436 437 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN); 438 geni_se_setup_m_cmd(se, I2C_WRITE, m_param); 439 440 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) { 441 geni_se_select_mode(se, GENI_SE_FIFO); 442 i2c_put_dma_safe_msg_buf(dma_buf, msg, false); 443 dma_buf = NULL; 444 } else { 445 gi2c->xfer_len = len; 446 gi2c->dma_addr = tx_dma; 447 gi2c->dma_buf = dma_buf; 448 } 449 450 if (!dma_buf) /* Get FIFO IRQ */ 451 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG); 452 453 cur = gi2c->cur; 454 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT); 455 if (!time_left) 456 geni_i2c_abort_xfer(gi2c); 457 458 geni_i2c_tx_msg_cleanup(gi2c, cur); 459 460 return gi2c->err; 461} 462 463static int geni_i2c_xfer(struct i2c_adapter *adap, 464 struct i2c_msg msgs[], 465 int num) 466{ 467 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap); 468 int i, ret; 469 470 gi2c->err = 0; 471 reinit_completion(&gi2c->done); 472 ret = pm_runtime_get_sync(gi2c->se.dev); 473 if (ret < 0) { 474 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret); 475 pm_runtime_put_noidle(gi2c->se.dev); 476 /* Set device in suspended since resume failed */ 477 pm_runtime_set_suspended(gi2c->se.dev); 478 return ret; 479 } 480 481 qcom_geni_i2c_conf(gi2c); 482 for (i = 0; i < num; i++) { 483 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0; 484 485 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK); 486 487 gi2c->cur = &msgs[i]; 488 if (msgs[i].flags & I2C_M_RD) 489 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param); 490 else 491 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param); 492 493 if (ret) 494 break; 495 } 496 if (ret == 0) 497 ret = num; 498 499 pm_runtime_mark_last_busy(gi2c->se.dev); 500 pm_runtime_put_autosuspend(gi2c->se.dev); 501 gi2c->cur = NULL; 502 gi2c->err = 0; 503 return ret; 504} 505 506static u32 geni_i2c_func(struct i2c_adapter *adap) 507{ 508 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK); 509} 510 511static const struct i2c_algorithm geni_i2c_algo = { 512 .master_xfer = geni_i2c_xfer, 513 .functionality = geni_i2c_func, 514}; 515 516#ifdef CONFIG_ACPI 517static const struct acpi_device_id geni_i2c_acpi_match[] = { 518 { "QCOM0220"}, 519 { }, 520}; 521MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match); 522#endif 523 524static int geni_i2c_probe(struct platform_device *pdev) 525{ 526 struct geni_i2c_dev *gi2c; 527 struct resource *res; 528 u32 proto, tx_depth; 529 int ret; 530 struct device *dev = &pdev->dev; 531 532 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL); 533 if (!gi2c) 534 return -ENOMEM; 535 536 gi2c->se.dev = dev; 537 gi2c->se.wrapper = dev_get_drvdata(dev->parent); 538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 539 gi2c->se.base = devm_ioremap_resource(dev, res); 540 if (IS_ERR(gi2c->se.base)) 541 return PTR_ERR(gi2c->se.base); 542 543 gi2c->se.clk = devm_clk_get(dev, "se"); 544 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev)) 545 return PTR_ERR(gi2c->se.clk); 546 547 ret = device_property_read_u32(dev, "clock-frequency", 548 &gi2c->clk_freq_out); 549 if (ret) { 550 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n"); 551 gi2c->clk_freq_out = KHZ(100); 552 } 553 554 if (has_acpi_companion(dev)) 555 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev)); 556 557 gi2c->irq = platform_get_irq(pdev, 0); 558 if (gi2c->irq < 0) 559 return gi2c->irq; 560 561 ret = geni_i2c_clk_map_idx(gi2c); 562 if (ret) { 563 dev_err(dev, "Invalid clk frequency %d Hz: %d\n", 564 gi2c->clk_freq_out, ret); 565 return ret; 566 } 567 568 gi2c->adap.algo = &geni_i2c_algo; 569 init_completion(&gi2c->done); 570 spin_lock_init(&gi2c->lock); 571 platform_set_drvdata(pdev, gi2c); 572 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0, 573 dev_name(dev), gi2c); 574 if (ret) { 575 dev_err(dev, "Request_irq failed:%d: err:%d\n", 576 gi2c->irq, ret); 577 return ret; 578 } 579 /* Disable the interrupt so that the system can enter low-power mode */ 580 disable_irq(gi2c->irq); 581 i2c_set_adapdata(&gi2c->adap, gi2c); 582 gi2c->adap.dev.parent = dev; 583 gi2c->adap.dev.of_node = dev->of_node; 584 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name)); 585 586 ret = geni_icc_get(&gi2c->se, "qup-memory"); 587 if (ret) 588 return ret; 589 /* 590 * Set the bus quota for core and cpu to a reasonable value for 591 * register access. 592 * Set quota for DDR based on bus speed. 593 */ 594 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW; 595 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW; 596 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out); 597 598 ret = geni_icc_set_bw(&gi2c->se); 599 if (ret) 600 return ret; 601 602 ret = geni_se_resources_on(&gi2c->se); 603 if (ret) { 604 dev_err(dev, "Error turning on resources %d\n", ret); 605 return ret; 606 } 607 proto = geni_se_read_proto(&gi2c->se); 608 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se); 609 if (proto != GENI_SE_I2C) { 610 dev_err(dev, "Invalid proto %d\n", proto); 611 geni_se_resources_off(&gi2c->se); 612 return -ENXIO; 613 } 614 gi2c->tx_wm = tx_depth - 1; 615 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth); 616 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW, 617 true, true, true); 618 ret = geni_se_resources_off(&gi2c->se); 619 if (ret) { 620 dev_err(dev, "Error turning off resources %d\n", ret); 621 return ret; 622 } 623 624 ret = geni_icc_disable(&gi2c->se); 625 if (ret) 626 return ret; 627 628 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth); 629 630 gi2c->suspended = 1; 631 pm_runtime_set_suspended(gi2c->se.dev); 632 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY); 633 pm_runtime_use_autosuspend(gi2c->se.dev); 634 pm_runtime_enable(gi2c->se.dev); 635 636 ret = i2c_add_adapter(&gi2c->adap); 637 if (ret) { 638 dev_err(dev, "Error adding i2c adapter %d\n", ret); 639 pm_runtime_disable(gi2c->se.dev); 640 return ret; 641 } 642 643 dev_dbg(dev, "Geni-I2C adaptor successfully added\n"); 644 645 return 0; 646} 647 648static int geni_i2c_remove(struct platform_device *pdev) 649{ 650 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 651 652 i2c_del_adapter(&gi2c->adap); 653 pm_runtime_disable(gi2c->se.dev); 654 return 0; 655} 656 657static void geni_i2c_shutdown(struct platform_device *pdev) 658{ 659 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev); 660 661 /* Make client i2c transfers start failing */ 662 i2c_mark_adapter_suspended(&gi2c->adap); 663} 664 665static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev) 666{ 667 int ret; 668 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 669 670 disable_irq(gi2c->irq); 671 ret = geni_se_resources_off(&gi2c->se); 672 if (ret) { 673 enable_irq(gi2c->irq); 674 return ret; 675 676 } else { 677 gi2c->suspended = 1; 678 } 679 680 return geni_icc_disable(&gi2c->se); 681} 682 683static int __maybe_unused geni_i2c_runtime_resume(struct device *dev) 684{ 685 int ret; 686 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 687 688 ret = geni_icc_enable(&gi2c->se); 689 if (ret) 690 return ret; 691 692 ret = geni_se_resources_on(&gi2c->se); 693 if (ret) 694 return ret; 695 696 enable_irq(gi2c->irq); 697 gi2c->suspended = 0; 698 return 0; 699} 700 701static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev) 702{ 703 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 704 705 i2c_mark_adapter_suspended(&gi2c->adap); 706 707 if (!gi2c->suspended) { 708 geni_i2c_runtime_suspend(dev); 709 pm_runtime_disable(dev); 710 pm_runtime_set_suspended(dev); 711 pm_runtime_enable(dev); 712 } 713 return 0; 714} 715 716static int __maybe_unused geni_i2c_resume_noirq(struct device *dev) 717{ 718 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev); 719 720 i2c_mark_adapter_resumed(&gi2c->adap); 721 return 0; 722} 723 724static const struct dev_pm_ops geni_i2c_pm_ops = { 725 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq) 726 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume, 727 NULL) 728}; 729 730static const struct of_device_id geni_i2c_dt_match[] = { 731 { .compatible = "qcom,geni-i2c" }, 732 {} 733}; 734MODULE_DEVICE_TABLE(of, geni_i2c_dt_match); 735 736static struct platform_driver geni_i2c_driver = { 737 .probe = geni_i2c_probe, 738 .remove = geni_i2c_remove, 739 .shutdown = geni_i2c_shutdown, 740 .driver = { 741 .name = "geni_i2c", 742 .pm = &geni_i2c_pm_ops, 743 .of_match_table = geni_i2c_dt_match, 744 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match), 745 }, 746}; 747 748module_platform_driver(geni_i2c_driver); 749 750MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores"); 751MODULE_LICENSE("GPL v2"); 752