1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Actions Semiconductor Owl SoC's I2C driver 4 * 5 * Copyright (c) 2014 Actions Semi Inc. 6 * Author: David Liu <liuwei@actions-semi.com> 7 * 8 * Copyright (c) 2018 Linaro Ltd. 9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> 10 */ 11 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/i2c.h> 15#include <linux/interrupt.h> 16#include <linux/io.h> 17#include <linux/module.h> 18#include <linux/of_device.h> 19 20/* I2C registers */ 21#define OWL_I2C_REG_CTL 0x0000 22#define OWL_I2C_REG_CLKDIV 0x0004 23#define OWL_I2C_REG_STAT 0x0008 24#define OWL_I2C_REG_ADDR 0x000C 25#define OWL_I2C_REG_TXDAT 0x0010 26#define OWL_I2C_REG_RXDAT 0x0014 27#define OWL_I2C_REG_CMD 0x0018 28#define OWL_I2C_REG_FIFOCTL 0x001C 29#define OWL_I2C_REG_FIFOSTAT 0x0020 30#define OWL_I2C_REG_DATCNT 0x0024 31#define OWL_I2C_REG_RCNT 0x0028 32 33/* I2Cx_CTL Bit Mask */ 34#define OWL_I2C_CTL_RB BIT(1) 35#define OWL_I2C_CTL_GBCC(x) (((x) & 0x3) << 2) 36#define OWL_I2C_CTL_GBCC_NONE OWL_I2C_CTL_GBCC(0) 37#define OWL_I2C_CTL_GBCC_START OWL_I2C_CTL_GBCC(1) 38#define OWL_I2C_CTL_GBCC_STOP OWL_I2C_CTL_GBCC(2) 39#define OWL_I2C_CTL_GBCC_RSTART OWL_I2C_CTL_GBCC(3) 40#define OWL_I2C_CTL_IRQE BIT(5) 41#define OWL_I2C_CTL_EN BIT(7) 42#define OWL_I2C_CTL_AE BIT(8) 43#define OWL_I2C_CTL_SHSM BIT(10) 44 45#define OWL_I2C_DIV_FACTOR(x) ((x) & 0xff) 46 47/* I2Cx_STAT Bit Mask */ 48#define OWL_I2C_STAT_RACK BIT(0) 49#define OWL_I2C_STAT_BEB BIT(1) 50#define OWL_I2C_STAT_IRQP BIT(2) 51#define OWL_I2C_STAT_LAB BIT(3) 52#define OWL_I2C_STAT_STPD BIT(4) 53#define OWL_I2C_STAT_STAD BIT(5) 54#define OWL_I2C_STAT_BBB BIT(6) 55#define OWL_I2C_STAT_TCB BIT(7) 56#define OWL_I2C_STAT_LBST BIT(8) 57#define OWL_I2C_STAT_SAMB BIT(9) 58#define OWL_I2C_STAT_SRGC BIT(10) 59 60/* I2Cx_CMD Bit Mask */ 61#define OWL_I2C_CMD_SBE BIT(0) 62#define OWL_I2C_CMD_RBE BIT(4) 63#define OWL_I2C_CMD_DE BIT(8) 64#define OWL_I2C_CMD_NS BIT(9) 65#define OWL_I2C_CMD_SE BIT(10) 66#define OWL_I2C_CMD_MSS BIT(11) 67#define OWL_I2C_CMD_WRS BIT(12) 68#define OWL_I2C_CMD_SECL BIT(15) 69 70#define OWL_I2C_CMD_AS(x) (((x) & 0x7) << 1) 71#define OWL_I2C_CMD_SAS(x) (((x) & 0x7) << 5) 72 73/* I2Cx_FIFOCTL Bit Mask */ 74#define OWL_I2C_FIFOCTL_NIB BIT(0) 75#define OWL_I2C_FIFOCTL_RFR BIT(1) 76#define OWL_I2C_FIFOCTL_TFR BIT(2) 77 78/* I2Cc_FIFOSTAT Bit Mask */ 79#define OWL_I2C_FIFOSTAT_RNB BIT(1) 80#define OWL_I2C_FIFOSTAT_RFE BIT(2) 81#define OWL_I2C_FIFOSTAT_TFF BIT(5) 82#define OWL_I2C_FIFOSTAT_TFD GENMASK(23, 16) 83#define OWL_I2C_FIFOSTAT_RFD GENMASK(15, 8) 84 85/* I2C bus timeout */ 86#define OWL_I2C_TIMEOUT msecs_to_jiffies(4 * 1000) 87 88#define OWL_I2C_MAX_RETRIES 50 89 90struct owl_i2c_dev { 91 struct i2c_adapter adap; 92 struct i2c_msg *msg; 93 struct completion msg_complete; 94 struct clk *clk; 95 spinlock_t lock; 96 void __iomem *base; 97 unsigned long clk_rate; 98 u32 bus_freq; 99 u32 msg_ptr; 100 int err; 101}; 102 103static void owl_i2c_update_reg(void __iomem *reg, unsigned int val, bool state) 104{ 105 unsigned int regval; 106 107 regval = readl(reg); 108 109 if (state) 110 regval |= val; 111 else 112 regval &= ~val; 113 114 writel(regval, reg); 115} 116 117static void owl_i2c_reset(struct owl_i2c_dev *i2c_dev) 118{ 119 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 120 OWL_I2C_CTL_EN, false); 121 mdelay(1); 122 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 123 OWL_I2C_CTL_EN, true); 124 125 /* Clear status registers */ 126 writel(0, i2c_dev->base + OWL_I2C_REG_STAT); 127} 128 129static int owl_i2c_reset_fifo(struct owl_i2c_dev *i2c_dev) 130{ 131 unsigned int val, timeout = 0; 132 133 /* Reset FIFO */ 134 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 135 OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR, 136 true); 137 138 /* Wait 50ms for FIFO reset complete */ 139 do { 140 val = readl(i2c_dev->base + OWL_I2C_REG_FIFOCTL); 141 if (!(val & (OWL_I2C_FIFOCTL_RFR | OWL_I2C_FIFOCTL_TFR))) 142 break; 143 usleep_range(500, 1000); 144 } while (timeout++ < OWL_I2C_MAX_RETRIES); 145 146 if (timeout > OWL_I2C_MAX_RETRIES) { 147 dev_err(&i2c_dev->adap.dev, "FIFO reset timeout\n"); 148 return -ETIMEDOUT; 149 } 150 151 return 0; 152} 153 154static void owl_i2c_set_freq(struct owl_i2c_dev *i2c_dev) 155{ 156 unsigned int val; 157 158 val = DIV_ROUND_UP(i2c_dev->clk_rate, i2c_dev->bus_freq * 16); 159 160 /* Set clock divider factor */ 161 writel(OWL_I2C_DIV_FACTOR(val), i2c_dev->base + OWL_I2C_REG_CLKDIV); 162} 163 164static irqreturn_t owl_i2c_interrupt(int irq, void *_dev) 165{ 166 struct owl_i2c_dev *i2c_dev = _dev; 167 struct i2c_msg *msg = i2c_dev->msg; 168 unsigned int stat, fifostat; 169 170 spin_lock(&i2c_dev->lock); 171 172 i2c_dev->err = 0; 173 174 /* Handle NACK from slave */ 175 fifostat = readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT); 176 if (fifostat & OWL_I2C_FIFOSTAT_RNB) { 177 i2c_dev->err = -ENXIO; 178 /* Clear NACK error bit by writing "1" */ 179 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOSTAT, 180 OWL_I2C_FIFOSTAT_RNB, true); 181 goto stop; 182 } 183 184 /* Handle bus error */ 185 stat = readl(i2c_dev->base + OWL_I2C_REG_STAT); 186 if (stat & OWL_I2C_STAT_BEB) { 187 i2c_dev->err = -EIO; 188 /* Clear BUS error bit by writing "1" */ 189 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 190 OWL_I2C_STAT_BEB, true); 191 goto stop; 192 } 193 194 /* Handle FIFO read */ 195 if (msg->flags & I2C_M_RD) { 196 while ((readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 197 OWL_I2C_FIFOSTAT_RFE) && i2c_dev->msg_ptr < msg->len) { 198 msg->buf[i2c_dev->msg_ptr++] = readl(i2c_dev->base + 199 OWL_I2C_REG_RXDAT); 200 } 201 } else { 202 /* Handle the remaining bytes which were not sent */ 203 while (!(readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 204 OWL_I2C_FIFOSTAT_TFF) && i2c_dev->msg_ptr < msg->len) { 205 writel(msg->buf[i2c_dev->msg_ptr++], 206 i2c_dev->base + OWL_I2C_REG_TXDAT); 207 } 208 } 209 210stop: 211 /* Clear pending interrupts */ 212 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_STAT, 213 OWL_I2C_STAT_IRQP, true); 214 215 complete_all(&i2c_dev->msg_complete); 216 spin_unlock(&i2c_dev->lock); 217 218 return IRQ_HANDLED; 219} 220 221static u32 owl_i2c_func(struct i2c_adapter *adap) 222{ 223 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 224} 225 226static int owl_i2c_check_bus_busy(struct i2c_adapter *adap) 227{ 228 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 229 unsigned long timeout; 230 231 /* Check for Bus busy */ 232 timeout = jiffies + OWL_I2C_TIMEOUT; 233 while (readl(i2c_dev->base + OWL_I2C_REG_STAT) & OWL_I2C_STAT_BBB) { 234 if (time_after(jiffies, timeout)) { 235 dev_err(&adap->dev, "Bus busy timeout\n"); 236 return -ETIMEDOUT; 237 } 238 } 239 240 return 0; 241} 242 243static int owl_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 244 int num) 245{ 246 struct owl_i2c_dev *i2c_dev = i2c_get_adapdata(adap); 247 struct i2c_msg *msg; 248 unsigned long time_left, flags; 249 unsigned int i2c_cmd, val; 250 unsigned int addr; 251 int ret, idx; 252 253 spin_lock_irqsave(&i2c_dev->lock, flags); 254 255 /* Reset I2C controller */ 256 owl_i2c_reset(i2c_dev); 257 258 /* Set bus frequency */ 259 owl_i2c_set_freq(i2c_dev); 260 261 /* 262 * Spinlock should be released before calling reset FIFO and 263 * bus busy check since those functions may sleep 264 */ 265 spin_unlock_irqrestore(&i2c_dev->lock, flags); 266 267 /* Reset FIFO */ 268 ret = owl_i2c_reset_fifo(i2c_dev); 269 if (ret) 270 goto unlocked_err_exit; 271 272 /* Check for bus busy */ 273 ret = owl_i2c_check_bus_busy(adap); 274 if (ret) 275 goto unlocked_err_exit; 276 277 spin_lock_irqsave(&i2c_dev->lock, flags); 278 279 /* Check for Arbitration lost */ 280 val = readl(i2c_dev->base + OWL_I2C_REG_STAT); 281 if (val & OWL_I2C_STAT_LAB) { 282 val &= ~OWL_I2C_STAT_LAB; 283 writel(val, i2c_dev->base + OWL_I2C_REG_STAT); 284 ret = -EAGAIN; 285 goto err_exit; 286 } 287 288 reinit_completion(&i2c_dev->msg_complete); 289 290 /* Enable I2C controller interrupt */ 291 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 292 OWL_I2C_CTL_IRQE, true); 293 294 /* 295 * Select: FIFO enable, Master mode, Stop enable, Data count enable, 296 * Send start bit 297 */ 298 i2c_cmd = OWL_I2C_CMD_SECL | OWL_I2C_CMD_MSS | OWL_I2C_CMD_SE | 299 OWL_I2C_CMD_NS | OWL_I2C_CMD_DE | OWL_I2C_CMD_SBE; 300 301 /* Handle repeated start condition */ 302 if (num > 1) { 303 /* Set internal address length and enable repeated start */ 304 i2c_cmd |= OWL_I2C_CMD_AS(msgs[0].len + 1) | 305 OWL_I2C_CMD_SAS(1) | OWL_I2C_CMD_RBE; 306 307 /* Write slave address */ 308 addr = i2c_8bit_addr_from_msg(&msgs[0]); 309 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 310 311 /* Write internal register address */ 312 for (idx = 0; idx < msgs[0].len; idx++) 313 writel(msgs[0].buf[idx], 314 i2c_dev->base + OWL_I2C_REG_TXDAT); 315 316 msg = &msgs[1]; 317 } else { 318 /* Set address length */ 319 i2c_cmd |= OWL_I2C_CMD_AS(1); 320 msg = &msgs[0]; 321 } 322 323 i2c_dev->msg = msg; 324 i2c_dev->msg_ptr = 0; 325 326 /* Set data count for the message */ 327 writel(msg->len, i2c_dev->base + OWL_I2C_REG_DATCNT); 328 329 addr = i2c_8bit_addr_from_msg(msg); 330 writel(addr, i2c_dev->base + OWL_I2C_REG_TXDAT); 331 332 if (!(msg->flags & I2C_M_RD)) { 333 /* Write data to FIFO */ 334 for (idx = 0; idx < msg->len; idx++) { 335 /* Check for FIFO full */ 336 if (readl(i2c_dev->base + OWL_I2C_REG_FIFOSTAT) & 337 OWL_I2C_FIFOSTAT_TFF) 338 break; 339 340 writel(msg->buf[idx], 341 i2c_dev->base + OWL_I2C_REG_TXDAT); 342 } 343 344 i2c_dev->msg_ptr = idx; 345 } 346 347 /* Ignore the NACK if needed */ 348 if (msg->flags & I2C_M_IGNORE_NAK) 349 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 350 OWL_I2C_FIFOCTL_NIB, true); 351 else 352 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_FIFOCTL, 353 OWL_I2C_FIFOCTL_NIB, false); 354 355 /* Start the transfer */ 356 writel(i2c_cmd, i2c_dev->base + OWL_I2C_REG_CMD); 357 358 spin_unlock_irqrestore(&i2c_dev->lock, flags); 359 360 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, 361 adap->timeout); 362 363 spin_lock_irqsave(&i2c_dev->lock, flags); 364 if (time_left == 0) { 365 dev_err(&adap->dev, "Transaction timed out\n"); 366 /* Send stop condition and release the bus */ 367 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 368 OWL_I2C_CTL_GBCC_STOP | OWL_I2C_CTL_RB, 369 true); 370 ret = -ETIMEDOUT; 371 goto err_exit; 372 } 373 374 ret = i2c_dev->err < 0 ? i2c_dev->err : num; 375 376err_exit: 377 spin_unlock_irqrestore(&i2c_dev->lock, flags); 378 379unlocked_err_exit: 380 /* Disable I2C controller */ 381 owl_i2c_update_reg(i2c_dev->base + OWL_I2C_REG_CTL, 382 OWL_I2C_CTL_EN, false); 383 384 return ret; 385} 386 387static const struct i2c_algorithm owl_i2c_algorithm = { 388 .master_xfer = owl_i2c_master_xfer, 389 .functionality = owl_i2c_func, 390}; 391 392static const struct i2c_adapter_quirks owl_i2c_quirks = { 393 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST, 394 .max_read_len = 240, 395 .max_write_len = 240, 396 .max_comb_1st_msg_len = 6, 397 .max_comb_2nd_msg_len = 240, 398}; 399 400static int owl_i2c_probe(struct platform_device *pdev) 401{ 402 struct device *dev = &pdev->dev; 403 struct owl_i2c_dev *i2c_dev; 404 int ret, irq; 405 406 i2c_dev = devm_kzalloc(dev, sizeof(*i2c_dev), GFP_KERNEL); 407 if (!i2c_dev) 408 return -ENOMEM; 409 410 i2c_dev->base = devm_platform_ioremap_resource(pdev, 0); 411 if (IS_ERR(i2c_dev->base)) 412 return PTR_ERR(i2c_dev->base); 413 414 irq = platform_get_irq(pdev, 0); 415 if (irq < 0) 416 return irq; 417 418 if (of_property_read_u32(dev->of_node, "clock-frequency", 419 &i2c_dev->bus_freq)) 420 i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ; 421 422 /* We support only frequencies of 100k and 400k for now */ 423 if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ && 424 i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ) { 425 dev_err(dev, "invalid clock-frequency %d\n", i2c_dev->bus_freq); 426 return -EINVAL; 427 } 428 429 i2c_dev->clk = devm_clk_get(dev, NULL); 430 if (IS_ERR(i2c_dev->clk)) { 431 dev_err(dev, "failed to get clock\n"); 432 return PTR_ERR(i2c_dev->clk); 433 } 434 435 ret = clk_prepare_enable(i2c_dev->clk); 436 if (ret) 437 return ret; 438 439 i2c_dev->clk_rate = clk_get_rate(i2c_dev->clk); 440 if (!i2c_dev->clk_rate) { 441 dev_err(dev, "input clock rate should not be zero\n"); 442 ret = -EINVAL; 443 goto disable_clk; 444 } 445 446 init_completion(&i2c_dev->msg_complete); 447 spin_lock_init(&i2c_dev->lock); 448 i2c_dev->adap.owner = THIS_MODULE; 449 i2c_dev->adap.algo = &owl_i2c_algorithm; 450 i2c_dev->adap.timeout = OWL_I2C_TIMEOUT; 451 i2c_dev->adap.quirks = &owl_i2c_quirks; 452 i2c_dev->adap.dev.parent = dev; 453 i2c_dev->adap.dev.of_node = dev->of_node; 454 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name), 455 "%s", "OWL I2C adapter"); 456 i2c_set_adapdata(&i2c_dev->adap, i2c_dev); 457 458 platform_set_drvdata(pdev, i2c_dev); 459 460 ret = devm_request_irq(dev, irq, owl_i2c_interrupt, 0, pdev->name, 461 i2c_dev); 462 if (ret) { 463 dev_err(dev, "failed to request irq %d\n", irq); 464 goto disable_clk; 465 } 466 467 return i2c_add_adapter(&i2c_dev->adap); 468 469disable_clk: 470 clk_disable_unprepare(i2c_dev->clk); 471 472 return ret; 473} 474 475static const struct of_device_id owl_i2c_of_match[] = { 476 { .compatible = "actions,s700-i2c" }, 477 { .compatible = "actions,s900-i2c" }, 478 { /* sentinel */ } 479}; 480MODULE_DEVICE_TABLE(of, owl_i2c_of_match); 481 482static struct platform_driver owl_i2c_driver = { 483 .probe = owl_i2c_probe, 484 .driver = { 485 .name = "owl-i2c", 486 .of_match_table = of_match_ptr(owl_i2c_of_match), 487 }, 488}; 489module_platform_driver(owl_i2c_driver); 490 491MODULE_AUTHOR("David Liu <liuwei@actions-semi.com>"); 492MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>"); 493MODULE_DESCRIPTION("Actions Semiconductor Owl SoC's I2C driver"); 494MODULE_LICENSE("GPL"); 495