1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Nvidia GPU I2C controller Driver
4 *
5 * Copyright (C) 2018 NVIDIA Corporation. All rights reserved.
6 * Author: Ajay Gupta <ajayg@nvidia.com>
7 */
8#include <linux/delay.h>
9#include <linux/i2c.h>
10#include <linux/interrupt.h>
11#include <linux/iopoll.h>
12#include <linux/module.h>
13#include <linux/pci.h>
14#include <linux/platform_device.h>
15#include <linux/pm.h>
16#include <linux/pm_runtime.h>
17
18#include <asm/unaligned.h>
19
20/* I2C definitions */
21#define I2C_MST_CNTL				0x00
22#define I2C_MST_CNTL_GEN_START			BIT(0)
23#define I2C_MST_CNTL_GEN_STOP			BIT(1)
24#define I2C_MST_CNTL_CMD_READ			(1 << 2)
25#define I2C_MST_CNTL_CMD_WRITE			(2 << 2)
26#define I2C_MST_CNTL_BURST_SIZE_SHIFT		6
27#define I2C_MST_CNTL_GEN_NACK			BIT(28)
28#define I2C_MST_CNTL_STATUS			GENMASK(30, 29)
29#define I2C_MST_CNTL_STATUS_OKAY		(0 << 29)
30#define I2C_MST_CNTL_STATUS_NO_ACK		(1 << 29)
31#define I2C_MST_CNTL_STATUS_TIMEOUT		(2 << 29)
32#define I2C_MST_CNTL_STATUS_BUS_BUSY		(3 << 29)
33#define I2C_MST_CNTL_CYCLE_TRIGGER		BIT(31)
34
35#define I2C_MST_ADDR				0x04
36
37#define I2C_MST_I2C0_TIMING				0x08
38#define I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ		0x10e
39#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT		16
40#define I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX		255
41#define I2C_MST_I2C0_TIMING_TIMEOUT_CHECK		BIT(24)
42
43#define I2C_MST_DATA					0x0c
44
45#define I2C_MST_HYBRID_PADCTL				0x20
46#define I2C_MST_HYBRID_PADCTL_MODE_I2C			BIT(0)
47#define I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV		BIT(14)
48#define I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV		BIT(15)
49
50struct gpu_i2c_dev {
51	struct device *dev;
52	void __iomem *regs;
53	struct i2c_adapter adapter;
54	struct i2c_board_info *gpu_ccgx_ucsi;
55	struct i2c_client *ccgx_client;
56};
57
58static void gpu_enable_i2c_bus(struct gpu_i2c_dev *i2cd)
59{
60	u32 val;
61
62	/* enable I2C */
63	val = readl(i2cd->regs + I2C_MST_HYBRID_PADCTL);
64	val |= I2C_MST_HYBRID_PADCTL_MODE_I2C |
65		I2C_MST_HYBRID_PADCTL_I2C_SCL_INPUT_RCV |
66		I2C_MST_HYBRID_PADCTL_I2C_SDA_INPUT_RCV;
67	writel(val, i2cd->regs + I2C_MST_HYBRID_PADCTL);
68
69	/* enable 100KHZ mode */
70	val = I2C_MST_I2C0_TIMING_SCL_PERIOD_100KHZ;
71	val |= (I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT_MAX
72	    << I2C_MST_I2C0_TIMING_TIMEOUT_CLK_CNT);
73	val |= I2C_MST_I2C0_TIMING_TIMEOUT_CHECK;
74	writel(val, i2cd->regs + I2C_MST_I2C0_TIMING);
75}
76
77static int gpu_i2c_check_status(struct gpu_i2c_dev *i2cd)
78{
79	u32 val;
80	int ret;
81
82	ret = readl_poll_timeout(i2cd->regs + I2C_MST_CNTL, val,
83				 !(val & I2C_MST_CNTL_CYCLE_TRIGGER) ||
84				 (val & I2C_MST_CNTL_STATUS) != I2C_MST_CNTL_STATUS_BUS_BUSY,
85				 500, 1000 * USEC_PER_MSEC);
86
87	if (ret) {
88		dev_err(i2cd->dev, "i2c timeout error %x\n", val);
89		return -ETIMEDOUT;
90	}
91
92	val = readl(i2cd->regs + I2C_MST_CNTL);
93	switch (val & I2C_MST_CNTL_STATUS) {
94	case I2C_MST_CNTL_STATUS_OKAY:
95		return 0;
96	case I2C_MST_CNTL_STATUS_NO_ACK:
97		return -ENXIO;
98	case I2C_MST_CNTL_STATUS_TIMEOUT:
99		return -ETIMEDOUT;
100	default:
101		return 0;
102	}
103}
104
105static int gpu_i2c_read(struct gpu_i2c_dev *i2cd, u8 *data, u16 len)
106{
107	int status;
108	u32 val;
109
110	val = I2C_MST_CNTL_GEN_START | I2C_MST_CNTL_CMD_READ |
111		(len << I2C_MST_CNTL_BURST_SIZE_SHIFT) |
112		I2C_MST_CNTL_CYCLE_TRIGGER | I2C_MST_CNTL_GEN_NACK;
113	writel(val, i2cd->regs + I2C_MST_CNTL);
114
115	status = gpu_i2c_check_status(i2cd);
116	if (status < 0)
117		return status;
118
119	val = readl(i2cd->regs + I2C_MST_DATA);
120	switch (len) {
121	case 1:
122		data[0] = val;
123		break;
124	case 2:
125		put_unaligned_be16(val, data);
126		break;
127	case 3:
128		put_unaligned_be24(val, data);
129		break;
130	case 4:
131		put_unaligned_be32(val, data);
132		break;
133	default:
134		break;
135	}
136	return status;
137}
138
139static int gpu_i2c_start(struct gpu_i2c_dev *i2cd)
140{
141	writel(I2C_MST_CNTL_GEN_START, i2cd->regs + I2C_MST_CNTL);
142	return gpu_i2c_check_status(i2cd);
143}
144
145static int gpu_i2c_stop(struct gpu_i2c_dev *i2cd)
146{
147	writel(I2C_MST_CNTL_GEN_STOP, i2cd->regs + I2C_MST_CNTL);
148	return gpu_i2c_check_status(i2cd);
149}
150
151static int gpu_i2c_write(struct gpu_i2c_dev *i2cd, u8 data)
152{
153	u32 val;
154
155	writel(data, i2cd->regs + I2C_MST_DATA);
156
157	val = I2C_MST_CNTL_CMD_WRITE | (1 << I2C_MST_CNTL_BURST_SIZE_SHIFT);
158	writel(val, i2cd->regs + I2C_MST_CNTL);
159
160	return gpu_i2c_check_status(i2cd);
161}
162
163static int gpu_i2c_master_xfer(struct i2c_adapter *adap,
164			       struct i2c_msg *msgs, int num)
165{
166	struct gpu_i2c_dev *i2cd = i2c_get_adapdata(adap);
167	int status, status2;
168	bool send_stop = true;
169	int i, j;
170
171	/*
172	 * The controller supports maximum 4 byte read due to known
173	 * limitation of sending STOP after every read.
174	 */
175	pm_runtime_get_sync(i2cd->dev);
176	for (i = 0; i < num; i++) {
177		if (msgs[i].flags & I2C_M_RD) {
178			/* program client address before starting read */
179			writel(msgs[i].addr, i2cd->regs + I2C_MST_ADDR);
180			/* gpu_i2c_read has implicit start */
181			status = gpu_i2c_read(i2cd, msgs[i].buf, msgs[i].len);
182			if (status < 0)
183				goto exit;
184		} else {
185			u8 addr = i2c_8bit_addr_from_msg(msgs + i);
186
187			status = gpu_i2c_start(i2cd);
188			if (status < 0) {
189				if (i == 0)
190					send_stop = false;
191				goto exit;
192			}
193
194			status = gpu_i2c_write(i2cd, addr);
195			if (status < 0)
196				goto exit;
197
198			for (j = 0; j < msgs[i].len; j++) {
199				status = gpu_i2c_write(i2cd, msgs[i].buf[j]);
200				if (status < 0)
201					goto exit;
202			}
203		}
204	}
205	send_stop = false;
206	status = gpu_i2c_stop(i2cd);
207	if (status < 0)
208		goto exit;
209
210	status = i;
211exit:
212	if (send_stop) {
213		status2 = gpu_i2c_stop(i2cd);
214		if (status2 < 0)
215			dev_err(i2cd->dev, "i2c stop failed %d\n", status2);
216	}
217	pm_runtime_mark_last_busy(i2cd->dev);
218	pm_runtime_put_autosuspend(i2cd->dev);
219	return status;
220}
221
222static const struct i2c_adapter_quirks gpu_i2c_quirks = {
223	.max_read_len = 4,
224	.max_comb_2nd_msg_len = 4,
225	.flags = I2C_AQ_COMB_WRITE_THEN_READ,
226};
227
228static u32 gpu_i2c_functionality(struct i2c_adapter *adap)
229{
230	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
231}
232
233static const struct i2c_algorithm gpu_i2c_algorithm = {
234	.master_xfer	= gpu_i2c_master_xfer,
235	.functionality	= gpu_i2c_functionality,
236};
237
238/*
239 * This driver is for Nvidia GPU cards with USB Type-C interface.
240 * We want to identify the cards using vendor ID and class code only
241 * to avoid dependency of adding product id for any new card which
242 * requires this driver.
243 * Currently there is no class code defined for UCSI device over PCI
244 * so using UNKNOWN class for now and it will be updated when UCSI
245 * over PCI gets a class code.
246 * There is no other NVIDIA cards with UNKNOWN class code. Even if the
247 * driver gets loaded for an undesired card then eventually i2c_read()
248 * (initiated from UCSI i2c_client) will timeout or UCSI commands will
249 * timeout.
250 */
251#define PCI_CLASS_SERIAL_UNKNOWN	0x0c80
252static const struct pci_device_id gpu_i2c_ids[] = {
253	{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
254		PCI_CLASS_SERIAL_UNKNOWN << 8, 0xffffff00},
255	{ }
256};
257MODULE_DEVICE_TABLE(pci, gpu_i2c_ids);
258
259static const struct property_entry ccgx_props[] = {
260	/* Use FW built for NVIDIA (nv) only */
261	PROPERTY_ENTRY_U16("ccgx,firmware-build", ('n' << 8) | 'v'),
262	{ }
263};
264
265static int gpu_populate_client(struct gpu_i2c_dev *i2cd, int irq)
266{
267	i2cd->gpu_ccgx_ucsi = devm_kzalloc(i2cd->dev,
268					   sizeof(*i2cd->gpu_ccgx_ucsi),
269					   GFP_KERNEL);
270	if (!i2cd->gpu_ccgx_ucsi)
271		return -ENOMEM;
272
273	strlcpy(i2cd->gpu_ccgx_ucsi->type, "ccgx-ucsi",
274		sizeof(i2cd->gpu_ccgx_ucsi->type));
275	i2cd->gpu_ccgx_ucsi->addr = 0x8;
276	i2cd->gpu_ccgx_ucsi->irq = irq;
277	i2cd->gpu_ccgx_ucsi->properties = ccgx_props;
278	i2cd->ccgx_client = i2c_new_client_device(&i2cd->adapter, i2cd->gpu_ccgx_ucsi);
279	return PTR_ERR_OR_ZERO(i2cd->ccgx_client);
280}
281
282static int gpu_i2c_probe(struct pci_dev *pdev, const struct pci_device_id *id)
283{
284	struct gpu_i2c_dev *i2cd;
285	int status;
286
287	i2cd = devm_kzalloc(&pdev->dev, sizeof(*i2cd), GFP_KERNEL);
288	if (!i2cd)
289		return -ENOMEM;
290
291	i2cd->dev = &pdev->dev;
292	dev_set_drvdata(&pdev->dev, i2cd);
293
294	status = pcim_enable_device(pdev);
295	if (status < 0) {
296		dev_err(&pdev->dev, "pcim_enable_device failed %d\n", status);
297		return status;
298	}
299
300	pci_set_master(pdev);
301
302	i2cd->regs = pcim_iomap(pdev, 0, 0);
303	if (!i2cd->regs) {
304		dev_err(&pdev->dev, "pcim_iomap failed\n");
305		return -ENOMEM;
306	}
307
308	status = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
309	if (status < 0) {
310		dev_err(&pdev->dev, "pci_alloc_irq_vectors err %d\n", status);
311		return status;
312	}
313
314	gpu_enable_i2c_bus(i2cd);
315
316	i2c_set_adapdata(&i2cd->adapter, i2cd);
317	i2cd->adapter.owner = THIS_MODULE;
318	strlcpy(i2cd->adapter.name, "NVIDIA GPU I2C adapter",
319		sizeof(i2cd->adapter.name));
320	i2cd->adapter.algo = &gpu_i2c_algorithm;
321	i2cd->adapter.quirks = &gpu_i2c_quirks;
322	i2cd->adapter.dev.parent = &pdev->dev;
323	status = i2c_add_adapter(&i2cd->adapter);
324	if (status < 0)
325		goto free_irq_vectors;
326
327	status = gpu_populate_client(i2cd, pdev->irq);
328	if (status < 0) {
329		dev_err(&pdev->dev, "gpu_populate_client failed %d\n", status);
330		goto del_adapter;
331	}
332
333	pm_runtime_set_autosuspend_delay(&pdev->dev, 3000);
334	pm_runtime_use_autosuspend(&pdev->dev);
335	pm_runtime_put_autosuspend(&pdev->dev);
336	pm_runtime_allow(&pdev->dev);
337
338	return 0;
339
340del_adapter:
341	i2c_del_adapter(&i2cd->adapter);
342free_irq_vectors:
343	pci_free_irq_vectors(pdev);
344	return status;
345}
346
347static void gpu_i2c_remove(struct pci_dev *pdev)
348{
349	struct gpu_i2c_dev *i2cd = dev_get_drvdata(&pdev->dev);
350
351	pm_runtime_get_noresume(i2cd->dev);
352	i2c_del_adapter(&i2cd->adapter);
353	pci_free_irq_vectors(pdev);
354}
355
356/*
357 * We need gpu_i2c_suspend() even if it is stub, for runtime pm to work
358 * correctly. Without it, lspci shows runtime pm status as "D0" for the card.
359 * Documentation/power/pci.rst also insists for driver to provide this.
360 */
361static __maybe_unused int gpu_i2c_suspend(struct device *dev)
362{
363	return 0;
364}
365
366static __maybe_unused int gpu_i2c_resume(struct device *dev)
367{
368	struct gpu_i2c_dev *i2cd = dev_get_drvdata(dev);
369
370	gpu_enable_i2c_bus(i2cd);
371	/*
372	 * Runtime resume ccgx client so that it can see for any
373	 * connector change event. Old ccg firmware has known
374	 * issue of not triggering interrupt when a device is
375	 * connected to runtime resume the controller.
376	 */
377	pm_request_resume(&i2cd->ccgx_client->dev);
378	return 0;
379}
380
381static UNIVERSAL_DEV_PM_OPS(gpu_i2c_driver_pm, gpu_i2c_suspend, gpu_i2c_resume,
382			    NULL);
383
384static struct pci_driver gpu_i2c_driver = {
385	.name		= "nvidia-gpu",
386	.id_table	= gpu_i2c_ids,
387	.probe		= gpu_i2c_probe,
388	.remove		= gpu_i2c_remove,
389	.driver		= {
390		.pm	= &gpu_i2c_driver_pm,
391	},
392};
393
394module_pci_driver(gpu_i2c_driver);
395
396MODULE_AUTHOR("Ajay Gupta <ajayg@nvidia.com>");
397MODULE_DESCRIPTION("Nvidia GPU I2C controller Driver");
398MODULE_LICENSE("GPL v2");
399