1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Nuvoton NPCM7xx I2C Controller driver 4 * 5 * Copyright (C) 2020 Nuvoton Technologies tali.perry@nuvoton.com 6 */ 7#include <linux/bitfield.h> 8#include <linux/clk.h> 9#include <linux/debugfs.h> 10#include <linux/errno.h> 11#include <linux/i2c.h> 12#include <linux/interrupt.h> 13#include <linux/iopoll.h> 14#include <linux/irq.h> 15#include <linux/jiffies.h> 16#include <linux/kernel.h> 17#include <linux/mfd/syscon.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/platform_device.h> 21#include <linux/regmap.h> 22 23enum i2c_mode { 24 I2C_MASTER, 25 I2C_SLAVE, 26}; 27 28/* 29 * External I2C Interface driver xfer indication values, which indicate status 30 * of the bus. 31 */ 32enum i2c_state_ind { 33 I2C_NO_STATUS_IND = 0, 34 I2C_SLAVE_RCV_IND, 35 I2C_SLAVE_XMIT_IND, 36 I2C_SLAVE_XMIT_MISSING_DATA_IND, 37 I2C_SLAVE_RESTART_IND, 38 I2C_SLAVE_DONE_IND, 39 I2C_MASTER_DONE_IND, 40 I2C_NACK_IND, 41 I2C_BUS_ERR_IND, 42 I2C_WAKE_UP_IND, 43 I2C_BLOCK_BYTES_ERR_IND, 44 I2C_SLAVE_RCV_MISSING_DATA_IND, 45}; 46 47/* 48 * Operation type values (used to define the operation currently running) 49 * module is interrupt driven, on each interrupt the current operation is 50 * checked to see if the module is currently reading or writing. 51 */ 52enum i2c_oper { 53 I2C_NO_OPER = 0, 54 I2C_WRITE_OPER, 55 I2C_READ_OPER, 56}; 57 58/* I2C Bank (module had 2 banks of registers) */ 59enum i2c_bank { 60 I2C_BANK_0 = 0, 61 I2C_BANK_1, 62}; 63 64/* Internal I2C states values (for the I2C module state machine). */ 65enum i2c_state { 66 I2C_DISABLE = 0, 67 I2C_IDLE, 68 I2C_MASTER_START, 69 I2C_SLAVE_MATCH, 70 I2C_OPER_STARTED, 71 I2C_STOP_PENDING, 72}; 73 74#if IS_ENABLED(CONFIG_I2C_SLAVE) 75/* Module supports setting multiple own slave addresses */ 76enum i2c_addr { 77 I2C_SLAVE_ADDR1 = 0, 78 I2C_SLAVE_ADDR2, 79 I2C_SLAVE_ADDR3, 80 I2C_SLAVE_ADDR4, 81 I2C_SLAVE_ADDR5, 82 I2C_SLAVE_ADDR6, 83 I2C_SLAVE_ADDR7, 84 I2C_SLAVE_ADDR8, 85 I2C_SLAVE_ADDR9, 86 I2C_SLAVE_ADDR10, 87 I2C_GC_ADDR, 88 I2C_ARP_ADDR, 89}; 90#endif 91 92/* init register and default value required to enable module */ 93#define NPCM_I2CSEGCTL 0xE4 94#define NPCM_I2CSEGCTL_INIT_VAL 0x0333F000 95 96/* Common regs */ 97#define NPCM_I2CSDA 0x00 98#define NPCM_I2CST 0x02 99#define NPCM_I2CCST 0x04 100#define NPCM_I2CCTL1 0x06 101#define NPCM_I2CADDR1 0x08 102#define NPCM_I2CCTL2 0x0A 103#define NPCM_I2CADDR2 0x0C 104#define NPCM_I2CCTL3 0x0E 105#define NPCM_I2CCST2 0x18 106#define NPCM_I2CCST3 0x19 107#define I2C_VER 0x1F 108 109/*BANK0 regs*/ 110#define NPCM_I2CADDR3 0x10 111#define NPCM_I2CADDR7 0x11 112#define NPCM_I2CADDR4 0x12 113#define NPCM_I2CADDR8 0x13 114#define NPCM_I2CADDR5 0x14 115#define NPCM_I2CADDR9 0x15 116#define NPCM_I2CADDR6 0x16 117#define NPCM_I2CADDR10 0x17 118 119#if IS_ENABLED(CONFIG_I2C_SLAVE) 120/* 121 * npcm_i2caddr array: 122 * The module supports having multiple own slave addresses. 123 * Since the addr regs are sprinkled all over the address space, 124 * use this array to get the address or each register. 125 */ 126#define I2C_NUM_OWN_ADDR 2 127#define I2C_NUM_OWN_ADDR_SUPPORTED 2 128 129static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { 130 NPCM_I2CADDR1, NPCM_I2CADDR2, 131}; 132#endif 133 134#define NPCM_I2CCTL4 0x1A 135#define NPCM_I2CCTL5 0x1B 136#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ 137#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ 138#define NPCM_I2CSCLHT 0x1E /* SCL High Time */ 139 140/* BANK 1 regs */ 141#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ 142#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ 143#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ 144#define NPCM_I2CPEC 0x16 /* PEC Data */ 145#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ 146#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ 147#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ 148 149/* NPCM_I2CST reg fields */ 150#define NPCM_I2CST_XMIT BIT(0) 151#define NPCM_I2CST_MASTER BIT(1) 152#define NPCM_I2CST_NMATCH BIT(2) 153#define NPCM_I2CST_STASTR BIT(3) 154#define NPCM_I2CST_NEGACK BIT(4) 155#define NPCM_I2CST_BER BIT(5) 156#define NPCM_I2CST_SDAST BIT(6) 157#define NPCM_I2CST_SLVSTP BIT(7) 158 159/* NPCM_I2CCST reg fields */ 160#define NPCM_I2CCST_BUSY BIT(0) 161#define NPCM_I2CCST_BB BIT(1) 162#define NPCM_I2CCST_MATCH BIT(2) 163#define NPCM_I2CCST_GCMATCH BIT(3) 164#define NPCM_I2CCST_TSDA BIT(4) 165#define NPCM_I2CCST_TGSCL BIT(5) 166#define NPCM_I2CCST_MATCHAF BIT(6) 167#define NPCM_I2CCST_ARPMATCH BIT(7) 168 169/* NPCM_I2CCTL1 reg fields */ 170#define NPCM_I2CCTL1_START BIT(0) 171#define NPCM_I2CCTL1_STOP BIT(1) 172#define NPCM_I2CCTL1_INTEN BIT(2) 173#define NPCM_I2CCTL1_EOBINTE BIT(3) 174#define NPCM_I2CCTL1_ACK BIT(4) 175#define NPCM_I2CCTL1_GCMEN BIT(5) 176#define NPCM_I2CCTL1_NMINTE BIT(6) 177#define NPCM_I2CCTL1_STASTRE BIT(7) 178 179/* RW1S fields (inside a RW reg): */ 180#define NPCM_I2CCTL1_RWS \ 181 (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK) 182 183/* npcm_i2caddr reg fields */ 184#define NPCM_I2CADDR_A GENMASK(6, 0) 185#define NPCM_I2CADDR_SAEN BIT(7) 186 187/* NPCM_I2CCTL2 reg fields */ 188#define I2CCTL2_ENABLE BIT(0) 189#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) 190 191/* NPCM_I2CCTL3 reg fields */ 192#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) 193#define I2CCTL3_ARPMEN BIT(2) 194#define I2CCTL3_IDL_START BIT(3) 195#define I2CCTL3_400K_MODE BIT(4) 196#define I2CCTL3_BNK_SEL BIT(5) 197#define I2CCTL3_SDA_LVL BIT(6) 198#define I2CCTL3_SCL_LVL BIT(7) 199 200/* NPCM_I2CCST2 reg fields */ 201#define NPCM_I2CCST2_MATCHA1F BIT(0) 202#define NPCM_I2CCST2_MATCHA2F BIT(1) 203#define NPCM_I2CCST2_MATCHA3F BIT(2) 204#define NPCM_I2CCST2_MATCHA4F BIT(3) 205#define NPCM_I2CCST2_MATCHA5F BIT(4) 206#define NPCM_I2CCST2_MATCHA6F BIT(5) 207#define NPCM_I2CCST2_MATCHA7F BIT(5) 208#define NPCM_I2CCST2_INTSTS BIT(7) 209 210/* NPCM_I2CCST3 reg fields */ 211#define NPCM_I2CCST3_MATCHA8F BIT(0) 212#define NPCM_I2CCST3_MATCHA9F BIT(1) 213#define NPCM_I2CCST3_MATCHA10F BIT(2) 214#define NPCM_I2CCST3_EO_BUSY BIT(7) 215 216/* NPCM_I2CCTL4 reg fields */ 217#define I2CCTL4_HLDT GENMASK(5, 0) 218#define I2CCTL4_LVL_WE BIT(7) 219 220/* NPCM_I2CCTL5 reg fields */ 221#define I2CCTL5_DBNCT GENMASK(3, 0) 222 223/* NPCM_I2CFIF_CTS reg fields */ 224#define NPCM_I2CFIF_CTS_RXF_TXE BIT(1) 225#define NPCM_I2CFIF_CTS_RFTE_IE BIT(3) 226#define NPCM_I2CFIF_CTS_CLR_FIFO BIT(6) 227#define NPCM_I2CFIF_CTS_SLVRSTR BIT(7) 228 229/* NPCM_I2CTXF_CTL reg fields */ 230#define NPCM_I2CTXF_CTL_TX_THR GENMASK(4, 0) 231#define NPCM_I2CTXF_CTL_THR_TXIE BIT(6) 232 233/* NPCM_I2CT_OUT reg fields */ 234#define NPCM_I2CT_OUT_TO_CKDIV GENMASK(5, 0) 235#define NPCM_I2CT_OUT_T_OUTIE BIT(6) 236#define NPCM_I2CT_OUT_T_OUTST BIT(7) 237 238/* NPCM_I2CTXF_STS reg fields */ 239#define NPCM_I2CTXF_STS_TX_BYTES GENMASK(4, 0) 240#define NPCM_I2CTXF_STS_TX_THST BIT(6) 241 242/* NPCM_I2CRXF_STS reg fields */ 243#define NPCM_I2CRXF_STS_RX_BYTES GENMASK(4, 0) 244#define NPCM_I2CRXF_STS_RX_THST BIT(6) 245 246/* NPCM_I2CFIF_CTL reg fields */ 247#define NPCM_I2CFIF_CTL_FIFO_EN BIT(4) 248 249/* NPCM_I2CRXF_CTL reg fields */ 250#define NPCM_I2CRXF_CTL_RX_THR GENMASK(4, 0) 251#define NPCM_I2CRXF_CTL_LAST_PEC BIT(5) 252#define NPCM_I2CRXF_CTL_THR_RXIE BIT(6) 253 254#define I2C_HW_FIFO_SIZE 16 255 256/* I2C_VER reg fields */ 257#define I2C_VER_VERSION GENMASK(6, 0) 258#define I2C_VER_FIFO_EN BIT(7) 259 260/* stall/stuck timeout in us */ 261#define DEFAULT_STALL_COUNT 25 262 263/* SCLFRQ field position */ 264#define SCLFRQ_0_TO_6 GENMASK(6, 0) 265#define SCLFRQ_7_TO_8 GENMASK(8, 7) 266 267/* supported clk settings. values in Hz. */ 268#define I2C_FREQ_MIN_HZ 10000 269#define I2C_FREQ_MAX_HZ I2C_MAX_FAST_MODE_PLUS_FREQ 270 271/* Status of one I2C module */ 272struct npcm_i2c { 273 struct i2c_adapter adap; 274 struct device *dev; 275 unsigned char __iomem *reg; 276 spinlock_t lock; /* IRQ synchronization */ 277 struct completion cmd_complete; 278 int cmd_err; 279 struct i2c_msg *msgs; 280 int msgs_num; 281 int num; 282 u32 apb_clk; 283 struct i2c_bus_recovery_info rinfo; 284 enum i2c_state state; 285 enum i2c_oper operation; 286 enum i2c_mode master_or_slave; 287 enum i2c_state_ind stop_ind; 288 u8 dest_addr; 289 u8 *rd_buf; 290 u16 rd_size; 291 u16 rd_ind; 292 u8 *wr_buf; 293 u16 wr_size; 294 u16 wr_ind; 295 bool fifo_use; 296 u16 PEC_mask; /* PEC bit mask per slave address */ 297 bool PEC_use; 298 bool read_block_use; 299 unsigned long int_time_stamp; 300 unsigned long bus_freq; /* in Hz */ 301#if IS_ENABLED(CONFIG_I2C_SLAVE) 302 u8 own_slave_addr; 303 struct i2c_client *slave; 304 int slv_rd_size; 305 int slv_rd_ind; 306 int slv_wr_size; 307 int slv_wr_ind; 308 u8 slv_rd_buf[I2C_HW_FIFO_SIZE]; 309 u8 slv_wr_buf[I2C_HW_FIFO_SIZE]; 310#endif 311 struct dentry *debugfs; /* debugfs device directory */ 312 u64 ber_cnt; 313 u64 rec_succ_cnt; 314 u64 rec_fail_cnt; 315 u64 nack_cnt; 316 u64 timeout_cnt; 317}; 318 319static inline void npcm_i2c_select_bank(struct npcm_i2c *bus, 320 enum i2c_bank bank) 321{ 322 u8 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 323 324 if (bank == I2C_BANK_0) 325 i2cctl3 = i2cctl3 & ~I2CCTL3_BNK_SEL; 326 else 327 i2cctl3 = i2cctl3 | I2CCTL3_BNK_SEL; 328 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 329} 330 331static void npcm_i2c_init_params(struct npcm_i2c *bus) 332{ 333 bus->stop_ind = I2C_NO_STATUS_IND; 334 bus->rd_size = 0; 335 bus->wr_size = 0; 336 bus->rd_ind = 0; 337 bus->wr_ind = 0; 338 bus->read_block_use = false; 339 bus->int_time_stamp = 0; 340 bus->PEC_use = false; 341 bus->PEC_mask = 0; 342#if IS_ENABLED(CONFIG_I2C_SLAVE) 343 if (bus->slave) 344 bus->master_or_slave = I2C_SLAVE; 345#endif 346} 347 348static inline void npcm_i2c_wr_byte(struct npcm_i2c *bus, u8 data) 349{ 350 iowrite8(data, bus->reg + NPCM_I2CSDA); 351} 352 353static inline u8 npcm_i2c_rd_byte(struct npcm_i2c *bus) 354{ 355 return ioread8(bus->reg + NPCM_I2CSDA); 356} 357 358static int npcm_i2c_get_SCL(struct i2c_adapter *_adap) 359{ 360 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 361 362 return !!(I2CCTL3_SCL_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 363} 364 365static int npcm_i2c_get_SDA(struct i2c_adapter *_adap) 366{ 367 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 368 369 return !!(I2CCTL3_SDA_LVL & ioread8(bus->reg + NPCM_I2CCTL3)); 370} 371 372static inline u16 npcm_i2c_get_index(struct npcm_i2c *bus) 373{ 374 if (bus->operation == I2C_READ_OPER) 375 return bus->rd_ind; 376 if (bus->operation == I2C_WRITE_OPER) 377 return bus->wr_ind; 378 return 0; 379} 380 381/* quick protocol (just address) */ 382static inline bool npcm_i2c_is_quick(struct npcm_i2c *bus) 383{ 384 return bus->wr_size == 0 && bus->rd_size == 0; 385} 386 387static void npcm_i2c_disable(struct npcm_i2c *bus) 388{ 389 u8 i2cctl2; 390 391#if IS_ENABLED(CONFIG_I2C_SLAVE) 392 int i; 393 394 /* Slave addresses removal */ 395 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) 396 iowrite8(0, bus->reg + npcm_i2caddr[i]); 397 398#endif 399 /* Disable module */ 400 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 401 i2cctl2 = i2cctl2 & ~I2CCTL2_ENABLE; 402 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 403 404 bus->state = I2C_DISABLE; 405} 406 407static void npcm_i2c_enable(struct npcm_i2c *bus) 408{ 409 u8 i2cctl2 = ioread8(bus->reg + NPCM_I2CCTL2); 410 411 i2cctl2 = i2cctl2 | I2CCTL2_ENABLE; 412 iowrite8(i2cctl2, bus->reg + NPCM_I2CCTL2); 413 bus->state = I2C_IDLE; 414} 415 416/* enable\disable end of busy (EOB) interrupts */ 417static inline void npcm_i2c_eob_int(struct npcm_i2c *bus, bool enable) 418{ 419 u8 val; 420 421 /* Clear EO_BUSY pending bit: */ 422 val = ioread8(bus->reg + NPCM_I2CCST3); 423 val = val | NPCM_I2CCST3_EO_BUSY; 424 iowrite8(val, bus->reg + NPCM_I2CCST3); 425 426 val = ioread8(bus->reg + NPCM_I2CCTL1); 427 val &= ~NPCM_I2CCTL1_RWS; 428 if (enable) 429 val |= NPCM_I2CCTL1_EOBINTE; 430 else 431 val &= ~NPCM_I2CCTL1_EOBINTE; 432 iowrite8(val, bus->reg + NPCM_I2CCTL1); 433} 434 435static inline bool npcm_i2c_tx_fifo_empty(struct npcm_i2c *bus) 436{ 437 u8 tx_fifo_sts; 438 439 tx_fifo_sts = ioread8(bus->reg + NPCM_I2CTXF_STS); 440 /* check if TX FIFO is not empty */ 441 if ((tx_fifo_sts & NPCM_I2CTXF_STS_TX_BYTES) == 0) 442 return false; 443 444 /* check if TX FIFO status bit is set: */ 445 return !!FIELD_GET(NPCM_I2CTXF_STS_TX_THST, tx_fifo_sts); 446} 447 448static inline bool npcm_i2c_rx_fifo_full(struct npcm_i2c *bus) 449{ 450 u8 rx_fifo_sts; 451 452 rx_fifo_sts = ioread8(bus->reg + NPCM_I2CRXF_STS); 453 /* check if RX FIFO is not empty: */ 454 if ((rx_fifo_sts & NPCM_I2CRXF_STS_RX_BYTES) == 0) 455 return false; 456 457 /* check if rx fifo full status is set: */ 458 return !!FIELD_GET(NPCM_I2CRXF_STS_RX_THST, rx_fifo_sts); 459} 460 461static inline void npcm_i2c_clear_fifo_int(struct npcm_i2c *bus) 462{ 463 u8 val; 464 465 val = ioread8(bus->reg + NPCM_I2CFIF_CTS); 466 val = (val & NPCM_I2CFIF_CTS_SLVRSTR) | NPCM_I2CFIF_CTS_RXF_TXE; 467 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 468} 469 470static inline void npcm_i2c_clear_tx_fifo(struct npcm_i2c *bus) 471{ 472 u8 val; 473 474 val = ioread8(bus->reg + NPCM_I2CTXF_STS); 475 val = val | NPCM_I2CTXF_STS_TX_THST; 476 iowrite8(val, bus->reg + NPCM_I2CTXF_STS); 477} 478 479static inline void npcm_i2c_clear_rx_fifo(struct npcm_i2c *bus) 480{ 481 u8 val; 482 483 val = ioread8(bus->reg + NPCM_I2CRXF_STS); 484 val = val | NPCM_I2CRXF_STS_RX_THST; 485 iowrite8(val, bus->reg + NPCM_I2CRXF_STS); 486} 487 488static void npcm_i2c_int_enable(struct npcm_i2c *bus, bool enable) 489{ 490 u8 val; 491 492 val = ioread8(bus->reg + NPCM_I2CCTL1); 493 val &= ~NPCM_I2CCTL1_RWS; 494 if (enable) 495 val |= NPCM_I2CCTL1_INTEN; 496 else 497 val &= ~NPCM_I2CCTL1_INTEN; 498 iowrite8(val, bus->reg + NPCM_I2CCTL1); 499} 500 501static inline void npcm_i2c_master_start(struct npcm_i2c *bus) 502{ 503 u8 val; 504 505 val = ioread8(bus->reg + NPCM_I2CCTL1); 506 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK); 507 val |= NPCM_I2CCTL1_START; 508 iowrite8(val, bus->reg + NPCM_I2CCTL1); 509} 510 511static inline void npcm_i2c_master_stop(struct npcm_i2c *bus) 512{ 513 u8 val; 514 515 /* 516 * override HW issue: I2C may fail to supply stop condition in Master 517 * Write operation. 518 * Need to delay at least 5 us from the last int, before issueing a stop 519 */ 520 udelay(10); /* function called from interrupt, can't sleep */ 521 val = ioread8(bus->reg + NPCM_I2CCTL1); 522 val &= ~(NPCM_I2CCTL1_START | NPCM_I2CCTL1_ACK); 523 val |= NPCM_I2CCTL1_STOP; 524 iowrite8(val, bus->reg + NPCM_I2CCTL1); 525 526 if (!bus->fifo_use) 527 return; 528 529 npcm_i2c_select_bank(bus, I2C_BANK_1); 530 531 if (bus->operation == I2C_READ_OPER) 532 npcm_i2c_clear_rx_fifo(bus); 533 else 534 npcm_i2c_clear_tx_fifo(bus); 535 npcm_i2c_clear_fifo_int(bus); 536 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 537} 538 539static inline void npcm_i2c_stall_after_start(struct npcm_i2c *bus, bool stall) 540{ 541 u8 val; 542 543 val = ioread8(bus->reg + NPCM_I2CCTL1); 544 val &= ~NPCM_I2CCTL1_RWS; 545 if (stall) 546 val |= NPCM_I2CCTL1_STASTRE; 547 else 548 val &= ~NPCM_I2CCTL1_STASTRE; 549 iowrite8(val, bus->reg + NPCM_I2CCTL1); 550} 551 552static inline void npcm_i2c_nack(struct npcm_i2c *bus) 553{ 554 u8 val; 555 556 val = ioread8(bus->reg + NPCM_I2CCTL1); 557 val &= ~(NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_START); 558 val |= NPCM_I2CCTL1_ACK; 559 iowrite8(val, bus->reg + NPCM_I2CCTL1); 560} 561 562static inline void npcm_i2c_clear_master_status(struct npcm_i2c *bus) 563{ 564 u8 val; 565 566 /* Clear NEGACK, STASTR and BER bits */ 567 val = NPCM_I2CST_BER | NPCM_I2CST_NEGACK | NPCM_I2CST_STASTR; 568 iowrite8(val, bus->reg + NPCM_I2CST); 569} 570 571#if IS_ENABLED(CONFIG_I2C_SLAVE) 572static void npcm_i2c_slave_int_enable(struct npcm_i2c *bus, bool enable) 573{ 574 u8 i2cctl1; 575 576 /* enable interrupt on slave match: */ 577 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 578 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 579 if (enable) 580 i2cctl1 |= NPCM_I2CCTL1_NMINTE; 581 else 582 i2cctl1 &= ~NPCM_I2CCTL1_NMINTE; 583 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 584} 585 586static int npcm_i2c_slave_enable(struct npcm_i2c *bus, enum i2c_addr addr_type, 587 u8 addr, bool enable) 588{ 589 u8 i2cctl1; 590 u8 i2cctl3; 591 u8 sa_reg; 592 593 sa_reg = (addr & 0x7F) | FIELD_PREP(NPCM_I2CADDR_SAEN, enable); 594 if (addr_type == I2C_GC_ADDR) { 595 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 596 if (enable) 597 i2cctl1 |= NPCM_I2CCTL1_GCMEN; 598 else 599 i2cctl1 &= ~NPCM_I2CCTL1_GCMEN; 600 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 601 return 0; 602 } else if (addr_type == I2C_ARP_ADDR) { 603 i2cctl3 = ioread8(bus->reg + NPCM_I2CCTL3); 604 if (enable) 605 i2cctl3 |= I2CCTL3_ARPMEN; 606 else 607 i2cctl3 &= ~I2CCTL3_ARPMEN; 608 iowrite8(i2cctl3, bus->reg + NPCM_I2CCTL3); 609 return 0; 610 } 611 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 612 dev_err(bus->dev, "try to enable more than 2 SA not supported\n"); 613 614 if (addr_type >= I2C_ARP_ADDR) 615 return -EFAULT; 616 617 /* Set and enable the address */ 618 iowrite8(sa_reg, bus->reg + npcm_i2caddr[addr_type]); 619 npcm_i2c_slave_int_enable(bus, enable); 620 621 return 0; 622} 623#endif 624 625static void npcm_i2c_reset(struct npcm_i2c *bus) 626{ 627 /* 628 * Save I2CCTL1 relevant bits. It is being cleared when the module 629 * is disabled. 630 */ 631 u8 i2cctl1; 632#if IS_ENABLED(CONFIG_I2C_SLAVE) 633 u8 addr; 634#endif 635 636 i2cctl1 = ioread8(bus->reg + NPCM_I2CCTL1); 637 638 npcm_i2c_disable(bus); 639 npcm_i2c_enable(bus); 640 641 /* Restore NPCM_I2CCTL1 Status */ 642 i2cctl1 &= ~NPCM_I2CCTL1_RWS; 643 iowrite8(i2cctl1, bus->reg + NPCM_I2CCTL1); 644 645 /* Clear BB (BUS BUSY) bit */ 646 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 647 iowrite8(0xFF, bus->reg + NPCM_I2CST); 648 649 /* Clear and disable EOB */ 650 npcm_i2c_eob_int(bus, false); 651 652 /* Clear all fifo bits: */ 653 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 654 655#if IS_ENABLED(CONFIG_I2C_SLAVE) 656 if (bus->slave) { 657 addr = bus->slave->addr; 658 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, addr, true); 659 } 660#endif 661 662 /* clear status bits for spurious interrupts */ 663 npcm_i2c_clear_master_status(bus); 664 665 bus->state = I2C_IDLE; 666} 667 668static inline bool npcm_i2c_is_master(struct npcm_i2c *bus) 669{ 670 return !!FIELD_GET(NPCM_I2CST_MASTER, ioread8(bus->reg + NPCM_I2CST)); 671} 672 673static void npcm_i2c_callback(struct npcm_i2c *bus, 674 enum i2c_state_ind op_status, u16 info) 675{ 676 struct i2c_msg *msgs; 677 int msgs_num; 678 bool do_complete = false; 679 680 msgs = bus->msgs; 681 msgs_num = bus->msgs_num; 682 /* 683 * check that transaction was not timed-out, and msgs still 684 * holds a valid value. 685 */ 686 if (!msgs) 687 return; 688 689 if (completion_done(&bus->cmd_complete)) 690 return; 691 692 switch (op_status) { 693 case I2C_MASTER_DONE_IND: 694 bus->cmd_err = bus->msgs_num; 695 fallthrough; 696 case I2C_BLOCK_BYTES_ERR_IND: 697 /* Master tx finished and all transmit bytes were sent */ 698 if (bus->msgs) { 699 if (msgs[0].flags & I2C_M_RD) 700 msgs[0].len = info; 701 else if (msgs_num == 2 && 702 msgs[1].flags & I2C_M_RD) 703 msgs[1].len = info; 704 } 705 do_complete = true; 706 break; 707 case I2C_NACK_IND: 708 /* MASTER transmit got a NACK before tx all bytes */ 709 bus->cmd_err = -ENXIO; 710 do_complete = true; 711 break; 712 case I2C_BUS_ERR_IND: 713 /* Bus error */ 714 bus->cmd_err = -EAGAIN; 715 do_complete = true; 716 break; 717 case I2C_WAKE_UP_IND: 718 /* I2C wake up */ 719 break; 720 default: 721 break; 722 } 723 724 bus->operation = I2C_NO_OPER; 725#if IS_ENABLED(CONFIG_I2C_SLAVE) 726 if (bus->slave) 727 bus->master_or_slave = I2C_SLAVE; 728#endif 729 if (do_complete) 730 complete(&bus->cmd_complete); 731} 732 733static u8 npcm_i2c_fifo_usage(struct npcm_i2c *bus) 734{ 735 if (bus->operation == I2C_WRITE_OPER) 736 return FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES, 737 ioread8(bus->reg + NPCM_I2CTXF_STS)); 738 if (bus->operation == I2C_READ_OPER) 739 return FIELD_GET(NPCM_I2CRXF_STS_RX_BYTES, 740 ioread8(bus->reg + NPCM_I2CRXF_STS)); 741 return 0; 742} 743 744static void npcm_i2c_write_to_fifo_master(struct npcm_i2c *bus, u16 max_bytes) 745{ 746 u8 size_free_fifo; 747 748 /* 749 * Fill the FIFO, while the FIFO is not full and there are more bytes 750 * to write 751 */ 752 size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus); 753 while (max_bytes-- && size_free_fifo) { 754 if (bus->wr_ind < bus->wr_size) 755 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 756 else 757 npcm_i2c_wr_byte(bus, 0xFF); 758 size_free_fifo = I2C_HW_FIFO_SIZE - npcm_i2c_fifo_usage(bus); 759 } 760} 761 762/* 763 * npcm_i2c_set_fifo: 764 * configure the FIFO before using it. If nread is -1 RX FIFO will not be 765 * configured. same for nwrite 766 */ 767static void npcm_i2c_set_fifo(struct npcm_i2c *bus, int nread, int nwrite) 768{ 769 u8 rxf_ctl = 0; 770 771 if (!bus->fifo_use) 772 return; 773 npcm_i2c_select_bank(bus, I2C_BANK_1); 774 npcm_i2c_clear_tx_fifo(bus); 775 npcm_i2c_clear_rx_fifo(bus); 776 777 /* configure RX FIFO */ 778 if (nread > 0) { 779 rxf_ctl = min_t(int, nread, I2C_HW_FIFO_SIZE); 780 781 /* set LAST bit. if LAST is set next FIFO packet is nacked */ 782 if (nread <= I2C_HW_FIFO_SIZE) 783 rxf_ctl |= NPCM_I2CRXF_CTL_LAST_PEC; 784 785 /* 786 * if we are about to read the first byte in blk rd mode, 787 * don't NACK it. If slave returns zero size HW can't NACK 788 * it immidiattly, it will read extra byte and then NACK. 789 */ 790 if (bus->rd_ind == 0 && bus->read_block_use) { 791 /* set fifo to read one byte, no last: */ 792 rxf_ctl = 1; 793 } 794 795 /* set fifo size: */ 796 iowrite8(rxf_ctl, bus->reg + NPCM_I2CRXF_CTL); 797 } 798 799 /* configure TX FIFO */ 800 if (nwrite > 0) { 801 if (nwrite > I2C_HW_FIFO_SIZE) 802 /* data to send is more then FIFO size. */ 803 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CTXF_CTL); 804 else 805 iowrite8(nwrite, bus->reg + NPCM_I2CTXF_CTL); 806 807 npcm_i2c_clear_tx_fifo(bus); 808 } 809} 810 811static void npcm_i2c_read_fifo(struct npcm_i2c *bus, u8 bytes_in_fifo) 812{ 813 u8 data; 814 815 while (bytes_in_fifo--) { 816 data = npcm_i2c_rd_byte(bus); 817 if (bus->rd_ind < bus->rd_size) 818 bus->rd_buf[bus->rd_ind++] = data; 819 } 820} 821 822static void npcm_i2c_master_abort(struct npcm_i2c *bus) 823{ 824 /* Only current master is allowed to issue a stop condition */ 825 if (!npcm_i2c_is_master(bus)) 826 return; 827 828 npcm_i2c_eob_int(bus, true); 829 npcm_i2c_master_stop(bus); 830 npcm_i2c_clear_master_status(bus); 831} 832 833#if IS_ENABLED(CONFIG_I2C_SLAVE) 834static u8 npcm_i2c_get_slave_addr(struct npcm_i2c *bus, enum i2c_addr addr_type) 835{ 836 u8 slave_add; 837 838 if (addr_type > I2C_SLAVE_ADDR2 && addr_type <= I2C_SLAVE_ADDR10) 839 dev_err(bus->dev, "get slave: try to use more than 2 SA not supported\n"); 840 841 slave_add = ioread8(bus->reg + npcm_i2caddr[(int)addr_type]); 842 843 return slave_add; 844} 845 846static int npcm_i2c_remove_slave_addr(struct npcm_i2c *bus, u8 slave_add) 847{ 848 int i; 849 850 /* Set the enable bit */ 851 slave_add |= 0x80; 852 853 for (i = I2C_SLAVE_ADDR1; i < I2C_NUM_OWN_ADDR_SUPPORTED; i++) { 854 if (ioread8(bus->reg + npcm_i2caddr[i]) == slave_add) 855 iowrite8(0, bus->reg + npcm_i2caddr[i]); 856 } 857 858 return 0; 859} 860 861static void npcm_i2c_write_fifo_slave(struct npcm_i2c *bus, u16 max_bytes) 862{ 863 /* 864 * Fill the FIFO, while the FIFO is not full and there are more bytes 865 * to write 866 */ 867 npcm_i2c_clear_fifo_int(bus); 868 npcm_i2c_clear_tx_fifo(bus); 869 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 870 while (max_bytes-- && I2C_HW_FIFO_SIZE != npcm_i2c_fifo_usage(bus)) { 871 if (bus->slv_wr_size <= 0) 872 break; 873 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE; 874 npcm_i2c_wr_byte(bus, bus->slv_wr_buf[bus->slv_wr_ind]); 875 bus->slv_wr_ind++; 876 bus->slv_wr_ind = bus->slv_wr_ind % I2C_HW_FIFO_SIZE; 877 bus->slv_wr_size--; 878 } 879} 880 881static void npcm_i2c_read_fifo_slave(struct npcm_i2c *bus, u8 bytes_in_fifo) 882{ 883 u8 data; 884 885 if (!bus->slave) 886 return; 887 888 while (bytes_in_fifo--) { 889 data = npcm_i2c_rd_byte(bus); 890 891 bus->slv_rd_ind = bus->slv_rd_ind % I2C_HW_FIFO_SIZE; 892 bus->slv_rd_buf[bus->slv_rd_ind] = data; 893 bus->slv_rd_ind++; 894 895 /* 1st byte is length in block protocol: */ 896 if (bus->slv_rd_ind == 1 && bus->read_block_use) 897 bus->slv_rd_size = data + bus->PEC_use + 1; 898 } 899} 900 901static int npcm_i2c_slave_get_wr_buf(struct npcm_i2c *bus) 902{ 903 int i; 904 u8 value; 905 int ind; 906 int ret = bus->slv_wr_ind; 907 908 /* fill a cyclic buffer */ 909 for (i = 0; i < I2C_HW_FIFO_SIZE; i++) { 910 if (bus->slv_wr_size >= I2C_HW_FIFO_SIZE) 911 break; 912 if (bus->state == I2C_SLAVE_MATCH) { 913 i2c_slave_event(bus->slave, I2C_SLAVE_READ_REQUESTED, &value); 914 bus->state = I2C_OPER_STARTED; 915 } else { 916 i2c_slave_event(bus->slave, I2C_SLAVE_READ_PROCESSED, &value); 917 } 918 ind = (bus->slv_wr_ind + bus->slv_wr_size) % I2C_HW_FIFO_SIZE; 919 bus->slv_wr_buf[ind] = value; 920 bus->slv_wr_size++; 921 } 922 return I2C_HW_FIFO_SIZE - ret; 923} 924 925static void npcm_i2c_slave_send_rd_buf(struct npcm_i2c *bus) 926{ 927 int i; 928 929 for (i = 0; i < bus->slv_rd_ind; i++) 930 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_RECEIVED, 931 &bus->slv_rd_buf[i]); 932 /* 933 * once we send bytes up, need to reset the counter of the wr buf 934 * got data from master (new offset in device), ignore wr fifo: 935 */ 936 if (bus->slv_rd_ind) { 937 bus->slv_wr_size = 0; 938 bus->slv_wr_ind = 0; 939 } 940 941 bus->slv_rd_ind = 0; 942 bus->slv_rd_size = bus->adap.quirks->max_read_len; 943 944 npcm_i2c_clear_fifo_int(bus); 945 npcm_i2c_clear_rx_fifo(bus); 946} 947 948static void npcm_i2c_slave_receive(struct npcm_i2c *bus, u16 nread, 949 u8 *read_data) 950{ 951 bus->state = I2C_OPER_STARTED; 952 bus->operation = I2C_READ_OPER; 953 bus->slv_rd_size = nread; 954 bus->slv_rd_ind = 0; 955 956 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 957 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL); 958 npcm_i2c_clear_tx_fifo(bus); 959 npcm_i2c_clear_rx_fifo(bus); 960} 961 962static void npcm_i2c_slave_xmit(struct npcm_i2c *bus, u16 nwrite, 963 u8 *write_data) 964{ 965 if (nwrite == 0) 966 return; 967 968 bus->operation = I2C_WRITE_OPER; 969 970 /* get the next buffer */ 971 npcm_i2c_slave_get_wr_buf(bus); 972 npcm_i2c_write_fifo_slave(bus, nwrite); 973} 974 975/* 976 * npcm_i2c_slave_wr_buf_sync: 977 * currently slave IF only supports single byte operations. 978 * in order to utilyze the npcm HW FIFO, the driver will ask for 16 bytes 979 * at a time, pack them in buffer, and then transmit them all together 980 * to the FIFO and onward to the bus. 981 * NACK on read will be once reached to bus->adap->quirks->max_read_len. 982 * sending a NACK wherever the backend requests for it is not supported. 983 * the next two functions allow reading to local buffer before writing it all 984 * to the HW FIFO. 985 */ 986static void npcm_i2c_slave_wr_buf_sync(struct npcm_i2c *bus) 987{ 988 int left_in_fifo; 989 990 left_in_fifo = FIELD_GET(NPCM_I2CTXF_STS_TX_BYTES, 991 ioread8(bus->reg + NPCM_I2CTXF_STS)); 992 993 /* fifo already full: */ 994 if (left_in_fifo >= I2C_HW_FIFO_SIZE || 995 bus->slv_wr_size >= I2C_HW_FIFO_SIZE) 996 return; 997 998 /* update the wr fifo index back to the untransmitted bytes: */ 999 bus->slv_wr_ind = bus->slv_wr_ind - left_in_fifo; 1000 bus->slv_wr_size = bus->slv_wr_size + left_in_fifo; 1001 1002 if (bus->slv_wr_ind < 0) 1003 bus->slv_wr_ind += I2C_HW_FIFO_SIZE; 1004} 1005 1006static void npcm_i2c_slave_rd_wr(struct npcm_i2c *bus) 1007{ 1008 if (NPCM_I2CST_XMIT & ioread8(bus->reg + NPCM_I2CST)) { 1009 /* 1010 * Slave got an address match with direction bit 1 so it should 1011 * transmit data. Write till the master will NACK 1012 */ 1013 bus->operation = I2C_WRITE_OPER; 1014 npcm_i2c_slave_xmit(bus, bus->adap.quirks->max_write_len, 1015 bus->slv_wr_buf); 1016 } else { 1017 /* 1018 * Slave got an address match with direction bit 0 so it should 1019 * receive data. 1020 * this module does not support saying no to bytes. 1021 * it will always ACK. 1022 */ 1023 bus->operation = I2C_READ_OPER; 1024 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1025 bus->stop_ind = I2C_SLAVE_RCV_IND; 1026 npcm_i2c_slave_send_rd_buf(bus); 1027 npcm_i2c_slave_receive(bus, bus->adap.quirks->max_read_len, 1028 bus->slv_rd_buf); 1029 } 1030} 1031 1032static irqreturn_t npcm_i2c_int_slave_handler(struct npcm_i2c *bus) 1033{ 1034 u8 val; 1035 irqreturn_t ret = IRQ_NONE; 1036 u8 i2cst = ioread8(bus->reg + NPCM_I2CST); 1037 1038 /* Slave: A NACK has occurred */ 1039 if (NPCM_I2CST_NEGACK & i2cst) { 1040 bus->stop_ind = I2C_NACK_IND; 1041 npcm_i2c_slave_wr_buf_sync(bus); 1042 if (bus->fifo_use) 1043 /* clear the FIFO */ 1044 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1045 bus->reg + NPCM_I2CFIF_CTS); 1046 1047 /* In slave write, NACK is OK, otherwise it is a problem */ 1048 bus->stop_ind = I2C_NO_STATUS_IND; 1049 bus->operation = I2C_NO_OPER; 1050 bus->own_slave_addr = 0xFF; 1051 1052 /* 1053 * Slave has to wait for STOP to decide this is the end 1054 * of the transaction. tx is not yet considered as done 1055 */ 1056 iowrite8(NPCM_I2CST_NEGACK, bus->reg + NPCM_I2CST); 1057 1058 ret = IRQ_HANDLED; 1059 } 1060 1061 /* Slave mode: a Bus Error (BER) has been identified */ 1062 if (NPCM_I2CST_BER & i2cst) { 1063 /* 1064 * Check whether bus arbitration or Start or Stop during data 1065 * xfer bus arbitration problem should not result in recovery 1066 */ 1067 bus->stop_ind = I2C_BUS_ERR_IND; 1068 1069 /* wait for bus busy before clear fifo */ 1070 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1071 1072 bus->state = I2C_IDLE; 1073 1074 /* 1075 * in BER case we might get 2 interrupts: one for slave one for 1076 * master ( for a channel which is master\slave switching) 1077 */ 1078 if (completion_done(&bus->cmd_complete) == false) { 1079 bus->cmd_err = -EIO; 1080 complete(&bus->cmd_complete); 1081 } 1082 bus->own_slave_addr = 0xFF; 1083 iowrite8(NPCM_I2CST_BER, bus->reg + NPCM_I2CST); 1084 ret = IRQ_HANDLED; 1085 } 1086 1087 /* A Slave Stop Condition has been identified */ 1088 if (NPCM_I2CST_SLVSTP & i2cst) { 1089 u8 bytes_in_fifo = npcm_i2c_fifo_usage(bus); 1090 1091 bus->stop_ind = I2C_SLAVE_DONE_IND; 1092 1093 if (bus->operation == I2C_READ_OPER) 1094 npcm_i2c_read_fifo_slave(bus, bytes_in_fifo); 1095 1096 /* if the buffer is empty nothing will be sent */ 1097 npcm_i2c_slave_send_rd_buf(bus); 1098 1099 /* Slave done transmitting or receiving */ 1100 bus->stop_ind = I2C_NO_STATUS_IND; 1101 1102 /* 1103 * Note, just because we got here, it doesn't mean we through 1104 * away the wr buffer. 1105 * we keep it until the next received offset. 1106 */ 1107 bus->operation = I2C_NO_OPER; 1108 bus->own_slave_addr = 0xFF; 1109 i2c_slave_event(bus->slave, I2C_SLAVE_STOP, 0); 1110 iowrite8(NPCM_I2CST_SLVSTP, bus->reg + NPCM_I2CST); 1111 if (bus->fifo_use) { 1112 npcm_i2c_clear_fifo_int(bus); 1113 npcm_i2c_clear_rx_fifo(bus); 1114 npcm_i2c_clear_tx_fifo(bus); 1115 1116 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, 1117 bus->reg + NPCM_I2CFIF_CTS); 1118 } 1119 bus->state = I2C_IDLE; 1120 ret = IRQ_HANDLED; 1121 } 1122 1123 /* restart condition occurred and Rx-FIFO was not empty */ 1124 if (bus->fifo_use && FIELD_GET(NPCM_I2CFIF_CTS_SLVRSTR, 1125 ioread8(bus->reg + NPCM_I2CFIF_CTS))) { 1126 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1127 bus->master_or_slave = I2C_SLAVE; 1128 if (bus->operation == I2C_READ_OPER) 1129 npcm_i2c_read_fifo_slave(bus, npcm_i2c_fifo_usage(bus)); 1130 bus->operation = I2C_WRITE_OPER; 1131 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1132 val = NPCM_I2CFIF_CTS_CLR_FIFO | NPCM_I2CFIF_CTS_SLVRSTR | 1133 NPCM_I2CFIF_CTS_RXF_TXE; 1134 iowrite8(val, bus->reg + NPCM_I2CFIF_CTS); 1135 npcm_i2c_slave_rd_wr(bus); 1136 ret = IRQ_HANDLED; 1137 } 1138 1139 /* A Slave Address Match has been identified */ 1140 if (NPCM_I2CST_NMATCH & i2cst) { 1141 u8 info = 0; 1142 1143 /* Address match automatically implies slave mode */ 1144 bus->master_or_slave = I2C_SLAVE; 1145 npcm_i2c_clear_fifo_int(bus); 1146 npcm_i2c_clear_rx_fifo(bus); 1147 npcm_i2c_clear_tx_fifo(bus); 1148 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1149 iowrite8(I2C_HW_FIFO_SIZE, bus->reg + NPCM_I2CRXF_CTL); 1150 if (NPCM_I2CST_XMIT & i2cst) { 1151 bus->operation = I2C_WRITE_OPER; 1152 } else { 1153 i2c_slave_event(bus->slave, I2C_SLAVE_WRITE_REQUESTED, 1154 &info); 1155 bus->operation = I2C_READ_OPER; 1156 } 1157 if (bus->own_slave_addr == 0xFF) { 1158 /* Check which type of address match */ 1159 val = ioread8(bus->reg + NPCM_I2CCST); 1160 if (NPCM_I2CCST_MATCH & val) { 1161 u16 addr; 1162 enum i2c_addr eaddr; 1163 u8 i2ccst2; 1164 u8 i2ccst3; 1165 1166 i2ccst3 = ioread8(bus->reg + NPCM_I2CCST3); 1167 i2ccst2 = ioread8(bus->reg + NPCM_I2CCST2); 1168 1169 /* 1170 * the i2c module can response to 10 own SA. 1171 * check which one was addressed by the master. 1172 * repond to the first one. 1173 */ 1174 addr = ((i2ccst3 & 0x07) << 7) | 1175 (i2ccst2 & 0x7F); 1176 info = ffs(addr); 1177 eaddr = (enum i2c_addr)info; 1178 addr = npcm_i2c_get_slave_addr(bus, eaddr); 1179 addr &= 0x7F; 1180 bus->own_slave_addr = addr; 1181 if (bus->PEC_mask & BIT(info)) 1182 bus->PEC_use = true; 1183 else 1184 bus->PEC_use = false; 1185 } else { 1186 if (NPCM_I2CCST_GCMATCH & val) 1187 bus->own_slave_addr = 0; 1188 if (NPCM_I2CCST_ARPMATCH & val) 1189 bus->own_slave_addr = 0x61; 1190 } 1191 } else { 1192 /* 1193 * Slave match can happen in two options: 1194 * 1. Start, SA, read (slave read without further ado) 1195 * 2. Start, SA, read, data, restart, SA, read, ... 1196 * (slave read in fragmented mode) 1197 * 3. Start, SA, write, data, restart, SA, read, .. 1198 * (regular write-read mode) 1199 */ 1200 if ((bus->state == I2C_OPER_STARTED && 1201 bus->operation == I2C_READ_OPER && 1202 bus->stop_ind == I2C_SLAVE_XMIT_IND) || 1203 bus->stop_ind == I2C_SLAVE_RCV_IND) { 1204 /* slave tx after slave rx w/o STOP */ 1205 bus->stop_ind = I2C_SLAVE_RESTART_IND; 1206 } 1207 } 1208 1209 if (NPCM_I2CST_XMIT & i2cst) 1210 bus->stop_ind = I2C_SLAVE_XMIT_IND; 1211 else 1212 bus->stop_ind = I2C_SLAVE_RCV_IND; 1213 bus->state = I2C_SLAVE_MATCH; 1214 npcm_i2c_slave_rd_wr(bus); 1215 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1216 ret = IRQ_HANDLED; 1217 } 1218 1219 /* Slave SDA status is set - tx or rx */ 1220 if ((NPCM_I2CST_SDAST & i2cst) || 1221 (bus->fifo_use && 1222 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1223 npcm_i2c_slave_rd_wr(bus); 1224 iowrite8(NPCM_I2CST_SDAST, bus->reg + NPCM_I2CST); 1225 ret = IRQ_HANDLED; 1226 } /* SDAST */ 1227 1228 /* 1229 * if irq is not one of the above, make sure EOB is disabled and all 1230 * status bits are cleared. 1231 */ 1232 if (ret == IRQ_NONE) { 1233 npcm_i2c_eob_int(bus, false); 1234 npcm_i2c_clear_master_status(bus); 1235 } 1236 1237 return IRQ_HANDLED; 1238} 1239 1240static int npcm_i2c_reg_slave(struct i2c_client *client) 1241{ 1242 unsigned long lock_flags; 1243 struct npcm_i2c *bus = i2c_get_adapdata(client->adapter); 1244 1245 bus->slave = client; 1246 1247 if (!bus->slave) 1248 return -EINVAL; 1249 1250 if (client->flags & I2C_CLIENT_TEN) 1251 return -EAFNOSUPPORT; 1252 1253 spin_lock_irqsave(&bus->lock, lock_flags); 1254 1255 npcm_i2c_init_params(bus); 1256 bus->slv_rd_size = 0; 1257 bus->slv_wr_size = 0; 1258 bus->slv_rd_ind = 0; 1259 bus->slv_wr_ind = 0; 1260 if (client->flags & I2C_CLIENT_PEC) 1261 bus->PEC_use = true; 1262 1263 dev_info(bus->dev, "i2c%d register slave SA=0x%x, PEC=%d\n", bus->num, 1264 client->addr, bus->PEC_use); 1265 1266 npcm_i2c_slave_enable(bus, I2C_SLAVE_ADDR1, client->addr, true); 1267 npcm_i2c_clear_fifo_int(bus); 1268 npcm_i2c_clear_rx_fifo(bus); 1269 npcm_i2c_clear_tx_fifo(bus); 1270 npcm_i2c_slave_int_enable(bus, true); 1271 1272 spin_unlock_irqrestore(&bus->lock, lock_flags); 1273 return 0; 1274} 1275 1276static int npcm_i2c_unreg_slave(struct i2c_client *client) 1277{ 1278 struct npcm_i2c *bus = client->adapter->algo_data; 1279 unsigned long lock_flags; 1280 1281 spin_lock_irqsave(&bus->lock, lock_flags); 1282 if (!bus->slave) { 1283 spin_unlock_irqrestore(&bus->lock, lock_flags); 1284 return -EINVAL; 1285 } 1286 npcm_i2c_slave_int_enable(bus, false); 1287 npcm_i2c_remove_slave_addr(bus, client->addr); 1288 bus->slave = NULL; 1289 spin_unlock_irqrestore(&bus->lock, lock_flags); 1290 return 0; 1291} 1292#endif /* CONFIG_I2C_SLAVE */ 1293 1294static void npcm_i2c_master_fifo_read(struct npcm_i2c *bus) 1295{ 1296 int rcount; 1297 int fifo_bytes; 1298 enum i2c_state_ind ind = I2C_MASTER_DONE_IND; 1299 1300 fifo_bytes = npcm_i2c_fifo_usage(bus); 1301 rcount = bus->rd_size - bus->rd_ind; 1302 1303 /* 1304 * In order not to change the RX_TRH during transaction (we found that 1305 * this might be problematic if it takes too much time to read the FIFO) 1306 * we read the data in the following way. If the number of bytes to 1307 * read == FIFO Size + C (where C < FIFO Size)then first read C bytes 1308 * and in the next int we read rest of the data. 1309 */ 1310 if (rcount < (2 * I2C_HW_FIFO_SIZE) && rcount > I2C_HW_FIFO_SIZE) 1311 fifo_bytes = rcount - I2C_HW_FIFO_SIZE; 1312 1313 if (rcount <= fifo_bytes) { 1314 /* last bytes are about to be read - end of tx */ 1315 bus->state = I2C_STOP_PENDING; 1316 bus->stop_ind = ind; 1317 npcm_i2c_eob_int(bus, true); 1318 /* Stop should be set before reading last byte. */ 1319 npcm_i2c_master_stop(bus); 1320 npcm_i2c_read_fifo(bus, fifo_bytes); 1321 } else { 1322 npcm_i2c_read_fifo(bus, fifo_bytes); 1323 rcount = bus->rd_size - bus->rd_ind; 1324 npcm_i2c_set_fifo(bus, rcount, -1); 1325 } 1326} 1327 1328static void npcm_i2c_irq_master_handler_write(struct npcm_i2c *bus) 1329{ 1330 u16 wcount; 1331 1332 if (bus->fifo_use) 1333 npcm_i2c_clear_tx_fifo(bus); /* clear the TX fifo status bit */ 1334 1335 /* Master write operation - last byte handling */ 1336 if (bus->wr_ind == bus->wr_size) { 1337 if (bus->fifo_use && npcm_i2c_fifo_usage(bus) > 0) 1338 /* 1339 * No more bytes to send (to add to the FIFO), 1340 * however the FIFO is not empty yet. It is 1341 * still in the middle of tx. Currently there's nothing 1342 * to do except for waiting to the end of the tx 1343 * We will get an int when the FIFO will get empty. 1344 */ 1345 return; 1346 1347 if (bus->rd_size == 0) { 1348 /* all bytes have been written, in wr only operation */ 1349 npcm_i2c_eob_int(bus, true); 1350 bus->state = I2C_STOP_PENDING; 1351 bus->stop_ind = I2C_MASTER_DONE_IND; 1352 npcm_i2c_master_stop(bus); 1353 /* Clear SDA Status bit (by writing dummy byte) */ 1354 npcm_i2c_wr_byte(bus, 0xFF); 1355 1356 } else { 1357 /* last write-byte written on previous int - restart */ 1358 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1359 /* Generate repeated start upon next write to SDA */ 1360 npcm_i2c_master_start(bus); 1361 1362 /* 1363 * Receiving one byte only - stall after successful 1364 * completion of send address byte. If we NACK here, and 1365 * slave doesn't ACK the address, we might 1366 * unintentionally NACK the next multi-byte read. 1367 */ 1368 if (bus->rd_size == 1) 1369 npcm_i2c_stall_after_start(bus, true); 1370 1371 /* Next int will occur on read */ 1372 bus->operation = I2C_READ_OPER; 1373 /* send the slave address in read direction */ 1374 npcm_i2c_wr_byte(bus, bus->dest_addr | 0x1); 1375 } 1376 } else { 1377 /* write next byte not last byte and not slave address */ 1378 if (!bus->fifo_use || bus->wr_size == 1) { 1379 npcm_i2c_wr_byte(bus, bus->wr_buf[bus->wr_ind++]); 1380 } else { 1381 wcount = bus->wr_size - bus->wr_ind; 1382 npcm_i2c_set_fifo(bus, -1, wcount); 1383 if (wcount) 1384 npcm_i2c_write_to_fifo_master(bus, wcount); 1385 } 1386 } 1387} 1388 1389static void npcm_i2c_irq_master_handler_read(struct npcm_i2c *bus) 1390{ 1391 u16 block_extra_bytes_size; 1392 u8 data; 1393 1394 /* added bytes to the packet: */ 1395 block_extra_bytes_size = bus->read_block_use + bus->PEC_use; 1396 1397 /* 1398 * Perform master read, distinguishing between last byte and the rest of 1399 * the bytes. The last byte should be read when the clock is stopped 1400 */ 1401 if (bus->rd_ind == 0) { /* first byte handling: */ 1402 if (bus->read_block_use) { 1403 /* first byte in block protocol is the size: */ 1404 data = npcm_i2c_rd_byte(bus); 1405 data = clamp_val(data, 1, I2C_SMBUS_BLOCK_MAX); 1406 bus->rd_size = data + block_extra_bytes_size; 1407 bus->rd_buf[bus->rd_ind++] = data; 1408 1409 /* clear RX FIFO interrupt status: */ 1410 if (bus->fifo_use) { 1411 data = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1412 data = data | NPCM_I2CFIF_CTS_RXF_TXE; 1413 iowrite8(data, bus->reg + NPCM_I2CFIF_CTS); 1414 } 1415 1416 npcm_i2c_set_fifo(bus, bus->rd_size - 1, -1); 1417 npcm_i2c_stall_after_start(bus, false); 1418 } else { 1419 npcm_i2c_clear_tx_fifo(bus); 1420 npcm_i2c_master_fifo_read(bus); 1421 } 1422 } else { 1423 if (bus->rd_size == block_extra_bytes_size && 1424 bus->read_block_use) { 1425 bus->state = I2C_STOP_PENDING; 1426 bus->stop_ind = I2C_BLOCK_BYTES_ERR_IND; 1427 bus->cmd_err = -EIO; 1428 npcm_i2c_eob_int(bus, true); 1429 npcm_i2c_master_stop(bus); 1430 npcm_i2c_read_fifo(bus, npcm_i2c_fifo_usage(bus)); 1431 } else { 1432 npcm_i2c_master_fifo_read(bus); 1433 } 1434 } 1435} 1436 1437static void npcm_i2c_irq_handle_nmatch(struct npcm_i2c *bus) 1438{ 1439 iowrite8(NPCM_I2CST_NMATCH, bus->reg + NPCM_I2CST); 1440 npcm_i2c_nack(bus); 1441 bus->stop_ind = I2C_BUS_ERR_IND; 1442 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1443} 1444 1445/* A NACK has occurred */ 1446static void npcm_i2c_irq_handle_nack(struct npcm_i2c *bus) 1447{ 1448 u8 val; 1449 1450 if (bus->nack_cnt < ULLONG_MAX) 1451 bus->nack_cnt++; 1452 1453 if (bus->fifo_use) { 1454 /* 1455 * if there are still untransmitted bytes in TX FIFO 1456 * reduce them from wr_ind 1457 */ 1458 if (bus->operation == I2C_WRITE_OPER) 1459 bus->wr_ind -= npcm_i2c_fifo_usage(bus); 1460 1461 /* clear the FIFO */ 1462 iowrite8(NPCM_I2CFIF_CTS_CLR_FIFO, bus->reg + NPCM_I2CFIF_CTS); 1463 } 1464 1465 /* In master write operation, got unexpected NACK */ 1466 bus->stop_ind = I2C_NACK_IND; 1467 /* Only current master is allowed to issue Stop Condition */ 1468 if (npcm_i2c_is_master(bus)) { 1469 /* stopping in the middle */ 1470 npcm_i2c_eob_int(bus, false); 1471 npcm_i2c_master_stop(bus); 1472 1473 /* Clear SDA Status bit (by reading dummy byte) */ 1474 npcm_i2c_rd_byte(bus); 1475 1476 /* 1477 * The bus is released from stall only after the SW clears 1478 * NEGACK bit. Then a Stop condition is sent. 1479 */ 1480 npcm_i2c_clear_master_status(bus); 1481 readx_poll_timeout_atomic(ioread8, bus->reg + NPCM_I2CCST, val, 1482 !(val & NPCM_I2CCST_BUSY), 10, 200); 1483 /* verify no status bits are still set after bus is released */ 1484 npcm_i2c_clear_master_status(bus); 1485 } 1486 bus->state = I2C_IDLE; 1487 1488 /* 1489 * In Master mode, NACK should be cleared only after STOP. 1490 * In such case, the bus is released from stall only after the 1491 * software clears NACK bit. Then a Stop condition is sent. 1492 */ 1493 npcm_i2c_callback(bus, bus->stop_ind, bus->wr_ind); 1494} 1495 1496 /* Master mode: a Bus Error has been identified */ 1497static void npcm_i2c_irq_handle_ber(struct npcm_i2c *bus) 1498{ 1499 if (bus->ber_cnt < ULLONG_MAX) 1500 bus->ber_cnt++; 1501 bus->stop_ind = I2C_BUS_ERR_IND; 1502 if (npcm_i2c_is_master(bus)) { 1503 npcm_i2c_master_abort(bus); 1504 } else { 1505 npcm_i2c_clear_master_status(bus); 1506 1507 /* Clear BB (BUS BUSY) bit */ 1508 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1509 1510 bus->cmd_err = -EAGAIN; 1511 npcm_i2c_callback(bus, bus->stop_ind, npcm_i2c_get_index(bus)); 1512 } 1513 bus->state = I2C_IDLE; 1514} 1515 1516 /* EOB: a master End Of Busy (meaning STOP completed) */ 1517static void npcm_i2c_irq_handle_eob(struct npcm_i2c *bus) 1518{ 1519 npcm_i2c_eob_int(bus, false); 1520 bus->state = I2C_IDLE; 1521 npcm_i2c_callback(bus, bus->stop_ind, bus->rd_ind); 1522} 1523 1524/* Address sent and requested stall occurred (Master mode) */ 1525static void npcm_i2c_irq_handle_stall_after_start(struct npcm_i2c *bus) 1526{ 1527 if (npcm_i2c_is_quick(bus)) { 1528 bus->state = I2C_STOP_PENDING; 1529 bus->stop_ind = I2C_MASTER_DONE_IND; 1530 npcm_i2c_eob_int(bus, true); 1531 npcm_i2c_master_stop(bus); 1532 } else if ((bus->rd_size == 1) && !bus->read_block_use) { 1533 /* 1534 * Receiving one byte only - set NACK after ensuring 1535 * slave ACKed the address byte. 1536 */ 1537 npcm_i2c_nack(bus); 1538 } 1539 1540 /* Reset stall-after-address-byte */ 1541 npcm_i2c_stall_after_start(bus, false); 1542 1543 /* Clear stall only after setting STOP */ 1544 iowrite8(NPCM_I2CST_STASTR, bus->reg + NPCM_I2CST); 1545} 1546 1547/* SDA status is set - TX or RX, master */ 1548static void npcm_i2c_irq_handle_sda(struct npcm_i2c *bus, u8 i2cst) 1549{ 1550 u8 fif_cts; 1551 1552 if (!npcm_i2c_is_master(bus)) 1553 return; 1554 1555 if (bus->state == I2C_IDLE) { 1556 bus->stop_ind = I2C_WAKE_UP_IND; 1557 1558 if (npcm_i2c_is_quick(bus) || bus->read_block_use) 1559 /* 1560 * Need to stall after successful 1561 * completion of sending address byte 1562 */ 1563 npcm_i2c_stall_after_start(bus, true); 1564 else 1565 npcm_i2c_stall_after_start(bus, false); 1566 1567 /* 1568 * Receiving one byte only - stall after successful completion 1569 * of sending address byte If we NACK here, and slave doesn't 1570 * ACK the address, we might unintentionally NACK the next 1571 * multi-byte read 1572 */ 1573 if (bus->wr_size == 0 && bus->rd_size == 1) 1574 npcm_i2c_stall_after_start(bus, true); 1575 1576 /* Initiate I2C master tx */ 1577 1578 /* select bank 1 for FIFO regs */ 1579 npcm_i2c_select_bank(bus, I2C_BANK_1); 1580 1581 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1582 fif_cts = fif_cts & ~NPCM_I2CFIF_CTS_SLVRSTR; 1583 1584 /* clear FIFO and relevant status bits. */ 1585 fif_cts = fif_cts | NPCM_I2CFIF_CTS_CLR_FIFO; 1586 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1587 1588 /* re-enable */ 1589 fif_cts = fif_cts | NPCM_I2CFIF_CTS_RXF_TXE; 1590 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1591 1592 /* 1593 * Configure the FIFO threshold: 1594 * according to the needed # of bytes to read. 1595 * Note: due to HW limitation can't config the rx fifo before it 1596 * got and ACK on the restart. LAST bit will not be reset unless 1597 * RX completed. It will stay set on the next tx. 1598 */ 1599 if (bus->wr_size) 1600 npcm_i2c_set_fifo(bus, -1, bus->wr_size); 1601 else 1602 npcm_i2c_set_fifo(bus, bus->rd_size, -1); 1603 1604 bus->state = I2C_OPER_STARTED; 1605 1606 if (npcm_i2c_is_quick(bus) || bus->wr_size) 1607 npcm_i2c_wr_byte(bus, bus->dest_addr); 1608 else 1609 npcm_i2c_wr_byte(bus, bus->dest_addr | BIT(0)); 1610 /* SDA interrupt, after start\restart */ 1611 } else { 1612 if (NPCM_I2CST_XMIT & i2cst) { 1613 bus->operation = I2C_WRITE_OPER; 1614 npcm_i2c_irq_master_handler_write(bus); 1615 } else { 1616 bus->operation = I2C_READ_OPER; 1617 npcm_i2c_irq_master_handler_read(bus); 1618 } 1619 } 1620} 1621 1622static int npcm_i2c_int_master_handler(struct npcm_i2c *bus) 1623{ 1624 u8 i2cst; 1625 int ret = -EIO; 1626 1627 i2cst = ioread8(bus->reg + NPCM_I2CST); 1628 1629 if (FIELD_GET(NPCM_I2CST_NMATCH, i2cst)) { 1630 npcm_i2c_irq_handle_nmatch(bus); 1631 return 0; 1632 } 1633 /* A NACK has occurred */ 1634 if (FIELD_GET(NPCM_I2CST_NEGACK, i2cst)) { 1635 npcm_i2c_irq_handle_nack(bus); 1636 return 0; 1637 } 1638 1639 /* Master mode: a Bus Error has been identified */ 1640 if (FIELD_GET(NPCM_I2CST_BER, i2cst)) { 1641 npcm_i2c_irq_handle_ber(bus); 1642 return 0; 1643 } 1644 1645 /* EOB: a master End Of Busy (meaning STOP completed) */ 1646 if ((FIELD_GET(NPCM_I2CCTL1_EOBINTE, 1647 ioread8(bus->reg + NPCM_I2CCTL1)) == 1) && 1648 (FIELD_GET(NPCM_I2CCST3_EO_BUSY, 1649 ioread8(bus->reg + NPCM_I2CCST3)))) { 1650 npcm_i2c_irq_handle_eob(bus); 1651 return 0; 1652 } 1653 1654 /* Address sent and requested stall occurred (Master mode) */ 1655 if (FIELD_GET(NPCM_I2CST_STASTR, i2cst)) { 1656 npcm_i2c_irq_handle_stall_after_start(bus); 1657 ret = 0; 1658 } 1659 1660 /* SDA status is set - TX or RX, master */ 1661 if (FIELD_GET(NPCM_I2CST_SDAST, i2cst) || 1662 (bus->fifo_use && 1663 (npcm_i2c_tx_fifo_empty(bus) || npcm_i2c_rx_fifo_full(bus)))) { 1664 npcm_i2c_irq_handle_sda(bus, i2cst); 1665 ret = 0; 1666 } 1667 1668 return ret; 1669} 1670 1671/* recovery using TGCLK functionality of the module */ 1672static int npcm_i2c_recovery_tgclk(struct i2c_adapter *_adap) 1673{ 1674 u8 val; 1675 u8 fif_cts; 1676 bool done = false; 1677 int status = -ENOTRECOVERABLE; 1678 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 1679 /* Allow 3 bytes (27 toggles) to be read from the slave: */ 1680 int iter = 27; 1681 1682 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) { 1683 dev_dbg(bus->dev, "bus%d-0x%x recovery skipped, bus not stuck", 1684 bus->num, bus->dest_addr); 1685 npcm_i2c_reset(bus); 1686 return 0; 1687 } 1688 1689 npcm_i2c_int_enable(bus, false); 1690 npcm_i2c_disable(bus); 1691 npcm_i2c_enable(bus); 1692 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 1693 npcm_i2c_clear_tx_fifo(bus); 1694 npcm_i2c_clear_rx_fifo(bus); 1695 iowrite8(0, bus->reg + NPCM_I2CRXF_CTL); 1696 iowrite8(0, bus->reg + NPCM_I2CTXF_CTL); 1697 npcm_i2c_stall_after_start(bus, false); 1698 1699 /* select bank 1 for FIFO regs */ 1700 npcm_i2c_select_bank(bus, I2C_BANK_1); 1701 1702 /* clear FIFO and relevant status bits. */ 1703 fif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 1704 fif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 1705 fif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 1706 iowrite8(fif_cts, bus->reg + NPCM_I2CFIF_CTS); 1707 npcm_i2c_set_fifo(bus, -1, 0); 1708 1709 /* Repeat the following sequence until SDA is released */ 1710 do { 1711 /* Issue a single SCL toggle */ 1712 iowrite8(NPCM_I2CCST_TGSCL, bus->reg + NPCM_I2CCST); 1713 usleep_range(20, 30); 1714 /* If SDA line is inactive (high), stop */ 1715 if (npcm_i2c_get_SDA(_adap)) { 1716 done = true; 1717 status = 0; 1718 } 1719 } while (!done && iter--); 1720 1721 /* If SDA line is released: send start-addr-stop, to re-sync. */ 1722 if (npcm_i2c_get_SDA(_adap)) { 1723 /* Send an address byte in write direction: */ 1724 npcm_i2c_wr_byte(bus, bus->dest_addr); 1725 npcm_i2c_master_start(bus); 1726 /* Wait until START condition is sent */ 1727 status = readx_poll_timeout(npcm_i2c_get_SCL, _adap, val, !val, 1728 20, 200); 1729 /* If START condition was sent */ 1730 if (npcm_i2c_is_master(bus) > 0) { 1731 usleep_range(20, 30); 1732 npcm_i2c_master_stop(bus); 1733 usleep_range(200, 500); 1734 } 1735 } 1736 npcm_i2c_reset(bus); 1737 npcm_i2c_int_enable(bus, true); 1738 1739 if ((npcm_i2c_get_SDA(_adap) == 1) && (npcm_i2c_get_SCL(_adap) == 1)) 1740 status = 0; 1741 else 1742 status = -ENOTRECOVERABLE; 1743 if (status) { 1744 if (bus->rec_fail_cnt < ULLONG_MAX) 1745 bus->rec_fail_cnt++; 1746 } else { 1747 if (bus->rec_succ_cnt < ULLONG_MAX) 1748 bus->rec_succ_cnt++; 1749 } 1750 return status; 1751} 1752 1753/* recovery using bit banging functionality of the module */ 1754static void npcm_i2c_recovery_init(struct i2c_adapter *_adap) 1755{ 1756 struct npcm_i2c *bus = container_of(_adap, struct npcm_i2c, adap); 1757 struct i2c_bus_recovery_info *rinfo = &bus->rinfo; 1758 1759 rinfo->recover_bus = npcm_i2c_recovery_tgclk; 1760 1761 /* 1762 * npcm i2c HW allows direct reading of SCL and SDA. 1763 * However, it does not support setting SCL and SDA directly. 1764 * The recovery function can togle SCL when SDA is low (but not set) 1765 * Getter functions used internally, and can be used externaly. 1766 */ 1767 rinfo->get_scl = npcm_i2c_get_SCL; 1768 rinfo->get_sda = npcm_i2c_get_SDA; 1769 _adap->bus_recovery_info = rinfo; 1770} 1771 1772/* SCLFRQ min/max field values */ 1773#define SCLFRQ_MIN 10 1774#define SCLFRQ_MAX 511 1775#define clk_coef(freq, mul) DIV_ROUND_UP((freq) * (mul), 1000000) 1776 1777/* 1778 * npcm_i2c_init_clk: init HW timing parameters. 1779 * NPCM7XX i2c module timing parameters are depenent on module core clk (APB) 1780 * and bus frequency. 1781 * 100kHz bus requires tSCL = 4 * SCLFRQ * tCLK. LT and HT are simetric. 1782 * 400kHz bus requires assymetric HT and LT. A different equation is recomended 1783 * by the HW designer, given core clock range (equations in comments below). 1784 * 1785 */ 1786static int npcm_i2c_init_clk(struct npcm_i2c *bus, u32 bus_freq_hz) 1787{ 1788 u32 k1 = 0; 1789 u32 k2 = 0; 1790 u8 dbnct = 0; 1791 u32 sclfrq = 0; 1792 u8 hldt = 7; 1793 u8 fast_mode = 0; 1794 u32 src_clk_khz; 1795 u32 bus_freq_khz; 1796 1797 src_clk_khz = bus->apb_clk / 1000; 1798 bus_freq_khz = bus_freq_hz / 1000; 1799 bus->bus_freq = bus_freq_hz; 1800 1801 /* 100KHz and below: */ 1802 if (bus_freq_hz <= I2C_MAX_STANDARD_MODE_FREQ) { 1803 sclfrq = src_clk_khz / (bus_freq_khz * 4); 1804 1805 if (sclfrq < SCLFRQ_MIN || sclfrq > SCLFRQ_MAX) 1806 return -EDOM; 1807 1808 if (src_clk_khz >= 40000) 1809 hldt = 17; 1810 else if (src_clk_khz >= 12500) 1811 hldt = 15; 1812 else 1813 hldt = 7; 1814 } 1815 1816 /* 400KHz: */ 1817 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_FREQ) { 1818 sclfrq = 0; 1819 fast_mode = I2CCTL3_400K_MODE; 1820 1821 if (src_clk_khz < 7500) 1822 /* 400KHZ cannot be supported for core clock < 7.5MHz */ 1823 return -EDOM; 1824 1825 else if (src_clk_khz >= 50000) { 1826 k1 = 80; 1827 k2 = 48; 1828 hldt = 12; 1829 dbnct = 7; 1830 } 1831 1832 /* Master or Slave with frequency > 25MHz */ 1833 else if (src_clk_khz > 25000) { 1834 hldt = clk_coef(src_clk_khz, 300) + 7; 1835 k1 = clk_coef(src_clk_khz, 1600); 1836 k2 = clk_coef(src_clk_khz, 900); 1837 } 1838 } 1839 1840 /* 1MHz: */ 1841 else if (bus_freq_hz <= I2C_MAX_FAST_MODE_PLUS_FREQ) { 1842 sclfrq = 0; 1843 fast_mode = I2CCTL3_400K_MODE; 1844 1845 /* 1MHZ cannot be supported for core clock < 24 MHz */ 1846 if (src_clk_khz < 24000) 1847 return -EDOM; 1848 1849 k1 = clk_coef(src_clk_khz, 620); 1850 k2 = clk_coef(src_clk_khz, 380); 1851 1852 /* Core clk > 40 MHz */ 1853 if (src_clk_khz > 40000) { 1854 /* 1855 * Set HLDT: 1856 * SDA hold time: (HLDT-7) * T(CLK) >= 120 1857 * HLDT = 120/T(CLK) + 7 = 120 * FREQ(CLK) + 7 1858 */ 1859 hldt = clk_coef(src_clk_khz, 120) + 7; 1860 } else { 1861 hldt = 7; 1862 dbnct = 2; 1863 } 1864 } 1865 1866 /* Frequency larger than 1 MHz is not supported */ 1867 else 1868 return -EINVAL; 1869 1870 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 1871 k1 = round_up(k1, 2); 1872 k2 = round_up(k2 + 1, 2); 1873 if (k1 < SCLFRQ_MIN || k1 > SCLFRQ_MAX || 1874 k2 < SCLFRQ_MIN || k2 > SCLFRQ_MAX) 1875 return -EDOM; 1876 } 1877 1878 /* write sclfrq value. bits [6:0] are in I2CCTL2 reg */ 1879 iowrite8(FIELD_PREP(I2CCTL2_SCLFRQ6_0, sclfrq & 0x7F), 1880 bus->reg + NPCM_I2CCTL2); 1881 1882 /* bits [8:7] are in I2CCTL3 reg */ 1883 iowrite8(fast_mode | FIELD_PREP(I2CCTL3_SCLFRQ8_7, (sclfrq >> 7) & 0x3), 1884 bus->reg + NPCM_I2CCTL3); 1885 1886 /* Select Bank 0 to access NPCM_I2CCTL4/NPCM_I2CCTL5 */ 1887 npcm_i2c_select_bank(bus, I2C_BANK_0); 1888 1889 if (bus_freq_hz >= I2C_MAX_FAST_MODE_FREQ) { 1890 /* 1891 * Set SCL Low/High Time: 1892 * k1 = 2 * SCLLT7-0 -> Low Time = k1 / 2 1893 * k2 = 2 * SCLLT7-0 -> High Time = k2 / 2 1894 */ 1895 iowrite8(k1 / 2, bus->reg + NPCM_I2CSCLLT); 1896 iowrite8(k2 / 2, bus->reg + NPCM_I2CSCLHT); 1897 1898 iowrite8(dbnct, bus->reg + NPCM_I2CCTL5); 1899 } 1900 1901 iowrite8(hldt, bus->reg + NPCM_I2CCTL4); 1902 1903 /* Return to Bank 1, and stay there by default: */ 1904 npcm_i2c_select_bank(bus, I2C_BANK_1); 1905 1906 return 0; 1907} 1908 1909static int npcm_i2c_init_module(struct npcm_i2c *bus, enum i2c_mode mode, 1910 u32 bus_freq_hz) 1911{ 1912 u8 val; 1913 int ret; 1914 1915 /* Check whether module already enabled or frequency is out of bounds */ 1916 if ((bus->state != I2C_DISABLE && bus->state != I2C_IDLE) || 1917 bus_freq_hz < I2C_FREQ_MIN_HZ || bus_freq_hz > I2C_FREQ_MAX_HZ) 1918 return -EINVAL; 1919 1920 npcm_i2c_int_enable(bus, false); 1921 npcm_i2c_disable(bus); 1922 1923 /* Configure FIFO mode : */ 1924 if (FIELD_GET(I2C_VER_FIFO_EN, ioread8(bus->reg + I2C_VER))) { 1925 bus->fifo_use = true; 1926 npcm_i2c_select_bank(bus, I2C_BANK_0); 1927 val = ioread8(bus->reg + NPCM_I2CFIF_CTL); 1928 val |= NPCM_I2CFIF_CTL_FIFO_EN; 1929 iowrite8(val, bus->reg + NPCM_I2CFIF_CTL); 1930 npcm_i2c_select_bank(bus, I2C_BANK_1); 1931 } else { 1932 bus->fifo_use = false; 1933 } 1934 1935 /* Configure I2C module clock frequency */ 1936 ret = npcm_i2c_init_clk(bus, bus_freq_hz); 1937 if (ret) { 1938 dev_err(bus->dev, "npcm_i2c_init_clk failed\n"); 1939 return ret; 1940 } 1941 1942 /* Enable module (before configuring CTL1) */ 1943 npcm_i2c_enable(bus); 1944 bus->state = I2C_IDLE; 1945 val = ioread8(bus->reg + NPCM_I2CCTL1); 1946 val = (val | NPCM_I2CCTL1_NMINTE) & ~NPCM_I2CCTL1_RWS; 1947 iowrite8(val, bus->reg + NPCM_I2CCTL1); 1948 1949 npcm_i2c_reset(bus); 1950 1951 /* check HW is OK: SDA and SCL should be high at this point. */ 1952 if ((npcm_i2c_get_SDA(&bus->adap) == 0) || (npcm_i2c_get_SCL(&bus->adap) == 0)) { 1953 dev_err(bus->dev, "I2C%d init fail: lines are low\n", bus->num); 1954 dev_err(bus->dev, "SDA=%d SCL=%d\n", npcm_i2c_get_SDA(&bus->adap), 1955 npcm_i2c_get_SCL(&bus->adap)); 1956 return -ENXIO; 1957 } 1958 1959 npcm_i2c_int_enable(bus, true); 1960 return 0; 1961} 1962 1963static int __npcm_i2c_init(struct npcm_i2c *bus, struct platform_device *pdev) 1964{ 1965 u32 clk_freq_hz; 1966 int ret; 1967 1968 /* Initialize the internal data structures */ 1969 bus->state = I2C_DISABLE; 1970 bus->master_or_slave = I2C_SLAVE; 1971 bus->int_time_stamp = 0; 1972#if IS_ENABLED(CONFIG_I2C_SLAVE) 1973 bus->slave = NULL; 1974#endif 1975 1976 ret = device_property_read_u32(&pdev->dev, "clock-frequency", 1977 &clk_freq_hz); 1978 if (ret) { 1979 dev_info(&pdev->dev, "Could not read clock-frequency property"); 1980 clk_freq_hz = I2C_MAX_STANDARD_MODE_FREQ; 1981 } 1982 1983 ret = npcm_i2c_init_module(bus, I2C_MASTER, clk_freq_hz); 1984 if (ret) { 1985 dev_err(&pdev->dev, "npcm_i2c_init_module failed\n"); 1986 return ret; 1987 } 1988 1989 return 0; 1990} 1991 1992static irqreturn_t npcm_i2c_bus_irq(int irq, void *dev_id) 1993{ 1994 struct npcm_i2c *bus = dev_id; 1995 1996 if (npcm_i2c_is_master(bus)) 1997 bus->master_or_slave = I2C_MASTER; 1998 1999 if (bus->master_or_slave == I2C_MASTER) { 2000 bus->int_time_stamp = jiffies; 2001 if (!npcm_i2c_int_master_handler(bus)) 2002 return IRQ_HANDLED; 2003 } 2004#if IS_ENABLED(CONFIG_I2C_SLAVE) 2005 if (bus->slave) { 2006 bus->master_or_slave = I2C_SLAVE; 2007 if (npcm_i2c_int_slave_handler(bus)) 2008 return IRQ_HANDLED; 2009 } 2010#endif 2011 /* clear status bits for spurious interrupts */ 2012 npcm_i2c_clear_master_status(bus); 2013 2014 return IRQ_HANDLED; 2015} 2016 2017static bool npcm_i2c_master_start_xmit(struct npcm_i2c *bus, 2018 u8 slave_addr, u16 nwrite, u16 nread, 2019 u8 *write_data, u8 *read_data, 2020 bool use_PEC, bool use_read_block) 2021{ 2022 if (bus->state != I2C_IDLE) { 2023 bus->cmd_err = -EBUSY; 2024 return false; 2025 } 2026 bus->dest_addr = slave_addr << 1; 2027 bus->wr_buf = write_data; 2028 bus->wr_size = nwrite; 2029 bus->wr_ind = 0; 2030 bus->rd_buf = read_data; 2031 bus->rd_size = nread; 2032 bus->rd_ind = 0; 2033 bus->PEC_use = 0; 2034 2035 /* for tx PEC is appended to buffer from i2c IF. PEC flag is ignored */ 2036 if (nread) 2037 bus->PEC_use = use_PEC; 2038 2039 bus->read_block_use = use_read_block; 2040 if (nread && !nwrite) 2041 bus->operation = I2C_READ_OPER; 2042 else 2043 bus->operation = I2C_WRITE_OPER; 2044 if (bus->fifo_use) { 2045 u8 i2cfif_cts; 2046 2047 npcm_i2c_select_bank(bus, I2C_BANK_1); 2048 /* clear FIFO and relevant status bits. */ 2049 i2cfif_cts = ioread8(bus->reg + NPCM_I2CFIF_CTS); 2050 i2cfif_cts &= ~NPCM_I2CFIF_CTS_SLVRSTR; 2051 i2cfif_cts |= NPCM_I2CFIF_CTS_CLR_FIFO; 2052 iowrite8(i2cfif_cts, bus->reg + NPCM_I2CFIF_CTS); 2053 } 2054 2055 bus->state = I2C_IDLE; 2056 npcm_i2c_stall_after_start(bus, true); 2057 npcm_i2c_master_start(bus); 2058 return true; 2059} 2060 2061static int npcm_i2c_master_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, 2062 int num) 2063{ 2064 struct npcm_i2c *bus = container_of(adap, struct npcm_i2c, adap); 2065 struct i2c_msg *msg0, *msg1; 2066 unsigned long time_left, flags; 2067 u16 nwrite, nread; 2068 u8 *write_data, *read_data; 2069 u8 slave_addr; 2070 unsigned long timeout; 2071 bool read_block = false; 2072 bool read_PEC = false; 2073 u8 bus_busy; 2074 unsigned long timeout_usec; 2075 2076 if (bus->state == I2C_DISABLE) { 2077 dev_err(bus->dev, "I2C%d module is disabled", bus->num); 2078 return -EINVAL; 2079 } 2080 2081 msg0 = &msgs[0]; 2082 slave_addr = msg0->addr; 2083 if (msg0->flags & I2C_M_RD) { /* read */ 2084 nwrite = 0; 2085 write_data = NULL; 2086 read_data = msg0->buf; 2087 if (msg0->flags & I2C_M_RECV_LEN) { 2088 nread = 1; 2089 read_block = true; 2090 if (msg0->flags & I2C_CLIENT_PEC) 2091 read_PEC = true; 2092 } else { 2093 nread = msg0->len; 2094 } 2095 } else { /* write */ 2096 nwrite = msg0->len; 2097 write_data = msg0->buf; 2098 nread = 0; 2099 read_data = NULL; 2100 if (num == 2) { 2101 msg1 = &msgs[1]; 2102 read_data = msg1->buf; 2103 if (msg1->flags & I2C_M_RECV_LEN) { 2104 nread = 1; 2105 read_block = true; 2106 if (msg1->flags & I2C_CLIENT_PEC) 2107 read_PEC = true; 2108 } else { 2109 nread = msg1->len; 2110 read_block = false; 2111 } 2112 } 2113 } 2114 2115 /* 2116 * Adaptive TimeOut: estimated time in usec + 100% margin: 2117 * 2: double the timeout for clock stretching case 2118 * 9: bits per transaction (including the ack/nack) 2119 */ 2120 timeout_usec = (2 * 9 * USEC_PER_SEC / bus->bus_freq) * (2 + nread + nwrite); 2121 timeout = max_t(unsigned long, bus->adap.timeout, usecs_to_jiffies(timeout_usec)); 2122 if (nwrite >= 32 * 1024 || nread >= 32 * 1024) { 2123 dev_err(bus->dev, "i2c%d buffer too big\n", bus->num); 2124 return -EINVAL; 2125 } 2126 2127 time_left = jiffies + timeout + 1; 2128 do { 2129 /* 2130 * we must clear slave address immediately when the bus is not 2131 * busy, so we spinlock it, but we don't keep the lock for the 2132 * entire while since it is too long. 2133 */ 2134 spin_lock_irqsave(&bus->lock, flags); 2135 bus_busy = ioread8(bus->reg + NPCM_I2CCST) & NPCM_I2CCST_BB; 2136#if IS_ENABLED(CONFIG_I2C_SLAVE) 2137 if (!bus_busy && bus->slave) 2138 iowrite8((bus->slave->addr & 0x7F), 2139 bus->reg + NPCM_I2CADDR1); 2140#endif 2141 spin_unlock_irqrestore(&bus->lock, flags); 2142 2143 } while (time_is_after_jiffies(time_left) && bus_busy); 2144 2145 if (bus_busy) { 2146 iowrite8(NPCM_I2CCST_BB, bus->reg + NPCM_I2CCST); 2147 npcm_i2c_reset(bus); 2148 i2c_recover_bus(adap); 2149 return -EAGAIN; 2150 } 2151 2152 npcm_i2c_init_params(bus); 2153 bus->dest_addr = slave_addr; 2154 bus->msgs = msgs; 2155 bus->msgs_num = num; 2156 bus->cmd_err = 0; 2157 bus->read_block_use = read_block; 2158 2159 reinit_completion(&bus->cmd_complete); 2160 2161 npcm_i2c_int_enable(bus, true); 2162 2163 if (npcm_i2c_master_start_xmit(bus, slave_addr, nwrite, nread, 2164 write_data, read_data, read_PEC, 2165 read_block)) { 2166 time_left = wait_for_completion_timeout(&bus->cmd_complete, 2167 timeout); 2168 2169 if (time_left == 0) { 2170 if (bus->timeout_cnt < ULLONG_MAX) 2171 bus->timeout_cnt++; 2172 if (bus->master_or_slave == I2C_MASTER) { 2173 i2c_recover_bus(adap); 2174 bus->cmd_err = -EIO; 2175 bus->state = I2C_IDLE; 2176 } 2177 } 2178 } 2179 2180 /* if there was BER, check if need to recover the bus: */ 2181 if (bus->cmd_err == -EAGAIN) 2182 bus->cmd_err = i2c_recover_bus(adap); 2183 2184 /* 2185 * After any type of error, check if LAST bit is still set, 2186 * due to a HW issue. 2187 * It cannot be cleared without resetting the module. 2188 */ 2189 else if (bus->cmd_err && 2190 (NPCM_I2CRXF_CTL_LAST_PEC & ioread8(bus->reg + NPCM_I2CRXF_CTL))) 2191 npcm_i2c_reset(bus); 2192 2193 /* after any xfer, successful or not, stall and EOB must be disabled */ 2194 npcm_i2c_stall_after_start(bus, false); 2195 npcm_i2c_eob_int(bus, false); 2196 2197#if IS_ENABLED(CONFIG_I2C_SLAVE) 2198 /* reenable slave if it was enabled */ 2199 if (bus->slave) 2200 iowrite8((bus->slave->addr & 0x7F) | NPCM_I2CADDR_SAEN, 2201 bus->reg + NPCM_I2CADDR1); 2202#else 2203 npcm_i2c_int_enable(bus, false); 2204#endif 2205 return bus->cmd_err; 2206} 2207 2208static u32 npcm_i2c_functionality(struct i2c_adapter *adap) 2209{ 2210 return I2C_FUNC_I2C | 2211 I2C_FUNC_SMBUS_EMUL | 2212 I2C_FUNC_SMBUS_BLOCK_DATA | 2213 I2C_FUNC_SMBUS_PEC | 2214 I2C_FUNC_SLAVE; 2215} 2216 2217static const struct i2c_adapter_quirks npcm_i2c_quirks = { 2218 .max_read_len = 32768, 2219 .max_write_len = 32768, 2220 .flags = I2C_AQ_COMB_WRITE_THEN_READ, 2221}; 2222 2223static const struct i2c_algorithm npcm_i2c_algo = { 2224 .master_xfer = npcm_i2c_master_xfer, 2225 .functionality = npcm_i2c_functionality, 2226#if IS_ENABLED(CONFIG_I2C_SLAVE) 2227 .reg_slave = npcm_i2c_reg_slave, 2228 .unreg_slave = npcm_i2c_unreg_slave, 2229#endif 2230}; 2231 2232/* i2c debugfs directory: used to keep health monitor of i2c devices */ 2233static struct dentry *npcm_i2c_debugfs_dir; 2234 2235static void npcm_i2c_init_debugfs(struct platform_device *pdev, 2236 struct npcm_i2c *bus) 2237{ 2238 struct dentry *d; 2239 2240 if (!npcm_i2c_debugfs_dir) 2241 return; 2242 d = debugfs_create_dir(dev_name(&pdev->dev), npcm_i2c_debugfs_dir); 2243 if (IS_ERR_OR_NULL(d)) 2244 return; 2245 debugfs_create_u64("ber_cnt", 0444, d, &bus->ber_cnt); 2246 debugfs_create_u64("nack_cnt", 0444, d, &bus->nack_cnt); 2247 debugfs_create_u64("rec_succ_cnt", 0444, d, &bus->rec_succ_cnt); 2248 debugfs_create_u64("rec_fail_cnt", 0444, d, &bus->rec_fail_cnt); 2249 debugfs_create_u64("timeout_cnt", 0444, d, &bus->timeout_cnt); 2250 2251 bus->debugfs = d; 2252} 2253 2254static int npcm_i2c_probe_bus(struct platform_device *pdev) 2255{ 2256 struct npcm_i2c *bus; 2257 struct i2c_adapter *adap; 2258 struct clk *i2c_clk; 2259 static struct regmap *gcr_regmap; 2260 static struct regmap *clk_regmap; 2261 int irq; 2262 int ret; 2263 2264 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); 2265 if (!bus) 2266 return -ENOMEM; 2267 2268 bus->dev = &pdev->dev; 2269 2270 bus->num = of_alias_get_id(pdev->dev.of_node, "i2c"); 2271 /* core clk must be acquired to calculate module timing settings */ 2272 i2c_clk = devm_clk_get(&pdev->dev, NULL); 2273 if (IS_ERR(i2c_clk)) 2274 return PTR_ERR(i2c_clk); 2275 bus->apb_clk = clk_get_rate(i2c_clk); 2276 2277 gcr_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 2278 if (IS_ERR(gcr_regmap)) 2279 return PTR_ERR(gcr_regmap); 2280 regmap_write(gcr_regmap, NPCM_I2CSEGCTL, NPCM_I2CSEGCTL_INIT_VAL); 2281 2282 clk_regmap = syscon_regmap_lookup_by_compatible("nuvoton,npcm750-clk"); 2283 if (IS_ERR(clk_regmap)) 2284 return PTR_ERR(clk_regmap); 2285 2286 bus->reg = devm_platform_ioremap_resource(pdev, 0); 2287 if (IS_ERR(bus->reg)) 2288 return PTR_ERR(bus->reg); 2289 2290 spin_lock_init(&bus->lock); 2291 init_completion(&bus->cmd_complete); 2292 2293 adap = &bus->adap; 2294 adap->owner = THIS_MODULE; 2295 adap->retries = 3; 2296 adap->timeout = msecs_to_jiffies(35); 2297 adap->algo = &npcm_i2c_algo; 2298 adap->quirks = &npcm_i2c_quirks; 2299 adap->algo_data = bus; 2300 adap->dev.parent = &pdev->dev; 2301 adap->dev.of_node = pdev->dev.of_node; 2302 adap->nr = pdev->id; 2303 2304 irq = platform_get_irq(pdev, 0); 2305 if (irq < 0) 2306 return irq; 2307 2308 ret = devm_request_irq(bus->dev, irq, npcm_i2c_bus_irq, 0, 2309 dev_name(bus->dev), bus); 2310 if (ret) 2311 return ret; 2312 2313 ret = __npcm_i2c_init(bus, pdev); 2314 if (ret) 2315 return ret; 2316 2317 npcm_i2c_recovery_init(adap); 2318 2319 i2c_set_adapdata(adap, bus); 2320 2321 snprintf(bus->adap.name, sizeof(bus->adap.name), "npcm_i2c_%d", 2322 bus->num); 2323 ret = i2c_add_numbered_adapter(&bus->adap); 2324 if (ret) 2325 return ret; 2326 2327 platform_set_drvdata(pdev, bus); 2328 npcm_i2c_init_debugfs(pdev, bus); 2329 return 0; 2330} 2331 2332static int npcm_i2c_remove_bus(struct platform_device *pdev) 2333{ 2334 unsigned long lock_flags; 2335 struct npcm_i2c *bus = platform_get_drvdata(pdev); 2336 2337 debugfs_remove_recursive(bus->debugfs); 2338 spin_lock_irqsave(&bus->lock, lock_flags); 2339 npcm_i2c_disable(bus); 2340 spin_unlock_irqrestore(&bus->lock, lock_flags); 2341 i2c_del_adapter(&bus->adap); 2342 return 0; 2343} 2344 2345static const struct of_device_id npcm_i2c_bus_of_table[] = { 2346 { .compatible = "nuvoton,npcm750-i2c", }, 2347 {} 2348}; 2349MODULE_DEVICE_TABLE(of, npcm_i2c_bus_of_table); 2350 2351static struct platform_driver npcm_i2c_bus_driver = { 2352 .probe = npcm_i2c_probe_bus, 2353 .remove = npcm_i2c_remove_bus, 2354 .driver = { 2355 .name = "nuvoton-i2c", 2356 .of_match_table = npcm_i2c_bus_of_table, 2357 } 2358}; 2359 2360static int __init npcm_i2c_init(void) 2361{ 2362 int ret; 2363 2364 npcm_i2c_debugfs_dir = debugfs_create_dir("npcm_i2c", NULL); 2365 2366 ret = platform_driver_register(&npcm_i2c_bus_driver); 2367 if (ret) { 2368 debugfs_remove_recursive(npcm_i2c_debugfs_dir); 2369 return ret; 2370 } 2371 2372 return 0; 2373} 2374module_init(npcm_i2c_init); 2375 2376static void __exit npcm_i2c_exit(void) 2377{ 2378 platform_driver_unregister(&npcm_i2c_bus_driver); 2379 debugfs_remove_recursive(npcm_i2c_debugfs_dir); 2380} 2381module_exit(npcm_i2c_exit); 2382 2383MODULE_AUTHOR("Avi Fishman <avi.fishman@gmail.com>"); 2384MODULE_AUTHOR("Tali Perry <tali.perry@nuvoton.com>"); 2385MODULE_AUTHOR("Tyrone Ting <kfting@nuvoton.com>"); 2386MODULE_DESCRIPTION("Nuvoton I2C Bus Driver"); 2387MODULE_LICENSE("GPL v2"); 2388