1/* 2 * This file is provided under a dual BSD/GPLv2 license. When using or 3 * redistributing this file, you may do so under either license. 4 * 5 * Copyright(c) 2012 Intel Corporation. All rights reserved. 6 * 7 * GPL LICENSE SUMMARY 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of version 2 of the GNU General Public License as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, but 14 * WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * General Public License for more details. 17 * The full GNU General Public License is included in this distribution 18 * in the file called LICENSE.GPL. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * * Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * * Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * * Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 */ 48 49/* 50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor 51 * S12xx Product Family. 52 * 53 * Features supported by this driver: 54 * Hardware PEC yes 55 * Block buffer yes 56 * Block process call transaction no 57 * Slave mode no 58 */ 59 60#include <linux/module.h> 61#include <linux/pci.h> 62#include <linux/kernel.h> 63#include <linux/stddef.h> 64#include <linux/completion.h> 65#include <linux/dma-mapping.h> 66#include <linux/i2c.h> 67#include <linux/acpi.h> 68#include <linux/interrupt.h> 69 70#include <linux/io-64-nonatomic-lo-hi.h> 71 72/* PCI Address Constants */ 73#define SMBBAR 0 74 75/* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */ 76#define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59 77#define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a 78#define PCI_DEVICE_ID_INTEL_CDF_SMT 0x18ac 79#define PCI_DEVICE_ID_INTEL_DNV_SMT 0x19ac 80#define PCI_DEVICE_ID_INTEL_EBG_SMT 0x1bff 81#define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15 82 83#define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */ 84#define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */ 85#define ISMT_LOG_ENTRIES 3 /* number of interrupt cause log entries */ 86 87/* Hardware Descriptor Constants - Control Field */ 88#define ISMT_DESC_CWRL 0x01 /* Command/Write Length */ 89#define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */ 90#define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */ 91#define ISMT_DESC_PEC 0x10 /* Packet Error Code */ 92#define ISMT_DESC_I2C 0x20 /* I2C Enable */ 93#define ISMT_DESC_INT 0x40 /* Interrupt */ 94#define ISMT_DESC_SOE 0x80 /* Stop On Error */ 95 96/* Hardware Descriptor Constants - Status Field */ 97#define ISMT_DESC_SCS 0x01 /* Success */ 98#define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */ 99#define ISMT_DESC_NAK 0x08 /* NAK Received */ 100#define ISMT_DESC_CRC 0x10 /* CRC Error */ 101#define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */ 102#define ISMT_DESC_COL 0x40 /* Collisions */ 103#define ISMT_DESC_LPR 0x80 /* Large Packet Received */ 104 105/* Macros */ 106#define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw)) 107 108/* iSMT General Register address offsets (SMBBAR + <addr>) */ 109#define ISMT_GR_GCTRL 0x000 /* General Control */ 110#define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */ 111#define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */ 112#define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */ 113#define ISMT_GR_ERRSTS 0x018 /* Error Status */ 114#define ISMT_GR_ERRINFO 0x01c /* Error Information */ 115 116/* iSMT Master Registers */ 117#define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */ 118#define ISMT_MSTR_MCTRL 0x108 /* Master Control */ 119#define ISMT_MSTR_MSTS 0x10c /* Master Status */ 120#define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */ 121#define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */ 122 123/* iSMT Miscellaneous Registers */ 124#define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */ 125 126/* General Control Register (GCTRL) bit definitions */ 127#define ISMT_GCTRL_TRST 0x04 /* Target Reset */ 128#define ISMT_GCTRL_KILL 0x08 /* Kill */ 129#define ISMT_GCTRL_SRST 0x40 /* Soft Reset */ 130 131/* Master Control Register (MCTRL) bit definitions */ 132#define ISMT_MCTRL_SS 0x01 /* Start/Stop */ 133#define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */ 134#define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */ 135 136/* Master Status Register (MSTS) bit definitions */ 137#define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */ 138#define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */ 139#define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */ 140#define ISMT_MSTS_IP 0x01 /* In Progress */ 141 142/* Master Descriptor Size (MDS) bit definitions */ 143#define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */ 144 145/* SMBus PHY Global Timing Register (SPGT) bit definitions */ 146#define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */ 147#define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */ 148#define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */ 149#define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */ 150#define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */ 151 152 153/* MSI Control Register (MSICTL) bit definitions */ 154#define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */ 155 156/* iSMT Hardware Descriptor */ 157struct ismt_desc { 158 u8 tgtaddr_rw; /* target address & r/w bit */ 159 u8 wr_len_cmd; /* write length in bytes or a command */ 160 u8 rd_len; /* read length */ 161 u8 control; /* control bits */ 162 u8 status; /* status bits */ 163 u8 retry; /* collision retry and retry count */ 164 u8 rxbytes; /* received bytes */ 165 u8 txbytes; /* transmitted bytes */ 166 u32 dptr_low; /* lower 32 bit of the data pointer */ 167 u32 dptr_high; /* upper 32 bit of the data pointer */ 168} __packed; 169 170struct ismt_priv { 171 struct i2c_adapter adapter; 172 void __iomem *smba; /* PCI BAR */ 173 struct pci_dev *pci_dev; 174 struct ismt_desc *hw; /* descriptor virt base addr */ 175 dma_addr_t io_rng_dma; /* descriptor HW base addr */ 176 u8 head; /* ring buffer head pointer */ 177 struct completion cmp; /* interrupt completion */ 178 u8 buffer[I2C_SMBUS_BLOCK_MAX + 16]; /* temp R/W data buffer */ 179 dma_addr_t log_dma; 180 u32 *log; 181}; 182 183static const struct pci_device_id ismt_ids[] = { 184 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) }, 185 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) }, 186 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMT) }, 187 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMT) }, 188 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMT) }, 189 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) }, 190 { 0, } 191}; 192 193MODULE_DEVICE_TABLE(pci, ismt_ids); 194 195/* Bus speed control bits for slow debuggers - refer to the docs for usage */ 196static unsigned int bus_speed; 197module_param(bus_speed, uint, S_IRUGO); 198MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)"); 199 200/** 201 * __ismt_desc_dump() - dump the contents of a specific descriptor 202 * @dev: the iSMT device 203 * @desc: the iSMT hardware descriptor 204 */ 205static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc) 206{ 207 208 dev_dbg(dev, "Descriptor struct: %p\n", desc); 209 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw); 210 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd); 211 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len); 212 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control); 213 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status); 214 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry); 215 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes); 216 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes); 217 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low); 218 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high); 219} 220/** 221 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes 222 * @priv: iSMT private data 223 */ 224static void ismt_desc_dump(struct ismt_priv *priv) 225{ 226 struct device *dev = &priv->pci_dev->dev; 227 struct ismt_desc *desc = &priv->hw[priv->head]; 228 229 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head); 230 __ismt_desc_dump(dev, desc); 231} 232 233/** 234 * ismt_gen_reg_dump() - dump the iSMT General Registers 235 * @priv: iSMT private data 236 */ 237static void ismt_gen_reg_dump(struct ismt_priv *priv) 238{ 239 struct device *dev = &priv->pci_dev->dev; 240 241 dev_dbg(dev, "Dump of the iSMT General Registers\n"); 242 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n", 243 priv->smba + ISMT_GR_GCTRL, 244 readl(priv->smba + ISMT_GR_GCTRL)); 245 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n", 246 priv->smba + ISMT_GR_SMTICL, 247 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL)); 248 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n", 249 priv->smba + ISMT_GR_ERRINTMSK, 250 readl(priv->smba + ISMT_GR_ERRINTMSK)); 251 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n", 252 priv->smba + ISMT_GR_ERRAERMSK, 253 readl(priv->smba + ISMT_GR_ERRAERMSK)); 254 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n", 255 priv->smba + ISMT_GR_ERRSTS, 256 readl(priv->smba + ISMT_GR_ERRSTS)); 257 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n", 258 priv->smba + ISMT_GR_ERRINFO, 259 readl(priv->smba + ISMT_GR_ERRINFO)); 260} 261 262/** 263 * ismt_mstr_reg_dump() - dump the iSMT Master Registers 264 * @priv: iSMT private data 265 */ 266static void ismt_mstr_reg_dump(struct ismt_priv *priv) 267{ 268 struct device *dev = &priv->pci_dev->dev; 269 270 dev_dbg(dev, "Dump of the iSMT Master Registers\n"); 271 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n", 272 priv->smba + ISMT_MSTR_MDBA, 273 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA)); 274 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n", 275 priv->smba + ISMT_MSTR_MCTRL, 276 readl(priv->smba + ISMT_MSTR_MCTRL)); 277 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n", 278 priv->smba + ISMT_MSTR_MSTS, 279 readl(priv->smba + ISMT_MSTR_MSTS)); 280 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n", 281 priv->smba + ISMT_MSTR_MDS, 282 readl(priv->smba + ISMT_MSTR_MDS)); 283 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n", 284 priv->smba + ISMT_MSTR_RPOLICY, 285 readl(priv->smba + ISMT_MSTR_RPOLICY)); 286 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n", 287 priv->smba + ISMT_SPGT, 288 readl(priv->smba + ISMT_SPGT)); 289} 290 291/** 292 * ismt_submit_desc() - add a descriptor to the ring 293 * @priv: iSMT private data 294 */ 295static void ismt_submit_desc(struct ismt_priv *priv) 296{ 297 uint fmhp; 298 uint val; 299 300 ismt_desc_dump(priv); 301 ismt_gen_reg_dump(priv); 302 ismt_mstr_reg_dump(priv); 303 304 /* Set the FMHP (Firmware Master Head Pointer)*/ 305 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16; 306 val = readl(priv->smba + ISMT_MSTR_MCTRL); 307 writel((val & ~ISMT_MCTRL_FMHP) | fmhp, 308 priv->smba + ISMT_MSTR_MCTRL); 309 310 /* Set the start bit */ 311 val = readl(priv->smba + ISMT_MSTR_MCTRL); 312 writel(val | ISMT_MCTRL_SS, 313 priv->smba + ISMT_MSTR_MCTRL); 314} 315 316/** 317 * ismt_process_desc() - handle the completion of the descriptor 318 * @desc: the iSMT hardware descriptor 319 * @data: data buffer from the upper layer 320 * @priv: ismt_priv struct holding our dma buffer 321 * @size: SMBus transaction type 322 * @read_write: flag to indicate if this is a read or write 323 */ 324static int ismt_process_desc(const struct ismt_desc *desc, 325 union i2c_smbus_data *data, 326 struct ismt_priv *priv, int size, 327 char read_write) 328{ 329 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); 330 331 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n"); 332 __ismt_desc_dump(&priv->pci_dev->dev, desc); 333 ismt_gen_reg_dump(priv); 334 ismt_mstr_reg_dump(priv); 335 336 if (desc->status & ISMT_DESC_SCS) { 337 if (read_write == I2C_SMBUS_WRITE && 338 size != I2C_SMBUS_PROC_CALL) 339 return 0; 340 341 switch (size) { 342 case I2C_SMBUS_BYTE: 343 case I2C_SMBUS_BYTE_DATA: 344 data->byte = dma_buffer[0]; 345 break; 346 case I2C_SMBUS_WORD_DATA: 347 case I2C_SMBUS_PROC_CALL: 348 data->word = dma_buffer[0] | (dma_buffer[1] << 8); 349 break; 350 case I2C_SMBUS_BLOCK_DATA: 351 if (desc->rxbytes != dma_buffer[0] + 1) 352 return -EMSGSIZE; 353 354 memcpy(data->block, dma_buffer, desc->rxbytes); 355 break; 356 case I2C_SMBUS_I2C_BLOCK_DATA: 357 memcpy(&data->block[1], dma_buffer, desc->rxbytes); 358 data->block[0] = desc->rxbytes; 359 break; 360 } 361 return 0; 362 } 363 364 if (likely(desc->status & ISMT_DESC_NAK)) 365 return -ENXIO; 366 367 if (desc->status & ISMT_DESC_CRC) 368 return -EBADMSG; 369 370 if (desc->status & ISMT_DESC_COL) 371 return -EAGAIN; 372 373 if (desc->status & ISMT_DESC_LPR) 374 return -EPROTO; 375 376 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO)) 377 return -ETIMEDOUT; 378 379 return -EIO; 380} 381 382/** 383 * ismt_access() - process an SMBus command 384 * @adap: the i2c host adapter 385 * @addr: address of the i2c/SMBus target 386 * @flags: command options 387 * @read_write: read from or write to device 388 * @command: the i2c/SMBus command to issue 389 * @size: SMBus transaction type 390 * @data: read/write data buffer 391 */ 392static int ismt_access(struct i2c_adapter *adap, u16 addr, 393 unsigned short flags, char read_write, u8 command, 394 int size, union i2c_smbus_data *data) 395{ 396 int ret; 397 unsigned long time_left; 398 dma_addr_t dma_addr = 0; /* address of the data buffer */ 399 u8 dma_size = 0; 400 enum dma_data_direction dma_direction = 0; 401 struct ismt_desc *desc; 402 struct ismt_priv *priv = i2c_get_adapdata(adap); 403 struct device *dev = &priv->pci_dev->dev; 404 u8 *dma_buffer = PTR_ALIGN(&priv->buffer[0], 16); 405 406 desc = &priv->hw[priv->head]; 407 408 /* Initialize the DMA buffer */ 409 memset(priv->buffer, 0, sizeof(priv->buffer)); 410 411 /* Initialize the descriptor */ 412 memset(desc, 0, sizeof(struct ismt_desc)); 413 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write); 414 415 /* Always clear the log entries */ 416 memset(priv->log, 0, ISMT_LOG_ENTRIES * sizeof(u32)); 417 418 /* Initialize common control bits */ 419 if (likely(pci_dev_msi_enabled(priv->pci_dev))) 420 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR; 421 else 422 desc->control = ISMT_DESC_FAIR; 423 424 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK) 425 && (size != I2C_SMBUS_I2C_BLOCK_DATA)) 426 desc->control |= ISMT_DESC_PEC; 427 428 switch (size) { 429 case I2C_SMBUS_QUICK: 430 dev_dbg(dev, "I2C_SMBUS_QUICK\n"); 431 break; 432 433 case I2C_SMBUS_BYTE: 434 if (read_write == I2C_SMBUS_WRITE) { 435 /* 436 * Send Byte 437 * The command field contains the write data 438 */ 439 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n"); 440 desc->control |= ISMT_DESC_CWRL; 441 desc->wr_len_cmd = command; 442 } else { 443 /* Receive Byte */ 444 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n"); 445 dma_size = 1; 446 dma_direction = DMA_FROM_DEVICE; 447 desc->rd_len = 1; 448 } 449 break; 450 451 case I2C_SMBUS_BYTE_DATA: 452 if (read_write == I2C_SMBUS_WRITE) { 453 /* 454 * Write Byte 455 * Command plus 1 data byte 456 */ 457 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n"); 458 desc->wr_len_cmd = 2; 459 dma_size = 2; 460 dma_direction = DMA_TO_DEVICE; 461 dma_buffer[0] = command; 462 dma_buffer[1] = data->byte; 463 } else { 464 /* Read Byte */ 465 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n"); 466 desc->control |= ISMT_DESC_CWRL; 467 desc->wr_len_cmd = command; 468 desc->rd_len = 1; 469 dma_size = 1; 470 dma_direction = DMA_FROM_DEVICE; 471 } 472 break; 473 474 case I2C_SMBUS_WORD_DATA: 475 if (read_write == I2C_SMBUS_WRITE) { 476 /* Write Word */ 477 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n"); 478 desc->wr_len_cmd = 3; 479 dma_size = 3; 480 dma_direction = DMA_TO_DEVICE; 481 dma_buffer[0] = command; 482 dma_buffer[1] = data->word & 0xff; 483 dma_buffer[2] = data->word >> 8; 484 } else { 485 /* Read Word */ 486 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n"); 487 desc->wr_len_cmd = command; 488 desc->control |= ISMT_DESC_CWRL; 489 desc->rd_len = 2; 490 dma_size = 2; 491 dma_direction = DMA_FROM_DEVICE; 492 } 493 break; 494 495 case I2C_SMBUS_PROC_CALL: 496 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n"); 497 desc->wr_len_cmd = 3; 498 desc->rd_len = 2; 499 dma_size = 3; 500 dma_direction = DMA_BIDIRECTIONAL; 501 dma_buffer[0] = command; 502 dma_buffer[1] = data->word & 0xff; 503 dma_buffer[2] = data->word >> 8; 504 break; 505 506 case I2C_SMBUS_BLOCK_DATA: 507 if (read_write == I2C_SMBUS_WRITE) { 508 /* Block Write */ 509 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n"); 510 if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 511 return -EINVAL; 512 513 dma_size = data->block[0] + 1; 514 dma_direction = DMA_TO_DEVICE; 515 desc->wr_len_cmd = dma_size; 516 desc->control |= ISMT_DESC_BLK; 517 dma_buffer[0] = command; 518 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); 519 } else { 520 /* Block Read */ 521 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n"); 522 dma_size = I2C_SMBUS_BLOCK_MAX; 523 dma_direction = DMA_FROM_DEVICE; 524 desc->rd_len = dma_size; 525 desc->wr_len_cmd = command; 526 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL); 527 } 528 break; 529 530 case I2C_SMBUS_I2C_BLOCK_DATA: 531 /* Make sure the length is valid */ 532 if (data->block[0] < 1) 533 data->block[0] = 1; 534 535 if (data->block[0] > I2C_SMBUS_BLOCK_MAX) 536 data->block[0] = I2C_SMBUS_BLOCK_MAX; 537 538 if (read_write == I2C_SMBUS_WRITE) { 539 /* i2c Block Write */ 540 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n"); 541 dma_size = data->block[0] + 1; 542 dma_direction = DMA_TO_DEVICE; 543 desc->wr_len_cmd = dma_size; 544 desc->control |= ISMT_DESC_I2C; 545 dma_buffer[0] = command; 546 memcpy(&dma_buffer[1], &data->block[1], dma_size - 1); 547 } else { 548 /* i2c Block Read */ 549 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n"); 550 dma_size = data->block[0]; 551 dma_direction = DMA_FROM_DEVICE; 552 desc->rd_len = dma_size; 553 desc->wr_len_cmd = command; 554 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL); 555 /* 556 * Per the "Table 15-15. I2C Commands", 557 * in the External Design Specification (EDS), 558 * (Document Number: 508084, Revision: 2.0), 559 * the _rw bit must be 0 560 */ 561 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0); 562 } 563 break; 564 565 default: 566 dev_err(dev, "Unsupported transaction %d\n", 567 size); 568 return -EOPNOTSUPP; 569 } 570 571 /* map the data buffer */ 572 if (dma_size != 0) { 573 dev_dbg(dev, " dev=%p\n", dev); 574 dev_dbg(dev, " data=%p\n", data); 575 dev_dbg(dev, " dma_buffer=%p\n", dma_buffer); 576 dev_dbg(dev, " dma_size=%d\n", dma_size); 577 dev_dbg(dev, " dma_direction=%d\n", dma_direction); 578 579 dma_addr = dma_map_single(dev, 580 dma_buffer, 581 dma_size, 582 dma_direction); 583 584 if (dma_mapping_error(dev, dma_addr)) { 585 dev_err(dev, "Error in mapping dma buffer %p\n", 586 dma_buffer); 587 return -EIO; 588 } 589 590 dev_dbg(dev, " dma_addr = %pad\n", &dma_addr); 591 592 desc->dptr_low = lower_32_bits(dma_addr); 593 desc->dptr_high = upper_32_bits(dma_addr); 594 } 595 596 reinit_completion(&priv->cmp); 597 598 /* Add the descriptor */ 599 ismt_submit_desc(priv); 600 601 /* Now we wait for interrupt completion, 1s */ 602 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1); 603 604 /* unmap the data buffer */ 605 if (dma_size != 0) 606 dma_unmap_single(dev, dma_addr, dma_size, dma_direction); 607 608 if (unlikely(!time_left)) { 609 dev_err(dev, "completion wait timed out\n"); 610 ret = -ETIMEDOUT; 611 goto out; 612 } 613 614 /* do any post processing of the descriptor here */ 615 ret = ismt_process_desc(desc, data, priv, size, read_write); 616 617out: 618 /* Update the ring pointer */ 619 priv->head++; 620 priv->head %= ISMT_DESC_ENTRIES; 621 622 return ret; 623} 624 625/** 626 * ismt_func() - report which i2c commands are supported by this adapter 627 * @adap: the i2c host adapter 628 */ 629static u32 ismt_func(struct i2c_adapter *adap) 630{ 631 return I2C_FUNC_SMBUS_QUICK | 632 I2C_FUNC_SMBUS_BYTE | 633 I2C_FUNC_SMBUS_BYTE_DATA | 634 I2C_FUNC_SMBUS_WORD_DATA | 635 I2C_FUNC_SMBUS_PROC_CALL | 636 I2C_FUNC_SMBUS_BLOCK_DATA | 637 I2C_FUNC_SMBUS_I2C_BLOCK | 638 I2C_FUNC_SMBUS_PEC; 639} 640 641static const struct i2c_algorithm smbus_algorithm = { 642 .smbus_xfer = ismt_access, 643 .functionality = ismt_func, 644}; 645 646/** 647 * ismt_handle_isr() - interrupt handler bottom half 648 * @priv: iSMT private data 649 */ 650static irqreturn_t ismt_handle_isr(struct ismt_priv *priv) 651{ 652 complete(&priv->cmp); 653 654 return IRQ_HANDLED; 655} 656 657 658/** 659 * ismt_do_interrupt() - IRQ interrupt handler 660 * @vec: interrupt vector 661 * @data: iSMT private data 662 */ 663static irqreturn_t ismt_do_interrupt(int vec, void *data) 664{ 665 u32 val; 666 struct ismt_priv *priv = data; 667 668 /* 669 * check to see it's our interrupt, return IRQ_NONE if not ours 670 * since we are sharing interrupt 671 */ 672 val = readl(priv->smba + ISMT_MSTR_MSTS); 673 674 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS))) 675 return IRQ_NONE; 676 else 677 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS, 678 priv->smba + ISMT_MSTR_MSTS); 679 680 return ismt_handle_isr(priv); 681} 682 683/** 684 * ismt_do_msi_interrupt() - MSI interrupt handler 685 * @vec: interrupt vector 686 * @data: iSMT private data 687 */ 688static irqreturn_t ismt_do_msi_interrupt(int vec, void *data) 689{ 690 return ismt_handle_isr(data); 691} 692 693/** 694 * ismt_hw_init() - initialize the iSMT hardware 695 * @priv: iSMT private data 696 */ 697static void ismt_hw_init(struct ismt_priv *priv) 698{ 699 u32 val; 700 struct device *dev = &priv->pci_dev->dev; 701 702 /* initialize the Master Descriptor Base Address (MDBA) */ 703 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA); 704 705 writeq(priv->log_dma, priv->smba + ISMT_GR_SMTICL); 706 707 /* initialize the Master Control Register (MCTRL) */ 708 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL); 709 710 /* initialize the Master Status Register (MSTS) */ 711 writel(0, priv->smba + ISMT_MSTR_MSTS); 712 713 /* initialize the Master Descriptor Size (MDS) */ 714 val = readl(priv->smba + ISMT_MSTR_MDS); 715 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1), 716 priv->smba + ISMT_MSTR_MDS); 717 718 /* 719 * Set the SMBus speed (could use this for slow HW debuggers) 720 */ 721 722 val = readl(priv->smba + ISMT_SPGT); 723 724 switch (bus_speed) { 725 case 0: 726 break; 727 728 case 80: 729 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n"); 730 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K), 731 priv->smba + ISMT_SPGT); 732 break; 733 734 case 100: 735 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n"); 736 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K), 737 priv->smba + ISMT_SPGT); 738 break; 739 740 case 400: 741 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n"); 742 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K), 743 priv->smba + ISMT_SPGT); 744 break; 745 746 case 1000: 747 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n"); 748 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M), 749 priv->smba + ISMT_SPGT); 750 break; 751 752 default: 753 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n"); 754 break; 755 } 756 757 val = readl(priv->smba + ISMT_SPGT); 758 759 switch (val & ISMT_SPGT_SPD_MASK) { 760 case ISMT_SPGT_SPD_80K: 761 bus_speed = 80; 762 break; 763 case ISMT_SPGT_SPD_100K: 764 bus_speed = 100; 765 break; 766 case ISMT_SPGT_SPD_400K: 767 bus_speed = 400; 768 break; 769 case ISMT_SPGT_SPD_1M: 770 bus_speed = 1000; 771 break; 772 } 773 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed); 774} 775 776/** 777 * ismt_dev_init() - initialize the iSMT data structures 778 * @priv: iSMT private data 779 */ 780static int ismt_dev_init(struct ismt_priv *priv) 781{ 782 /* allocate memory for the descriptor */ 783 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev, 784 (ISMT_DESC_ENTRIES 785 * sizeof(struct ismt_desc)), 786 &priv->io_rng_dma, 787 GFP_KERNEL); 788 if (!priv->hw) 789 return -ENOMEM; 790 791 priv->head = 0; 792 init_completion(&priv->cmp); 793 794 priv->log = dmam_alloc_coherent(&priv->pci_dev->dev, 795 ISMT_LOG_ENTRIES * sizeof(u32), 796 &priv->log_dma, GFP_KERNEL); 797 if (!priv->log) 798 return -ENOMEM; 799 800 return 0; 801} 802 803/** 804 * ismt_int_init() - initialize interrupts 805 * @priv: iSMT private data 806 */ 807static int ismt_int_init(struct ismt_priv *priv) 808{ 809 int err; 810 811 /* Try using MSI interrupts */ 812 err = pci_enable_msi(priv->pci_dev); 813 if (err) 814 goto intx; 815 816 err = devm_request_irq(&priv->pci_dev->dev, 817 priv->pci_dev->irq, 818 ismt_do_msi_interrupt, 819 0, 820 "ismt-msi", 821 priv); 822 if (err) { 823 pci_disable_msi(priv->pci_dev); 824 goto intx; 825 } 826 827 return 0; 828 829 /* Try using legacy interrupts */ 830intx: 831 dev_warn(&priv->pci_dev->dev, 832 "Unable to use MSI interrupts, falling back to legacy\n"); 833 834 err = devm_request_irq(&priv->pci_dev->dev, 835 priv->pci_dev->irq, 836 ismt_do_interrupt, 837 IRQF_SHARED, 838 "ismt-intx", 839 priv); 840 if (err) { 841 dev_err(&priv->pci_dev->dev, "no usable interrupts\n"); 842 return err; 843 } 844 845 return 0; 846} 847 848static struct pci_driver ismt_driver; 849 850/** 851 * ismt_probe() - probe for iSMT devices 852 * @pdev: PCI-Express device 853 * @id: PCI-Express device ID 854 */ 855static int 856ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id) 857{ 858 int err; 859 struct ismt_priv *priv; 860 unsigned long start, len; 861 862 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 863 if (!priv) 864 return -ENOMEM; 865 866 pci_set_drvdata(pdev, priv); 867 868 i2c_set_adapdata(&priv->adapter, priv); 869 priv->adapter.owner = THIS_MODULE; 870 priv->adapter.class = I2C_CLASS_HWMON; 871 priv->adapter.algo = &smbus_algorithm; 872 priv->adapter.dev.parent = &pdev->dev; 873 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev)); 874 priv->adapter.retries = ISMT_MAX_RETRIES; 875 876 priv->pci_dev = pdev; 877 878 err = pcim_enable_device(pdev); 879 if (err) { 880 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n", 881 err); 882 return err; 883 } 884 885 /* enable bus mastering */ 886 pci_set_master(pdev); 887 888 /* Determine the address of the SMBus area */ 889 start = pci_resource_start(pdev, SMBBAR); 890 len = pci_resource_len(pdev, SMBBAR); 891 if (!start || !len) { 892 dev_err(&pdev->dev, 893 "SMBus base address uninitialized, upgrade BIOS\n"); 894 return -ENODEV; 895 } 896 897 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 898 "SMBus iSMT adapter at %lx", start); 899 900 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start); 901 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len); 902 903 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]); 904 if (err) { 905 dev_err(&pdev->dev, "ACPI resource conflict!\n"); 906 return err; 907 } 908 909 err = pci_request_region(pdev, SMBBAR, ismt_driver.name); 910 if (err) { 911 dev_err(&pdev->dev, 912 "Failed to request SMBus region 0x%lx-0x%lx\n", 913 start, start + len); 914 return err; 915 } 916 917 priv->smba = pcim_iomap(pdev, SMBBAR, len); 918 if (!priv->smba) { 919 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n"); 920 return -ENODEV; 921 } 922 923 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) || 924 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) { 925 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) || 926 (pci_set_consistent_dma_mask(pdev, 927 DMA_BIT_MASK(32)) != 0)) { 928 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n", 929 pdev); 930 return -ENODEV; 931 } 932 } 933 934 err = ismt_dev_init(priv); 935 if (err) 936 return err; 937 938 ismt_hw_init(priv); 939 940 err = ismt_int_init(priv); 941 if (err) 942 return err; 943 944 err = i2c_add_adapter(&priv->adapter); 945 if (err) 946 return -ENODEV; 947 return 0; 948} 949 950/** 951 * ismt_remove() - release driver resources 952 * @pdev: PCI-Express device 953 */ 954static void ismt_remove(struct pci_dev *pdev) 955{ 956 struct ismt_priv *priv = pci_get_drvdata(pdev); 957 958 i2c_del_adapter(&priv->adapter); 959} 960 961static struct pci_driver ismt_driver = { 962 .name = "ismt_smbus", 963 .id_table = ismt_ids, 964 .probe = ismt_probe, 965 .remove = ismt_remove, 966}; 967 968module_pci_driver(ismt_driver); 969 970MODULE_LICENSE("Dual BSD/GPL"); 971MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>"); 972MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver"); 973