1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2002 Motorola GSG-China 4 * 5 * Author: 6 * Darius Augulis, Teltonika Inc. 7 * 8 * Desc.: 9 * Implementation of I2C Adapter/Algorithm Driver 10 * for I2C Bus integrated in Freescale i.MX/MXC processors 11 * 12 * Derived from Motorola GSG China I2C example driver 13 * 14 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de 15 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de 16 * Copyright (C) 2007 RightHand Technologies, Inc. 17 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 18 * 19 * Copyright 2013 Freescale Semiconductor, Inc. 20 * 21 */ 22 23#include <linux/acpi.h> 24#include <linux/clk.h> 25#include <linux/completion.h> 26#include <linux/delay.h> 27#include <linux/dma-mapping.h> 28#include <linux/dmaengine.h> 29#include <linux/dmapool.h> 30#include <linux/err.h> 31#include <linux/errno.h> 32#include <linux/gpio/consumer.h> 33#include <linux/i2c.h> 34#include <linux/init.h> 35#include <linux/interrupt.h> 36#include <linux/io.h> 37#include <linux/iopoll.h> 38#include <linux/kernel.h> 39#include <linux/module.h> 40#include <linux/of.h> 41#include <linux/of_device.h> 42#include <linux/of_dma.h> 43#include <linux/pinctrl/consumer.h> 44#include <linux/platform_data/i2c-imx.h> 45#include <linux/platform_device.h> 46#include <linux/pm_runtime.h> 47#include <linux/sched.h> 48#include <linux/slab.h> 49 50/* This will be the driver name the kernel reports */ 51#define DRIVER_NAME "imx-i2c" 52 53/* 54 * Enable DMA if transfer byte size is bigger than this threshold. 55 * As the hardware request, it must bigger than 4 bytes.\ 56 * I have set '16' here, maybe it's not the best but I think it's 57 * the appropriate. 58 */ 59#define DMA_THRESHOLD 16 60#define DMA_TIMEOUT 1000 61 62/* IMX I2C registers: 63 * the I2C register offset is different between SoCs, 64 * to provid support for all these chips, split the 65 * register offset into a fixed base address and a 66 * variable shift value, then the full register offset 67 * will be calculated by 68 * reg_off = ( reg_base_addr << reg_shift) 69 */ 70#define IMX_I2C_IADR 0x00 /* i2c slave address */ 71#define IMX_I2C_IFDR 0x01 /* i2c frequency divider */ 72#define IMX_I2C_I2CR 0x02 /* i2c control */ 73#define IMX_I2C_I2SR 0x03 /* i2c status */ 74#define IMX_I2C_I2DR 0x04 /* i2c transfer data */ 75 76#define IMX_I2C_REGSHIFT 2 77#define VF610_I2C_REGSHIFT 0 78 79/* Bits of IMX I2C registers */ 80#define I2SR_RXAK 0x01 81#define I2SR_IIF 0x02 82#define I2SR_SRW 0x04 83#define I2SR_IAL 0x10 84#define I2SR_IBB 0x20 85#define I2SR_IAAS 0x40 86#define I2SR_ICF 0x80 87#define I2CR_DMAEN 0x02 88#define I2CR_RSTA 0x04 89#define I2CR_TXAK 0x08 90#define I2CR_MTX 0x10 91#define I2CR_MSTA 0x20 92#define I2CR_IIEN 0x40 93#define I2CR_IEN 0x80 94 95/* register bits different operating codes definition: 96 * 1) I2SR: Interrupt flags clear operation differ between SoCs: 97 * - write zero to clear(w0c) INT flag on i.MX, 98 * - but write one to clear(w1c) INT flag on Vybrid. 99 * 2) I2CR: I2C module enable operation also differ between SoCs: 100 * - set I2CR_IEN bit enable the module on i.MX, 101 * - but clear I2CR_IEN bit enable the module on Vybrid. 102 */ 103#define I2SR_CLR_OPCODE_W0C 0x0 104#define I2SR_CLR_OPCODE_W1C (I2SR_IAL | I2SR_IIF) 105#define I2CR_IEN_OPCODE_0 0x0 106#define I2CR_IEN_OPCODE_1 I2CR_IEN 107 108#define I2C_PM_TIMEOUT 10 /* ms */ 109 110/* 111 * sorted list of clock divider, register value pairs 112 * taken from table 26-5, p.26-9, Freescale i.MX 113 * Integrated Portable System Processor Reference Manual 114 * Document Number: MC9328MXLRM, Rev. 5.1, 06/2007 115 * 116 * Duplicated divider values removed from list 117 */ 118struct imx_i2c_clk_pair { 119 u16 div; 120 u16 val; 121}; 122 123static struct imx_i2c_clk_pair imx_i2c_clk_div[] = { 124 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 125 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 126 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 127 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 128 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 129 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 130 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 131 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 132 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 133 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 134 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 135 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 136 { 3072, 0x1E }, { 3840, 0x1F } 137}; 138 139/* Vybrid VF610 clock divider, register value pairs */ 140static struct imx_i2c_clk_pair vf610_i2c_clk_div[] = { 141 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 142 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 143 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 144 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 145 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 146 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 147 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 148 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 149 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 150 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 151 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 152 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 153 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 154 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 155 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 156}; 157 158enum imx_i2c_type { 159 IMX1_I2C, 160 IMX21_I2C, 161 VF610_I2C, 162}; 163 164struct imx_i2c_hwdata { 165 enum imx_i2c_type devtype; 166 unsigned regshift; 167 struct imx_i2c_clk_pair *clk_div; 168 unsigned ndivs; 169 unsigned i2sr_clr_opcode; 170 unsigned i2cr_ien_opcode; 171}; 172 173struct imx_i2c_dma { 174 struct dma_chan *chan_tx; 175 struct dma_chan *chan_rx; 176 struct dma_chan *chan_using; 177 struct completion cmd_complete; 178 dma_addr_t dma_buf; 179 unsigned int dma_len; 180 enum dma_transfer_direction dma_transfer_dir; 181 enum dma_data_direction dma_data_dir; 182}; 183 184struct imx_i2c_struct { 185 struct i2c_adapter adapter; 186 struct clk *clk; 187 struct notifier_block clk_change_nb; 188 void __iomem *base; 189 wait_queue_head_t queue; 190 unsigned long i2csr; 191 unsigned int disable_delay; 192 int stopped; 193 unsigned int ifdr; /* IMX_I2C_IFDR */ 194 unsigned int cur_clk; 195 unsigned int bitrate; 196 const struct imx_i2c_hwdata *hwdata; 197 struct i2c_bus_recovery_info rinfo; 198 199 struct pinctrl *pinctrl; 200 struct pinctrl_state *pinctrl_pins_default; 201 struct pinctrl_state *pinctrl_pins_gpio; 202 203 struct imx_i2c_dma *dma; 204}; 205 206static const struct imx_i2c_hwdata imx1_i2c_hwdata = { 207 .devtype = IMX1_I2C, 208 .regshift = IMX_I2C_REGSHIFT, 209 .clk_div = imx_i2c_clk_div, 210 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 211 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 212 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 213 214}; 215 216static const struct imx_i2c_hwdata imx21_i2c_hwdata = { 217 .devtype = IMX21_I2C, 218 .regshift = IMX_I2C_REGSHIFT, 219 .clk_div = imx_i2c_clk_div, 220 .ndivs = ARRAY_SIZE(imx_i2c_clk_div), 221 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W0C, 222 .i2cr_ien_opcode = I2CR_IEN_OPCODE_1, 223 224}; 225 226static struct imx_i2c_hwdata vf610_i2c_hwdata = { 227 .devtype = VF610_I2C, 228 .regshift = VF610_I2C_REGSHIFT, 229 .clk_div = vf610_i2c_clk_div, 230 .ndivs = ARRAY_SIZE(vf610_i2c_clk_div), 231 .i2sr_clr_opcode = I2SR_CLR_OPCODE_W1C, 232 .i2cr_ien_opcode = I2CR_IEN_OPCODE_0, 233 234}; 235 236static const struct platform_device_id imx_i2c_devtype[] = { 237 { 238 .name = "imx1-i2c", 239 .driver_data = (kernel_ulong_t)&imx1_i2c_hwdata, 240 }, { 241 .name = "imx21-i2c", 242 .driver_data = (kernel_ulong_t)&imx21_i2c_hwdata, 243 }, { 244 /* sentinel */ 245 } 246}; 247MODULE_DEVICE_TABLE(platform, imx_i2c_devtype); 248 249static const struct of_device_id i2c_imx_dt_ids[] = { 250 { .compatible = "fsl,imx1-i2c", .data = &imx1_i2c_hwdata, }, 251 { .compatible = "fsl,imx21-i2c", .data = &imx21_i2c_hwdata, }, 252 { .compatible = "fsl,vf610-i2c", .data = &vf610_i2c_hwdata, }, 253 { /* sentinel */ } 254}; 255MODULE_DEVICE_TABLE(of, i2c_imx_dt_ids); 256 257static const struct acpi_device_id i2c_imx_acpi_ids[] = { 258 {"NXP0001", .driver_data = (kernel_ulong_t)&vf610_i2c_hwdata}, 259 { } 260}; 261MODULE_DEVICE_TABLE(acpi, i2c_imx_acpi_ids); 262 263static inline int is_imx1_i2c(struct imx_i2c_struct *i2c_imx) 264{ 265 return i2c_imx->hwdata->devtype == IMX1_I2C; 266} 267 268static inline void imx_i2c_write_reg(unsigned int val, 269 struct imx_i2c_struct *i2c_imx, unsigned int reg) 270{ 271 writeb(val, i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 272} 273 274static inline unsigned char imx_i2c_read_reg(struct imx_i2c_struct *i2c_imx, 275 unsigned int reg) 276{ 277 return readb(i2c_imx->base + (reg << i2c_imx->hwdata->regshift)); 278} 279 280/* Functions for DMA support */ 281static void i2c_imx_dma_request(struct imx_i2c_struct *i2c_imx, 282 dma_addr_t phy_addr) 283{ 284 struct imx_i2c_dma *dma; 285 struct dma_slave_config dma_sconfig; 286 struct device *dev = &i2c_imx->adapter.dev; 287 int ret; 288 289 dma = devm_kzalloc(dev, sizeof(*dma), GFP_KERNEL); 290 if (!dma) 291 return; 292 293 dma->chan_tx = dma_request_chan(dev, "tx"); 294 if (IS_ERR(dma->chan_tx)) { 295 ret = PTR_ERR(dma->chan_tx); 296 if (ret != -ENODEV && ret != -EPROBE_DEFER) 297 dev_err(dev, "can't request DMA tx channel (%d)\n", ret); 298 goto fail_al; 299 } 300 301 dma_sconfig.dst_addr = phy_addr + 302 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 303 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 304 dma_sconfig.dst_maxburst = 1; 305 dma_sconfig.direction = DMA_MEM_TO_DEV; 306 ret = dmaengine_slave_config(dma->chan_tx, &dma_sconfig); 307 if (ret < 0) { 308 dev_err(dev, "can't configure tx channel (%d)\n", ret); 309 goto fail_tx; 310 } 311 312 dma->chan_rx = dma_request_chan(dev, "rx"); 313 if (IS_ERR(dma->chan_rx)) { 314 ret = PTR_ERR(dma->chan_rx); 315 if (ret != -ENODEV && ret != -EPROBE_DEFER) 316 dev_err(dev, "can't request DMA rx channel (%d)\n", ret); 317 goto fail_tx; 318 } 319 320 dma_sconfig.src_addr = phy_addr + 321 (IMX_I2C_I2DR << i2c_imx->hwdata->regshift); 322 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 323 dma_sconfig.src_maxburst = 1; 324 dma_sconfig.direction = DMA_DEV_TO_MEM; 325 ret = dmaengine_slave_config(dma->chan_rx, &dma_sconfig); 326 if (ret < 0) { 327 dev_err(dev, "can't configure rx channel (%d)\n", ret); 328 goto fail_rx; 329 } 330 331 i2c_imx->dma = dma; 332 init_completion(&dma->cmd_complete); 333 dev_info(dev, "using %s (tx) and %s (rx) for DMA transfers\n", 334 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx)); 335 336 return; 337 338fail_rx: 339 dma_release_channel(dma->chan_rx); 340fail_tx: 341 dma_release_channel(dma->chan_tx); 342fail_al: 343 devm_kfree(dev, dma); 344} 345 346static void i2c_imx_dma_callback(void *arg) 347{ 348 struct imx_i2c_struct *i2c_imx = (struct imx_i2c_struct *)arg; 349 struct imx_i2c_dma *dma = i2c_imx->dma; 350 351 dma_unmap_single(dma->chan_using->device->dev, dma->dma_buf, 352 dma->dma_len, dma->dma_data_dir); 353 complete(&dma->cmd_complete); 354} 355 356static int i2c_imx_dma_xfer(struct imx_i2c_struct *i2c_imx, 357 struct i2c_msg *msgs) 358{ 359 struct imx_i2c_dma *dma = i2c_imx->dma; 360 struct dma_async_tx_descriptor *txdesc; 361 struct device *dev = &i2c_imx->adapter.dev; 362 struct device *chan_dev = dma->chan_using->device->dev; 363 364 dma->dma_buf = dma_map_single(chan_dev, msgs->buf, 365 dma->dma_len, dma->dma_data_dir); 366 if (dma_mapping_error(chan_dev, dma->dma_buf)) { 367 dev_err(dev, "DMA mapping failed\n"); 368 goto err_map; 369 } 370 371 txdesc = dmaengine_prep_slave_single(dma->chan_using, dma->dma_buf, 372 dma->dma_len, dma->dma_transfer_dir, 373 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 374 if (!txdesc) { 375 dev_err(dev, "Not able to get desc for DMA xfer\n"); 376 goto err_desc; 377 } 378 379 reinit_completion(&dma->cmd_complete); 380 txdesc->callback = i2c_imx_dma_callback; 381 txdesc->callback_param = i2c_imx; 382 if (dma_submit_error(dmaengine_submit(txdesc))) { 383 dev_err(dev, "DMA submit failed\n"); 384 goto err_submit; 385 } 386 387 dma_async_issue_pending(dma->chan_using); 388 return 0; 389 390err_submit: 391 dmaengine_terminate_all(dma->chan_using); 392err_desc: 393 dma_unmap_single(chan_dev, dma->dma_buf, 394 dma->dma_len, dma->dma_data_dir); 395err_map: 396 return -EINVAL; 397} 398 399static void i2c_imx_dma_free(struct imx_i2c_struct *i2c_imx) 400{ 401 struct imx_i2c_dma *dma = i2c_imx->dma; 402 403 dma->dma_buf = 0; 404 dma->dma_len = 0; 405 406 dma_release_channel(dma->chan_tx); 407 dma->chan_tx = NULL; 408 409 dma_release_channel(dma->chan_rx); 410 dma->chan_rx = NULL; 411 412 dma->chan_using = NULL; 413} 414 415static void i2c_imx_clear_irq(struct imx_i2c_struct *i2c_imx, unsigned int bits) 416{ 417 unsigned int temp; 418 419 /* 420 * i2sr_clr_opcode is the value to clear all interrupts. Here we want to 421 * clear only <bits>, so we write ~i2sr_clr_opcode with just <bits> 422 * toggled. This is required because i.MX needs W0C and Vybrid uses W1C. 423 */ 424 temp = ~i2c_imx->hwdata->i2sr_clr_opcode ^ bits; 425 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR); 426} 427 428static int i2c_imx_bus_busy(struct imx_i2c_struct *i2c_imx, int for_busy, bool atomic) 429{ 430 unsigned long orig_jiffies = jiffies; 431 unsigned int temp; 432 433 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 434 435 while (1) { 436 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 437 438 /* check for arbitration lost */ 439 if (temp & I2SR_IAL) { 440 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 441 return -EAGAIN; 442 } 443 444 if (for_busy && (temp & I2SR_IBB)) { 445 i2c_imx->stopped = 0; 446 break; 447 } 448 if (!for_busy && !(temp & I2SR_IBB)) { 449 i2c_imx->stopped = 1; 450 break; 451 } 452 if (time_after(jiffies, orig_jiffies + msecs_to_jiffies(500))) { 453 dev_dbg(&i2c_imx->adapter.dev, 454 "<%s> I2C bus is busy\n", __func__); 455 return -ETIMEDOUT; 456 } 457 if (atomic) 458 udelay(100); 459 else 460 schedule(); 461 } 462 463 return 0; 464} 465 466static int i2c_imx_trx_complete(struct imx_i2c_struct *i2c_imx, bool atomic) 467{ 468 if (atomic) { 469 void __iomem *addr = i2c_imx->base + (IMX_I2C_I2SR << i2c_imx->hwdata->regshift); 470 unsigned int regval; 471 472 /* 473 * The formula for the poll timeout is documented in the RM 474 * Rev.5 on page 1878: 475 * T_min = 10/F_scl 476 * Set the value hard as it is done for the non-atomic use-case. 477 * Use 10 kHz for the calculation since this is the minimum 478 * allowed SMBus frequency. Also add an offset of 100us since it 479 * turned out that the I2SR_IIF bit isn't set correctly within 480 * the minimum timeout in polling mode. 481 */ 482 readb_poll_timeout_atomic(addr, regval, regval & I2SR_IIF, 5, 1000 + 100); 483 i2c_imx->i2csr = regval; 484 i2c_imx_clear_irq(i2c_imx, I2SR_IIF | I2SR_IAL); 485 } else { 486 wait_event_timeout(i2c_imx->queue, i2c_imx->i2csr & I2SR_IIF, HZ / 10); 487 } 488 489 if (unlikely(!(i2c_imx->i2csr & I2SR_IIF))) { 490 dev_dbg(&i2c_imx->adapter.dev, "<%s> Timeout\n", __func__); 491 return -ETIMEDOUT; 492 } 493 494 /* check for arbitration lost */ 495 if (i2c_imx->i2csr & I2SR_IAL) { 496 dev_dbg(&i2c_imx->adapter.dev, "<%s> Arbitration lost\n", __func__); 497 i2c_imx_clear_irq(i2c_imx, I2SR_IAL); 498 499 i2c_imx->i2csr = 0; 500 return -EAGAIN; 501 } 502 503 dev_dbg(&i2c_imx->adapter.dev, "<%s> TRX complete\n", __func__); 504 i2c_imx->i2csr = 0; 505 return 0; 506} 507 508static int i2c_imx_acked(struct imx_i2c_struct *i2c_imx) 509{ 510 if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { 511 dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); 512 return -ENXIO; /* No ACK */ 513 } 514 515 dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); 516 return 0; 517} 518 519static void i2c_imx_set_clk(struct imx_i2c_struct *i2c_imx, 520 unsigned int i2c_clk_rate) 521{ 522 struct imx_i2c_clk_pair *i2c_clk_div = i2c_imx->hwdata->clk_div; 523 unsigned int div; 524 int i; 525 526 /* Divider value calculation */ 527 if (i2c_imx->cur_clk == i2c_clk_rate) 528 return; 529 530 i2c_imx->cur_clk = i2c_clk_rate; 531 532 div = (i2c_clk_rate + i2c_imx->bitrate - 1) / i2c_imx->bitrate; 533 if (div < i2c_clk_div[0].div) 534 i = 0; 535 else if (div > i2c_clk_div[i2c_imx->hwdata->ndivs - 1].div) 536 i = i2c_imx->hwdata->ndivs - 1; 537 else 538 for (i = 0; i2c_clk_div[i].div < div; i++) 539 ; 540 541 /* Store divider value */ 542 i2c_imx->ifdr = i2c_clk_div[i].val; 543 544 /* 545 * There dummy delay is calculated. 546 * It should be about one I2C clock period long. 547 * This delay is used in I2C bus disable function 548 * to fix chip hardware bug. 549 */ 550 i2c_imx->disable_delay = (500000U * i2c_clk_div[i].div 551 + (i2c_clk_rate / 2) - 1) / (i2c_clk_rate / 2); 552 553#ifdef CONFIG_I2C_DEBUG_BUS 554 dev_dbg(&i2c_imx->adapter.dev, "I2C_CLK=%d, REQ DIV=%d\n", 555 i2c_clk_rate, div); 556 dev_dbg(&i2c_imx->adapter.dev, "IFDR[IC]=0x%x, REAL DIV=%d\n", 557 i2c_clk_div[i].val, i2c_clk_div[i].div); 558#endif 559} 560 561static int i2c_imx_clk_notifier_call(struct notifier_block *nb, 562 unsigned long action, void *data) 563{ 564 struct clk_notifier_data *ndata = data; 565 struct imx_i2c_struct *i2c_imx = container_of(nb, 566 struct imx_i2c_struct, 567 clk_change_nb); 568 569 if (action & POST_RATE_CHANGE) 570 i2c_imx_set_clk(i2c_imx, ndata->new_rate); 571 572 return NOTIFY_OK; 573} 574 575static int i2c_imx_start(struct imx_i2c_struct *i2c_imx, bool atomic) 576{ 577 unsigned int temp = 0; 578 int result; 579 580 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 581 582 imx_i2c_write_reg(i2c_imx->ifdr, i2c_imx, IMX_I2C_IFDR); 583 /* Enable I2C controller */ 584 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 585 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode, i2c_imx, IMX_I2C_I2CR); 586 587 /* Wait controller to be stable */ 588 if (atomic) 589 udelay(50); 590 else 591 usleep_range(50, 150); 592 593 /* Start I2C transaction */ 594 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 595 temp |= I2CR_MSTA; 596 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 597 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 598 if (result) 599 return result; 600 601 temp |= I2CR_IIEN | I2CR_MTX | I2CR_TXAK; 602 if (atomic) 603 temp &= ~I2CR_IIEN; /* Disable interrupt */ 604 605 temp &= ~I2CR_DMAEN; 606 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 607 return result; 608} 609 610static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx, bool atomic) 611{ 612 unsigned int temp = 0; 613 614 if (!i2c_imx->stopped) { 615 /* Stop I2C transaction */ 616 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 617 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 618 if (!(temp & I2CR_MSTA)) 619 i2c_imx->stopped = 1; 620 temp &= ~(I2CR_MSTA | I2CR_MTX); 621 if (i2c_imx->dma) 622 temp &= ~I2CR_DMAEN; 623 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 624 } 625 if (is_imx1_i2c(i2c_imx)) { 626 /* 627 * This delay caused by an i.MXL hardware bug. 628 * If no (or too short) delay, no "STOP" bit will be generated. 629 */ 630 udelay(i2c_imx->disable_delay); 631 } 632 633 if (!i2c_imx->stopped) 634 i2c_imx_bus_busy(i2c_imx, 0, atomic); 635 636 /* Disable I2C controller */ 637 temp = i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 638 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 639} 640 641static irqreturn_t i2c_imx_isr(int irq, void *dev_id) 642{ 643 struct imx_i2c_struct *i2c_imx = dev_id; 644 unsigned int temp; 645 646 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 647 if (temp & I2SR_IIF) { 648 /* save status register */ 649 i2c_imx->i2csr = temp; 650 i2c_imx_clear_irq(i2c_imx, I2SR_IIF); 651 wake_up(&i2c_imx->queue); 652 return IRQ_HANDLED; 653 } 654 655 return IRQ_NONE; 656} 657 658static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, 659 struct i2c_msg *msgs) 660{ 661 int result; 662 unsigned long time_left; 663 unsigned int temp = 0; 664 unsigned long orig_jiffies = jiffies; 665 struct imx_i2c_dma *dma = i2c_imx->dma; 666 struct device *dev = &i2c_imx->adapter.dev; 667 668 dma->chan_using = dma->chan_tx; 669 dma->dma_transfer_dir = DMA_MEM_TO_DEV; 670 dma->dma_data_dir = DMA_TO_DEVICE; 671 dma->dma_len = msgs->len - 1; 672 result = i2c_imx_dma_xfer(i2c_imx, msgs); 673 if (result) 674 return result; 675 676 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 677 temp |= I2CR_DMAEN; 678 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 679 680 /* 681 * Write slave address. 682 * The first byte must be transmitted by the CPU. 683 */ 684 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 685 time_left = wait_for_completion_timeout( 686 &i2c_imx->dma->cmd_complete, 687 msecs_to_jiffies(DMA_TIMEOUT)); 688 if (time_left == 0) { 689 dmaengine_terminate_all(dma->chan_using); 690 return -ETIMEDOUT; 691 } 692 693 /* Waiting for transfer complete. */ 694 while (1) { 695 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 696 if (temp & I2SR_ICF) 697 break; 698 if (time_after(jiffies, orig_jiffies + 699 msecs_to_jiffies(DMA_TIMEOUT))) { 700 dev_dbg(dev, "<%s> Timeout\n", __func__); 701 return -ETIMEDOUT; 702 } 703 schedule(); 704 } 705 706 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 707 temp &= ~I2CR_DMAEN; 708 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 709 710 /* The last data byte must be transferred by the CPU. */ 711 imx_i2c_write_reg(msgs->buf[msgs->len-1], 712 i2c_imx, IMX_I2C_I2DR); 713 result = i2c_imx_trx_complete(i2c_imx, false); 714 if (result) 715 return result; 716 717 return i2c_imx_acked(i2c_imx); 718} 719 720static int i2c_imx_dma_read(struct imx_i2c_struct *i2c_imx, 721 struct i2c_msg *msgs, bool is_lastmsg) 722{ 723 int result; 724 unsigned long time_left; 725 unsigned int temp; 726 unsigned long orig_jiffies = jiffies; 727 struct imx_i2c_dma *dma = i2c_imx->dma; 728 struct device *dev = &i2c_imx->adapter.dev; 729 730 731 dma->chan_using = dma->chan_rx; 732 dma->dma_transfer_dir = DMA_DEV_TO_MEM; 733 dma->dma_data_dir = DMA_FROM_DEVICE; 734 /* The last two data bytes must be transferred by the CPU. */ 735 dma->dma_len = msgs->len - 2; 736 result = i2c_imx_dma_xfer(i2c_imx, msgs); 737 if (result) 738 return result; 739 740 time_left = wait_for_completion_timeout( 741 &i2c_imx->dma->cmd_complete, 742 msecs_to_jiffies(DMA_TIMEOUT)); 743 if (time_left == 0) { 744 dmaengine_terminate_all(dma->chan_using); 745 return -ETIMEDOUT; 746 } 747 748 /* waiting for transfer complete. */ 749 while (1) { 750 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 751 if (temp & I2SR_ICF) 752 break; 753 if (time_after(jiffies, orig_jiffies + 754 msecs_to_jiffies(DMA_TIMEOUT))) { 755 dev_dbg(dev, "<%s> Timeout\n", __func__); 756 return -ETIMEDOUT; 757 } 758 schedule(); 759 } 760 761 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 762 temp &= ~I2CR_DMAEN; 763 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 764 765 /* read n-1 byte data */ 766 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 767 temp |= I2CR_TXAK; 768 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 769 770 msgs->buf[msgs->len-2] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 771 /* read n byte data */ 772 result = i2c_imx_trx_complete(i2c_imx, false); 773 if (result) 774 return result; 775 776 if (is_lastmsg) { 777 /* 778 * It must generate STOP before read I2DR to prevent 779 * controller from generating another clock cycle 780 */ 781 dev_dbg(dev, "<%s> clear MSTA\n", __func__); 782 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 783 if (!(temp & I2CR_MSTA)) 784 i2c_imx->stopped = 1; 785 temp &= ~(I2CR_MSTA | I2CR_MTX); 786 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 787 if (!i2c_imx->stopped) 788 i2c_imx_bus_busy(i2c_imx, 0, false); 789 } else { 790 /* 791 * For i2c master receiver repeat restart operation like: 792 * read -> repeat MSTA -> read/write 793 * The controller must set MTX before read the last byte in 794 * the first read operation, otherwise the first read cost 795 * one extra clock cycle. 796 */ 797 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 798 temp |= I2CR_MTX; 799 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 800 } 801 msgs->buf[msgs->len-1] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 802 803 return 0; 804} 805 806static int i2c_imx_write(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 807 bool atomic) 808{ 809 int i, result; 810 811 dev_dbg(&i2c_imx->adapter.dev, "<%s> write slave address: addr=0x%x\n", 812 __func__, i2c_8bit_addr_from_msg(msgs)); 813 814 /* write slave address */ 815 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 816 result = i2c_imx_trx_complete(i2c_imx, atomic); 817 if (result) 818 return result; 819 result = i2c_imx_acked(i2c_imx); 820 if (result) 821 return result; 822 dev_dbg(&i2c_imx->adapter.dev, "<%s> write data\n", __func__); 823 824 /* write data */ 825 for (i = 0; i < msgs->len; i++) { 826 dev_dbg(&i2c_imx->adapter.dev, 827 "<%s> write byte: B%d=0x%X\n", 828 __func__, i, msgs->buf[i]); 829 imx_i2c_write_reg(msgs->buf[i], i2c_imx, IMX_I2C_I2DR); 830 result = i2c_imx_trx_complete(i2c_imx, atomic); 831 if (result) 832 return result; 833 result = i2c_imx_acked(i2c_imx); 834 if (result) 835 return result; 836 } 837 return 0; 838} 839 840static int i2c_imx_read(struct imx_i2c_struct *i2c_imx, struct i2c_msg *msgs, 841 bool is_lastmsg, bool atomic) 842{ 843 int i, result; 844 unsigned int temp; 845 int block_data = msgs->flags & I2C_M_RECV_LEN; 846 int use_dma = i2c_imx->dma && msgs->flags & I2C_M_DMA_SAFE && 847 msgs->len >= DMA_THRESHOLD && !block_data; 848 849 dev_dbg(&i2c_imx->adapter.dev, 850 "<%s> write slave address: addr=0x%x\n", 851 __func__, i2c_8bit_addr_from_msg(msgs)); 852 853 /* write slave address */ 854 imx_i2c_write_reg(i2c_8bit_addr_from_msg(msgs), i2c_imx, IMX_I2C_I2DR); 855 result = i2c_imx_trx_complete(i2c_imx, atomic); 856 if (result) 857 return result; 858 result = i2c_imx_acked(i2c_imx); 859 if (result) 860 return result; 861 862 dev_dbg(&i2c_imx->adapter.dev, "<%s> setup bus\n", __func__); 863 864 /* setup bus to read data */ 865 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 866 temp &= ~I2CR_MTX; 867 868 /* 869 * Reset the I2CR_TXAK flag initially for SMBus block read since the 870 * length is unknown 871 */ 872 if ((msgs->len - 1) || block_data) 873 temp &= ~I2CR_TXAK; 874 if (use_dma) 875 temp |= I2CR_DMAEN; 876 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 877 imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); /* dummy read */ 878 879 dev_dbg(&i2c_imx->adapter.dev, "<%s> read data\n", __func__); 880 881 if (use_dma) 882 return i2c_imx_dma_read(i2c_imx, msgs, is_lastmsg); 883 884 /* read data */ 885 for (i = 0; i < msgs->len; i++) { 886 u8 len = 0; 887 888 result = i2c_imx_trx_complete(i2c_imx, atomic); 889 if (result) 890 return result; 891 /* 892 * First byte is the length of remaining packet 893 * in the SMBus block data read. Add it to 894 * msgs->len. 895 */ 896 if ((!i) && block_data) { 897 len = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 898 if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) 899 return -EPROTO; 900 dev_dbg(&i2c_imx->adapter.dev, 901 "<%s> read length: 0x%X\n", 902 __func__, len); 903 msgs->len += len; 904 } 905 if (i == (msgs->len - 1)) { 906 if (is_lastmsg) { 907 /* 908 * It must generate STOP before read I2DR to prevent 909 * controller from generating another clock cycle 910 */ 911 dev_dbg(&i2c_imx->adapter.dev, 912 "<%s> clear MSTA\n", __func__); 913 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 914 if (!(temp & I2CR_MSTA)) 915 i2c_imx->stopped = 1; 916 temp &= ~(I2CR_MSTA | I2CR_MTX); 917 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 918 if (!i2c_imx->stopped) 919 i2c_imx_bus_busy(i2c_imx, 0, atomic); 920 } else { 921 /* 922 * For i2c master receiver repeat restart operation like: 923 * read -> repeat MSTA -> read/write 924 * The controller must set MTX before read the last byte in 925 * the first read operation, otherwise the first read cost 926 * one extra clock cycle. 927 */ 928 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 929 temp |= I2CR_MTX; 930 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 931 } 932 } else if (i == (msgs->len - 2)) { 933 dev_dbg(&i2c_imx->adapter.dev, 934 "<%s> set TXAK\n", __func__); 935 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 936 temp |= I2CR_TXAK; 937 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 938 } 939 if ((!i) && block_data) 940 msgs->buf[0] = len; 941 else 942 msgs->buf[i] = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2DR); 943 dev_dbg(&i2c_imx->adapter.dev, 944 "<%s> read byte: B%d=0x%X\n", 945 __func__, i, msgs->buf[i]); 946 } 947 return 0; 948} 949 950static int i2c_imx_xfer_common(struct i2c_adapter *adapter, 951 struct i2c_msg *msgs, int num, bool atomic) 952{ 953 unsigned int i, temp; 954 int result; 955 bool is_lastmsg = false; 956 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 957 958 dev_dbg(&i2c_imx->adapter.dev, "<%s>\n", __func__); 959 960 /* Start I2C transfer */ 961 result = i2c_imx_start(i2c_imx, atomic); 962 if (result) { 963 /* 964 * Bus recovery uses gpiod_get_value_cansleep() which is not 965 * allowed within atomic context. 966 */ 967 if (!atomic && i2c_imx->adapter.bus_recovery_info) { 968 i2c_recover_bus(&i2c_imx->adapter); 969 result = i2c_imx_start(i2c_imx, atomic); 970 } 971 } 972 973 if (result) 974 goto fail0; 975 976 /* read/write data */ 977 for (i = 0; i < num; i++) { 978 if (i == num - 1) 979 is_lastmsg = true; 980 981 if (i) { 982 dev_dbg(&i2c_imx->adapter.dev, 983 "<%s> repeated start\n", __func__); 984 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 985 temp |= I2CR_RSTA; 986 imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); 987 result = i2c_imx_bus_busy(i2c_imx, 1, atomic); 988 if (result) 989 goto fail0; 990 } 991 dev_dbg(&i2c_imx->adapter.dev, 992 "<%s> transfer message: %d\n", __func__, i); 993 /* write/read data */ 994#ifdef CONFIG_I2C_DEBUG_BUS 995 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR); 996 dev_dbg(&i2c_imx->adapter.dev, 997 "<%s> CONTROL: IEN=%d, IIEN=%d, MSTA=%d, MTX=%d, TXAK=%d, RSTA=%d\n", 998 __func__, 999 (temp & I2CR_IEN ? 1 : 0), (temp & I2CR_IIEN ? 1 : 0), 1000 (temp & I2CR_MSTA ? 1 : 0), (temp & I2CR_MTX ? 1 : 0), 1001 (temp & I2CR_TXAK ? 1 : 0), (temp & I2CR_RSTA ? 1 : 0)); 1002 temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR); 1003 dev_dbg(&i2c_imx->adapter.dev, 1004 "<%s> STATUS: ICF=%d, IAAS=%d, IBB=%d, IAL=%d, SRW=%d, IIF=%d, RXAK=%d\n", 1005 __func__, 1006 (temp & I2SR_ICF ? 1 : 0), (temp & I2SR_IAAS ? 1 : 0), 1007 (temp & I2SR_IBB ? 1 : 0), (temp & I2SR_IAL ? 1 : 0), 1008 (temp & I2SR_SRW ? 1 : 0), (temp & I2SR_IIF ? 1 : 0), 1009 (temp & I2SR_RXAK ? 1 : 0)); 1010#endif 1011 if (msgs[i].flags & I2C_M_RD) { 1012 result = i2c_imx_read(i2c_imx, &msgs[i], is_lastmsg, atomic); 1013 } else { 1014 if (!atomic && 1015 i2c_imx->dma && msgs[i].len >= DMA_THRESHOLD && 1016 msgs[i].flags & I2C_M_DMA_SAFE) 1017 result = i2c_imx_dma_write(i2c_imx, &msgs[i]); 1018 else 1019 result = i2c_imx_write(i2c_imx, &msgs[i], atomic); 1020 } 1021 if (result) 1022 goto fail0; 1023 } 1024 1025fail0: 1026 /* Stop I2C transfer */ 1027 i2c_imx_stop(i2c_imx, atomic); 1028 1029 dev_dbg(&i2c_imx->adapter.dev, "<%s> exit with: %s: %d\n", __func__, 1030 (result < 0) ? "error" : "success msg", 1031 (result < 0) ? result : num); 1032 return (result < 0) ? result : num; 1033} 1034 1035static int i2c_imx_xfer(struct i2c_adapter *adapter, 1036 struct i2c_msg *msgs, int num) 1037{ 1038 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1039 int result; 1040 1041 result = pm_runtime_resume_and_get(i2c_imx->adapter.dev.parent); 1042 if (result < 0) 1043 return result; 1044 1045 result = i2c_imx_xfer_common(adapter, msgs, num, false); 1046 1047 pm_runtime_mark_last_busy(i2c_imx->adapter.dev.parent); 1048 pm_runtime_put_autosuspend(i2c_imx->adapter.dev.parent); 1049 1050 return result; 1051} 1052 1053static int i2c_imx_xfer_atomic(struct i2c_adapter *adapter, 1054 struct i2c_msg *msgs, int num) 1055{ 1056 struct imx_i2c_struct *i2c_imx = i2c_get_adapdata(adapter); 1057 int result; 1058 1059 result = clk_enable(i2c_imx->clk); 1060 if (result) 1061 return result; 1062 1063 result = i2c_imx_xfer_common(adapter, msgs, num, true); 1064 1065 clk_disable(i2c_imx->clk); 1066 1067 return result; 1068} 1069 1070static void i2c_imx_prepare_recovery(struct i2c_adapter *adap) 1071{ 1072 struct imx_i2c_struct *i2c_imx; 1073 1074 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1075 1076 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_gpio); 1077} 1078 1079static void i2c_imx_unprepare_recovery(struct i2c_adapter *adap) 1080{ 1081 struct imx_i2c_struct *i2c_imx; 1082 1083 i2c_imx = container_of(adap, struct imx_i2c_struct, adapter); 1084 1085 pinctrl_select_state(i2c_imx->pinctrl, i2c_imx->pinctrl_pins_default); 1086} 1087 1088/* 1089 * We switch SCL and SDA to their GPIO function and do some bitbanging 1090 * for bus recovery. These alternative pinmux settings can be 1091 * described in the device tree by a separate pinctrl state "gpio". If 1092 * this is missing this is not a big problem, the only implication is 1093 * that we can't do bus recovery. 1094 */ 1095static int i2c_imx_init_recovery_info(struct imx_i2c_struct *i2c_imx, 1096 struct platform_device *pdev) 1097{ 1098 struct i2c_bus_recovery_info *rinfo = &i2c_imx->rinfo; 1099 1100 i2c_imx->pinctrl = devm_pinctrl_get(&pdev->dev); 1101 if (!i2c_imx->pinctrl || IS_ERR(i2c_imx->pinctrl)) { 1102 dev_info(&pdev->dev, "can't get pinctrl, bus recovery not supported\n"); 1103 return PTR_ERR(i2c_imx->pinctrl); 1104 } 1105 1106 i2c_imx->pinctrl_pins_default = pinctrl_lookup_state(i2c_imx->pinctrl, 1107 PINCTRL_STATE_DEFAULT); 1108 i2c_imx->pinctrl_pins_gpio = pinctrl_lookup_state(i2c_imx->pinctrl, 1109 "gpio"); 1110 rinfo->sda_gpiod = devm_gpiod_get(&pdev->dev, "sda", GPIOD_IN); 1111 rinfo->scl_gpiod = devm_gpiod_get(&pdev->dev, "scl", GPIOD_OUT_HIGH_OPEN_DRAIN); 1112 1113 if (PTR_ERR(rinfo->sda_gpiod) == -EPROBE_DEFER || 1114 PTR_ERR(rinfo->scl_gpiod) == -EPROBE_DEFER) { 1115 return -EPROBE_DEFER; 1116 } else if (IS_ERR(rinfo->sda_gpiod) || 1117 IS_ERR(rinfo->scl_gpiod) || 1118 IS_ERR(i2c_imx->pinctrl_pins_default) || 1119 IS_ERR(i2c_imx->pinctrl_pins_gpio)) { 1120 dev_dbg(&pdev->dev, "recovery information incomplete\n"); 1121 return 0; 1122 } 1123 1124 dev_dbg(&pdev->dev, "using scl%s for recovery\n", 1125 rinfo->sda_gpiod ? ",sda" : ""); 1126 1127 rinfo->prepare_recovery = i2c_imx_prepare_recovery; 1128 rinfo->unprepare_recovery = i2c_imx_unprepare_recovery; 1129 rinfo->recover_bus = i2c_generic_scl_recovery; 1130 i2c_imx->adapter.bus_recovery_info = rinfo; 1131 1132 return 0; 1133} 1134 1135static u32 i2c_imx_func(struct i2c_adapter *adapter) 1136{ 1137 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL 1138 | I2C_FUNC_SMBUS_READ_BLOCK_DATA; 1139} 1140 1141static const struct i2c_algorithm i2c_imx_algo = { 1142 .master_xfer = i2c_imx_xfer, 1143 .master_xfer_atomic = i2c_imx_xfer_atomic, 1144 .functionality = i2c_imx_func, 1145}; 1146 1147static int i2c_imx_probe(struct platform_device *pdev) 1148{ 1149 struct imx_i2c_struct *i2c_imx; 1150 struct resource *res; 1151 struct imxi2c_platform_data *pdata = dev_get_platdata(&pdev->dev); 1152 void __iomem *base; 1153 int irq, ret; 1154 dma_addr_t phy_addr; 1155 const struct imx_i2c_hwdata *match; 1156 1157 dev_dbg(&pdev->dev, "<%s>\n", __func__); 1158 1159 irq = platform_get_irq(pdev, 0); 1160 if (irq < 0) 1161 return irq; 1162 1163 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1164 base = devm_ioremap_resource(&pdev->dev, res); 1165 if (IS_ERR(base)) 1166 return PTR_ERR(base); 1167 1168 phy_addr = (dma_addr_t)res->start; 1169 i2c_imx = devm_kzalloc(&pdev->dev, sizeof(*i2c_imx), GFP_KERNEL); 1170 if (!i2c_imx) 1171 return -ENOMEM; 1172 1173 match = device_get_match_data(&pdev->dev); 1174 if (match) 1175 i2c_imx->hwdata = match; 1176 else 1177 i2c_imx->hwdata = (struct imx_i2c_hwdata *) 1178 platform_get_device_id(pdev)->driver_data; 1179 1180 /* Setup i2c_imx driver structure */ 1181 strlcpy(i2c_imx->adapter.name, pdev->name, sizeof(i2c_imx->adapter.name)); 1182 i2c_imx->adapter.owner = THIS_MODULE; 1183 i2c_imx->adapter.algo = &i2c_imx_algo; 1184 i2c_imx->adapter.dev.parent = &pdev->dev; 1185 i2c_imx->adapter.nr = pdev->id; 1186 i2c_imx->adapter.dev.of_node = pdev->dev.of_node; 1187 i2c_imx->base = base; 1188 ACPI_COMPANION_SET(&i2c_imx->adapter.dev, ACPI_COMPANION(&pdev->dev)); 1189 1190 /* Get I2C clock */ 1191 i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); 1192 if (IS_ERR(i2c_imx->clk)) 1193 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_imx->clk), 1194 "can't get I2C clock\n"); 1195 1196 ret = clk_prepare_enable(i2c_imx->clk); 1197 if (ret) { 1198 dev_err(&pdev->dev, "can't enable I2C clock, ret=%d\n", ret); 1199 return ret; 1200 } 1201 1202 /* Init queue */ 1203 init_waitqueue_head(&i2c_imx->queue); 1204 1205 /* Set up adapter data */ 1206 i2c_set_adapdata(&i2c_imx->adapter, i2c_imx); 1207 1208 /* Set up platform driver data */ 1209 platform_set_drvdata(pdev, i2c_imx); 1210 1211 pm_runtime_set_autosuspend_delay(&pdev->dev, I2C_PM_TIMEOUT); 1212 pm_runtime_use_autosuspend(&pdev->dev); 1213 pm_runtime_set_active(&pdev->dev); 1214 pm_runtime_enable(&pdev->dev); 1215 1216 ret = pm_runtime_get_sync(&pdev->dev); 1217 if (ret < 0) 1218 goto rpm_disable; 1219 1220 /* Request IRQ */ 1221 ret = request_threaded_irq(irq, i2c_imx_isr, NULL, IRQF_SHARED, 1222 pdev->name, i2c_imx); 1223 if (ret) { 1224 dev_err(&pdev->dev, "can't claim irq %d\n", irq); 1225 goto rpm_disable; 1226 } 1227 1228 /* Set up clock divider */ 1229 i2c_imx->bitrate = I2C_MAX_STANDARD_MODE_FREQ; 1230 ret = of_property_read_u32(pdev->dev.of_node, 1231 "clock-frequency", &i2c_imx->bitrate); 1232 if (ret < 0 && pdata && pdata->bitrate) 1233 i2c_imx->bitrate = pdata->bitrate; 1234 i2c_imx->clk_change_nb.notifier_call = i2c_imx_clk_notifier_call; 1235 clk_notifier_register(i2c_imx->clk, &i2c_imx->clk_change_nb); 1236 i2c_imx_set_clk(i2c_imx, clk_get_rate(i2c_imx->clk)); 1237 1238 /* Set up chip registers to defaults */ 1239 imx_i2c_write_reg(i2c_imx->hwdata->i2cr_ien_opcode ^ I2CR_IEN, 1240 i2c_imx, IMX_I2C_I2CR); 1241 imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx, IMX_I2C_I2SR); 1242 1243 /* Init optional bus recovery function */ 1244 ret = i2c_imx_init_recovery_info(i2c_imx, pdev); 1245 /* Give it another chance if pinctrl used is not ready yet */ 1246 if (ret == -EPROBE_DEFER) 1247 goto clk_notifier_unregister; 1248 1249 /* Add I2C adapter */ 1250 ret = i2c_add_numbered_adapter(&i2c_imx->adapter); 1251 if (ret < 0) 1252 goto clk_notifier_unregister; 1253 1254 pm_runtime_mark_last_busy(&pdev->dev); 1255 pm_runtime_put_autosuspend(&pdev->dev); 1256 1257 dev_dbg(&i2c_imx->adapter.dev, "claimed irq %d\n", irq); 1258 dev_dbg(&i2c_imx->adapter.dev, "device resources: %pR\n", res); 1259 dev_dbg(&i2c_imx->adapter.dev, "adapter name: \"%s\"\n", 1260 i2c_imx->adapter.name); 1261 dev_info(&i2c_imx->adapter.dev, "IMX I2C adapter registered\n"); 1262 1263 /* Init DMA config if supported */ 1264 i2c_imx_dma_request(i2c_imx, phy_addr); 1265 1266 return 0; /* Return OK */ 1267 1268clk_notifier_unregister: 1269 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1270 free_irq(irq, i2c_imx); 1271rpm_disable: 1272 pm_runtime_put_noidle(&pdev->dev); 1273 pm_runtime_disable(&pdev->dev); 1274 pm_runtime_set_suspended(&pdev->dev); 1275 pm_runtime_dont_use_autosuspend(&pdev->dev); 1276 clk_disable_unprepare(i2c_imx->clk); 1277 return ret; 1278} 1279 1280static int i2c_imx_remove(struct platform_device *pdev) 1281{ 1282 struct imx_i2c_struct *i2c_imx = platform_get_drvdata(pdev); 1283 int irq, ret; 1284 1285 ret = pm_runtime_get_sync(&pdev->dev); 1286 1287 /* remove adapter */ 1288 dev_dbg(&i2c_imx->adapter.dev, "adapter removed\n"); 1289 i2c_del_adapter(&i2c_imx->adapter); 1290 1291 if (i2c_imx->dma) 1292 i2c_imx_dma_free(i2c_imx); 1293 1294 if (ret >= 0) { 1295 /* setup chip registers to defaults */ 1296 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IADR); 1297 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_IFDR); 1298 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2CR); 1299 imx_i2c_write_reg(0, i2c_imx, IMX_I2C_I2SR); 1300 clk_disable(i2c_imx->clk); 1301 } 1302 1303 clk_notifier_unregister(i2c_imx->clk, &i2c_imx->clk_change_nb); 1304 irq = platform_get_irq(pdev, 0); 1305 if (irq >= 0) 1306 free_irq(irq, i2c_imx); 1307 1308 clk_unprepare(i2c_imx->clk); 1309 1310 pm_runtime_put_noidle(&pdev->dev); 1311 pm_runtime_disable(&pdev->dev); 1312 1313 return 0; 1314} 1315 1316static int __maybe_unused i2c_imx_runtime_suspend(struct device *dev) 1317{ 1318 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1319 1320 clk_disable(i2c_imx->clk); 1321 1322 return 0; 1323} 1324 1325static int __maybe_unused i2c_imx_runtime_resume(struct device *dev) 1326{ 1327 struct imx_i2c_struct *i2c_imx = dev_get_drvdata(dev); 1328 int ret; 1329 1330 ret = clk_enable(i2c_imx->clk); 1331 if (ret) 1332 dev_err(dev, "can't enable I2C clock, ret=%d\n", ret); 1333 1334 return ret; 1335} 1336 1337static const struct dev_pm_ops i2c_imx_pm_ops = { 1338 SET_RUNTIME_PM_OPS(i2c_imx_runtime_suspend, 1339 i2c_imx_runtime_resume, NULL) 1340}; 1341 1342static struct platform_driver i2c_imx_driver = { 1343 .probe = i2c_imx_probe, 1344 .remove = i2c_imx_remove, 1345 .driver = { 1346 .name = DRIVER_NAME, 1347 .pm = &i2c_imx_pm_ops, 1348 .of_match_table = i2c_imx_dt_ids, 1349 .acpi_match_table = i2c_imx_acpi_ids, 1350 }, 1351 .id_table = imx_i2c_devtype, 1352}; 1353 1354static int __init i2c_adap_imx_init(void) 1355{ 1356 return platform_driver_register(&i2c_imx_driver); 1357} 1358subsys_initcall(i2c_adap_imx_init); 1359 1360static void __exit i2c_adap_imx_exit(void) 1361{ 1362 platform_driver_unregister(&i2c_imx_driver); 1363} 1364module_exit(i2c_adap_imx_exit); 1365 1366MODULE_LICENSE("GPL"); 1367MODULE_AUTHOR("Darius Augulis"); 1368MODULE_DESCRIPTION("I2C adapter driver for IMX I2C bus"); 1369MODULE_ALIAS("platform:" DRIVER_NAME); 1370