1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>, 4 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker 5 <mdsxyz123@yahoo.com> 6 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de> 7 Copyright (C) 2010 Intel Corporation, 8 David Woodhouse <dwmw2@infradead.org> 9 10*/ 11 12/* 13 * Supports the following Intel I/O Controller Hubs (ICH): 14 * 15 * I/O Block I2C 16 * region SMBus Block proc. block 17 * Chip name PCI ID size PEC buffer call read 18 * --------------------------------------------------------------------------- 19 * 82801AA (ICH) 0x2413 16 no no no no 20 * 82801AB (ICH0) 0x2423 16 no no no no 21 * 82801BA (ICH2) 0x2443 16 no no no no 22 * 82801CA (ICH3) 0x2483 32 soft no no no 23 * 82801DB (ICH4) 0x24c3 32 hard yes no no 24 * 82801E (ICH5) 0x24d3 32 hard yes yes yes 25 * 6300ESB 0x25a4 32 hard yes yes yes 26 * 82801F (ICH6) 0x266a 32 hard yes yes yes 27 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes 28 * 82801G (ICH7) 0x27da 32 hard yes yes yes 29 * 82801H (ICH8) 0x283e 32 hard yes yes yes 30 * 82801I (ICH9) 0x2930 32 hard yes yes yes 31 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes 32 * ICH10 0x3a30 32 hard yes yes yes 33 * ICH10 0x3a60 32 hard yes yes yes 34 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes 35 * 6 Series (PCH) 0x1c22 32 hard yes yes yes 36 * Patsburg (PCH) 0x1d22 32 hard yes yes yes 37 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes 38 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes 39 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes 40 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes 41 * Panther Point (PCH) 0x1e22 32 hard yes yes yes 42 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes 43 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes 44 * Avoton (SOC) 0x1f3c 32 hard yes yes yes 45 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes 46 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes 47 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes 48 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes 49 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes 50 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes 51 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes 52 * BayTrail (SOC) 0x0f12 32 hard yes yes yes 53 * Braswell (SOC) 0x2292 32 hard yes yes yes 54 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes 55 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes 56 * DNV (SOC) 0x19df 32 hard yes yes yes 57 * Emmitsburg (PCH) 0x1bc9 32 hard yes yes yes 58 * Broxton (SOC) 0x5ad4 32 hard yes yes yes 59 * Lewisburg (PCH) 0xa1a3 32 hard yes yes yes 60 * Lewisburg Supersku (PCH) 0xa223 32 hard yes yes yes 61 * Kaby Lake PCH-H (PCH) 0xa2a3 32 hard yes yes yes 62 * Gemini Lake (SOC) 0x31d4 32 hard yes yes yes 63 * Cannon Lake-H (PCH) 0xa323 32 hard yes yes yes 64 * Cannon Lake-LP (PCH) 0x9da3 32 hard yes yes yes 65 * Cedar Fork (PCH) 0x18df 32 hard yes yes yes 66 * Ice Lake-LP (PCH) 0x34a3 32 hard yes yes yes 67 * Comet Lake (PCH) 0x02a3 32 hard yes yes yes 68 * Comet Lake-H (PCH) 0x06a3 32 hard yes yes yes 69 * Elkhart Lake (PCH) 0x4b23 32 hard yes yes yes 70 * Tiger Lake-LP (PCH) 0xa0a3 32 hard yes yes yes 71 * Tiger Lake-H (PCH) 0x43a3 32 hard yes yes yes 72 * Jasper Lake (SOC) 0x4da3 32 hard yes yes yes 73 * Comet Lake-V (PCH) 0xa3a3 32 hard yes yes yes 74 * Alder Lake-S (PCH) 0x7aa3 32 hard yes yes yes 75 * 76 * Features supported by this driver: 77 * Software PEC no 78 * Hardware PEC yes 79 * Block buffer yes 80 * Block process call transaction yes 81 * I2C block read transaction yes (doesn't use the block buffer) 82 * Slave mode no 83 * SMBus Host Notify yes 84 * Interrupt processing yes 85 * 86 * See the file Documentation/i2c/busses/i2c-i801.rst for details. 87 */ 88 89#include <linux/interrupt.h> 90#include <linux/module.h> 91#include <linux/pci.h> 92#include <linux/kernel.h> 93#include <linux/stddef.h> 94#include <linux/delay.h> 95#include <linux/ioport.h> 96#include <linux/init.h> 97#include <linux/i2c.h> 98#include <linux/i2c-smbus.h> 99#include <linux/acpi.h> 100#include <linux/io.h> 101#include <linux/dmi.h> 102#include <linux/slab.h> 103#include <linux/string.h> 104#include <linux/wait.h> 105#include <linux/err.h> 106#include <linux/platform_device.h> 107#include <linux/platform_data/itco_wdt.h> 108#include <linux/pm_runtime.h> 109 110#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 111#include <linux/gpio/machine.h> 112#include <linux/platform_data/i2c-mux-gpio.h> 113#endif 114 115/* I801 SMBus address offsets */ 116#define SMBHSTSTS(p) (0 + (p)->smba) 117#define SMBHSTCNT(p) (2 + (p)->smba) 118#define SMBHSTCMD(p) (3 + (p)->smba) 119#define SMBHSTADD(p) (4 + (p)->smba) 120#define SMBHSTDAT0(p) (5 + (p)->smba) 121#define SMBHSTDAT1(p) (6 + (p)->smba) 122#define SMBBLKDAT(p) (7 + (p)->smba) 123#define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */ 124#define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */ 125#define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */ 126#define SMBSLVSTS(p) (16 + (p)->smba) /* ICH3 and later */ 127#define SMBSLVCMD(p) (17 + (p)->smba) /* ICH3 and later */ 128#define SMBNTFDADD(p) (20 + (p)->smba) /* ICH3 and later */ 129 130/* PCI Address Constants */ 131#define SMBBAR 4 132#define SMBPCICTL 0x004 133#define SMBPCISTS 0x006 134#define SMBHSTCFG 0x040 135#define TCOBASE 0x050 136#define TCOCTL 0x054 137 138#define SBREG_BAR 0x10 139#define SBREG_SMBCTRL 0xc6000c 140#define SBREG_SMBCTRL_DNV 0xcf000c 141 142/* Host status bits for SMBPCISTS */ 143#define SMBPCISTS_INTS BIT(3) 144 145/* Control bits for SMBPCICTL */ 146#define SMBPCICTL_INTDIS BIT(10) 147 148/* Host configuration bits for SMBHSTCFG */ 149#define SMBHSTCFG_HST_EN BIT(0) 150#define SMBHSTCFG_SMB_SMI_EN BIT(1) 151#define SMBHSTCFG_I2C_EN BIT(2) 152#define SMBHSTCFG_SPD_WD BIT(4) 153 154/* TCO configuration bits for TCOCTL */ 155#define TCOCTL_EN BIT(8) 156 157/* Auxiliary status register bits, ICH4+ only */ 158#define SMBAUXSTS_CRCE BIT(0) 159#define SMBAUXSTS_STCO BIT(1) 160 161/* Auxiliary control register bits, ICH4+ only */ 162#define SMBAUXCTL_CRC BIT(0) 163#define SMBAUXCTL_E32B BIT(1) 164 165/* Other settings */ 166#define MAX_RETRIES 400 167 168/* I801 command constants */ 169#define I801_QUICK 0x00 170#define I801_BYTE 0x04 171#define I801_BYTE_DATA 0x08 172#define I801_WORD_DATA 0x0C 173#define I801_PROC_CALL 0x10 /* unimplemented */ 174#define I801_BLOCK_DATA 0x14 175#define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */ 176#define I801_BLOCK_PROC_CALL 0x1C 177 178/* I801 Host Control register bits */ 179#define SMBHSTCNT_INTREN BIT(0) 180#define SMBHSTCNT_KILL BIT(1) 181#define SMBHSTCNT_LAST_BYTE BIT(5) 182#define SMBHSTCNT_START BIT(6) 183#define SMBHSTCNT_PEC_EN BIT(7) /* ICH3 and later */ 184 185/* I801 Hosts Status register bits */ 186#define SMBHSTSTS_BYTE_DONE BIT(7) 187#define SMBHSTSTS_INUSE_STS BIT(6) 188#define SMBHSTSTS_SMBALERT_STS BIT(5) 189#define SMBHSTSTS_FAILED BIT(4) 190#define SMBHSTSTS_BUS_ERR BIT(3) 191#define SMBHSTSTS_DEV_ERR BIT(2) 192#define SMBHSTSTS_INTR BIT(1) 193#define SMBHSTSTS_HOST_BUSY BIT(0) 194 195/* Host Notify Status register bits */ 196#define SMBSLVSTS_HST_NTFY_STS BIT(0) 197 198/* Host Notify Command register bits */ 199#define SMBSLVCMD_HST_NTFY_INTREN BIT(0) 200 201#define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \ 202 SMBHSTSTS_DEV_ERR) 203 204#define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \ 205 STATUS_ERROR_FLAGS) 206 207/* Older devices have their ID defined in <linux/pci_ids.h> */ 208#define PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS 0x02a3 209#define PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS 0x06a3 210#define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12 211#define PCI_DEVICE_ID_INTEL_CDF_SMBUS 0x18df 212#define PCI_DEVICE_ID_INTEL_DNV_SMBUS 0x19df 213#define PCI_DEVICE_ID_INTEL_EBG_SMBUS 0x1bc9 214#define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22 215#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22 216/* Patsburg also has three 'Integrated Device Function' SMBus controllers */ 217#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70 218#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71 219#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72 220#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22 221#define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c 222#define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292 223#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330 224#define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0 225#define PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS 0x31d4 226#define PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS 0x34a3 227#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30 228#define PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS 0x43a3 229#define PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS 0x4b23 230#define PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS 0x4da3 231#define PCI_DEVICE_ID_INTEL_BROXTON_SMBUS 0x5ad4 232#define PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS 0x7aa3 233#define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22 234#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2 235#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22 236#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d 237#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e 238#define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f 239#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22 240#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2 241#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23 242#define PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS 0x9da3 243#define PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS 0xa0a3 244#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123 245#define PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS 0xa1a3 246#define PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS 0xa223 247#define PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS 0xa2a3 248#define PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS 0xa323 249#define PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS 0xa3a3 250 251struct i801_mux_config { 252 char *gpio_chip; 253 unsigned values[3]; 254 int n_values; 255 unsigned classes[3]; 256 unsigned gpios[2]; /* Relative to gpio_chip->base */ 257 int n_gpios; 258}; 259 260struct i801_priv { 261 struct i2c_adapter adapter; 262 unsigned long smba; 263 unsigned char original_hstcfg; 264 unsigned char original_slvcmd; 265 struct pci_dev *pci_dev; 266 unsigned int features; 267 268 /* isr processing */ 269 wait_queue_head_t waitq; 270 u8 status; 271 272 /* Command state used by isr for byte-by-byte block transactions */ 273 u8 cmd; 274 bool is_read; 275 int count; 276 int len; 277 u8 *data; 278 279#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 280 const struct i801_mux_config *mux_drvdata; 281 struct platform_device *mux_pdev; 282 struct gpiod_lookup_table *lookup; 283#endif 284 struct platform_device *tco_pdev; 285 286 /* 287 * If set to true the host controller registers are reserved for 288 * ACPI AML use. Protected by acpi_lock. 289 */ 290 bool acpi_reserved; 291 struct mutex acpi_lock; 292}; 293 294#define FEATURE_SMBUS_PEC BIT(0) 295#define FEATURE_BLOCK_BUFFER BIT(1) 296#define FEATURE_BLOCK_PROC BIT(2) 297#define FEATURE_I2C_BLOCK_READ BIT(3) 298#define FEATURE_IRQ BIT(4) 299#define FEATURE_HOST_NOTIFY BIT(5) 300/* Not really a feature, but it's convenient to handle it as such */ 301#define FEATURE_IDF BIT(15) 302#define FEATURE_TCO_SPT BIT(16) 303#define FEATURE_TCO_CNL BIT(17) 304 305static const char *i801_feature_names[] = { 306 "SMBus PEC", 307 "Block buffer", 308 "Block process call", 309 "I2C block read", 310 "Interrupt", 311 "SMBus Host Notify", 312}; 313 314static unsigned int disable_features; 315module_param(disable_features, uint, S_IRUGO | S_IWUSR); 316MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n" 317 "\t\t 0x01 disable SMBus PEC\n" 318 "\t\t 0x02 disable the block buffer\n" 319 "\t\t 0x08 disable the I2C block read functionality\n" 320 "\t\t 0x10 don't use interrupts\n" 321 "\t\t 0x20 disable SMBus Host Notify "); 322 323/* Make sure the SMBus host is ready to start transmitting. 324 Return 0 if it is, -EBUSY if it is not. */ 325static int i801_check_pre(struct i801_priv *priv) 326{ 327 int status; 328 329 status = inb_p(SMBHSTSTS(priv)); 330 if (status & SMBHSTSTS_HOST_BUSY) { 331 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n"); 332 return -EBUSY; 333 } 334 335 status &= STATUS_FLAGS; 336 if (status) { 337 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n", 338 status); 339 outb_p(status, SMBHSTSTS(priv)); 340 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS; 341 if (status) { 342 dev_err(&priv->pci_dev->dev, 343 "Failed clearing status flags (%02x)\n", 344 status); 345 return -EBUSY; 346 } 347 } 348 349 /* 350 * Clear CRC status if needed. 351 * During normal operation, i801_check_post() takes care 352 * of it after every operation. We do it here only in case 353 * the hardware was already in this state when the driver 354 * started. 355 */ 356 if (priv->features & FEATURE_SMBUS_PEC) { 357 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 358 if (status) { 359 dev_dbg(&priv->pci_dev->dev, 360 "Clearing aux status flags (%02x)\n", status); 361 outb_p(status, SMBAUXSTS(priv)); 362 status = inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE; 363 if (status) { 364 dev_err(&priv->pci_dev->dev, 365 "Failed clearing aux status flags (%02x)\n", 366 status); 367 return -EBUSY; 368 } 369 } 370 } 371 372 return 0; 373} 374 375/* 376 * Convert the status register to an error code, and clear it. 377 * Note that status only contains the bits we want to clear, not the 378 * actual register value. 379 */ 380static int i801_check_post(struct i801_priv *priv, int status) 381{ 382 int result = 0; 383 384 /* 385 * If the SMBus is still busy, we give up 386 * Note: This timeout condition only happens when using polling 387 * transactions. For interrupt operation, NAK/timeout is indicated by 388 * DEV_ERR. 389 */ 390 if (unlikely(status < 0)) { 391 dev_err(&priv->pci_dev->dev, "Transaction timeout\n"); 392 /* try to stop the current command */ 393 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n"); 394 outb_p(SMBHSTCNT_KILL, SMBHSTCNT(priv)); 395 usleep_range(1000, 2000); 396 outb_p(0, SMBHSTCNT(priv)); 397 398 /* Check if it worked */ 399 status = inb_p(SMBHSTSTS(priv)); 400 if ((status & SMBHSTSTS_HOST_BUSY) || 401 !(status & SMBHSTSTS_FAILED)) 402 dev_err(&priv->pci_dev->dev, 403 "Failed terminating the transaction\n"); 404 outb_p(STATUS_FLAGS, SMBHSTSTS(priv)); 405 return -ETIMEDOUT; 406 } 407 408 if (status & SMBHSTSTS_FAILED) { 409 result = -EIO; 410 dev_err(&priv->pci_dev->dev, "Transaction failed\n"); 411 } 412 if (status & SMBHSTSTS_DEV_ERR) { 413 /* 414 * This may be a PEC error, check and clear it. 415 * 416 * AUXSTS is handled differently from HSTSTS. 417 * For HSTSTS, i801_isr() or i801_wait_intr() 418 * has already cleared the error bits in hardware, 419 * and we are passed a copy of the original value 420 * in "status". 421 * For AUXSTS, the hardware register is left 422 * for us to handle here. 423 * This is asymmetric, slightly iffy, but safe, 424 * since all this code is serialized and the CRCE 425 * bit is harmless as long as it's cleared before 426 * the next operation. 427 */ 428 if ((priv->features & FEATURE_SMBUS_PEC) && 429 (inb_p(SMBAUXSTS(priv)) & SMBAUXSTS_CRCE)) { 430 outb_p(SMBAUXSTS_CRCE, SMBAUXSTS(priv)); 431 result = -EBADMSG; 432 dev_dbg(&priv->pci_dev->dev, "PEC error\n"); 433 } else { 434 result = -ENXIO; 435 dev_dbg(&priv->pci_dev->dev, "No response\n"); 436 } 437 } 438 if (status & SMBHSTSTS_BUS_ERR) { 439 result = -EAGAIN; 440 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n"); 441 } 442 443 /* Clear status flags except BYTE_DONE, to be cleared by caller */ 444 outb_p(status, SMBHSTSTS(priv)); 445 446 return result; 447} 448 449/* Wait for BUSY being cleared and either INTR or an error flag being set */ 450static int i801_wait_intr(struct i801_priv *priv) 451{ 452 int timeout = 0; 453 int status; 454 455 /* We will always wait for a fraction of a second! */ 456 do { 457 usleep_range(250, 500); 458 status = inb_p(SMBHSTSTS(priv)); 459 } while (((status & SMBHSTSTS_HOST_BUSY) || 460 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) && 461 (timeout++ < MAX_RETRIES)); 462 463 if (timeout > MAX_RETRIES) { 464 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n"); 465 return -ETIMEDOUT; 466 } 467 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR); 468} 469 470/* Wait for either BYTE_DONE or an error flag being set */ 471static int i801_wait_byte_done(struct i801_priv *priv) 472{ 473 int timeout = 0; 474 int status; 475 476 /* We will always wait for a fraction of a second! */ 477 do { 478 usleep_range(250, 500); 479 status = inb_p(SMBHSTSTS(priv)); 480 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) && 481 (timeout++ < MAX_RETRIES)); 482 483 if (timeout > MAX_RETRIES) { 484 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n"); 485 return -ETIMEDOUT; 486 } 487 return status & STATUS_ERROR_FLAGS; 488} 489 490static int i801_transaction(struct i801_priv *priv, int xact) 491{ 492 int status; 493 int result; 494 const struct i2c_adapter *adap = &priv->adapter; 495 496 result = i801_check_pre(priv); 497 if (result < 0) 498 return result; 499 500 if (priv->features & FEATURE_IRQ) { 501 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START, 502 SMBHSTCNT(priv)); 503 result = wait_event_timeout(priv->waitq, 504 (status = priv->status), 505 adap->timeout); 506 if (!result) { 507 status = -ETIMEDOUT; 508 dev_warn(&priv->pci_dev->dev, 509 "Timeout waiting for interrupt!\n"); 510 } 511 priv->status = 0; 512 return i801_check_post(priv, status); 513 } 514 515 /* the current contents of SMBHSTCNT can be overwritten, since PEC, 516 * SMBSCMD are passed in xact */ 517 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv)); 518 519 status = i801_wait_intr(priv); 520 return i801_check_post(priv, status); 521} 522 523static int i801_block_transaction_by_block(struct i801_priv *priv, 524 union i2c_smbus_data *data, 525 char read_write, int command, 526 int hwpec) 527{ 528 int i, len; 529 int status; 530 int xact = hwpec ? SMBHSTCNT_PEC_EN : 0; 531 532 switch (command) { 533 case I2C_SMBUS_BLOCK_PROC_CALL: 534 xact |= I801_BLOCK_PROC_CALL; 535 break; 536 case I2C_SMBUS_BLOCK_DATA: 537 xact |= I801_BLOCK_DATA; 538 break; 539 default: 540 return -EOPNOTSUPP; 541 } 542 543 /* Set block buffer mode */ 544 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv)); 545 546 if (read_write == I2C_SMBUS_WRITE) { 547 len = data->block[0]; 548 outb_p(len, SMBHSTDAT0(priv)); 549 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 550 for (i = 0; i < len; i++) 551 outb_p(data->block[i+1], SMBBLKDAT(priv)); 552 } 553 554 status = i801_transaction(priv, xact); 555 if (status) 556 return status; 557 558 if (read_write == I2C_SMBUS_READ || 559 command == I2C_SMBUS_BLOCK_PROC_CALL) { 560 len = inb_p(SMBHSTDAT0(priv)); 561 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) 562 return -EPROTO; 563 564 data->block[0] = len; 565 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */ 566 for (i = 0; i < len; i++) 567 data->block[i + 1] = inb_p(SMBBLKDAT(priv)); 568 } 569 return 0; 570} 571 572static void i801_isr_byte_done(struct i801_priv *priv) 573{ 574 if (priv->is_read) { 575 /* For SMBus block reads, length is received with first byte */ 576 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) && 577 (priv->count == 0)) { 578 priv->len = inb_p(SMBHSTDAT0(priv)); 579 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) { 580 dev_err(&priv->pci_dev->dev, 581 "Illegal SMBus block read size %d\n", 582 priv->len); 583 /* FIXME: Recover */ 584 priv->len = I2C_SMBUS_BLOCK_MAX; 585 } else { 586 dev_dbg(&priv->pci_dev->dev, 587 "SMBus block read size is %d\n", 588 priv->len); 589 } 590 priv->data[-1] = priv->len; 591 } 592 593 /* Read next byte */ 594 if (priv->count < priv->len) 595 priv->data[priv->count++] = inb(SMBBLKDAT(priv)); 596 else 597 dev_dbg(&priv->pci_dev->dev, 598 "Discarding extra byte on block read\n"); 599 600 /* Set LAST_BYTE for last byte of read transaction */ 601 if (priv->count == priv->len - 1) 602 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE, 603 SMBHSTCNT(priv)); 604 } else if (priv->count < priv->len - 1) { 605 /* Write next byte, except for IRQ after last byte */ 606 outb_p(priv->data[++priv->count], SMBBLKDAT(priv)); 607 } 608 609 /* Clear BYTE_DONE to continue with next byte */ 610 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 611} 612 613static irqreturn_t i801_host_notify_isr(struct i801_priv *priv) 614{ 615 unsigned short addr; 616 617 addr = inb_p(SMBNTFDADD(priv)) >> 1; 618 619 /* 620 * With the tested platforms, reading SMBNTFDDAT (22 + (p)->smba) 621 * always returns 0. Our current implementation doesn't provide 622 * data, so we just ignore it. 623 */ 624 i2c_handle_smbus_host_notify(&priv->adapter, addr); 625 626 /* clear Host Notify bit and return */ 627 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 628 return IRQ_HANDLED; 629} 630 631/* 632 * There are three kinds of interrupts: 633 * 634 * 1) i801 signals transaction completion with one of these interrupts: 635 * INTR - Success 636 * DEV_ERR - Invalid command, NAK or communication timeout 637 * BUS_ERR - SMI# transaction collision 638 * FAILED - transaction was canceled due to a KILL request 639 * When any of these occur, update ->status and wake up the waitq. 640 * ->status must be cleared before kicking off the next transaction. 641 * 642 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt 643 * occurs for each byte of a byte-by-byte to prepare the next byte. 644 * 645 * 3) Host Notify interrupts 646 */ 647static irqreturn_t i801_isr(int irq, void *dev_id) 648{ 649 struct i801_priv *priv = dev_id; 650 u16 pcists; 651 u8 status; 652 653 /* Confirm this is our interrupt */ 654 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 655 if (!(pcists & SMBPCISTS_INTS)) 656 return IRQ_NONE; 657 658 if (priv->features & FEATURE_HOST_NOTIFY) { 659 status = inb_p(SMBSLVSTS(priv)); 660 if (status & SMBSLVSTS_HST_NTFY_STS) 661 return i801_host_notify_isr(priv); 662 } 663 664 status = inb_p(SMBHSTSTS(priv)); 665 if (status & SMBHSTSTS_BYTE_DONE) 666 i801_isr_byte_done(priv); 667 668 /* 669 * Clear irq sources and report transaction result. 670 * ->status must be cleared before the next transaction is started. 671 */ 672 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS; 673 if (status) { 674 outb_p(status, SMBHSTSTS(priv)); 675 priv->status = status; 676 wake_up(&priv->waitq); 677 } 678 679 return IRQ_HANDLED; 680} 681 682/* 683 * For "byte-by-byte" block transactions: 684 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1 685 * I2C read uses cmd=I801_I2C_BLOCK_DATA 686 */ 687static int i801_block_transaction_byte_by_byte(struct i801_priv *priv, 688 union i2c_smbus_data *data, 689 char read_write, int command, 690 int hwpec) 691{ 692 int i, len; 693 int smbcmd; 694 int status; 695 int result; 696 const struct i2c_adapter *adap = &priv->adapter; 697 698 if (command == I2C_SMBUS_BLOCK_PROC_CALL) 699 return -EOPNOTSUPP; 700 701 result = i801_check_pre(priv); 702 if (result < 0) 703 return result; 704 705 len = data->block[0]; 706 707 if (read_write == I2C_SMBUS_WRITE) { 708 outb_p(len, SMBHSTDAT0(priv)); 709 outb_p(data->block[1], SMBBLKDAT(priv)); 710 } 711 712 if (command == I2C_SMBUS_I2C_BLOCK_DATA && 713 read_write == I2C_SMBUS_READ) 714 smbcmd = I801_I2C_BLOCK_DATA; 715 else 716 smbcmd = I801_BLOCK_DATA; 717 718 if (priv->features & FEATURE_IRQ) { 719 priv->is_read = (read_write == I2C_SMBUS_READ); 720 if (len == 1 && priv->is_read) 721 smbcmd |= SMBHSTCNT_LAST_BYTE; 722 priv->cmd = smbcmd | SMBHSTCNT_INTREN; 723 priv->len = len; 724 priv->count = 0; 725 priv->data = &data->block[1]; 726 727 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 728 result = wait_event_timeout(priv->waitq, 729 (status = priv->status), 730 adap->timeout); 731 if (!result) { 732 status = -ETIMEDOUT; 733 dev_warn(&priv->pci_dev->dev, 734 "Timeout waiting for interrupt!\n"); 735 } 736 priv->status = 0; 737 return i801_check_post(priv, status); 738 } 739 740 if (len == 1 && read_write == I2C_SMBUS_READ) 741 smbcmd |= SMBHSTCNT_LAST_BYTE; 742 outb_p(smbcmd | SMBHSTCNT_START, SMBHSTCNT(priv)); 743 744 for (i = 1; i <= len; i++) { 745 status = i801_wait_byte_done(priv); 746 if (status) 747 goto exit; 748 749 if (i == 1 && read_write == I2C_SMBUS_READ 750 && command != I2C_SMBUS_I2C_BLOCK_DATA) { 751 len = inb_p(SMBHSTDAT0(priv)); 752 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) { 753 dev_err(&priv->pci_dev->dev, 754 "Illegal SMBus block read size %d\n", 755 len); 756 /* Recover */ 757 while (inb_p(SMBHSTSTS(priv)) & 758 SMBHSTSTS_HOST_BUSY) 759 outb_p(SMBHSTSTS_BYTE_DONE, 760 SMBHSTSTS(priv)); 761 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv)); 762 return -EPROTO; 763 } 764 data->block[0] = len; 765 } 766 767 if (read_write == I2C_SMBUS_READ) { 768 data->block[i] = inb_p(SMBBLKDAT(priv)); 769 if (i == len - 1) 770 outb_p(smbcmd | SMBHSTCNT_LAST_BYTE, SMBHSTCNT(priv)); 771 } 772 773 if (read_write == I2C_SMBUS_WRITE && i+1 <= len) 774 outb_p(data->block[i+1], SMBBLKDAT(priv)); 775 776 /* signals SMBBLKDAT ready */ 777 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv)); 778 } 779 780 status = i801_wait_intr(priv); 781exit: 782 return i801_check_post(priv, status); 783} 784 785/* Block transaction function */ 786static int i801_block_transaction(struct i801_priv *priv, 787 union i2c_smbus_data *data, char read_write, 788 int command, int hwpec) 789{ 790 int result = 0; 791 unsigned char hostc; 792 793 if (read_write == I2C_SMBUS_READ && command == I2C_SMBUS_BLOCK_DATA) 794 data->block[0] = I2C_SMBUS_BLOCK_MAX; 795 else if (data->block[0] < 1 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 796 return -EPROTO; 797 798 if (command == I2C_SMBUS_I2C_BLOCK_DATA) { 799 if (read_write == I2C_SMBUS_WRITE) { 800 /* set I2C_EN bit in configuration register */ 801 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc); 802 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, 803 hostc | SMBHSTCFG_I2C_EN); 804 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) { 805 dev_err(&priv->pci_dev->dev, 806 "I2C block read is unsupported!\n"); 807 return -EOPNOTSUPP; 808 } 809 } 810 811 /* Experience has shown that the block buffer can only be used for 812 SMBus (not I2C) block transactions, even though the datasheet 813 doesn't mention this limitation. */ 814 if ((priv->features & FEATURE_BLOCK_BUFFER) && 815 command != I2C_SMBUS_I2C_BLOCK_DATA) 816 result = i801_block_transaction_by_block(priv, data, 817 read_write, 818 command, hwpec); 819 else 820 result = i801_block_transaction_byte_by_byte(priv, data, 821 read_write, 822 command, hwpec); 823 824 if (command == I2C_SMBUS_I2C_BLOCK_DATA 825 && read_write == I2C_SMBUS_WRITE) { 826 /* restore saved configuration register value */ 827 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc); 828 } 829 return result; 830} 831 832/* Return negative errno on error. */ 833static s32 i801_access(struct i2c_adapter *adap, u16 addr, 834 unsigned short flags, char read_write, u8 command, 835 int size, union i2c_smbus_data *data) 836{ 837 int hwpec; 838 int block = 0; 839 int ret = 0, xact = 0; 840 struct i801_priv *priv = i2c_get_adapdata(adap); 841 842 mutex_lock(&priv->acpi_lock); 843 if (priv->acpi_reserved) { 844 mutex_unlock(&priv->acpi_lock); 845 return -EBUSY; 846 } 847 848 pm_runtime_get_sync(&priv->pci_dev->dev); 849 850 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC) 851 && size != I2C_SMBUS_QUICK 852 && size != I2C_SMBUS_I2C_BLOCK_DATA; 853 854 switch (size) { 855 case I2C_SMBUS_QUICK: 856 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 857 SMBHSTADD(priv)); 858 xact = I801_QUICK; 859 break; 860 case I2C_SMBUS_BYTE: 861 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 862 SMBHSTADD(priv)); 863 if (read_write == I2C_SMBUS_WRITE) 864 outb_p(command, SMBHSTCMD(priv)); 865 xact = I801_BYTE; 866 break; 867 case I2C_SMBUS_BYTE_DATA: 868 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 869 SMBHSTADD(priv)); 870 outb_p(command, SMBHSTCMD(priv)); 871 if (read_write == I2C_SMBUS_WRITE) 872 outb_p(data->byte, SMBHSTDAT0(priv)); 873 xact = I801_BYTE_DATA; 874 break; 875 case I2C_SMBUS_WORD_DATA: 876 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 877 SMBHSTADD(priv)); 878 outb_p(command, SMBHSTCMD(priv)); 879 if (read_write == I2C_SMBUS_WRITE) { 880 outb_p(data->word & 0xff, SMBHSTDAT0(priv)); 881 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv)); 882 } 883 xact = I801_WORD_DATA; 884 break; 885 case I2C_SMBUS_BLOCK_DATA: 886 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01), 887 SMBHSTADD(priv)); 888 outb_p(command, SMBHSTCMD(priv)); 889 block = 1; 890 break; 891 case I2C_SMBUS_I2C_BLOCK_DATA: 892 /* 893 * NB: page 240 of ICH5 datasheet shows that the R/#W 894 * bit should be cleared here, even when reading. 895 * However if SPD Write Disable is set (Lynx Point and later), 896 * the read will fail if we don't set the R/#W bit. 897 */ 898 outb_p(((addr & 0x7f) << 1) | 899 ((priv->original_hstcfg & SMBHSTCFG_SPD_WD) ? 900 (read_write & 0x01) : 0), 901 SMBHSTADD(priv)); 902 if (read_write == I2C_SMBUS_READ) { 903 /* NB: page 240 of ICH5 datasheet also shows 904 * that DATA1 is the cmd field when reading */ 905 outb_p(command, SMBHSTDAT1(priv)); 906 } else 907 outb_p(command, SMBHSTCMD(priv)); 908 block = 1; 909 break; 910 case I2C_SMBUS_BLOCK_PROC_CALL: 911 /* 912 * Bit 0 of the slave address register always indicate a write 913 * command. 914 */ 915 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv)); 916 outb_p(command, SMBHSTCMD(priv)); 917 block = 1; 918 break; 919 default: 920 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n", 921 size); 922 ret = -EOPNOTSUPP; 923 goto out; 924 } 925 926 if (hwpec) /* enable/disable hardware PEC */ 927 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv)); 928 else 929 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC), 930 SMBAUXCTL(priv)); 931 932 if (block) 933 ret = i801_block_transaction(priv, data, read_write, size, 934 hwpec); 935 else 936 ret = i801_transaction(priv, xact); 937 938 /* Some BIOSes don't like it when PEC is enabled at reboot or resume 939 time, so we forcibly disable it after every transaction. Turn off 940 E32B for the same reason. */ 941 if (hwpec || block) 942 outb_p(inb_p(SMBAUXCTL(priv)) & 943 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 944 945 if (block) 946 goto out; 947 if (ret) 948 goto out; 949 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK)) 950 goto out; 951 952 switch (xact & 0x7f) { 953 case I801_BYTE: /* Result put in SMBHSTDAT0 */ 954 case I801_BYTE_DATA: 955 data->byte = inb_p(SMBHSTDAT0(priv)); 956 break; 957 case I801_WORD_DATA: 958 data->word = inb_p(SMBHSTDAT0(priv)) + 959 (inb_p(SMBHSTDAT1(priv)) << 8); 960 break; 961 } 962 963out: 964 /* Unlock the SMBus device for use by BIOS/ACPI */ 965 outb_p(SMBHSTSTS_INUSE_STS, SMBHSTSTS(priv)); 966 967 pm_runtime_mark_last_busy(&priv->pci_dev->dev); 968 pm_runtime_put_autosuspend(&priv->pci_dev->dev); 969 mutex_unlock(&priv->acpi_lock); 970 return ret; 971} 972 973 974static u32 i801_func(struct i2c_adapter *adapter) 975{ 976 struct i801_priv *priv = i2c_get_adapdata(adapter); 977 978 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 979 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 980 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK | 981 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) | 982 ((priv->features & FEATURE_BLOCK_PROC) ? 983 I2C_FUNC_SMBUS_BLOCK_PROC_CALL : 0) | 984 ((priv->features & FEATURE_I2C_BLOCK_READ) ? 985 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0) | 986 ((priv->features & FEATURE_HOST_NOTIFY) ? 987 I2C_FUNC_SMBUS_HOST_NOTIFY : 0); 988} 989 990static void i801_enable_host_notify(struct i2c_adapter *adapter) 991{ 992 struct i801_priv *priv = i2c_get_adapdata(adapter); 993 994 if (!(priv->features & FEATURE_HOST_NOTIFY)) 995 return; 996 997 if (!(SMBSLVCMD_HST_NTFY_INTREN & priv->original_slvcmd)) 998 outb_p(SMBSLVCMD_HST_NTFY_INTREN | priv->original_slvcmd, 999 SMBSLVCMD(priv)); 1000 1001 /* clear Host Notify bit to allow a new notification */ 1002 outb_p(SMBSLVSTS_HST_NTFY_STS, SMBSLVSTS(priv)); 1003} 1004 1005static void i801_disable_host_notify(struct i801_priv *priv) 1006{ 1007 if (!(priv->features & FEATURE_HOST_NOTIFY)) 1008 return; 1009 1010 outb_p(priv->original_slvcmd, SMBSLVCMD(priv)); 1011} 1012 1013static const struct i2c_algorithm smbus_algorithm = { 1014 .smbus_xfer = i801_access, 1015 .functionality = i801_func, 1016}; 1017 1018static const struct pci_device_id i801_ids[] = { 1019 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) }, 1020 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) }, 1021 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) }, 1022 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) }, 1023 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) }, 1024 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) }, 1025 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) }, 1026 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) }, 1027 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) }, 1028 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) }, 1029 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) }, 1030 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) }, 1031 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) }, 1032 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) }, 1033 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) }, 1034 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) }, 1035 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) }, 1036 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) }, 1037 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) }, 1038 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) }, 1039 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) }, 1040 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) }, 1041 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) }, 1042 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) }, 1043 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) }, 1044 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) }, 1045 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) }, 1046 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) }, 1047 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) }, 1048 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) }, 1049 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) }, 1050 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GEMINILAKE_SMBUS) }, 1051 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) }, 1052 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) }, 1053 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) }, 1054 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) }, 1055 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) }, 1056 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) }, 1057 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CDF_SMBUS) }, 1058 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) }, 1059 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EBG_SMBUS) }, 1060 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BROXTON_SMBUS) }, 1061 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS) }, 1062 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS) }, 1063 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS) }, 1064 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS) }, 1065 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS) }, 1066 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS) }, 1067 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS) }, 1068 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS) }, 1069 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS) }, 1070 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS) }, 1071 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS) }, 1072 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS) }, 1073 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS) }, 1074 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS) }, 1075 { 0, } 1076}; 1077 1078MODULE_DEVICE_TABLE(pci, i801_ids); 1079 1080#if defined CONFIG_X86 && defined CONFIG_DMI 1081static unsigned char apanel_addr; 1082 1083/* Scan the system ROM for the signature "FJKEYINF" */ 1084static __init const void __iomem *bios_signature(const void __iomem *bios) 1085{ 1086 ssize_t offset; 1087 const unsigned char signature[] = "FJKEYINF"; 1088 1089 for (offset = 0; offset < 0x10000; offset += 0x10) { 1090 if (check_signature(bios + offset, signature, 1091 sizeof(signature)-1)) 1092 return bios + offset; 1093 } 1094 return NULL; 1095} 1096 1097static void __init input_apanel_init(void) 1098{ 1099 void __iomem *bios; 1100 const void __iomem *p; 1101 1102 bios = ioremap(0xF0000, 0x10000); /* Can't fail */ 1103 p = bios_signature(bios); 1104 if (p) { 1105 /* just use the first address */ 1106 apanel_addr = readb(p + 8 + 3) >> 1; 1107 } 1108 iounmap(bios); 1109} 1110 1111struct dmi_onboard_device_info { 1112 const char *name; 1113 u8 type; 1114 unsigned short i2c_addr; 1115 const char *i2c_type; 1116}; 1117 1118static const struct dmi_onboard_device_info dmi_devices[] = { 1119 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" }, 1120 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" }, 1121 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" }, 1122}; 1123 1124static void dmi_check_onboard_device(u8 type, const char *name, 1125 struct i2c_adapter *adap) 1126{ 1127 int i; 1128 struct i2c_board_info info; 1129 1130 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) { 1131 /* & ~0x80, ignore enabled/disabled bit */ 1132 if ((type & ~0x80) != dmi_devices[i].type) 1133 continue; 1134 if (strcasecmp(name, dmi_devices[i].name)) 1135 continue; 1136 1137 memset(&info, 0, sizeof(struct i2c_board_info)); 1138 info.addr = dmi_devices[i].i2c_addr; 1139 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE); 1140 i2c_new_client_device(adap, &info); 1141 break; 1142 } 1143} 1144 1145/* We use our own function to check for onboard devices instead of 1146 dmi_find_device() as some buggy BIOS's have the devices we are interested 1147 in marked as disabled */ 1148static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap) 1149{ 1150 int i, count; 1151 1152 if (dm->type != 10) 1153 return; 1154 1155 count = (dm->length - sizeof(struct dmi_header)) / 2; 1156 for (i = 0; i < count; i++) { 1157 const u8 *d = (char *)(dm + 1) + (i * 2); 1158 const char *name = ((char *) dm) + dm->length; 1159 u8 type = d[0]; 1160 u8 s = d[1]; 1161 1162 if (!s) 1163 continue; 1164 s--; 1165 while (s > 0 && name[0]) { 1166 name += strlen(name) + 1; 1167 s--; 1168 } 1169 if (name[0] == 0) /* Bogus string reference */ 1170 continue; 1171 1172 dmi_check_onboard_device(type, name, adap); 1173 } 1174} 1175 1176/* NOTE: Keep this list in sync with drivers/platform/x86/dell-smo8800.c */ 1177static const char *const acpi_smo8800_ids[] = { 1178 "SMO8800", 1179 "SMO8801", 1180 "SMO8810", 1181 "SMO8811", 1182 "SMO8820", 1183 "SMO8821", 1184 "SMO8830", 1185 "SMO8831", 1186}; 1187 1188static acpi_status check_acpi_smo88xx_device(acpi_handle obj_handle, 1189 u32 nesting_level, 1190 void *context, 1191 void **return_value) 1192{ 1193 struct acpi_device_info *info; 1194 acpi_status status; 1195 char *hid; 1196 int i; 1197 1198 status = acpi_get_object_info(obj_handle, &info); 1199 if (ACPI_FAILURE(status)) 1200 return AE_OK; 1201 1202 if (!(info->valid & ACPI_VALID_HID)) 1203 goto smo88xx_not_found; 1204 1205 hid = info->hardware_id.string; 1206 if (!hid) 1207 goto smo88xx_not_found; 1208 1209 i = match_string(acpi_smo8800_ids, ARRAY_SIZE(acpi_smo8800_ids), hid); 1210 if (i < 0) 1211 goto smo88xx_not_found; 1212 1213 kfree(info); 1214 1215 *((bool *)return_value) = true; 1216 return AE_CTRL_TERMINATE; 1217 1218smo88xx_not_found: 1219 kfree(info); 1220 return AE_OK; 1221} 1222 1223static bool is_dell_system_with_lis3lv02d(void) 1224{ 1225 bool found; 1226 const char *vendor; 1227 1228 vendor = dmi_get_system_info(DMI_SYS_VENDOR); 1229 if (!vendor || strcmp(vendor, "Dell Inc.")) 1230 return false; 1231 1232 /* 1233 * Check that ACPI device SMO88xx is present and is functioning. 1234 * Function acpi_get_devices() already filters all ACPI devices 1235 * which are not present or are not functioning. 1236 * ACPI device SMO88xx represents our ST microelectronics lis3lv02d 1237 * accelerometer but unfortunately ACPI does not provide any other 1238 * information (like I2C address). 1239 */ 1240 found = false; 1241 acpi_get_devices(NULL, check_acpi_smo88xx_device, NULL, 1242 (void **)&found); 1243 1244 return found; 1245} 1246 1247/* 1248 * Accelerometer's I2C address is not specified in DMI nor ACPI, 1249 * so it is needed to define mapping table based on DMI product names. 1250 */ 1251static const struct { 1252 const char *dmi_product_name; 1253 unsigned short i2c_addr; 1254} dell_lis3lv02d_devices[] = { 1255 /* 1256 * Dell platform team told us that these Latitude devices have 1257 * ST microelectronics accelerometer at I2C address 0x29. 1258 */ 1259 { "Latitude E5250", 0x29 }, 1260 { "Latitude E5450", 0x29 }, 1261 { "Latitude E5550", 0x29 }, 1262 { "Latitude E6440", 0x29 }, 1263 { "Latitude E6440 ATG", 0x29 }, 1264 { "Latitude E6540", 0x29 }, 1265 /* 1266 * Additional individual entries were added after verification. 1267 */ 1268 { "Latitude 5480", 0x29 }, 1269 { "Vostro V131", 0x1d }, 1270 { "Vostro 5568", 0x29 }, 1271}; 1272 1273static void register_dell_lis3lv02d_i2c_device(struct i801_priv *priv) 1274{ 1275 struct i2c_board_info info; 1276 const char *dmi_product_name; 1277 int i; 1278 1279 dmi_product_name = dmi_get_system_info(DMI_PRODUCT_NAME); 1280 for (i = 0; i < ARRAY_SIZE(dell_lis3lv02d_devices); ++i) { 1281 if (strcmp(dmi_product_name, 1282 dell_lis3lv02d_devices[i].dmi_product_name) == 0) 1283 break; 1284 } 1285 1286 if (i == ARRAY_SIZE(dell_lis3lv02d_devices)) { 1287 dev_warn(&priv->pci_dev->dev, 1288 "Accelerometer lis3lv02d is present on SMBus but its" 1289 " address is unknown, skipping registration\n"); 1290 return; 1291 } 1292 1293 memset(&info, 0, sizeof(struct i2c_board_info)); 1294 info.addr = dell_lis3lv02d_devices[i].i2c_addr; 1295 strlcpy(info.type, "lis3lv02d", I2C_NAME_SIZE); 1296 i2c_new_client_device(&priv->adapter, &info); 1297} 1298 1299/* Register optional slaves */ 1300static void i801_probe_optional_slaves(struct i801_priv *priv) 1301{ 1302 /* Only register slaves on main SMBus channel */ 1303 if (priv->features & FEATURE_IDF) 1304 return; 1305 1306 if (apanel_addr) { 1307 struct i2c_board_info info; 1308 1309 memset(&info, 0, sizeof(struct i2c_board_info)); 1310 info.addr = apanel_addr; 1311 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE); 1312 i2c_new_client_device(&priv->adapter, &info); 1313 } 1314 1315 if (dmi_name_in_vendors("FUJITSU")) 1316 dmi_walk(dmi_check_onboard_devices, &priv->adapter); 1317 1318 if (is_dell_system_with_lis3lv02d()) 1319 register_dell_lis3lv02d_i2c_device(priv); 1320 1321 /* Instantiate SPD EEPROMs unless the SMBus is multiplexed */ 1322#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) 1323 if (!priv->mux_drvdata) 1324#endif 1325 i2c_register_spd(&priv->adapter); 1326} 1327#else 1328static void __init input_apanel_init(void) {} 1329static void i801_probe_optional_slaves(struct i801_priv *priv) {} 1330#endif /* CONFIG_X86 && CONFIG_DMI */ 1331 1332#if IS_ENABLED(CONFIG_I2C_MUX_GPIO) && defined CONFIG_DMI 1333static struct i801_mux_config i801_mux_config_asus_z8_d12 = { 1334 .gpio_chip = "gpio_ich", 1335 .values = { 0x02, 0x03 }, 1336 .n_values = 2, 1337 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD }, 1338 .gpios = { 52, 53 }, 1339 .n_gpios = 2, 1340}; 1341 1342static struct i801_mux_config i801_mux_config_asus_z8_d18 = { 1343 .gpio_chip = "gpio_ich", 1344 .values = { 0x02, 0x03, 0x01 }, 1345 .n_values = 3, 1346 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD }, 1347 .gpios = { 52, 53 }, 1348 .n_gpios = 2, 1349}; 1350 1351static const struct dmi_system_id mux_dmi_table[] = { 1352 { 1353 .matches = { 1354 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1355 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"), 1356 }, 1357 .driver_data = &i801_mux_config_asus_z8_d12, 1358 }, 1359 { 1360 .matches = { 1361 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1362 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"), 1363 }, 1364 .driver_data = &i801_mux_config_asus_z8_d12, 1365 }, 1366 { 1367 .matches = { 1368 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1369 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"), 1370 }, 1371 .driver_data = &i801_mux_config_asus_z8_d12, 1372 }, 1373 { 1374 .matches = { 1375 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1376 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"), 1377 }, 1378 .driver_data = &i801_mux_config_asus_z8_d12, 1379 }, 1380 { 1381 .matches = { 1382 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1383 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"), 1384 }, 1385 .driver_data = &i801_mux_config_asus_z8_d12, 1386 }, 1387 { 1388 .matches = { 1389 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1390 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"), 1391 }, 1392 .driver_data = &i801_mux_config_asus_z8_d12, 1393 }, 1394 { 1395 .matches = { 1396 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1397 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"), 1398 }, 1399 .driver_data = &i801_mux_config_asus_z8_d18, 1400 }, 1401 { 1402 .matches = { 1403 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1404 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"), 1405 }, 1406 .driver_data = &i801_mux_config_asus_z8_d18, 1407 }, 1408 { 1409 .matches = { 1410 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), 1411 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"), 1412 }, 1413 .driver_data = &i801_mux_config_asus_z8_d12, 1414 }, 1415 { } 1416}; 1417 1418/* Setup multiplexing if needed */ 1419static int i801_add_mux(struct i801_priv *priv) 1420{ 1421 struct device *dev = &priv->adapter.dev; 1422 const struct i801_mux_config *mux_config; 1423 struct i2c_mux_gpio_platform_data gpio_data; 1424 struct gpiod_lookup_table *lookup; 1425 int err, i; 1426 1427 if (!priv->mux_drvdata) 1428 return 0; 1429 mux_config = priv->mux_drvdata; 1430 1431 /* Prepare the platform data */ 1432 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data)); 1433 gpio_data.parent = priv->adapter.nr; 1434 gpio_data.values = mux_config->values; 1435 gpio_data.n_values = mux_config->n_values; 1436 gpio_data.classes = mux_config->classes; 1437 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE; 1438 1439 /* Register GPIO descriptor lookup table */ 1440 lookup = devm_kzalloc(dev, 1441 struct_size(lookup, table, mux_config->n_gpios + 1), 1442 GFP_KERNEL); 1443 if (!lookup) 1444 return -ENOMEM; 1445 lookup->dev_id = "i2c-mux-gpio"; 1446 for (i = 0; i < mux_config->n_gpios; i++) { 1447 lookup->table[i] = (struct gpiod_lookup) 1448 GPIO_LOOKUP(mux_config->gpio_chip, 1449 mux_config->gpios[i], "mux", 0); 1450 } 1451 gpiod_add_lookup_table(lookup); 1452 priv->lookup = lookup; 1453 1454 /* 1455 * Register the mux device, we use PLATFORM_DEVID_NONE here 1456 * because since we are referring to the GPIO chip by name we are 1457 * anyways in deep trouble if there is more than one of these 1458 * devices, and there should likely only be one platform controller 1459 * hub. 1460 */ 1461 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio", 1462 PLATFORM_DEVID_NONE, &gpio_data, 1463 sizeof(struct i2c_mux_gpio_platform_data)); 1464 if (IS_ERR(priv->mux_pdev)) { 1465 err = PTR_ERR(priv->mux_pdev); 1466 gpiod_remove_lookup_table(lookup); 1467 priv->mux_pdev = NULL; 1468 dev_err(dev, "Failed to register i2c-mux-gpio device\n"); 1469 return err; 1470 } 1471 1472 return 0; 1473} 1474 1475static void i801_del_mux(struct i801_priv *priv) 1476{ 1477 if (priv->mux_pdev) 1478 platform_device_unregister(priv->mux_pdev); 1479 if (priv->lookup) 1480 gpiod_remove_lookup_table(priv->lookup); 1481} 1482 1483static unsigned int i801_get_adapter_class(struct i801_priv *priv) 1484{ 1485 const struct dmi_system_id *id; 1486 const struct i801_mux_config *mux_config; 1487 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 1488 int i; 1489 1490 id = dmi_first_match(mux_dmi_table); 1491 if (id) { 1492 /* Remove branch classes from trunk */ 1493 mux_config = id->driver_data; 1494 for (i = 0; i < mux_config->n_values; i++) 1495 class &= ~mux_config->classes[i]; 1496 1497 /* Remember for later */ 1498 priv->mux_drvdata = mux_config; 1499 } 1500 1501 return class; 1502} 1503#else 1504static inline int i801_add_mux(struct i801_priv *priv) { return 0; } 1505static inline void i801_del_mux(struct i801_priv *priv) { } 1506 1507static inline unsigned int i801_get_adapter_class(struct i801_priv *priv) 1508{ 1509 return I2C_CLASS_HWMON | I2C_CLASS_SPD; 1510} 1511#endif 1512 1513static const struct itco_wdt_platform_data spt_tco_platform_data = { 1514 .name = "Intel PCH", 1515 .version = 4, 1516}; 1517 1518static DEFINE_SPINLOCK(p2sb_spinlock); 1519 1520static struct platform_device * 1521i801_add_tco_spt(struct i801_priv *priv, struct pci_dev *pci_dev, 1522 struct resource *tco_res) 1523{ 1524 struct resource *res; 1525 unsigned int devfn; 1526 u64 base64_addr; 1527 u32 base_addr; 1528 u8 hidden; 1529 1530 /* 1531 * We must access the NO_REBOOT bit over the Primary to Sideband 1532 * bridge (P2SB). The BIOS prevents the P2SB device from being 1533 * enumerated by the PCI subsystem, so we need to unhide/hide it 1534 * to lookup the P2SB BAR. 1535 */ 1536 spin_lock(&p2sb_spinlock); 1537 1538 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1); 1539 1540 /* Unhide the P2SB device, if it is hidden */ 1541 pci_bus_read_config_byte(pci_dev->bus, devfn, 0xe1, &hidden); 1542 if (hidden) 1543 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0); 1544 1545 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr); 1546 base64_addr = base_addr & 0xfffffff0; 1547 1548 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr); 1549 base64_addr |= (u64)base_addr << 32; 1550 1551 /* Hide the P2SB device, if it was hidden before */ 1552 if (hidden) 1553 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, hidden); 1554 spin_unlock(&p2sb_spinlock); 1555 1556 res = &tco_res[1]; 1557 if (pci_dev->device == PCI_DEVICE_ID_INTEL_DNV_SMBUS) 1558 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL_DNV; 1559 else 1560 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL; 1561 1562 res->end = res->start + 3; 1563 res->flags = IORESOURCE_MEM; 1564 1565 return platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1, 1566 tco_res, 2, &spt_tco_platform_data, 1567 sizeof(spt_tco_platform_data)); 1568} 1569 1570static const struct itco_wdt_platform_data cnl_tco_platform_data = { 1571 .name = "Intel PCH", 1572 .version = 6, 1573}; 1574 1575static struct platform_device * 1576i801_add_tco_cnl(struct i801_priv *priv, struct pci_dev *pci_dev, 1577 struct resource *tco_res) 1578{ 1579 return platform_device_register_resndata(&pci_dev->dev, 1580 "iTCO_wdt", -1, tco_res, 1, &cnl_tco_platform_data, 1581 sizeof(cnl_tco_platform_data)); 1582} 1583 1584static void i801_add_tco(struct i801_priv *priv) 1585{ 1586 struct pci_dev *pci_dev = priv->pci_dev; 1587 struct resource tco_res[2], *res; 1588 u32 tco_base, tco_ctl; 1589 1590 /* If we have ACPI based watchdog use that instead */ 1591 if (acpi_has_watchdog()) 1592 return; 1593 1594 if (!(priv->features & (FEATURE_TCO_SPT | FEATURE_TCO_CNL))) 1595 return; 1596 1597 pci_read_config_dword(pci_dev, TCOBASE, &tco_base); 1598 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl); 1599 if (!(tco_ctl & TCOCTL_EN)) 1600 return; 1601 1602 memset(tco_res, 0, sizeof(tco_res)); 1603 /* 1604 * Always populate the main iTCO IO resource here. The second entry 1605 * for NO_REBOOT MMIO is filled by the SPT specific function. 1606 */ 1607 res = &tco_res[0]; 1608 res->start = tco_base & ~1; 1609 res->end = res->start + 32 - 1; 1610 res->flags = IORESOURCE_IO; 1611 1612 if (priv->features & FEATURE_TCO_CNL) 1613 priv->tco_pdev = i801_add_tco_cnl(priv, pci_dev, tco_res); 1614 else 1615 priv->tco_pdev = i801_add_tco_spt(priv, pci_dev, tco_res); 1616 1617 if (IS_ERR(priv->tco_pdev)) 1618 dev_warn(&pci_dev->dev, "failed to create iTCO device\n"); 1619} 1620 1621#ifdef CONFIG_ACPI 1622static bool i801_acpi_is_smbus_ioport(const struct i801_priv *priv, 1623 acpi_physical_address address) 1624{ 1625 return address >= priv->smba && 1626 address <= pci_resource_end(priv->pci_dev, SMBBAR); 1627} 1628 1629static acpi_status 1630i801_acpi_io_handler(u32 function, acpi_physical_address address, u32 bits, 1631 u64 *value, void *handler_context, void *region_context) 1632{ 1633 struct i801_priv *priv = handler_context; 1634 struct pci_dev *pdev = priv->pci_dev; 1635 acpi_status status; 1636 1637 /* 1638 * Once BIOS AML code touches the OpRegion we warn and inhibit any 1639 * further access from the driver itself. This device is now owned 1640 * by the system firmware. 1641 */ 1642 mutex_lock(&priv->acpi_lock); 1643 1644 if (!priv->acpi_reserved && i801_acpi_is_smbus_ioport(priv, address)) { 1645 priv->acpi_reserved = true; 1646 1647 dev_warn(&pdev->dev, "BIOS is accessing SMBus registers\n"); 1648 dev_warn(&pdev->dev, "Driver SMBus register access inhibited\n"); 1649 1650 /* 1651 * BIOS is accessing the host controller so prevent it from 1652 * suspending automatically from now on. 1653 */ 1654 pm_runtime_get_sync(&pdev->dev); 1655 } 1656 1657 if ((function & ACPI_IO_MASK) == ACPI_READ) 1658 status = acpi_os_read_port(address, (u32 *)value, bits); 1659 else 1660 status = acpi_os_write_port(address, (u32)*value, bits); 1661 1662 mutex_unlock(&priv->acpi_lock); 1663 1664 return status; 1665} 1666 1667static int i801_acpi_probe(struct i801_priv *priv) 1668{ 1669 struct acpi_device *adev; 1670 acpi_status status; 1671 1672 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1673 if (adev) { 1674 status = acpi_install_address_space_handler(adev->handle, 1675 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler, 1676 NULL, priv); 1677 if (ACPI_SUCCESS(status)) 1678 return 0; 1679 } 1680 1681 return acpi_check_resource_conflict(&priv->pci_dev->resource[SMBBAR]); 1682} 1683 1684static void i801_acpi_remove(struct i801_priv *priv) 1685{ 1686 struct acpi_device *adev; 1687 1688 adev = ACPI_COMPANION(&priv->pci_dev->dev); 1689 if (!adev) 1690 return; 1691 1692 acpi_remove_address_space_handler(adev->handle, 1693 ACPI_ADR_SPACE_SYSTEM_IO, i801_acpi_io_handler); 1694 1695 mutex_lock(&priv->acpi_lock); 1696 if (priv->acpi_reserved) 1697 pm_runtime_put(&priv->pci_dev->dev); 1698 mutex_unlock(&priv->acpi_lock); 1699} 1700#else 1701static inline int i801_acpi_probe(struct i801_priv *priv) { return 0; } 1702static inline void i801_acpi_remove(struct i801_priv *priv) { } 1703#endif 1704 1705static unsigned char i801_setup_hstcfg(struct i801_priv *priv) 1706{ 1707 unsigned char hstcfg = priv->original_hstcfg; 1708 1709 hstcfg &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */ 1710 hstcfg |= SMBHSTCFG_HST_EN; 1711 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hstcfg); 1712 return hstcfg; 1713} 1714 1715static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id) 1716{ 1717 unsigned char temp; 1718 int err, i; 1719 struct i801_priv *priv; 1720 1721 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL); 1722 if (!priv) 1723 return -ENOMEM; 1724 1725 i2c_set_adapdata(&priv->adapter, priv); 1726 priv->adapter.owner = THIS_MODULE; 1727 priv->adapter.class = i801_get_adapter_class(priv); 1728 priv->adapter.algo = &smbus_algorithm; 1729 priv->adapter.dev.parent = &dev->dev; 1730 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&dev->dev)); 1731 priv->adapter.retries = 3; 1732 mutex_init(&priv->acpi_lock); 1733 1734 priv->pci_dev = dev; 1735 switch (dev->device) { 1736 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS: 1737 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS: 1738 case PCI_DEVICE_ID_INTEL_LEWISBURG_SMBUS: 1739 case PCI_DEVICE_ID_INTEL_LEWISBURG_SSKU_SMBUS: 1740 case PCI_DEVICE_ID_INTEL_DNV_SMBUS: 1741 case PCI_DEVICE_ID_INTEL_KABYLAKE_PCH_H_SMBUS: 1742 case PCI_DEVICE_ID_INTEL_COMETLAKE_V_SMBUS: 1743 priv->features |= FEATURE_BLOCK_PROC; 1744 priv->features |= FEATURE_I2C_BLOCK_READ; 1745 priv->features |= FEATURE_IRQ; 1746 priv->features |= FEATURE_SMBUS_PEC; 1747 priv->features |= FEATURE_BLOCK_BUFFER; 1748 priv->features |= FEATURE_TCO_SPT; 1749 priv->features |= FEATURE_HOST_NOTIFY; 1750 break; 1751 1752 case PCI_DEVICE_ID_INTEL_CANNONLAKE_H_SMBUS: 1753 case PCI_DEVICE_ID_INTEL_CANNONLAKE_LP_SMBUS: 1754 case PCI_DEVICE_ID_INTEL_CDF_SMBUS: 1755 case PCI_DEVICE_ID_INTEL_ICELAKE_LP_SMBUS: 1756 case PCI_DEVICE_ID_INTEL_COMETLAKE_SMBUS: 1757 case PCI_DEVICE_ID_INTEL_COMETLAKE_H_SMBUS: 1758 case PCI_DEVICE_ID_INTEL_ELKHART_LAKE_SMBUS: 1759 case PCI_DEVICE_ID_INTEL_TIGERLAKE_LP_SMBUS: 1760 case PCI_DEVICE_ID_INTEL_TIGERLAKE_H_SMBUS: 1761 case PCI_DEVICE_ID_INTEL_JASPER_LAKE_SMBUS: 1762 case PCI_DEVICE_ID_INTEL_EBG_SMBUS: 1763 case PCI_DEVICE_ID_INTEL_ALDER_LAKE_S_SMBUS: 1764 priv->features |= FEATURE_BLOCK_PROC; 1765 priv->features |= FEATURE_I2C_BLOCK_READ; 1766 priv->features |= FEATURE_IRQ; 1767 priv->features |= FEATURE_SMBUS_PEC; 1768 priv->features |= FEATURE_BLOCK_BUFFER; 1769 priv->features |= FEATURE_TCO_CNL; 1770 priv->features |= FEATURE_HOST_NOTIFY; 1771 break; 1772 1773 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0: 1774 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1: 1775 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2: 1776 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0: 1777 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1: 1778 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2: 1779 priv->features |= FEATURE_IDF; 1780 fallthrough; 1781 default: 1782 priv->features |= FEATURE_BLOCK_PROC; 1783 priv->features |= FEATURE_I2C_BLOCK_READ; 1784 priv->features |= FEATURE_IRQ; 1785 fallthrough; 1786 case PCI_DEVICE_ID_INTEL_82801DB_3: 1787 priv->features |= FEATURE_SMBUS_PEC; 1788 priv->features |= FEATURE_BLOCK_BUFFER; 1789 fallthrough; 1790 case PCI_DEVICE_ID_INTEL_82801CA_3: 1791 priv->features |= FEATURE_HOST_NOTIFY; 1792 fallthrough; 1793 case PCI_DEVICE_ID_INTEL_82801BA_2: 1794 case PCI_DEVICE_ID_INTEL_82801AB_3: 1795 case PCI_DEVICE_ID_INTEL_82801AA_3: 1796 break; 1797 } 1798 1799 /* Disable features on user request */ 1800 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) { 1801 if (priv->features & disable_features & (1 << i)) 1802 dev_notice(&dev->dev, "%s disabled by user\n", 1803 i801_feature_names[i]); 1804 } 1805 priv->features &= ~disable_features; 1806 1807 err = pcim_enable_device(dev); 1808 if (err) { 1809 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n", 1810 err); 1811 return err; 1812 } 1813 pcim_pin_device(dev); 1814 1815 /* Determine the address of the SMBus area */ 1816 priv->smba = pci_resource_start(dev, SMBBAR); 1817 if (!priv->smba) { 1818 dev_err(&dev->dev, 1819 "SMBus base address uninitialized, upgrade BIOS\n"); 1820 return -ENODEV; 1821 } 1822 1823 if (i801_acpi_probe(priv)) 1824 return -ENODEV; 1825 1826 err = pcim_iomap_regions(dev, 1 << SMBBAR, 1827 dev_driver_string(&dev->dev)); 1828 if (err) { 1829 dev_err(&dev->dev, 1830 "Failed to request SMBus region 0x%lx-0x%Lx\n", 1831 priv->smba, 1832 (unsigned long long)pci_resource_end(dev, SMBBAR)); 1833 i801_acpi_remove(priv); 1834 return err; 1835 } 1836 1837 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &priv->original_hstcfg); 1838 temp = i801_setup_hstcfg(priv); 1839 if (!(priv->original_hstcfg & SMBHSTCFG_HST_EN)) 1840 dev_info(&dev->dev, "Enabling SMBus device\n"); 1841 1842 if (temp & SMBHSTCFG_SMB_SMI_EN) { 1843 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n"); 1844 /* Disable SMBus interrupt feature if SMBus using SMI# */ 1845 priv->features &= ~FEATURE_IRQ; 1846 } 1847 if (temp & SMBHSTCFG_SPD_WD) 1848 dev_info(&dev->dev, "SPD Write Disable is set\n"); 1849 1850 /* Clear special mode bits */ 1851 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER)) 1852 outb_p(inb_p(SMBAUXCTL(priv)) & 1853 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv)); 1854 1855 /* Remember original Host Notify setting */ 1856 if (priv->features & FEATURE_HOST_NOTIFY) 1857 priv->original_slvcmd = inb_p(SMBSLVCMD(priv)); 1858 1859 /* Default timeout in interrupt mode: 200 ms */ 1860 priv->adapter.timeout = HZ / 5; 1861 1862 if (dev->irq == IRQ_NOTCONNECTED) 1863 priv->features &= ~FEATURE_IRQ; 1864 1865 if (priv->features & FEATURE_IRQ) { 1866 u16 pcictl, pcists; 1867 1868 /* Complain if an interrupt is already pending */ 1869 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists); 1870 if (pcists & SMBPCISTS_INTS) 1871 dev_warn(&dev->dev, "An interrupt is pending!\n"); 1872 1873 /* Check if interrupts have been disabled */ 1874 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl); 1875 if (pcictl & SMBPCICTL_INTDIS) { 1876 dev_info(&dev->dev, "Interrupts are disabled\n"); 1877 priv->features &= ~FEATURE_IRQ; 1878 } 1879 } 1880 1881 if (priv->features & FEATURE_IRQ) { 1882 init_waitqueue_head(&priv->waitq); 1883 1884 err = devm_request_irq(&dev->dev, dev->irq, i801_isr, 1885 IRQF_SHARED, 1886 dev_driver_string(&dev->dev), priv); 1887 if (err) { 1888 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n", 1889 dev->irq, err); 1890 priv->features &= ~FEATURE_IRQ; 1891 } 1892 } 1893 dev_info(&dev->dev, "SMBus using %s\n", 1894 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling"); 1895 1896 i801_add_tco(priv); 1897 1898 snprintf(priv->adapter.name, sizeof(priv->adapter.name), 1899 "SMBus I801 adapter at %04lx", priv->smba); 1900 err = i2c_add_adapter(&priv->adapter); 1901 if (err) { 1902 platform_device_unregister(priv->tco_pdev); 1903 i801_acpi_remove(priv); 1904 return err; 1905 } 1906 1907 i801_enable_host_notify(&priv->adapter); 1908 1909 i801_probe_optional_slaves(priv); 1910 /* We ignore errors - multiplexing is optional */ 1911 i801_add_mux(priv); 1912 1913 pci_set_drvdata(dev, priv); 1914 1915 dev_pm_set_driver_flags(&dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE); 1916 pm_runtime_set_autosuspend_delay(&dev->dev, 1000); 1917 pm_runtime_use_autosuspend(&dev->dev); 1918 pm_runtime_put_autosuspend(&dev->dev); 1919 pm_runtime_allow(&dev->dev); 1920 1921 return 0; 1922} 1923 1924static void i801_remove(struct pci_dev *dev) 1925{ 1926 struct i801_priv *priv = pci_get_drvdata(dev); 1927 1928 pm_runtime_forbid(&dev->dev); 1929 pm_runtime_get_noresume(&dev->dev); 1930 1931 i801_disable_host_notify(priv); 1932 i801_del_mux(priv); 1933 i2c_del_adapter(&priv->adapter); 1934 i801_acpi_remove(priv); 1935 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1936 1937 platform_device_unregister(priv->tco_pdev); 1938 1939 /* 1940 * do not call pci_disable_device(dev) since it can cause hard hangs on 1941 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010) 1942 */ 1943} 1944 1945static void i801_shutdown(struct pci_dev *dev) 1946{ 1947 struct i801_priv *priv = pci_get_drvdata(dev); 1948 1949 /* Restore config registers to avoid hard hang on some systems */ 1950 i801_disable_host_notify(priv); 1951 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg); 1952} 1953 1954#ifdef CONFIG_PM_SLEEP 1955static int i801_suspend(struct device *dev) 1956{ 1957 struct i801_priv *priv = dev_get_drvdata(dev); 1958 1959 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, priv->original_hstcfg); 1960 return 0; 1961} 1962 1963static int i801_resume(struct device *dev) 1964{ 1965 struct i801_priv *priv = dev_get_drvdata(dev); 1966 1967 i801_setup_hstcfg(priv); 1968 i801_enable_host_notify(&priv->adapter); 1969 1970 return 0; 1971} 1972#endif 1973 1974static SIMPLE_DEV_PM_OPS(i801_pm_ops, i801_suspend, i801_resume); 1975 1976static struct pci_driver i801_driver = { 1977 .name = "i801_smbus", 1978 .id_table = i801_ids, 1979 .probe = i801_probe, 1980 .remove = i801_remove, 1981 .shutdown = i801_shutdown, 1982 .driver = { 1983 .pm = &i801_pm_ops, 1984 }, 1985}; 1986 1987static int __init i2c_i801_init(void) 1988{ 1989 if (dmi_name_in_vendors("FUJITSU")) 1990 input_apanel_init(); 1991 return pci_register_driver(&i801_driver); 1992} 1993 1994static void __exit i2c_i801_exit(void) 1995{ 1996 pci_unregister_driver(&i801_driver); 1997} 1998 1999MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>"); 2000MODULE_AUTHOR("Jean Delvare <jdelvare@suse.de>"); 2001MODULE_DESCRIPTION("I801 SMBus driver"); 2002MODULE_LICENSE("GPL"); 2003 2004module_init(i2c_i801_init); 2005module_exit(i2c_i801_exit); 2006