1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2014 Uwe Kleine-Koenig for Pengutronix 4 */ 5#include <linux/module.h> 6#include <linux/platform_device.h> 7#include <linux/i2c.h> 8#include <linux/io.h> 9#include <linux/interrupt.h> 10#include <linux/err.h> 11#include <linux/clk.h> 12 13#define DRIVER_NAME "efm32-i2c" 14 15#define MASK_VAL(mask, val) ((val << __ffs(mask)) & mask) 16 17#define REG_CTRL 0x00 18#define REG_CTRL_EN 0x00001 19#define REG_CTRL_SLAVE 0x00002 20#define REG_CTRL_AUTOACK 0x00004 21#define REG_CTRL_AUTOSE 0x00008 22#define REG_CTRL_AUTOSN 0x00010 23#define REG_CTRL_ARBDIS 0x00020 24#define REG_CTRL_GCAMEN 0x00040 25#define REG_CTRL_CLHR__MASK 0x00300 26#define REG_CTRL_BITO__MASK 0x03000 27#define REG_CTRL_BITO_OFF 0x00000 28#define REG_CTRL_BITO_40PCC 0x01000 29#define REG_CTRL_BITO_80PCC 0x02000 30#define REG_CTRL_BITO_160PCC 0x03000 31#define REG_CTRL_GIBITO 0x08000 32#define REG_CTRL_CLTO__MASK 0x70000 33#define REG_CTRL_CLTO_OFF 0x00000 34 35#define REG_CMD 0x04 36#define REG_CMD_START 0x00001 37#define REG_CMD_STOP 0x00002 38#define REG_CMD_ACK 0x00004 39#define REG_CMD_NACK 0x00008 40#define REG_CMD_CONT 0x00010 41#define REG_CMD_ABORT 0x00020 42#define REG_CMD_CLEARTX 0x00040 43#define REG_CMD_CLEARPC 0x00080 44 45#define REG_STATE 0x08 46#define REG_STATE_BUSY 0x00001 47#define REG_STATE_MASTER 0x00002 48#define REG_STATE_TRANSMITTER 0x00004 49#define REG_STATE_NACKED 0x00008 50#define REG_STATE_BUSHOLD 0x00010 51#define REG_STATE_STATE__MASK 0x000e0 52#define REG_STATE_STATE_IDLE 0x00000 53#define REG_STATE_STATE_WAIT 0x00020 54#define REG_STATE_STATE_START 0x00040 55#define REG_STATE_STATE_ADDR 0x00060 56#define REG_STATE_STATE_ADDRACK 0x00080 57#define REG_STATE_STATE_DATA 0x000a0 58#define REG_STATE_STATE_DATAACK 0x000c0 59 60#define REG_STATUS 0x0c 61#define REG_STATUS_PSTART 0x00001 62#define REG_STATUS_PSTOP 0x00002 63#define REG_STATUS_PACK 0x00004 64#define REG_STATUS_PNACK 0x00008 65#define REG_STATUS_PCONT 0x00010 66#define REG_STATUS_PABORT 0x00020 67#define REG_STATUS_TXC 0x00040 68#define REG_STATUS_TXBL 0x00080 69#define REG_STATUS_RXDATAV 0x00100 70 71#define REG_CLKDIV 0x10 72#define REG_CLKDIV_DIV__MASK 0x001ff 73#define REG_CLKDIV_DIV(div) MASK_VAL(REG_CLKDIV_DIV__MASK, (div)) 74 75#define REG_SADDR 0x14 76#define REG_SADDRMASK 0x18 77#define REG_RXDATA 0x1c 78#define REG_RXDATAP 0x20 79#define REG_TXDATA 0x24 80#define REG_IF 0x28 81#define REG_IF_START 0x00001 82#define REG_IF_RSTART 0x00002 83#define REG_IF_ADDR 0x00004 84#define REG_IF_TXC 0x00008 85#define REG_IF_TXBL 0x00010 86#define REG_IF_RXDATAV 0x00020 87#define REG_IF_ACK 0x00040 88#define REG_IF_NACK 0x00080 89#define REG_IF_MSTOP 0x00100 90#define REG_IF_ARBLOST 0x00200 91#define REG_IF_BUSERR 0x00400 92#define REG_IF_BUSHOLD 0x00800 93#define REG_IF_TXOF 0x01000 94#define REG_IF_RXUF 0x02000 95#define REG_IF_BITO 0x04000 96#define REG_IF_CLTO 0x08000 97#define REG_IF_SSTOP 0x10000 98 99#define REG_IFS 0x2c 100#define REG_IFC 0x30 101#define REG_IFC__MASK 0x1ffcf 102 103#define REG_IEN 0x34 104 105#define REG_ROUTE 0x38 106#define REG_ROUTE_SDAPEN 0x00001 107#define REG_ROUTE_SCLPEN 0x00002 108#define REG_ROUTE_LOCATION__MASK 0x00700 109#define REG_ROUTE_LOCATION(n) MASK_VAL(REG_ROUTE_LOCATION__MASK, (n)) 110 111struct efm32_i2c_ddata { 112 struct i2c_adapter adapter; 113 114 struct clk *clk; 115 void __iomem *base; 116 unsigned int irq; 117 u8 location; 118 unsigned long frequency; 119 120 /* transfer data */ 121 struct completion done; 122 struct i2c_msg *msgs; 123 size_t num_msgs; 124 size_t current_word, current_msg; 125 int retval; 126}; 127 128static u32 efm32_i2c_read32(struct efm32_i2c_ddata *ddata, unsigned offset) 129{ 130 return readl(ddata->base + offset); 131} 132 133static void efm32_i2c_write32(struct efm32_i2c_ddata *ddata, 134 unsigned offset, u32 value) 135{ 136 writel(value, ddata->base + offset); 137} 138 139static void efm32_i2c_send_next_msg(struct efm32_i2c_ddata *ddata) 140{ 141 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; 142 143 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_START); 144 efm32_i2c_write32(ddata, REG_TXDATA, i2c_8bit_addr_from_msg(cur_msg)); 145} 146 147static void efm32_i2c_send_next_byte(struct efm32_i2c_ddata *ddata) 148{ 149 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; 150 151 if (ddata->current_word >= cur_msg->len) { 152 /* cur_msg completely transferred */ 153 ddata->current_word = 0; 154 ddata->current_msg += 1; 155 156 if (ddata->current_msg >= ddata->num_msgs) { 157 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP); 158 complete(&ddata->done); 159 } else { 160 efm32_i2c_send_next_msg(ddata); 161 } 162 } else { 163 efm32_i2c_write32(ddata, REG_TXDATA, 164 cur_msg->buf[ddata->current_word++]); 165 } 166} 167 168static void efm32_i2c_recv_next_byte(struct efm32_i2c_ddata *ddata) 169{ 170 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; 171 172 cur_msg->buf[ddata->current_word] = efm32_i2c_read32(ddata, REG_RXDATA); 173 ddata->current_word += 1; 174 if (ddata->current_word >= cur_msg->len) { 175 /* cur_msg completely transferred */ 176 ddata->current_word = 0; 177 ddata->current_msg += 1; 178 179 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_NACK); 180 181 if (ddata->current_msg >= ddata->num_msgs) { 182 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP); 183 complete(&ddata->done); 184 } else { 185 efm32_i2c_send_next_msg(ddata); 186 } 187 } else { 188 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ACK); 189 } 190} 191 192static irqreturn_t efm32_i2c_irq(int irq, void *dev_id) 193{ 194 struct efm32_i2c_ddata *ddata = dev_id; 195 struct i2c_msg *cur_msg = &ddata->msgs[ddata->current_msg]; 196 u32 irqflag = efm32_i2c_read32(ddata, REG_IF); 197 u32 state = efm32_i2c_read32(ddata, REG_STATE); 198 199 efm32_i2c_write32(ddata, REG_IFC, irqflag & REG_IFC__MASK); 200 201 switch (state & REG_STATE_STATE__MASK) { 202 case REG_STATE_STATE_IDLE: 203 /* arbitration lost? */ 204 ddata->retval = -EAGAIN; 205 complete(&ddata->done); 206 break; 207 case REG_STATE_STATE_WAIT: 208 /* 209 * huh, this shouldn't happen. 210 * Reset hardware state and get out 211 */ 212 ddata->retval = -EIO; 213 efm32_i2c_write32(ddata, REG_CMD, 214 REG_CMD_STOP | REG_CMD_ABORT | 215 REG_CMD_CLEARTX | REG_CMD_CLEARPC); 216 complete(&ddata->done); 217 break; 218 case REG_STATE_STATE_START: 219 /* "caller" is expected to send an address */ 220 break; 221 case REG_STATE_STATE_ADDR: 222 /* wait for Ack or NAck of slave */ 223 break; 224 case REG_STATE_STATE_ADDRACK: 225 if (state & REG_STATE_NACKED) { 226 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP); 227 ddata->retval = -ENXIO; 228 complete(&ddata->done); 229 } else if (cur_msg->flags & I2C_M_RD) { 230 /* wait for slave to send first data byte */ 231 } else { 232 efm32_i2c_send_next_byte(ddata); 233 } 234 break; 235 case REG_STATE_STATE_DATA: 236 if (cur_msg->flags & I2C_M_RD) { 237 efm32_i2c_recv_next_byte(ddata); 238 } else { 239 /* wait for Ack or Nack of slave */ 240 } 241 break; 242 case REG_STATE_STATE_DATAACK: 243 if (state & REG_STATE_NACKED) { 244 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_STOP); 245 complete(&ddata->done); 246 } else { 247 efm32_i2c_send_next_byte(ddata); 248 } 249 } 250 251 return IRQ_HANDLED; 252} 253 254static int efm32_i2c_master_xfer(struct i2c_adapter *adap, 255 struct i2c_msg *msgs, int num) 256{ 257 struct efm32_i2c_ddata *ddata = i2c_get_adapdata(adap); 258 int ret; 259 260 if (ddata->msgs) 261 return -EBUSY; 262 263 ddata->msgs = msgs; 264 ddata->num_msgs = num; 265 ddata->current_word = 0; 266 ddata->current_msg = 0; 267 ddata->retval = -EIO; 268 269 reinit_completion(&ddata->done); 270 271 dev_dbg(&ddata->adapter.dev, "state: %08x, status: %08x\n", 272 efm32_i2c_read32(ddata, REG_STATE), 273 efm32_i2c_read32(ddata, REG_STATUS)); 274 275 efm32_i2c_send_next_msg(ddata); 276 277 wait_for_completion(&ddata->done); 278 279 if (ddata->current_msg >= ddata->num_msgs) 280 ret = ddata->num_msgs; 281 else 282 ret = ddata->retval; 283 284 return ret; 285} 286 287static u32 efm32_i2c_functionality(struct i2c_adapter *adap) 288{ 289 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 290} 291 292static const struct i2c_algorithm efm32_i2c_algo = { 293 .master_xfer = efm32_i2c_master_xfer, 294 .functionality = efm32_i2c_functionality, 295}; 296 297static u32 efm32_i2c_get_configured_location(struct efm32_i2c_ddata *ddata) 298{ 299 u32 reg = efm32_i2c_read32(ddata, REG_ROUTE); 300 301 return (reg & REG_ROUTE_LOCATION__MASK) >> 302 __ffs(REG_ROUTE_LOCATION__MASK); 303} 304 305static int efm32_i2c_probe(struct platform_device *pdev) 306{ 307 struct efm32_i2c_ddata *ddata; 308 struct resource *res; 309 unsigned long rate; 310 struct device_node *np = pdev->dev.of_node; 311 u32 location, frequency; 312 int ret; 313 u32 clkdiv; 314 315 ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL); 316 if (!ddata) 317 return -ENOMEM; 318 platform_set_drvdata(pdev, ddata); 319 320 init_completion(&ddata->done); 321 strlcpy(ddata->adapter.name, pdev->name, sizeof(ddata->adapter.name)); 322 ddata->adapter.owner = THIS_MODULE; 323 ddata->adapter.algo = &efm32_i2c_algo; 324 ddata->adapter.dev.parent = &pdev->dev; 325 ddata->adapter.dev.of_node = pdev->dev.of_node; 326 i2c_set_adapdata(&ddata->adapter, ddata); 327 328 ddata->clk = devm_clk_get(&pdev->dev, NULL); 329 if (IS_ERR(ddata->clk)) { 330 ret = PTR_ERR(ddata->clk); 331 dev_err(&pdev->dev, "failed to get clock: %d\n", ret); 332 return ret; 333 } 334 335 ddata->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 336 if (IS_ERR(ddata->base)) 337 return PTR_ERR(ddata->base); 338 339 if (resource_size(res) < 0x42) { 340 dev_err(&pdev->dev, "memory resource too small\n"); 341 return -EINVAL; 342 } 343 344 ret = platform_get_irq(pdev, 0); 345 if (ret <= 0) { 346 if (!ret) 347 ret = -EINVAL; 348 return ret; 349 } 350 351 ddata->irq = ret; 352 353 ret = clk_prepare_enable(ddata->clk); 354 if (ret < 0) { 355 dev_err(&pdev->dev, "failed to enable clock (%d)\n", ret); 356 return ret; 357 } 358 359 360 ret = of_property_read_u32(np, "energymicro,location", &location); 361 362 if (ret) 363 /* fall back to wrongly namespaced property */ 364 ret = of_property_read_u32(np, "efm32,location", &location); 365 366 if (!ret) { 367 dev_dbg(&pdev->dev, "using location %u\n", location); 368 } else { 369 /* default to location configured in hardware */ 370 location = efm32_i2c_get_configured_location(ddata); 371 372 dev_info(&pdev->dev, "fall back to location %u\n", location); 373 } 374 375 ddata->location = location; 376 377 ret = of_property_read_u32(np, "clock-frequency", &frequency); 378 if (!ret) { 379 dev_dbg(&pdev->dev, "using frequency %u\n", frequency); 380 } else { 381 frequency = I2C_MAX_STANDARD_MODE_FREQ; 382 dev_info(&pdev->dev, "defaulting to 100 kHz\n"); 383 } 384 ddata->frequency = frequency; 385 386 rate = clk_get_rate(ddata->clk); 387 if (!rate) { 388 dev_err(&pdev->dev, "there is no input clock available\n"); 389 ret = -EINVAL; 390 goto err_disable_clk; 391 } 392 clkdiv = DIV_ROUND_UP(rate, 8 * ddata->frequency) - 1; 393 if (clkdiv >= 0x200) { 394 dev_err(&pdev->dev, 395 "input clock too fast (%lu) to divide down to bus freq (%lu)", 396 rate, ddata->frequency); 397 ret = -EINVAL; 398 goto err_disable_clk; 399 } 400 401 dev_dbg(&pdev->dev, "input clock = %lu, bus freq = %lu, clkdiv = %lu\n", 402 rate, ddata->frequency, (unsigned long)clkdiv); 403 efm32_i2c_write32(ddata, REG_CLKDIV, REG_CLKDIV_DIV(clkdiv)); 404 405 efm32_i2c_write32(ddata, REG_ROUTE, REG_ROUTE_SDAPEN | 406 REG_ROUTE_SCLPEN | 407 REG_ROUTE_LOCATION(ddata->location)); 408 409 efm32_i2c_write32(ddata, REG_CTRL, REG_CTRL_EN | 410 REG_CTRL_BITO_160PCC | 0 * REG_CTRL_GIBITO); 411 412 efm32_i2c_write32(ddata, REG_IFC, REG_IFC__MASK); 413 efm32_i2c_write32(ddata, REG_IEN, REG_IF_TXC | REG_IF_ACK | REG_IF_NACK 414 | REG_IF_ARBLOST | REG_IF_BUSERR | REG_IF_RXDATAV); 415 416 /* to make bus idle */ 417 efm32_i2c_write32(ddata, REG_CMD, REG_CMD_ABORT); 418 419 ret = request_irq(ddata->irq, efm32_i2c_irq, 0, DRIVER_NAME, ddata); 420 if (ret < 0) { 421 dev_err(&pdev->dev, "failed to request irq (%d)\n", ret); 422 goto err_disable_clk; 423 } 424 425 ret = i2c_add_adapter(&ddata->adapter); 426 if (ret) { 427 free_irq(ddata->irq, ddata); 428 429err_disable_clk: 430 clk_disable_unprepare(ddata->clk); 431 } 432 return ret; 433} 434 435static int efm32_i2c_remove(struct platform_device *pdev) 436{ 437 struct efm32_i2c_ddata *ddata = platform_get_drvdata(pdev); 438 439 i2c_del_adapter(&ddata->adapter); 440 free_irq(ddata->irq, ddata); 441 clk_disable_unprepare(ddata->clk); 442 443 return 0; 444} 445 446static const struct of_device_id efm32_i2c_dt_ids[] = { 447 { 448 .compatible = "energymicro,efm32-i2c", 449 }, { 450 /* sentinel */ 451 } 452}; 453MODULE_DEVICE_TABLE(of, efm32_i2c_dt_ids); 454 455static struct platform_driver efm32_i2c_driver = { 456 .probe = efm32_i2c_probe, 457 .remove = efm32_i2c_remove, 458 459 .driver = { 460 .name = DRIVER_NAME, 461 .of_match_table = efm32_i2c_dt_ids, 462 }, 463}; 464module_platform_driver(efm32_i2c_driver); 465 466MODULE_AUTHOR("Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>"); 467MODULE_DESCRIPTION("EFM32 i2c driver"); 468MODULE_LICENSE("GPL v2"); 469MODULE_ALIAS("platform:" DRIVER_NAME); 470