1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Synopsys DesignWare I2C adapter driver.
4 *
5 * Based on the TI DAVINCI I2C adapter driver.
6 *
7 * Copyright (C) 2006 Texas Instruments.
8 * Copyright (C) 2007 MontaVista Software Inc.
9 * Copyright (C) 2009 Provigent Ltd.
10 */
11#include <linux/acpi.h>
12#include <linux/clk-provider.h>
13#include <linux/clk.h>
14#include <linux/delay.h>
15#include <linux/dmi.h>
16#include <linux/err.h>
17#include <linux/errno.h>
18#include <linux/i2c.h>
19#include <linux/interrupt.h>
20#include <linux/io.h>
21#include <linux/kernel.h>
22#include <linux/mfd/syscon.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/platform_data/i2c-designware.h>
26#include <linux/platform_device.h>
27#include <linux/pm.h>
28#include <linux/pm_runtime.h>
29#include <linux/property.h>
30#include <linux/regmap.h>
31#include <linux/reset.h>
32#include <linux/sched.h>
33#include <linux/slab.h>
34#include <linux/suspend.h>
35#include <linux/units.h>
36
37#include "i2c-designware-core.h"
38
39static u32 i2c_dw_get_clk_rate_khz(struct dw_i2c_dev *dev)
40{
41	return clk_get_rate(dev->clk) / KILO;
42}
43
44#ifdef CONFIG_ACPI
45static const struct acpi_device_id dw_i2c_acpi_match[] = {
46	{ "INT33C2", 0 },
47	{ "INT33C3", 0 },
48	{ "INT3432", 0 },
49	{ "INT3433", 0 },
50	{ "80860F41", ACCESS_NO_IRQ_SUSPEND },
51	{ "808622C1", ACCESS_NO_IRQ_SUSPEND },
52	{ "AMD0010", ACCESS_INTR_MASK },
53	{ "AMDI0010", ACCESS_INTR_MASK },
54	{ "AMDI0510", 0 },
55	{ "APMC0D0F", 0 },
56	{ "HISI02A1", 0 },
57	{ "HISI02A2", 0 },
58	{ "HISI02A3", 0 },
59	{ "HYGO0010", ACCESS_INTR_MASK },
60	{ }
61};
62MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match);
63#endif
64
65#ifdef CONFIG_OF
66#define BT1_I2C_CTL			0x100
67#define BT1_I2C_CTL_ADDR_MASK		GENMASK(7, 0)
68#define BT1_I2C_CTL_WR			BIT(8)
69#define BT1_I2C_CTL_GO			BIT(31)
70#define BT1_I2C_DI			0x104
71#define BT1_I2C_DO			0x108
72
73static int bt1_i2c_read(void *context, unsigned int reg, unsigned int *val)
74{
75	struct dw_i2c_dev *dev = context;
76	int ret;
77
78	/*
79	 * Note these methods shouldn't ever fail because the system controller
80	 * registers are memory mapped. We check the return value just in case.
81	 */
82	ret = regmap_write(dev->sysmap, BT1_I2C_CTL,
83			   BT1_I2C_CTL_GO | (reg & BT1_I2C_CTL_ADDR_MASK));
84	if (ret)
85		return ret;
86
87	return regmap_read(dev->sysmap, BT1_I2C_DO, val);
88}
89
90static int bt1_i2c_write(void *context, unsigned int reg, unsigned int val)
91{
92	struct dw_i2c_dev *dev = context;
93	int ret;
94
95	ret = regmap_write(dev->sysmap, BT1_I2C_DI, val);
96	if (ret)
97		return ret;
98
99	return regmap_write(dev->sysmap, BT1_I2C_CTL,
100		BT1_I2C_CTL_GO | BT1_I2C_CTL_WR | (reg & BT1_I2C_CTL_ADDR_MASK));
101}
102
103static struct regmap_config bt1_i2c_cfg = {
104	.reg_bits = 32,
105	.val_bits = 32,
106	.reg_stride = 4,
107	.fast_io = true,
108	.reg_read = bt1_i2c_read,
109	.reg_write = bt1_i2c_write,
110	.max_register = DW_IC_COMP_TYPE,
111};
112
113static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
114{
115	dev->sysmap = syscon_node_to_regmap(dev->dev->of_node->parent);
116	if (IS_ERR(dev->sysmap))
117		return PTR_ERR(dev->sysmap);
118
119	dev->map = devm_regmap_init(dev->dev, NULL, dev, &bt1_i2c_cfg);
120	return PTR_ERR_OR_ZERO(dev->map);
121}
122
123#define MSCC_ICPU_CFG_TWI_DELAY		0x0
124#define MSCC_ICPU_CFG_TWI_DELAY_ENABLE	BIT(0)
125#define MSCC_ICPU_CFG_TWI_SPIKE_FILTER	0x4
126
127static int mscc_twi_set_sda_hold_time(struct dw_i2c_dev *dev)
128{
129	writel((dev->sda_hold_time << 1) | MSCC_ICPU_CFG_TWI_DELAY_ENABLE,
130	       dev->ext + MSCC_ICPU_CFG_TWI_DELAY);
131
132	return 0;
133}
134
135static int dw_i2c_of_configure(struct platform_device *pdev)
136{
137	struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
138
139	switch (dev->flags & MODEL_MASK) {
140	case MODEL_MSCC_OCELOT:
141		dev->ext = devm_platform_ioremap_resource(pdev, 1);
142		if (!IS_ERR(dev->ext))
143			dev->set_sda_hold_time = mscc_twi_set_sda_hold_time;
144		break;
145	default:
146		break;
147	}
148
149	return 0;
150}
151
152static const struct of_device_id dw_i2c_of_match[] = {
153	{ .compatible = "snps,designware-i2c", },
154	{ .compatible = "mscc,ocelot-i2c", .data = (void *)MODEL_MSCC_OCELOT },
155	{ .compatible = "baikal,bt1-sys-i2c", .data = (void *)MODEL_BAIKAL_BT1 },
156	{},
157};
158MODULE_DEVICE_TABLE(of, dw_i2c_of_match);
159#else
160static int bt1_i2c_request_regs(struct dw_i2c_dev *dev)
161{
162	return -ENODEV;
163}
164
165static inline int dw_i2c_of_configure(struct platform_device *pdev)
166{
167	return -ENODEV;
168}
169#endif
170
171static void dw_i2c_plat_pm_cleanup(struct dw_i2c_dev *dev)
172{
173	pm_runtime_disable(dev->dev);
174
175	if (dev->shared_with_punit)
176		pm_runtime_put_noidle(dev->dev);
177}
178
179static int dw_i2c_plat_request_regs(struct dw_i2c_dev *dev)
180{
181	struct platform_device *pdev = to_platform_device(dev->dev);
182	int ret;
183
184	switch (dev->flags & MODEL_MASK) {
185	case MODEL_BAIKAL_BT1:
186		ret = bt1_i2c_request_regs(dev);
187		break;
188	default:
189		dev->base = devm_platform_ioremap_resource(pdev, 0);
190		ret = PTR_ERR_OR_ZERO(dev->base);
191		break;
192	}
193
194	return ret;
195}
196
197static const struct dmi_system_id dw_i2c_hwmon_class_dmi[] = {
198	{
199		.ident = "Qtechnology QT5222",
200		.matches = {
201			DMI_MATCH(DMI_SYS_VENDOR, "Qtechnology"),
202			DMI_MATCH(DMI_PRODUCT_NAME, "QT5222"),
203		},
204	},
205	{ } /* terminate list */
206};
207
208static int dw_i2c_plat_probe(struct platform_device *pdev)
209{
210	struct dw_i2c_platform_data *pdata = dev_get_platdata(&pdev->dev);
211	struct i2c_adapter *adap;
212	struct dw_i2c_dev *dev;
213	struct i2c_timings *t;
214	int irq, ret;
215
216	irq = platform_get_irq(pdev, 0);
217	if (irq < 0)
218		return irq;
219
220	dev = devm_kzalloc(&pdev->dev, sizeof(struct dw_i2c_dev), GFP_KERNEL);
221	if (!dev)
222		return -ENOMEM;
223
224	dev->flags = (uintptr_t)device_get_match_data(&pdev->dev);
225	dev->dev = &pdev->dev;
226	dev->irq = irq;
227	platform_set_drvdata(pdev, dev);
228
229	ret = dw_i2c_plat_request_regs(dev);
230	if (ret)
231		return ret;
232
233	dev->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
234	if (IS_ERR(dev->rst))
235		return PTR_ERR(dev->rst);
236
237	reset_control_deassert(dev->rst);
238
239	t = &dev->timings;
240	if (pdata)
241		t->bus_freq_hz = pdata->i2c_scl_freq;
242	else
243		i2c_parse_fw_timings(&pdev->dev, t, false);
244
245	i2c_dw_adjust_bus_speed(dev);
246
247	if (pdev->dev.of_node)
248		dw_i2c_of_configure(pdev);
249
250	if (has_acpi_companion(&pdev->dev))
251		i2c_dw_acpi_configure(&pdev->dev);
252
253	ret = i2c_dw_validate_speed(dev);
254	if (ret)
255		goto exit_reset;
256
257	ret = i2c_dw_probe_lock_support(dev);
258	if (ret)
259		goto exit_reset;
260
261	i2c_dw_configure(dev);
262
263	/* Optional interface clock */
264	dev->pclk = devm_clk_get_optional(&pdev->dev, "pclk");
265	if (IS_ERR(dev->pclk)) {
266		ret = PTR_ERR(dev->pclk);
267		goto exit_reset;
268	}
269
270	dev->clk = devm_clk_get_optional(&pdev->dev, NULL);
271	if (IS_ERR(dev->clk)) {
272		ret = PTR_ERR(dev->clk);
273		goto exit_reset;
274	}
275
276	ret = i2c_dw_prepare_clk(dev, true);
277	if (ret)
278		goto exit_reset;
279
280	if (dev->clk) {
281		u64 clk_khz;
282
283		dev->get_clk_rate_khz = i2c_dw_get_clk_rate_khz;
284		clk_khz = dev->get_clk_rate_khz(dev);
285
286		if (!dev->sda_hold_time && t->sda_hold_ns)
287			dev->sda_hold_time =
288				DIV_S64_ROUND_CLOSEST(clk_khz * t->sda_hold_ns, MICRO);
289	}
290
291	adap = &dev->adapter;
292	adap->owner = THIS_MODULE;
293	adap->class = dmi_check_system(dw_i2c_hwmon_class_dmi) ?
294					I2C_CLASS_HWMON : I2C_CLASS_DEPRECATED;
295	ACPI_COMPANION_SET(&adap->dev, ACPI_COMPANION(&pdev->dev));
296	adap->dev.of_node = pdev->dev.of_node;
297	adap->nr = -1;
298
299	if (dev->flags & ACCESS_NO_IRQ_SUSPEND) {
300		dev_pm_set_driver_flags(&pdev->dev,
301					DPM_FLAG_SMART_PREPARE |
302					DPM_FLAG_MAY_SKIP_RESUME);
303	} else {
304		dev_pm_set_driver_flags(&pdev->dev,
305					DPM_FLAG_SMART_PREPARE |
306					DPM_FLAG_SMART_SUSPEND |
307					DPM_FLAG_MAY_SKIP_RESUME);
308	}
309
310	/* The code below assumes runtime PM to be disabled. */
311	WARN_ON(pm_runtime_enabled(&pdev->dev));
312
313	pm_runtime_set_autosuspend_delay(&pdev->dev, 1000);
314	pm_runtime_use_autosuspend(&pdev->dev);
315	pm_runtime_set_active(&pdev->dev);
316
317	if (dev->shared_with_punit)
318		pm_runtime_get_noresume(&pdev->dev);
319
320	pm_runtime_enable(&pdev->dev);
321
322	ret = i2c_dw_probe(dev);
323	if (ret)
324		goto exit_probe;
325
326	return ret;
327
328exit_probe:
329	dw_i2c_plat_pm_cleanup(dev);
330exit_reset:
331	reset_control_assert(dev->rst);
332	return ret;
333}
334
335static int dw_i2c_plat_remove(struct platform_device *pdev)
336{
337	struct dw_i2c_dev *dev = platform_get_drvdata(pdev);
338
339	pm_runtime_get_sync(&pdev->dev);
340
341	i2c_del_adapter(&dev->adapter);
342
343	dev->disable(dev);
344
345	pm_runtime_dont_use_autosuspend(&pdev->dev);
346	pm_runtime_put_sync(&pdev->dev);
347	dw_i2c_plat_pm_cleanup(dev);
348
349	reset_control_assert(dev->rst);
350
351	return 0;
352}
353
354#ifdef CONFIG_PM_SLEEP
355static int dw_i2c_plat_prepare(struct device *dev)
356{
357	/*
358	 * If the ACPI companion device object is present for this device, it
359	 * may be accessed during suspend and resume of other devices via I2C
360	 * operation regions, so tell the PM core and middle layers to avoid
361	 * skipping system suspend/resume callbacks for it in that case.
362	 */
363	return !has_acpi_companion(dev);
364}
365
366static void dw_i2c_plat_complete(struct device *dev)
367{
368	/*
369	 * The device can only be in runtime suspend at this point if it has not
370	 * been resumed throughout the ending system suspend/resume cycle, so if
371	 * the platform firmware might mess up with it, request the runtime PM
372	 * framework to resume it.
373	 */
374	if (pm_runtime_suspended(dev) && pm_resume_via_firmware())
375		pm_request_resume(dev);
376}
377#else
378#define dw_i2c_plat_prepare	NULL
379#define dw_i2c_plat_complete	NULL
380#endif
381
382#ifdef CONFIG_PM
383static int dw_i2c_plat_suspend(struct device *dev)
384{
385	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
386
387	i_dev->suspended = true;
388
389	if (i_dev->shared_with_punit)
390		return 0;
391
392	i_dev->disable(i_dev);
393	i2c_dw_prepare_clk(i_dev, false);
394
395	return 0;
396}
397
398static int dw_i2c_plat_resume(struct device *dev)
399{
400	struct dw_i2c_dev *i_dev = dev_get_drvdata(dev);
401
402	if (!i_dev->shared_with_punit)
403		i2c_dw_prepare_clk(i_dev, true);
404
405	i_dev->init(i_dev);
406	i_dev->suspended = false;
407
408	return 0;
409}
410
411static const struct dev_pm_ops dw_i2c_dev_pm_ops = {
412	.prepare = dw_i2c_plat_prepare,
413	.complete = dw_i2c_plat_complete,
414	SET_LATE_SYSTEM_SLEEP_PM_OPS(dw_i2c_plat_suspend, dw_i2c_plat_resume)
415	SET_RUNTIME_PM_OPS(dw_i2c_plat_suspend, dw_i2c_plat_resume, NULL)
416};
417
418#define DW_I2C_DEV_PMOPS (&dw_i2c_dev_pm_ops)
419#else
420#define DW_I2C_DEV_PMOPS NULL
421#endif
422
423/* Work with hotplug and coldplug */
424MODULE_ALIAS("platform:i2c_designware");
425
426static struct platform_driver dw_i2c_driver = {
427	.probe = dw_i2c_plat_probe,
428	.remove = dw_i2c_plat_remove,
429	.driver		= {
430		.name	= "i2c_designware",
431		.of_match_table = of_match_ptr(dw_i2c_of_match),
432		.acpi_match_table = ACPI_PTR(dw_i2c_acpi_match),
433		.pm	= DW_I2C_DEV_PMOPS,
434	},
435};
436
437static int __init dw_i2c_init_driver(void)
438{
439	return platform_driver_register(&dw_i2c_driver);
440}
441subsys_initcall(dw_i2c_init_driver);
442
443static void __exit dw_i2c_exit_driver(void)
444{
445	platform_driver_unregister(&dw_i2c_driver);
446}
447module_exit(dw_i2c_exit_driver);
448
449MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
450MODULE_DESCRIPTION("Synopsys DesignWare I2C bus adapter");
451MODULE_LICENSE("GPL");
452