1/* 2 * Copyright (C) 2013 Broadcom Corporation 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation version 2. 7 * 8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 9 * kind, whether express or implied; without even the implied warranty 10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14#include <linux/device.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/sched.h> 18#include <linux/i2c.h> 19#include <linux/interrupt.h> 20#include <linux/platform_device.h> 21#include <linux/clk.h> 22#include <linux/io.h> 23#include <linux/slab.h> 24 25/* Hardware register offsets and field defintions */ 26#define CS_OFFSET 0x00000020 27#define CS_ACK_SHIFT 3 28#define CS_ACK_MASK 0x00000008 29#define CS_ACK_CMD_GEN_START 0x00000000 30#define CS_ACK_CMD_GEN_RESTART 0x00000001 31#define CS_CMD_SHIFT 1 32#define CS_CMD_CMD_NO_ACTION 0x00000000 33#define CS_CMD_CMD_START_RESTART 0x00000001 34#define CS_CMD_CMD_STOP 0x00000002 35#define CS_EN_SHIFT 0 36#define CS_EN_CMD_ENABLE_BSC 0x00000001 37 38#define TIM_OFFSET 0x00000024 39#define TIM_PRESCALE_SHIFT 6 40#define TIM_P_SHIFT 3 41#define TIM_NO_DIV_SHIFT 2 42#define TIM_DIV_SHIFT 0 43 44#define DAT_OFFSET 0x00000028 45 46#define TOUT_OFFSET 0x0000002c 47 48#define TXFCR_OFFSET 0x0000003c 49#define TXFCR_FIFO_FLUSH_MASK 0x00000080 50#define TXFCR_FIFO_EN_MASK 0x00000040 51 52#define IER_OFFSET 0x00000044 53#define IER_READ_COMPLETE_INT_MASK 0x00000010 54#define IER_I2C_INT_EN_MASK 0x00000008 55#define IER_FIFO_INT_EN_MASK 0x00000002 56#define IER_NOACK_EN_MASK 0x00000001 57 58#define ISR_OFFSET 0x00000048 59#define ISR_RESERVED_MASK 0xffffff60 60#define ISR_CMDBUSY_MASK 0x00000080 61#define ISR_READ_COMPLETE_MASK 0x00000010 62#define ISR_SES_DONE_MASK 0x00000008 63#define ISR_ERR_MASK 0x00000004 64#define ISR_TXFIFOEMPTY_MASK 0x00000002 65#define ISR_NOACK_MASK 0x00000001 66 67#define CLKEN_OFFSET 0x0000004C 68#define CLKEN_AUTOSENSE_OFF_MASK 0x00000080 69#define CLKEN_M_SHIFT 4 70#define CLKEN_N_SHIFT 1 71#define CLKEN_CLKEN_MASK 0x00000001 72 73#define FIFO_STATUS_OFFSET 0x00000054 74#define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004 75#define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010 76 77#define HSTIM_OFFSET 0x00000058 78#define HSTIM_HS_MODE_MASK 0x00008000 79#define HSTIM_HS_HOLD_SHIFT 10 80#define HSTIM_HS_HIGH_PHASE_SHIFT 5 81#define HSTIM_HS_SETUP_SHIFT 0 82 83#define PADCTL_OFFSET 0x0000005c 84#define PADCTL_PAD_OUT_EN_MASK 0x00000004 85 86#define RXFCR_OFFSET 0x00000068 87#define RXFCR_NACK_EN_SHIFT 7 88#define RXFCR_READ_COUNT_SHIFT 0 89#define RXFIFORDOUT_OFFSET 0x0000006c 90 91/* Locally used constants */ 92#define MAX_RX_FIFO_SIZE 64U /* bytes */ 93#define MAX_TX_FIFO_SIZE 64U /* bytes */ 94 95#define STD_EXT_CLK_FREQ 13000000UL 96#define HS_EXT_CLK_FREQ 104000000UL 97 98#define MASTERCODE 0x08 /* Mastercodes are 0000_1xxxb */ 99 100#define I2C_TIMEOUT 100 /* msecs */ 101 102/* Operations that can be commanded to the controller */ 103enum bcm_kona_cmd_t { 104 BCM_CMD_NOACTION = 0, 105 BCM_CMD_START, 106 BCM_CMD_RESTART, 107 BCM_CMD_STOP, 108}; 109 110enum bus_speed_index { 111 BCM_SPD_100K = 0, 112 BCM_SPD_400K, 113 BCM_SPD_1MHZ, 114}; 115 116enum hs_bus_speed_index { 117 BCM_SPD_3P4MHZ = 0, 118}; 119 120/* Internal divider settings for standard mode, fast mode and fast mode plus */ 121struct bus_speed_cfg { 122 uint8_t time_m; /* Number of cycles for setup time */ 123 uint8_t time_n; /* Number of cycles for hold time */ 124 uint8_t prescale; /* Prescale divider */ 125 uint8_t time_p; /* Timing coefficient */ 126 uint8_t no_div; /* Disable clock divider */ 127 uint8_t time_div; /* Post-prescale divider */ 128}; 129 130/* Internal divider settings for high-speed mode */ 131struct hs_bus_speed_cfg { 132 uint8_t hs_hold; /* Number of clock cycles SCL stays low until 133 the end of bit period */ 134 uint8_t hs_high_phase; /* Number of clock cycles SCL stays high 135 before it falls */ 136 uint8_t hs_setup; /* Number of clock cycles SCL stays low 137 before it rises */ 138 uint8_t prescale; /* Prescale divider */ 139 uint8_t time_p; /* Timing coefficient */ 140 uint8_t no_div; /* Disable clock divider */ 141 uint8_t time_div; /* Post-prescale divider */ 142}; 143 144static const struct bus_speed_cfg std_cfg_table[] = { 145 [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02}, 146 [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02}, 147 [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03}, 148}; 149 150static const struct hs_bus_speed_cfg hs_cfg_table[] = { 151 [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00}, 152}; 153 154struct bcm_kona_i2c_dev { 155 struct device *device; 156 157 void __iomem *base; 158 int irq; 159 struct clk *external_clk; 160 161 struct i2c_adapter adapter; 162 163 struct completion done; 164 165 const struct bus_speed_cfg *std_cfg; 166 const struct hs_bus_speed_cfg *hs_cfg; 167}; 168 169static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev, 170 enum bcm_kona_cmd_t cmd) 171{ 172 dev_dbg(dev->device, "%s, %d\n", __func__, cmd); 173 174 switch (cmd) { 175 case BCM_CMD_NOACTION: 176 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) | 177 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 178 dev->base + CS_OFFSET); 179 break; 180 181 case BCM_CMD_START: 182 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) | 183 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | 184 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 185 dev->base + CS_OFFSET); 186 break; 187 188 case BCM_CMD_RESTART: 189 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) | 190 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) | 191 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 192 dev->base + CS_OFFSET); 193 break; 194 195 case BCM_CMD_STOP: 196 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) | 197 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT), 198 dev->base + CS_OFFSET); 199 break; 200 201 default: 202 dev_err(dev->device, "Unknown command %d\n", cmd); 203 } 204} 205 206static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev) 207{ 208 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK, 209 dev->base + CLKEN_OFFSET); 210} 211 212static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev) 213{ 214 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK, 215 dev->base + CLKEN_OFFSET); 216} 217 218static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid) 219{ 220 struct bcm_kona_i2c_dev *dev = devid; 221 uint32_t status = readl(dev->base + ISR_OFFSET); 222 223 if ((status & ~ISR_RESERVED_MASK) == 0) 224 return IRQ_NONE; 225 226 /* Must flush the TX FIFO when NAK detected */ 227 if (status & ISR_NOACK_MASK) 228 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, 229 dev->base + TXFCR_OFFSET); 230 231 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET); 232 complete(&dev->done); 233 234 return IRQ_HANDLED; 235} 236 237/* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */ 238static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev) 239{ 240 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT); 241 242 while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK) 243 if (time_after(jiffies, timeout)) { 244 dev_err(dev->device, "CMDBUSY timeout\n"); 245 return -ETIMEDOUT; 246 } 247 248 return 0; 249} 250 251/* Send command to I2C bus */ 252static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev, 253 enum bcm_kona_cmd_t cmd) 254{ 255 int rc; 256 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 257 258 /* Make sure the hardware is ready */ 259 rc = bcm_kona_i2c_wait_if_busy(dev); 260 if (rc < 0) 261 return rc; 262 263 /* Unmask the session done interrupt */ 264 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); 265 266 /* Mark as incomplete before sending the command */ 267 reinit_completion(&dev->done); 268 269 /* Send the command */ 270 bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd); 271 272 /* Wait for transaction to finish or timeout */ 273 time_left = wait_for_completion_timeout(&dev->done, time_left); 274 275 /* Mask all interrupts */ 276 writel(0, dev->base + IER_OFFSET); 277 278 if (!time_left) { 279 dev_err(dev->device, "controller timed out\n"); 280 rc = -ETIMEDOUT; 281 } 282 283 /* Clear command */ 284 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); 285 286 return rc; 287} 288 289/* Read a single RX FIFO worth of data from the i2c bus */ 290static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev, 291 uint8_t *buf, unsigned int len, 292 unsigned int last_byte_nak) 293{ 294 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 295 296 /* Mark as incomplete before starting the RX FIFO */ 297 reinit_completion(&dev->done); 298 299 /* Unmask the read complete interrupt */ 300 writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET); 301 302 /* Start the RX FIFO */ 303 writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) | 304 (len << RXFCR_READ_COUNT_SHIFT), 305 dev->base + RXFCR_OFFSET); 306 307 /* Wait for FIFO read to complete */ 308 time_left = wait_for_completion_timeout(&dev->done, time_left); 309 310 /* Mask all interrupts */ 311 writel(0, dev->base + IER_OFFSET); 312 313 if (!time_left) { 314 dev_err(dev->device, "RX FIFO time out\n"); 315 return -EREMOTEIO; 316 } 317 318 /* Read data from FIFO */ 319 for (; len > 0; len--, buf++) 320 *buf = readl(dev->base + RXFIFORDOUT_OFFSET); 321 322 return 0; 323} 324 325/* Read any amount of data using the RX FIFO from the i2c bus */ 326static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev, 327 struct i2c_msg *msg) 328{ 329 unsigned int bytes_to_read = MAX_RX_FIFO_SIZE; 330 unsigned int last_byte_nak = 0; 331 unsigned int bytes_read = 0; 332 int rc; 333 334 uint8_t *tmp_buf = msg->buf; 335 336 while (bytes_read < msg->len) { 337 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) { 338 last_byte_nak = 1; /* NAK last byte of transfer */ 339 bytes_to_read = msg->len - bytes_read; 340 } 341 342 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read, 343 last_byte_nak); 344 if (rc < 0) 345 return -EREMOTEIO; 346 347 bytes_read += bytes_to_read; 348 tmp_buf += bytes_to_read; 349 } 350 351 return 0; 352} 353 354/* Write a single byte of data to the i2c bus */ 355static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data, 356 unsigned int nak_expected) 357{ 358 int rc; 359 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 360 unsigned int nak_received; 361 362 /* Make sure the hardware is ready */ 363 rc = bcm_kona_i2c_wait_if_busy(dev); 364 if (rc < 0) 365 return rc; 366 367 /* Clear pending session done interrupt */ 368 writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET); 369 370 /* Unmask the session done interrupt */ 371 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET); 372 373 /* Mark as incomplete before sending the data */ 374 reinit_completion(&dev->done); 375 376 /* Send one byte of data */ 377 writel(data, dev->base + DAT_OFFSET); 378 379 /* Wait for byte to be written */ 380 time_left = wait_for_completion_timeout(&dev->done, time_left); 381 382 /* Mask all interrupts */ 383 writel(0, dev->base + IER_OFFSET); 384 385 if (!time_left) { 386 dev_dbg(dev->device, "controller timed out\n"); 387 return -ETIMEDOUT; 388 } 389 390 nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0; 391 392 if (nak_received ^ nak_expected) { 393 dev_dbg(dev->device, "unexpected NAK/ACK\n"); 394 return -EREMOTEIO; 395 } 396 397 return 0; 398} 399 400/* Write a single TX FIFO worth of data to the i2c bus */ 401static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev, 402 uint8_t *buf, unsigned int len) 403{ 404 int k; 405 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT); 406 unsigned int fifo_status; 407 408 /* Mark as incomplete before sending data to the TX FIFO */ 409 reinit_completion(&dev->done); 410 411 /* Unmask the fifo empty and nak interrupt */ 412 writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK, 413 dev->base + IER_OFFSET); 414 415 /* Disable IRQ to load a FIFO worth of data without interruption */ 416 disable_irq(dev->irq); 417 418 /* Write data into FIFO */ 419 for (k = 0; k < len; k++) 420 writel(buf[k], (dev->base + DAT_OFFSET)); 421 422 /* Enable IRQ now that data has been loaded */ 423 enable_irq(dev->irq); 424 425 /* Wait for FIFO to empty */ 426 do { 427 time_left = wait_for_completion_timeout(&dev->done, time_left); 428 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET); 429 } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK)); 430 431 /* Mask all interrupts */ 432 writel(0, dev->base + IER_OFFSET); 433 434 /* Check if there was a NAK */ 435 if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) { 436 dev_err(dev->device, "unexpected NAK\n"); 437 return -EREMOTEIO; 438 } 439 440 /* Check if a timeout occured */ 441 if (!time_left) { 442 dev_err(dev->device, "completion timed out\n"); 443 return -EREMOTEIO; 444 } 445 446 return 0; 447} 448 449 450/* Write any amount of data using TX FIFO to the i2c bus */ 451static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev, 452 struct i2c_msg *msg) 453{ 454 unsigned int bytes_to_write = MAX_TX_FIFO_SIZE; 455 unsigned int bytes_written = 0; 456 int rc; 457 458 uint8_t *tmp_buf = msg->buf; 459 460 while (bytes_written < msg->len) { 461 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE) 462 bytes_to_write = msg->len - bytes_written; 463 464 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf, 465 bytes_to_write); 466 if (rc < 0) 467 return -EREMOTEIO; 468 469 bytes_written += bytes_to_write; 470 tmp_buf += bytes_to_write; 471 } 472 473 return 0; 474} 475 476/* Send i2c address */ 477static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev, 478 struct i2c_msg *msg) 479{ 480 unsigned char addr; 481 482 if (msg->flags & I2C_M_TEN) { 483 /* First byte is 11110XX0 where XX is upper 2 bits */ 484 addr = 0xF0 | ((msg->addr & 0x300) >> 7); 485 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 486 return -EREMOTEIO; 487 488 /* Second byte is the remaining 8 bits */ 489 addr = msg->addr & 0xFF; 490 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 491 return -EREMOTEIO; 492 493 if (msg->flags & I2C_M_RD) { 494 /* For read, send restart command */ 495 if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0) 496 return -EREMOTEIO; 497 498 /* Then re-send the first byte with the read bit set */ 499 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01; 500 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 501 return -EREMOTEIO; 502 } 503 } else { 504 addr = i2c_8bit_addr_from_msg(msg); 505 506 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0) 507 return -EREMOTEIO; 508 } 509 510 return 0; 511} 512 513static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev) 514{ 515 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK, 516 dev->base + CLKEN_OFFSET); 517} 518 519static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev) 520{ 521 writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK, 522 dev->base + HSTIM_OFFSET); 523 524 writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) | 525 (dev->std_cfg->time_p << TIM_P_SHIFT) | 526 (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) | 527 (dev->std_cfg->time_div << TIM_DIV_SHIFT), 528 dev->base + TIM_OFFSET); 529 530 writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) | 531 (dev->std_cfg->time_n << CLKEN_N_SHIFT) | 532 CLKEN_CLKEN_MASK, 533 dev->base + CLKEN_OFFSET); 534} 535 536static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev) 537{ 538 writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) | 539 (dev->hs_cfg->time_p << TIM_P_SHIFT) | 540 (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) | 541 (dev->hs_cfg->time_div << TIM_DIV_SHIFT), 542 dev->base + TIM_OFFSET); 543 544 writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) | 545 (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) | 546 (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT), 547 dev->base + HSTIM_OFFSET); 548 549 writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK, 550 dev->base + HSTIM_OFFSET); 551} 552 553static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev) 554{ 555 int rc; 556 557 /* Send mastercode at standard speed */ 558 rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1); 559 if (rc < 0) { 560 pr_err("High speed handshake failed\n"); 561 return rc; 562 } 563 564 /* Configure external clock to higher frequency */ 565 rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ); 566 if (rc) { 567 dev_err(dev->device, "%s: clk_set_rate returned %d\n", 568 __func__, rc); 569 return rc; 570 } 571 572 /* Reconfigure internal dividers */ 573 bcm_kona_i2c_config_timing_hs(dev); 574 575 /* Send a restart command */ 576 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); 577 if (rc < 0) 578 dev_err(dev->device, "High speed restart command failed\n"); 579 580 return rc; 581} 582 583static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev) 584{ 585 int rc; 586 587 /* Reconfigure internal dividers */ 588 bcm_kona_i2c_config_timing(dev); 589 590 /* Configure external clock to lower frequency */ 591 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); 592 if (rc) { 593 dev_err(dev->device, "%s: clk_set_rate returned %d\n", 594 __func__, rc); 595 } 596 597 return rc; 598} 599 600/* Master transfer function */ 601static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter, 602 struct i2c_msg msgs[], int num) 603{ 604 struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter); 605 struct i2c_msg *pmsg; 606 int rc = 0; 607 int i; 608 609 rc = clk_prepare_enable(dev->external_clk); 610 if (rc) { 611 dev_err(dev->device, "%s: peri clock enable failed. err %d\n", 612 __func__, rc); 613 return rc; 614 } 615 616 /* Enable pad output */ 617 writel(0, dev->base + PADCTL_OFFSET); 618 619 /* Enable internal clocks */ 620 bcm_kona_i2c_enable_clock(dev); 621 622 /* Send start command */ 623 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START); 624 if (rc < 0) { 625 dev_err(dev->device, "Start command failed rc = %d\n", rc); 626 goto xfer_disable_pad; 627 } 628 629 /* Switch to high speed if applicable */ 630 if (dev->hs_cfg) { 631 rc = bcm_kona_i2c_switch_to_hs(dev); 632 if (rc < 0) 633 goto xfer_send_stop; 634 } 635 636 /* Loop through all messages */ 637 for (i = 0; i < num; i++) { 638 pmsg = &msgs[i]; 639 640 /* Send restart for subsequent messages */ 641 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) { 642 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART); 643 if (rc < 0) { 644 dev_err(dev->device, 645 "restart cmd failed rc = %d\n", rc); 646 goto xfer_send_stop; 647 } 648 } 649 650 /* Send slave address */ 651 if (!(pmsg->flags & I2C_M_NOSTART)) { 652 rc = bcm_kona_i2c_do_addr(dev, pmsg); 653 if (rc < 0) { 654 dev_err(dev->device, 655 "NAK from addr %2.2x msg#%d rc = %d\n", 656 pmsg->addr, i, rc); 657 goto xfer_send_stop; 658 } 659 } 660 661 /* Perform data transfer */ 662 if (pmsg->flags & I2C_M_RD) { 663 rc = bcm_kona_i2c_read_fifo(dev, pmsg); 664 if (rc < 0) { 665 dev_err(dev->device, "read failure\n"); 666 goto xfer_send_stop; 667 } 668 } else { 669 rc = bcm_kona_i2c_write_fifo(dev, pmsg); 670 if (rc < 0) { 671 dev_err(dev->device, "write failure"); 672 goto xfer_send_stop; 673 } 674 } 675 } 676 677 rc = num; 678 679xfer_send_stop: 680 /* Send a STOP command */ 681 bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP); 682 683 /* Return from high speed if applicable */ 684 if (dev->hs_cfg) { 685 int hs_rc = bcm_kona_i2c_switch_to_std(dev); 686 687 if (hs_rc) 688 rc = hs_rc; 689 } 690 691xfer_disable_pad: 692 /* Disable pad output */ 693 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); 694 695 /* Stop internal clock */ 696 bcm_kona_i2c_disable_clock(dev); 697 698 clk_disable_unprepare(dev->external_clk); 699 700 return rc; 701} 702 703static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap) 704{ 705 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 706 I2C_FUNC_NOSTART; 707} 708 709static const struct i2c_algorithm bcm_algo = { 710 .master_xfer = bcm_kona_i2c_xfer, 711 .functionality = bcm_kona_i2c_functionality, 712}; 713 714static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev) 715{ 716 unsigned int bus_speed; 717 int ret = of_property_read_u32(dev->device->of_node, "clock-frequency", 718 &bus_speed); 719 if (ret < 0) { 720 dev_err(dev->device, "missing clock-frequency property\n"); 721 return -ENODEV; 722 } 723 724 switch (bus_speed) { 725 case I2C_MAX_STANDARD_MODE_FREQ: 726 dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; 727 break; 728 case I2C_MAX_FAST_MODE_FREQ: 729 dev->std_cfg = &std_cfg_table[BCM_SPD_400K]; 730 break; 731 case I2C_MAX_FAST_MODE_PLUS_FREQ: 732 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ]; 733 break; 734 case I2C_MAX_HIGH_SPEED_MODE_FREQ: 735 /* Send mastercode at 100k */ 736 dev->std_cfg = &std_cfg_table[BCM_SPD_100K]; 737 dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ]; 738 break; 739 default: 740 pr_err("%d hz bus speed not supported\n", bus_speed); 741 pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n"); 742 return -EINVAL; 743 } 744 745 return 0; 746} 747 748static int bcm_kona_i2c_probe(struct platform_device *pdev) 749{ 750 int rc = 0; 751 struct bcm_kona_i2c_dev *dev; 752 struct i2c_adapter *adap; 753 754 /* Allocate memory for private data structure */ 755 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL); 756 if (!dev) 757 return -ENOMEM; 758 759 platform_set_drvdata(pdev, dev); 760 dev->device = &pdev->dev; 761 init_completion(&dev->done); 762 763 /* Map hardware registers */ 764 dev->base = devm_platform_ioremap_resource(pdev, 0); 765 if (IS_ERR(dev->base)) 766 return -ENOMEM; 767 768 /* Get and enable external clock */ 769 dev->external_clk = devm_clk_get(dev->device, NULL); 770 if (IS_ERR(dev->external_clk)) { 771 dev_err(dev->device, "couldn't get clock\n"); 772 return -ENODEV; 773 } 774 775 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ); 776 if (rc) { 777 dev_err(dev->device, "%s: clk_set_rate returned %d\n", 778 __func__, rc); 779 return rc; 780 } 781 782 rc = clk_prepare_enable(dev->external_clk); 783 if (rc) { 784 dev_err(dev->device, "couldn't enable clock\n"); 785 return rc; 786 } 787 788 /* Parse bus speed */ 789 rc = bcm_kona_i2c_assign_bus_speed(dev); 790 if (rc) 791 goto probe_disable_clk; 792 793 /* Enable internal clocks */ 794 bcm_kona_i2c_enable_clock(dev); 795 796 /* Configure internal dividers */ 797 bcm_kona_i2c_config_timing(dev); 798 799 /* Disable timeout */ 800 writel(0, dev->base + TOUT_OFFSET); 801 802 /* Enable autosense */ 803 bcm_kona_i2c_enable_autosense(dev); 804 805 /* Enable TX FIFO */ 806 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK, 807 dev->base + TXFCR_OFFSET); 808 809 /* Mask all interrupts */ 810 writel(0, dev->base + IER_OFFSET); 811 812 /* Clear all pending interrupts */ 813 writel(ISR_CMDBUSY_MASK | 814 ISR_READ_COMPLETE_MASK | 815 ISR_SES_DONE_MASK | 816 ISR_ERR_MASK | 817 ISR_TXFIFOEMPTY_MASK | 818 ISR_NOACK_MASK, 819 dev->base + ISR_OFFSET); 820 821 /* Get the interrupt number */ 822 dev->irq = platform_get_irq(pdev, 0); 823 if (dev->irq < 0) { 824 rc = dev->irq; 825 goto probe_disable_clk; 826 } 827 828 /* register the ISR handler */ 829 rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr, 830 IRQF_SHARED, pdev->name, dev); 831 if (rc) { 832 dev_err(dev->device, "failed to request irq %i\n", dev->irq); 833 goto probe_disable_clk; 834 } 835 836 /* Enable the controller but leave it idle */ 837 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION); 838 839 /* Disable pad output */ 840 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET); 841 842 /* Disable internal clock */ 843 bcm_kona_i2c_disable_clock(dev); 844 845 /* Disable external clock */ 846 clk_disable_unprepare(dev->external_clk); 847 848 /* Add the i2c adapter */ 849 adap = &dev->adapter; 850 i2c_set_adapdata(adap, dev); 851 adap->owner = THIS_MODULE; 852 strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name)); 853 adap->algo = &bcm_algo; 854 adap->dev.parent = &pdev->dev; 855 adap->dev.of_node = pdev->dev.of_node; 856 857 rc = i2c_add_adapter(adap); 858 if (rc) 859 return rc; 860 861 dev_info(dev->device, "device registered successfully\n"); 862 863 return 0; 864 865probe_disable_clk: 866 bcm_kona_i2c_disable_clock(dev); 867 clk_disable_unprepare(dev->external_clk); 868 869 return rc; 870} 871 872static int bcm_kona_i2c_remove(struct platform_device *pdev) 873{ 874 struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev); 875 876 i2c_del_adapter(&dev->adapter); 877 878 return 0; 879} 880 881static const struct of_device_id bcm_kona_i2c_of_match[] = { 882 {.compatible = "brcm,kona-i2c",}, 883 {}, 884}; 885MODULE_DEVICE_TABLE(of, bcm_kona_i2c_of_match); 886 887static struct platform_driver bcm_kona_i2c_driver = { 888 .driver = { 889 .name = "bcm-kona-i2c", 890 .of_match_table = bcm_kona_i2c_of_match, 891 }, 892 .probe = bcm_kona_i2c_probe, 893 .remove = bcm_kona_i2c_remove, 894}; 895module_platform_driver(bcm_kona_i2c_driver); 896 897MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>"); 898MODULE_DESCRIPTION("Broadcom Kona I2C Driver"); 899MODULE_LICENSE("GPL v2"); 900