18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * SIRF hardware spinlock driver 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (c) 2015 Cambridge Silicon Radio Limited, a CSR plc group company. 68c2ecf20Sopenharmony_ci */ 78c2ecf20Sopenharmony_ci 88c2ecf20Sopenharmony_ci#include <linux/kernel.h> 98c2ecf20Sopenharmony_ci#include <linux/module.h> 108c2ecf20Sopenharmony_ci#include <linux/device.h> 118c2ecf20Sopenharmony_ci#include <linux/io.h> 128c2ecf20Sopenharmony_ci#include <linux/slab.h> 138c2ecf20Sopenharmony_ci#include <linux/spinlock.h> 148c2ecf20Sopenharmony_ci#include <linux/hwspinlock.h> 158c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 168c2ecf20Sopenharmony_ci#include <linux/of.h> 178c2ecf20Sopenharmony_ci#include <linux/of_address.h> 188c2ecf20Sopenharmony_ci 198c2ecf20Sopenharmony_ci#include "hwspinlock_internal.h" 208c2ecf20Sopenharmony_ci 218c2ecf20Sopenharmony_cistruct sirf_hwspinlock { 228c2ecf20Sopenharmony_ci void __iomem *io_base; 238c2ecf20Sopenharmony_ci struct hwspinlock_device bank; 248c2ecf20Sopenharmony_ci}; 258c2ecf20Sopenharmony_ci 268c2ecf20Sopenharmony_ci/* Number of Hardware Spinlocks*/ 278c2ecf20Sopenharmony_ci#define HW_SPINLOCK_NUMBER 30 288c2ecf20Sopenharmony_ci 298c2ecf20Sopenharmony_ci/* Hardware spinlock register offsets */ 308c2ecf20Sopenharmony_ci#define HW_SPINLOCK_BASE 0x404 318c2ecf20Sopenharmony_ci#define HW_SPINLOCK_OFFSET(x) (HW_SPINLOCK_BASE + 0x4 * (x)) 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_cistatic int sirf_hwspinlock_trylock(struct hwspinlock *lock) 348c2ecf20Sopenharmony_ci{ 358c2ecf20Sopenharmony_ci void __iomem *lock_addr = lock->priv; 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci /* attempt to acquire the lock by reading value == 1 from it */ 388c2ecf20Sopenharmony_ci return !!readl(lock_addr); 398c2ecf20Sopenharmony_ci} 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_cistatic void sirf_hwspinlock_unlock(struct hwspinlock *lock) 428c2ecf20Sopenharmony_ci{ 438c2ecf20Sopenharmony_ci void __iomem *lock_addr = lock->priv; 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_ci /* release the lock by writing 0 to it */ 468c2ecf20Sopenharmony_ci writel(0, lock_addr); 478c2ecf20Sopenharmony_ci} 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_cistatic const struct hwspinlock_ops sirf_hwspinlock_ops = { 508c2ecf20Sopenharmony_ci .trylock = sirf_hwspinlock_trylock, 518c2ecf20Sopenharmony_ci .unlock = sirf_hwspinlock_unlock, 528c2ecf20Sopenharmony_ci}; 538c2ecf20Sopenharmony_ci 548c2ecf20Sopenharmony_cistatic int sirf_hwspinlock_probe(struct platform_device *pdev) 558c2ecf20Sopenharmony_ci{ 568c2ecf20Sopenharmony_ci struct sirf_hwspinlock *hwspin; 578c2ecf20Sopenharmony_ci struct hwspinlock *hwlock; 588c2ecf20Sopenharmony_ci int idx; 598c2ecf20Sopenharmony_ci 608c2ecf20Sopenharmony_ci if (!pdev->dev.of_node) 618c2ecf20Sopenharmony_ci return -ENODEV; 628c2ecf20Sopenharmony_ci 638c2ecf20Sopenharmony_ci hwspin = devm_kzalloc(&pdev->dev, 648c2ecf20Sopenharmony_ci struct_size(hwspin, bank.lock, 658c2ecf20Sopenharmony_ci HW_SPINLOCK_NUMBER), 668c2ecf20Sopenharmony_ci GFP_KERNEL); 678c2ecf20Sopenharmony_ci if (!hwspin) 688c2ecf20Sopenharmony_ci return -ENOMEM; 698c2ecf20Sopenharmony_ci 708c2ecf20Sopenharmony_ci /* retrieve io base */ 718c2ecf20Sopenharmony_ci hwspin->io_base = devm_platform_ioremap_resource(pdev, 0); 728c2ecf20Sopenharmony_ci if (IS_ERR(hwspin->io_base)) 738c2ecf20Sopenharmony_ci return PTR_ERR(hwspin->io_base); 748c2ecf20Sopenharmony_ci 758c2ecf20Sopenharmony_ci for (idx = 0; idx < HW_SPINLOCK_NUMBER; idx++) { 768c2ecf20Sopenharmony_ci hwlock = &hwspin->bank.lock[idx]; 778c2ecf20Sopenharmony_ci hwlock->priv = hwspin->io_base + HW_SPINLOCK_OFFSET(idx); 788c2ecf20Sopenharmony_ci } 798c2ecf20Sopenharmony_ci 808c2ecf20Sopenharmony_ci platform_set_drvdata(pdev, hwspin); 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci return devm_hwspin_lock_register(&pdev->dev, &hwspin->bank, 838c2ecf20Sopenharmony_ci &sirf_hwspinlock_ops, 0, 848c2ecf20Sopenharmony_ci HW_SPINLOCK_NUMBER); 858c2ecf20Sopenharmony_ci} 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_cistatic const struct of_device_id sirf_hwpinlock_ids[] = { 888c2ecf20Sopenharmony_ci { .compatible = "sirf,hwspinlock", }, 898c2ecf20Sopenharmony_ci {}, 908c2ecf20Sopenharmony_ci}; 918c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, sirf_hwpinlock_ids); 928c2ecf20Sopenharmony_ci 938c2ecf20Sopenharmony_cistatic struct platform_driver sirf_hwspinlock_driver = { 948c2ecf20Sopenharmony_ci .probe = sirf_hwspinlock_probe, 958c2ecf20Sopenharmony_ci .driver = { 968c2ecf20Sopenharmony_ci .name = "atlas7_hwspinlock", 978c2ecf20Sopenharmony_ci .of_match_table = of_match_ptr(sirf_hwpinlock_ids), 988c2ecf20Sopenharmony_ci }, 998c2ecf20Sopenharmony_ci}; 1008c2ecf20Sopenharmony_ci 1018c2ecf20Sopenharmony_cimodule_platform_driver(sirf_hwspinlock_driver); 1028c2ecf20Sopenharmony_ci 1038c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL v2"); 1048c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("SIRF Hardware spinlock driver"); 1058c2ecf20Sopenharmony_ciMODULE_AUTHOR("Wei Chen <wei.chen@csr.com>"); 106