18c2ecf20Sopenharmony_ci// SPDX-License-Identifier: GPL-2.0 28c2ecf20Sopenharmony_ci/* 38c2ecf20Sopenharmony_ci * OMAP hardware spinlock driver 48c2ecf20Sopenharmony_ci * 58c2ecf20Sopenharmony_ci * Copyright (C) 2010-2015 Texas Instruments Incorporated - http://www.ti.com 68c2ecf20Sopenharmony_ci * 78c2ecf20Sopenharmony_ci * Contact: Simon Que <sque@ti.com> 88c2ecf20Sopenharmony_ci * Hari Kanigeri <h-kanigeri2@ti.com> 98c2ecf20Sopenharmony_ci * Ohad Ben-Cohen <ohad@wizery.com> 108c2ecf20Sopenharmony_ci */ 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci#include <linux/kernel.h> 138c2ecf20Sopenharmony_ci#include <linux/module.h> 148c2ecf20Sopenharmony_ci#include <linux/device.h> 158c2ecf20Sopenharmony_ci#include <linux/delay.h> 168c2ecf20Sopenharmony_ci#include <linux/io.h> 178c2ecf20Sopenharmony_ci#include <linux/bitops.h> 188c2ecf20Sopenharmony_ci#include <linux/pm_runtime.h> 198c2ecf20Sopenharmony_ci#include <linux/slab.h> 208c2ecf20Sopenharmony_ci#include <linux/spinlock.h> 218c2ecf20Sopenharmony_ci#include <linux/hwspinlock.h> 228c2ecf20Sopenharmony_ci#include <linux/of.h> 238c2ecf20Sopenharmony_ci#include <linux/platform_device.h> 248c2ecf20Sopenharmony_ci 258c2ecf20Sopenharmony_ci#include "hwspinlock_internal.h" 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_ci/* Spinlock register offsets */ 288c2ecf20Sopenharmony_ci#define SYSSTATUS_OFFSET 0x0014 298c2ecf20Sopenharmony_ci#define LOCK_BASE_OFFSET 0x0800 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci#define SPINLOCK_NUMLOCKS_BIT_OFFSET (24) 328c2ecf20Sopenharmony_ci 338c2ecf20Sopenharmony_ci/* Possible values of SPINLOCK_LOCK_REG */ 348c2ecf20Sopenharmony_ci#define SPINLOCK_NOTTAKEN (0) /* free */ 358c2ecf20Sopenharmony_ci#define SPINLOCK_TAKEN (1) /* locked */ 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_cistatic int omap_hwspinlock_trylock(struct hwspinlock *lock) 388c2ecf20Sopenharmony_ci{ 398c2ecf20Sopenharmony_ci void __iomem *lock_addr = lock->priv; 408c2ecf20Sopenharmony_ci 418c2ecf20Sopenharmony_ci /* attempt to acquire the lock by reading its value */ 428c2ecf20Sopenharmony_ci return (SPINLOCK_NOTTAKEN == readl(lock_addr)); 438c2ecf20Sopenharmony_ci} 448c2ecf20Sopenharmony_ci 458c2ecf20Sopenharmony_cistatic void omap_hwspinlock_unlock(struct hwspinlock *lock) 468c2ecf20Sopenharmony_ci{ 478c2ecf20Sopenharmony_ci void __iomem *lock_addr = lock->priv; 488c2ecf20Sopenharmony_ci 498c2ecf20Sopenharmony_ci /* release the lock by writing 0 to it */ 508c2ecf20Sopenharmony_ci writel(SPINLOCK_NOTTAKEN, lock_addr); 518c2ecf20Sopenharmony_ci} 528c2ecf20Sopenharmony_ci 538c2ecf20Sopenharmony_ci/* 548c2ecf20Sopenharmony_ci * relax the OMAP interconnect while spinning on it. 558c2ecf20Sopenharmony_ci * 568c2ecf20Sopenharmony_ci * The specs recommended that the retry delay time will be 578c2ecf20Sopenharmony_ci * just over half of the time that a requester would be 588c2ecf20Sopenharmony_ci * expected to hold the lock. 598c2ecf20Sopenharmony_ci * 608c2ecf20Sopenharmony_ci * The number below is taken from an hardware specs example, 618c2ecf20Sopenharmony_ci * obviously it is somewhat arbitrary. 628c2ecf20Sopenharmony_ci */ 638c2ecf20Sopenharmony_cistatic void omap_hwspinlock_relax(struct hwspinlock *lock) 648c2ecf20Sopenharmony_ci{ 658c2ecf20Sopenharmony_ci ndelay(50); 668c2ecf20Sopenharmony_ci} 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_cistatic const struct hwspinlock_ops omap_hwspinlock_ops = { 698c2ecf20Sopenharmony_ci .trylock = omap_hwspinlock_trylock, 708c2ecf20Sopenharmony_ci .unlock = omap_hwspinlock_unlock, 718c2ecf20Sopenharmony_ci .relax = omap_hwspinlock_relax, 728c2ecf20Sopenharmony_ci}; 738c2ecf20Sopenharmony_ci 748c2ecf20Sopenharmony_cistatic int omap_hwspinlock_probe(struct platform_device *pdev) 758c2ecf20Sopenharmony_ci{ 768c2ecf20Sopenharmony_ci struct device_node *node = pdev->dev.of_node; 778c2ecf20Sopenharmony_ci struct hwspinlock_device *bank; 788c2ecf20Sopenharmony_ci struct hwspinlock *hwlock; 798c2ecf20Sopenharmony_ci void __iomem *io_base; 808c2ecf20Sopenharmony_ci int num_locks, i, ret; 818c2ecf20Sopenharmony_ci /* Only a single hwspinlock block device is supported */ 828c2ecf20Sopenharmony_ci int base_id = 0; 838c2ecf20Sopenharmony_ci 848c2ecf20Sopenharmony_ci if (!node) 858c2ecf20Sopenharmony_ci return -ENODEV; 868c2ecf20Sopenharmony_ci 878c2ecf20Sopenharmony_ci io_base = devm_platform_ioremap_resource(pdev, 0); 888c2ecf20Sopenharmony_ci if (IS_ERR(io_base)) 898c2ecf20Sopenharmony_ci return PTR_ERR(io_base); 908c2ecf20Sopenharmony_ci 918c2ecf20Sopenharmony_ci /* 928c2ecf20Sopenharmony_ci * make sure the module is enabled and clocked before reading 938c2ecf20Sopenharmony_ci * the module SYSSTATUS register 948c2ecf20Sopenharmony_ci */ 958c2ecf20Sopenharmony_ci pm_runtime_enable(&pdev->dev); 968c2ecf20Sopenharmony_ci ret = pm_runtime_get_sync(&pdev->dev); 978c2ecf20Sopenharmony_ci if (ret < 0) { 988c2ecf20Sopenharmony_ci pm_runtime_put_noidle(&pdev->dev); 998c2ecf20Sopenharmony_ci goto runtime_err; 1008c2ecf20Sopenharmony_ci } 1018c2ecf20Sopenharmony_ci 1028c2ecf20Sopenharmony_ci /* Determine number of locks */ 1038c2ecf20Sopenharmony_ci i = readl(io_base + SYSSTATUS_OFFSET); 1048c2ecf20Sopenharmony_ci i >>= SPINLOCK_NUMLOCKS_BIT_OFFSET; 1058c2ecf20Sopenharmony_ci 1068c2ecf20Sopenharmony_ci /* 1078c2ecf20Sopenharmony_ci * runtime PM will make sure the clock of this module is 1088c2ecf20Sopenharmony_ci * enabled again iff at least one lock is requested 1098c2ecf20Sopenharmony_ci */ 1108c2ecf20Sopenharmony_ci ret = pm_runtime_put(&pdev->dev); 1118c2ecf20Sopenharmony_ci if (ret < 0) 1128c2ecf20Sopenharmony_ci goto runtime_err; 1138c2ecf20Sopenharmony_ci 1148c2ecf20Sopenharmony_ci /* one of the four lsb's must be set, and nothing else */ 1158c2ecf20Sopenharmony_ci if (hweight_long(i & 0xf) != 1 || i > 8) { 1168c2ecf20Sopenharmony_ci ret = -EINVAL; 1178c2ecf20Sopenharmony_ci goto runtime_err; 1188c2ecf20Sopenharmony_ci } 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_ci num_locks = i * 32; /* actual number of locks in this device */ 1218c2ecf20Sopenharmony_ci 1228c2ecf20Sopenharmony_ci bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks), 1238c2ecf20Sopenharmony_ci GFP_KERNEL); 1248c2ecf20Sopenharmony_ci if (!bank) { 1258c2ecf20Sopenharmony_ci ret = -ENOMEM; 1268c2ecf20Sopenharmony_ci goto runtime_err; 1278c2ecf20Sopenharmony_ci } 1288c2ecf20Sopenharmony_ci 1298c2ecf20Sopenharmony_ci platform_set_drvdata(pdev, bank); 1308c2ecf20Sopenharmony_ci 1318c2ecf20Sopenharmony_ci for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++) 1328c2ecf20Sopenharmony_ci hwlock->priv = io_base + LOCK_BASE_OFFSET + sizeof(u32) * i; 1338c2ecf20Sopenharmony_ci 1348c2ecf20Sopenharmony_ci ret = hwspin_lock_register(bank, &pdev->dev, &omap_hwspinlock_ops, 1358c2ecf20Sopenharmony_ci base_id, num_locks); 1368c2ecf20Sopenharmony_ci if (ret) 1378c2ecf20Sopenharmony_ci goto runtime_err; 1388c2ecf20Sopenharmony_ci 1398c2ecf20Sopenharmony_ci dev_dbg(&pdev->dev, "Registered %d locks with HwSpinlock core\n", 1408c2ecf20Sopenharmony_ci num_locks); 1418c2ecf20Sopenharmony_ci 1428c2ecf20Sopenharmony_ci return 0; 1438c2ecf20Sopenharmony_ci 1448c2ecf20Sopenharmony_ciruntime_err: 1458c2ecf20Sopenharmony_ci pm_runtime_disable(&pdev->dev); 1468c2ecf20Sopenharmony_ci return ret; 1478c2ecf20Sopenharmony_ci} 1488c2ecf20Sopenharmony_ci 1498c2ecf20Sopenharmony_cistatic int omap_hwspinlock_remove(struct platform_device *pdev) 1508c2ecf20Sopenharmony_ci{ 1518c2ecf20Sopenharmony_ci struct hwspinlock_device *bank = platform_get_drvdata(pdev); 1528c2ecf20Sopenharmony_ci int ret; 1538c2ecf20Sopenharmony_ci 1548c2ecf20Sopenharmony_ci ret = hwspin_lock_unregister(bank); 1558c2ecf20Sopenharmony_ci if (ret) { 1568c2ecf20Sopenharmony_ci dev_err(&pdev->dev, "%s failed: %d\n", __func__, ret); 1578c2ecf20Sopenharmony_ci return ret; 1588c2ecf20Sopenharmony_ci } 1598c2ecf20Sopenharmony_ci 1608c2ecf20Sopenharmony_ci pm_runtime_disable(&pdev->dev); 1618c2ecf20Sopenharmony_ci 1628c2ecf20Sopenharmony_ci return 0; 1638c2ecf20Sopenharmony_ci} 1648c2ecf20Sopenharmony_ci 1658c2ecf20Sopenharmony_cistatic const struct of_device_id omap_hwspinlock_of_match[] = { 1668c2ecf20Sopenharmony_ci { .compatible = "ti,omap4-hwspinlock", }, 1678c2ecf20Sopenharmony_ci { .compatible = "ti,am654-hwspinlock", }, 1688c2ecf20Sopenharmony_ci { /* end */ }, 1698c2ecf20Sopenharmony_ci}; 1708c2ecf20Sopenharmony_ciMODULE_DEVICE_TABLE(of, omap_hwspinlock_of_match); 1718c2ecf20Sopenharmony_ci 1728c2ecf20Sopenharmony_cistatic struct platform_driver omap_hwspinlock_driver = { 1738c2ecf20Sopenharmony_ci .probe = omap_hwspinlock_probe, 1748c2ecf20Sopenharmony_ci .remove = omap_hwspinlock_remove, 1758c2ecf20Sopenharmony_ci .driver = { 1768c2ecf20Sopenharmony_ci .name = "omap_hwspinlock", 1778c2ecf20Sopenharmony_ci .of_match_table = of_match_ptr(omap_hwspinlock_of_match), 1788c2ecf20Sopenharmony_ci }, 1798c2ecf20Sopenharmony_ci}; 1808c2ecf20Sopenharmony_ci 1818c2ecf20Sopenharmony_cistatic int __init omap_hwspinlock_init(void) 1828c2ecf20Sopenharmony_ci{ 1838c2ecf20Sopenharmony_ci return platform_driver_register(&omap_hwspinlock_driver); 1848c2ecf20Sopenharmony_ci} 1858c2ecf20Sopenharmony_ci/* board init code might need to reserve hwspinlocks for predefined purposes */ 1868c2ecf20Sopenharmony_cipostcore_initcall(omap_hwspinlock_init); 1878c2ecf20Sopenharmony_ci 1888c2ecf20Sopenharmony_cistatic void __exit omap_hwspinlock_exit(void) 1898c2ecf20Sopenharmony_ci{ 1908c2ecf20Sopenharmony_ci platform_driver_unregister(&omap_hwspinlock_driver); 1918c2ecf20Sopenharmony_ci} 1928c2ecf20Sopenharmony_cimodule_exit(omap_hwspinlock_exit); 1938c2ecf20Sopenharmony_ci 1948c2ecf20Sopenharmony_ciMODULE_LICENSE("GPL v2"); 1958c2ecf20Sopenharmony_ciMODULE_DESCRIPTION("Hardware spinlock driver for OMAP"); 1968c2ecf20Sopenharmony_ciMODULE_AUTHOR("Simon Que <sque@ti.com>"); 1978c2ecf20Sopenharmony_ciMODULE_AUTHOR("Hari Kanigeri <h-kanigeri2@ti.com>"); 1988c2ecf20Sopenharmony_ciMODULE_AUTHOR("Ohad Ben-Cohen <ohad@wizery.com>"); 199