1// SPDX-License-Identifier: GPL-2.0 OR MIT 2/************************************************************************** 3 * 4 * Copyright 2009-2016 VMware, Inc., Palo Alto, CA., USA 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 24 * USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#include <linux/console.h> 29#include <linux/dma-mapping.h> 30#include <linux/module.h> 31#include <linux/pci.h> 32#include <linux/mem_encrypt.h> 33 34#include <drm/drm_drv.h> 35#include <drm/drm_ioctl.h> 36#include <drm/drm_sysfs.h> 37#include <drm/ttm/ttm_bo_driver.h> 38#include <drm/ttm/ttm_module.h> 39#include <drm/ttm/ttm_placement.h> 40 41#include "ttm_object.h" 42#include "vmwgfx_binding.h" 43#include "vmwgfx_drv.h" 44 45#define VMWGFX_DRIVER_DESC "Linux drm driver for VMware graphics devices" 46#define VMWGFX_CHIP_SVGAII 0 47#define VMW_FB_RESERVATION 0 48 49#define VMW_MIN_INITIAL_WIDTH 800 50#define VMW_MIN_INITIAL_HEIGHT 600 51 52#ifndef VMWGFX_GIT_VERSION 53#define VMWGFX_GIT_VERSION "Unknown" 54#endif 55 56#define VMWGFX_REPO "In Tree" 57 58#define VMWGFX_VALIDATION_MEM_GRAN (16*PAGE_SIZE) 59 60 61/** 62 * Fully encoded drm commands. Might move to vmw_drm.h 63 */ 64 65#define DRM_IOCTL_VMW_GET_PARAM \ 66 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GET_PARAM, \ 67 struct drm_vmw_getparam_arg) 68#define DRM_IOCTL_VMW_ALLOC_DMABUF \ 69 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_ALLOC_DMABUF, \ 70 union drm_vmw_alloc_dmabuf_arg) 71#define DRM_IOCTL_VMW_UNREF_DMABUF \ 72 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_DMABUF, \ 73 struct drm_vmw_unref_dmabuf_arg) 74#define DRM_IOCTL_VMW_CURSOR_BYPASS \ 75 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CURSOR_BYPASS, \ 76 struct drm_vmw_cursor_bypass_arg) 77 78#define DRM_IOCTL_VMW_CONTROL_STREAM \ 79 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_CONTROL_STREAM, \ 80 struct drm_vmw_control_stream_arg) 81#define DRM_IOCTL_VMW_CLAIM_STREAM \ 82 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CLAIM_STREAM, \ 83 struct drm_vmw_stream_arg) 84#define DRM_IOCTL_VMW_UNREF_STREAM \ 85 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_STREAM, \ 86 struct drm_vmw_stream_arg) 87 88#define DRM_IOCTL_VMW_CREATE_CONTEXT \ 89 DRM_IOR(DRM_COMMAND_BASE + DRM_VMW_CREATE_CONTEXT, \ 90 struct drm_vmw_context_arg) 91#define DRM_IOCTL_VMW_UNREF_CONTEXT \ 92 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_CONTEXT, \ 93 struct drm_vmw_context_arg) 94#define DRM_IOCTL_VMW_CREATE_SURFACE \ 95 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SURFACE, \ 96 union drm_vmw_surface_create_arg) 97#define DRM_IOCTL_VMW_UNREF_SURFACE \ 98 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SURFACE, \ 99 struct drm_vmw_surface_arg) 100#define DRM_IOCTL_VMW_REF_SURFACE \ 101 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_REF_SURFACE, \ 102 union drm_vmw_surface_reference_arg) 103#define DRM_IOCTL_VMW_EXECBUF \ 104 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_EXECBUF, \ 105 struct drm_vmw_execbuf_arg) 106#define DRM_IOCTL_VMW_GET_3D_CAP \ 107 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_GET_3D_CAP, \ 108 struct drm_vmw_get_3d_cap_arg) 109#define DRM_IOCTL_VMW_FENCE_WAIT \ 110 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_WAIT, \ 111 struct drm_vmw_fence_wait_arg) 112#define DRM_IOCTL_VMW_FENCE_SIGNALED \ 113 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_FENCE_SIGNALED, \ 114 struct drm_vmw_fence_signaled_arg) 115#define DRM_IOCTL_VMW_FENCE_UNREF \ 116 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_UNREF, \ 117 struct drm_vmw_fence_arg) 118#define DRM_IOCTL_VMW_FENCE_EVENT \ 119 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_FENCE_EVENT, \ 120 struct drm_vmw_fence_event_arg) 121#define DRM_IOCTL_VMW_PRESENT \ 122 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT, \ 123 struct drm_vmw_present_arg) 124#define DRM_IOCTL_VMW_PRESENT_READBACK \ 125 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_PRESENT_READBACK, \ 126 struct drm_vmw_present_readback_arg) 127#define DRM_IOCTL_VMW_UPDATE_LAYOUT \ 128 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT, \ 129 struct drm_vmw_update_layout_arg) 130#define DRM_IOCTL_VMW_CREATE_SHADER \ 131 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_SHADER, \ 132 struct drm_vmw_shader_create_arg) 133#define DRM_IOCTL_VMW_UNREF_SHADER \ 134 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_UNREF_SHADER, \ 135 struct drm_vmw_shader_arg) 136#define DRM_IOCTL_VMW_GB_SURFACE_CREATE \ 137 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE, \ 138 union drm_vmw_gb_surface_create_arg) 139#define DRM_IOCTL_VMW_GB_SURFACE_REF \ 140 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF, \ 141 union drm_vmw_gb_surface_reference_arg) 142#define DRM_IOCTL_VMW_SYNCCPU \ 143 DRM_IOW(DRM_COMMAND_BASE + DRM_VMW_SYNCCPU, \ 144 struct drm_vmw_synccpu_arg) 145#define DRM_IOCTL_VMW_CREATE_EXTENDED_CONTEXT \ 146 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_CREATE_EXTENDED_CONTEXT, \ 147 struct drm_vmw_context_arg) 148#define DRM_IOCTL_VMW_GB_SURFACE_CREATE_EXT \ 149 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_CREATE_EXT, \ 150 union drm_vmw_gb_surface_create_ext_arg) 151#define DRM_IOCTL_VMW_GB_SURFACE_REF_EXT \ 152 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_GB_SURFACE_REF_EXT, \ 153 union drm_vmw_gb_surface_reference_ext_arg) 154#define DRM_IOCTL_VMW_MSG \ 155 DRM_IOWR(DRM_COMMAND_BASE + DRM_VMW_MSG, \ 156 struct drm_vmw_msg_arg) 157 158/** 159 * The core DRM version of this macro doesn't account for 160 * DRM_COMMAND_BASE. 161 */ 162 163#define VMW_IOCTL_DEF(ioctl, func, flags) \ 164 [DRM_IOCTL_NR(DRM_IOCTL_##ioctl) - DRM_COMMAND_BASE] = {DRM_IOCTL_##ioctl, flags, func} 165 166/** 167 * Ioctl definitions. 168 */ 169 170static const struct drm_ioctl_desc vmw_ioctls[] = { 171 VMW_IOCTL_DEF(VMW_GET_PARAM, vmw_getparam_ioctl, 172 DRM_RENDER_ALLOW), 173 VMW_IOCTL_DEF(VMW_ALLOC_DMABUF, vmw_bo_alloc_ioctl, 174 DRM_RENDER_ALLOW), 175 VMW_IOCTL_DEF(VMW_UNREF_DMABUF, vmw_bo_unref_ioctl, 176 DRM_RENDER_ALLOW), 177 VMW_IOCTL_DEF(VMW_CURSOR_BYPASS, 178 vmw_kms_cursor_bypass_ioctl, 179 DRM_MASTER), 180 181 VMW_IOCTL_DEF(VMW_CONTROL_STREAM, vmw_overlay_ioctl, 182 DRM_MASTER), 183 VMW_IOCTL_DEF(VMW_CLAIM_STREAM, vmw_stream_claim_ioctl, 184 DRM_MASTER), 185 VMW_IOCTL_DEF(VMW_UNREF_STREAM, vmw_stream_unref_ioctl, 186 DRM_MASTER), 187 188 VMW_IOCTL_DEF(VMW_CREATE_CONTEXT, vmw_context_define_ioctl, 189 DRM_RENDER_ALLOW), 190 VMW_IOCTL_DEF(VMW_UNREF_CONTEXT, vmw_context_destroy_ioctl, 191 DRM_RENDER_ALLOW), 192 VMW_IOCTL_DEF(VMW_CREATE_SURFACE, vmw_surface_define_ioctl, 193 DRM_RENDER_ALLOW), 194 VMW_IOCTL_DEF(VMW_UNREF_SURFACE, vmw_surface_destroy_ioctl, 195 DRM_RENDER_ALLOW), 196 VMW_IOCTL_DEF(VMW_REF_SURFACE, vmw_surface_reference_ioctl, 197 DRM_RENDER_ALLOW), 198 VMW_IOCTL_DEF(VMW_EXECBUF, vmw_execbuf_ioctl, 199 DRM_RENDER_ALLOW), 200 VMW_IOCTL_DEF(VMW_FENCE_WAIT, vmw_fence_obj_wait_ioctl, 201 DRM_RENDER_ALLOW), 202 VMW_IOCTL_DEF(VMW_FENCE_SIGNALED, 203 vmw_fence_obj_signaled_ioctl, 204 DRM_RENDER_ALLOW), 205 VMW_IOCTL_DEF(VMW_FENCE_UNREF, vmw_fence_obj_unref_ioctl, 206 DRM_RENDER_ALLOW), 207 VMW_IOCTL_DEF(VMW_FENCE_EVENT, vmw_fence_event_ioctl, 208 DRM_RENDER_ALLOW), 209 VMW_IOCTL_DEF(VMW_GET_3D_CAP, vmw_get_cap_3d_ioctl, 210 DRM_RENDER_ALLOW), 211 212 /* these allow direct access to the framebuffers mark as master only */ 213 VMW_IOCTL_DEF(VMW_PRESENT, vmw_present_ioctl, 214 DRM_MASTER | DRM_AUTH), 215 VMW_IOCTL_DEF(VMW_PRESENT_READBACK, 216 vmw_present_readback_ioctl, 217 DRM_MASTER | DRM_AUTH), 218 /* 219 * The permissions of the below ioctl are overridden in 220 * vmw_generic_ioctl(). We require either 221 * DRM_MASTER or capable(CAP_SYS_ADMIN). 222 */ 223 VMW_IOCTL_DEF(VMW_UPDATE_LAYOUT, 224 vmw_kms_update_layout_ioctl, 225 DRM_RENDER_ALLOW), 226 VMW_IOCTL_DEF(VMW_CREATE_SHADER, 227 vmw_shader_define_ioctl, 228 DRM_RENDER_ALLOW), 229 VMW_IOCTL_DEF(VMW_UNREF_SHADER, 230 vmw_shader_destroy_ioctl, 231 DRM_RENDER_ALLOW), 232 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE, 233 vmw_gb_surface_define_ioctl, 234 DRM_RENDER_ALLOW), 235 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF, 236 vmw_gb_surface_reference_ioctl, 237 DRM_RENDER_ALLOW), 238 VMW_IOCTL_DEF(VMW_SYNCCPU, 239 vmw_user_bo_synccpu_ioctl, 240 DRM_RENDER_ALLOW), 241 VMW_IOCTL_DEF(VMW_CREATE_EXTENDED_CONTEXT, 242 vmw_extended_context_define_ioctl, 243 DRM_RENDER_ALLOW), 244 VMW_IOCTL_DEF(VMW_GB_SURFACE_CREATE_EXT, 245 vmw_gb_surface_define_ext_ioctl, 246 DRM_RENDER_ALLOW), 247 VMW_IOCTL_DEF(VMW_GB_SURFACE_REF_EXT, 248 vmw_gb_surface_reference_ext_ioctl, 249 DRM_RENDER_ALLOW), 250 VMW_IOCTL_DEF(VMW_MSG, 251 vmw_msg_ioctl, 252 DRM_RENDER_ALLOW), 253}; 254 255static const struct pci_device_id vmw_pci_id_list[] = { 256 {0x15ad, 0x0405, PCI_ANY_ID, PCI_ANY_ID, 0, 0, VMWGFX_CHIP_SVGAII}, 257 {0, 0, 0} 258}; 259MODULE_DEVICE_TABLE(pci, vmw_pci_id_list); 260 261static int enable_fbdev = IS_ENABLED(CONFIG_DRM_VMWGFX_FBCON); 262static int vmw_force_iommu; 263static int vmw_restrict_iommu; 264static int vmw_force_coherent; 265static int vmw_restrict_dma_mask; 266static int vmw_assume_16bpp; 267 268static int vmw_probe(struct pci_dev *, const struct pci_device_id *); 269static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 270 void *ptr); 271 272MODULE_PARM_DESC(enable_fbdev, "Enable vmwgfx fbdev"); 273module_param_named(enable_fbdev, enable_fbdev, int, 0600); 274MODULE_PARM_DESC(force_dma_api, "Force using the DMA API for TTM pages"); 275module_param_named(force_dma_api, vmw_force_iommu, int, 0600); 276MODULE_PARM_DESC(restrict_iommu, "Try to limit IOMMU usage for TTM pages"); 277module_param_named(restrict_iommu, vmw_restrict_iommu, int, 0600); 278MODULE_PARM_DESC(force_coherent, "Force coherent TTM pages"); 279module_param_named(force_coherent, vmw_force_coherent, int, 0600); 280MODULE_PARM_DESC(restrict_dma_mask, "Restrict DMA mask to 44 bits with IOMMU"); 281module_param_named(restrict_dma_mask, vmw_restrict_dma_mask, int, 0600); 282MODULE_PARM_DESC(assume_16bpp, "Assume 16-bpp when filtering modes"); 283module_param_named(assume_16bpp, vmw_assume_16bpp, int, 0600); 284 285 286static void vmw_print_capabilities2(uint32_t capabilities2) 287{ 288 DRM_INFO("Capabilities2:\n"); 289 if (capabilities2 & SVGA_CAP2_GROW_OTABLE) 290 DRM_INFO(" Grow oTable.\n"); 291 if (capabilities2 & SVGA_CAP2_INTRA_SURFACE_COPY) 292 DRM_INFO(" IntraSurface copy.\n"); 293 if (capabilities2 & SVGA_CAP2_DX3) 294 DRM_INFO(" DX3.\n"); 295} 296 297static void vmw_print_capabilities(uint32_t capabilities) 298{ 299 DRM_INFO("Capabilities:\n"); 300 if (capabilities & SVGA_CAP_RECT_COPY) 301 DRM_INFO(" Rect copy.\n"); 302 if (capabilities & SVGA_CAP_CURSOR) 303 DRM_INFO(" Cursor.\n"); 304 if (capabilities & SVGA_CAP_CURSOR_BYPASS) 305 DRM_INFO(" Cursor bypass.\n"); 306 if (capabilities & SVGA_CAP_CURSOR_BYPASS_2) 307 DRM_INFO(" Cursor bypass 2.\n"); 308 if (capabilities & SVGA_CAP_8BIT_EMULATION) 309 DRM_INFO(" 8bit emulation.\n"); 310 if (capabilities & SVGA_CAP_ALPHA_CURSOR) 311 DRM_INFO(" Alpha cursor.\n"); 312 if (capabilities & SVGA_CAP_3D) 313 DRM_INFO(" 3D.\n"); 314 if (capabilities & SVGA_CAP_EXTENDED_FIFO) 315 DRM_INFO(" Extended Fifo.\n"); 316 if (capabilities & SVGA_CAP_MULTIMON) 317 DRM_INFO(" Multimon.\n"); 318 if (capabilities & SVGA_CAP_PITCHLOCK) 319 DRM_INFO(" Pitchlock.\n"); 320 if (capabilities & SVGA_CAP_IRQMASK) 321 DRM_INFO(" Irq mask.\n"); 322 if (capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) 323 DRM_INFO(" Display Topology.\n"); 324 if (capabilities & SVGA_CAP_GMR) 325 DRM_INFO(" GMR.\n"); 326 if (capabilities & SVGA_CAP_TRACES) 327 DRM_INFO(" Traces.\n"); 328 if (capabilities & SVGA_CAP_GMR2) 329 DRM_INFO(" GMR2.\n"); 330 if (capabilities & SVGA_CAP_SCREEN_OBJECT_2) 331 DRM_INFO(" Screen Object 2.\n"); 332 if (capabilities & SVGA_CAP_COMMAND_BUFFERS) 333 DRM_INFO(" Command Buffers.\n"); 334 if (capabilities & SVGA_CAP_CMD_BUFFERS_2) 335 DRM_INFO(" Command Buffers 2.\n"); 336 if (capabilities & SVGA_CAP_GBOBJECTS) 337 DRM_INFO(" Guest Backed Resources.\n"); 338 if (capabilities & SVGA_CAP_DX) 339 DRM_INFO(" DX Features.\n"); 340 if (capabilities & SVGA_CAP_HP_CMD_QUEUE) 341 DRM_INFO(" HP Command Queue.\n"); 342} 343 344/** 345 * vmw_dummy_query_bo_create - create a bo to hold a dummy query result 346 * 347 * @dev_priv: A device private structure. 348 * 349 * This function creates a small buffer object that holds the query 350 * result for dummy queries emitted as query barriers. 351 * The function will then map the first page and initialize a pending 352 * occlusion query result structure, Finally it will unmap the buffer. 353 * No interruptible waits are done within this function. 354 * 355 * Returns an error if bo creation or initialization fails. 356 */ 357static int vmw_dummy_query_bo_create(struct vmw_private *dev_priv) 358{ 359 int ret; 360 struct vmw_buffer_object *vbo; 361 struct ttm_bo_kmap_obj map; 362 volatile SVGA3dQueryResult *result; 363 bool dummy; 364 365 /* 366 * Create the vbo as pinned, so that a tryreserve will 367 * immediately succeed. This is because we're the only 368 * user of the bo currently. 369 */ 370 vbo = kzalloc(sizeof(*vbo), GFP_KERNEL); 371 if (!vbo) 372 return -ENOMEM; 373 374 ret = vmw_bo_init(dev_priv, vbo, PAGE_SIZE, 375 &vmw_sys_ne_placement, false, 376 &vmw_bo_bo_free); 377 if (unlikely(ret != 0)) 378 return ret; 379 380 ret = ttm_bo_reserve(&vbo->base, false, true, NULL); 381 BUG_ON(ret != 0); 382 vmw_bo_pin_reserved(vbo, true); 383 384 ret = ttm_bo_kmap(&vbo->base, 0, 1, &map); 385 if (likely(ret == 0)) { 386 result = ttm_kmap_obj_virtual(&map, &dummy); 387 result->totalSize = sizeof(*result); 388 result->state = SVGA3D_QUERYSTATE_PENDING; 389 result->result32 = 0xff; 390 ttm_bo_kunmap(&map); 391 } 392 vmw_bo_pin_reserved(vbo, false); 393 ttm_bo_unreserve(&vbo->base); 394 395 if (unlikely(ret != 0)) { 396 DRM_ERROR("Dummy query buffer map failed.\n"); 397 vmw_bo_unreference(&vbo); 398 } else 399 dev_priv->dummy_query_bo = vbo; 400 401 return ret; 402} 403 404/** 405 * vmw_request_device_late - Perform late device setup 406 * 407 * @dev_priv: Pointer to device private. 408 * 409 * This function performs setup of otables and enables large command 410 * buffer submission. These tasks are split out to a separate function 411 * because it reverts vmw_release_device_early and is intended to be used 412 * by an error path in the hibernation code. 413 */ 414static int vmw_request_device_late(struct vmw_private *dev_priv) 415{ 416 int ret; 417 418 if (dev_priv->has_mob) { 419 ret = vmw_otables_setup(dev_priv); 420 if (unlikely(ret != 0)) { 421 DRM_ERROR("Unable to initialize " 422 "guest Memory OBjects.\n"); 423 return ret; 424 } 425 } 426 427 if (dev_priv->cman) { 428 ret = vmw_cmdbuf_set_pool_size(dev_priv->cman, 429 256*4096, 2*4096); 430 if (ret) { 431 struct vmw_cmdbuf_man *man = dev_priv->cman; 432 433 dev_priv->cman = NULL; 434 vmw_cmdbuf_man_destroy(man); 435 } 436 } 437 438 return 0; 439} 440 441static int vmw_request_device(struct vmw_private *dev_priv) 442{ 443 int ret; 444 445 ret = vmw_fifo_init(dev_priv, &dev_priv->fifo); 446 if (unlikely(ret != 0)) { 447 DRM_ERROR("Unable to initialize FIFO.\n"); 448 return ret; 449 } 450 vmw_fence_fifo_up(dev_priv->fman); 451 dev_priv->cman = vmw_cmdbuf_man_create(dev_priv); 452 if (IS_ERR(dev_priv->cman)) { 453 dev_priv->cman = NULL; 454 dev_priv->sm_type = VMW_SM_LEGACY; 455 } 456 457 ret = vmw_request_device_late(dev_priv); 458 if (ret) 459 goto out_no_mob; 460 461 ret = vmw_dummy_query_bo_create(dev_priv); 462 if (unlikely(ret != 0)) 463 goto out_no_query_bo; 464 465 return 0; 466 467out_no_query_bo: 468 if (dev_priv->cman) 469 vmw_cmdbuf_remove_pool(dev_priv->cman); 470 if (dev_priv->has_mob) { 471 (void) ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 472 vmw_otables_takedown(dev_priv); 473 } 474 if (dev_priv->cman) 475 vmw_cmdbuf_man_destroy(dev_priv->cman); 476out_no_mob: 477 vmw_fence_fifo_down(dev_priv->fman); 478 vmw_fifo_release(dev_priv, &dev_priv->fifo); 479 return ret; 480} 481 482/** 483 * vmw_release_device_early - Early part of fifo takedown. 484 * 485 * @dev_priv: Pointer to device private struct. 486 * 487 * This is the first part of command submission takedown, to be called before 488 * buffer management is taken down. 489 */ 490static void vmw_release_device_early(struct vmw_private *dev_priv) 491{ 492 /* 493 * Previous destructions should've released 494 * the pinned bo. 495 */ 496 497 BUG_ON(dev_priv->pinned_bo != NULL); 498 499 vmw_bo_unreference(&dev_priv->dummy_query_bo); 500 if (dev_priv->cman) 501 vmw_cmdbuf_remove_pool(dev_priv->cman); 502 503 if (dev_priv->has_mob) { 504 ttm_bo_evict_mm(&dev_priv->bdev, VMW_PL_MOB); 505 vmw_otables_takedown(dev_priv); 506 } 507} 508 509/** 510 * vmw_release_device_late - Late part of fifo takedown. 511 * 512 * @dev_priv: Pointer to device private struct. 513 * 514 * This is the last part of the command submission takedown, to be called when 515 * command submission is no longer needed. It may wait on pending fences. 516 */ 517static void vmw_release_device_late(struct vmw_private *dev_priv) 518{ 519 vmw_fence_fifo_down(dev_priv->fman); 520 if (dev_priv->cman) 521 vmw_cmdbuf_man_destroy(dev_priv->cman); 522 523 vmw_fifo_release(dev_priv, &dev_priv->fifo); 524} 525 526/** 527 * Sets the initial_[width|height] fields on the given vmw_private. 528 * 529 * It does so by reading SVGA_REG_[WIDTH|HEIGHT] regs and then 530 * clamping the value to fb_max_[width|height] fields and the 531 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 532 * If the values appear to be invalid, set them to 533 * VMW_MIN_INITIAL_[WIDTH|HEIGHT]. 534 */ 535static void vmw_get_initial_size(struct vmw_private *dev_priv) 536{ 537 uint32_t width; 538 uint32_t height; 539 540 width = vmw_read(dev_priv, SVGA_REG_WIDTH); 541 height = vmw_read(dev_priv, SVGA_REG_HEIGHT); 542 543 width = max_t(uint32_t, width, VMW_MIN_INITIAL_WIDTH); 544 height = max_t(uint32_t, height, VMW_MIN_INITIAL_HEIGHT); 545 546 if (width > dev_priv->fb_max_width || 547 height > dev_priv->fb_max_height) { 548 549 /* 550 * This is a host error and shouldn't occur. 551 */ 552 553 width = VMW_MIN_INITIAL_WIDTH; 554 height = VMW_MIN_INITIAL_HEIGHT; 555 } 556 557 dev_priv->initial_width = width; 558 dev_priv->initial_height = height; 559} 560 561/** 562 * vmw_dma_select_mode - Determine how DMA mappings should be set up for this 563 * system. 564 * 565 * @dev_priv: Pointer to a struct vmw_private 566 * 567 * This functions tries to determine what actions need to be taken by the 568 * driver to make system pages visible to the device. 569 * If this function decides that DMA is not possible, it returns -EINVAL. 570 * The driver may then try to disable features of the device that require 571 * DMA. 572 */ 573static int vmw_dma_select_mode(struct vmw_private *dev_priv) 574{ 575 static const char *names[vmw_dma_map_max] = { 576 [vmw_dma_phys] = "Using physical TTM page addresses.", 577 [vmw_dma_alloc_coherent] = "Using coherent TTM pages.", 578 [vmw_dma_map_populate] = "Caching DMA mappings.", 579 [vmw_dma_map_bind] = "Giving up DMA mappings early."}; 580 581 /* TTM currently doesn't fully support SEV encryption. */ 582 if (mem_encrypt_active()) 583 return -EINVAL; 584 585 if (vmw_force_coherent) 586 dev_priv->map_mode = vmw_dma_alloc_coherent; 587 else if (vmw_restrict_iommu) 588 dev_priv->map_mode = vmw_dma_map_bind; 589 else 590 dev_priv->map_mode = vmw_dma_map_populate; 591 592 if (!IS_ENABLED(CONFIG_DRM_TTM_DMA_PAGE_POOL) && 593 (dev_priv->map_mode == vmw_dma_alloc_coherent)) 594 return -EINVAL; 595 596 DRM_INFO("DMA map mode: %s\n", names[dev_priv->map_mode]); 597 return 0; 598} 599 600/** 601 * vmw_dma_masks - set required page- and dma masks 602 * 603 * @dev: Pointer to struct drm-device 604 * 605 * With 32-bit we can only handle 32 bit PFNs. Optionally set that 606 * restriction also for 64-bit systems. 607 */ 608static int vmw_dma_masks(struct vmw_private *dev_priv) 609{ 610 struct drm_device *dev = dev_priv->dev; 611 int ret = 0; 612 613 ret = dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)); 614 if (dev_priv->map_mode != vmw_dma_phys && 615 (sizeof(unsigned long) == 4 || vmw_restrict_dma_mask)) { 616 DRM_INFO("Restricting DMA addresses to 44 bits.\n"); 617 return dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(44)); 618 } 619 620 return ret; 621} 622 623static int vmw_vram_manager_init(struct vmw_private *dev_priv) 624{ 625 int ret; 626#ifdef CONFIG_TRANSPARENT_HUGEPAGE 627 ret = vmw_thp_init(dev_priv); 628#else 629 ret = ttm_range_man_init(&dev_priv->bdev, TTM_PL_VRAM, false, 630 dev_priv->vram_size >> PAGE_SHIFT); 631#endif 632 ttm_resource_manager_set_used(ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM), false); 633 return ret; 634} 635 636static void vmw_vram_manager_fini(struct vmw_private *dev_priv) 637{ 638#ifdef CONFIG_TRANSPARENT_HUGEPAGE 639 vmw_thp_fini(dev_priv); 640#else 641 ttm_range_man_fini(&dev_priv->bdev, TTM_PL_VRAM); 642#endif 643} 644 645static int vmw_driver_load(struct drm_device *dev, unsigned long chipset) 646{ 647 struct vmw_private *dev_priv; 648 int ret; 649 uint32_t svga_id; 650 enum vmw_res_type i; 651 bool refuse_dma = false; 652 char host_log[100] = {0}; 653 654 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL); 655 if (unlikely(!dev_priv)) { 656 DRM_ERROR("Failed allocating a device private struct.\n"); 657 return -ENOMEM; 658 } 659 660 pci_set_master(dev->pdev); 661 662 dev_priv->dev = dev; 663 dev_priv->vmw_chipset = chipset; 664 dev_priv->last_read_seqno = (uint32_t) -100; 665 mutex_init(&dev_priv->cmdbuf_mutex); 666 mutex_init(&dev_priv->release_mutex); 667 mutex_init(&dev_priv->binding_mutex); 668 mutex_init(&dev_priv->global_kms_state_mutex); 669 ttm_lock_init(&dev_priv->reservation_sem); 670 spin_lock_init(&dev_priv->resource_lock); 671 spin_lock_init(&dev_priv->hw_lock); 672 spin_lock_init(&dev_priv->waiter_lock); 673 spin_lock_init(&dev_priv->cap_lock); 674 spin_lock_init(&dev_priv->svga_lock); 675 spin_lock_init(&dev_priv->cursor_lock); 676 677 for (i = vmw_res_context; i < vmw_res_max; ++i) { 678 idr_init(&dev_priv->res_idr[i]); 679 INIT_LIST_HEAD(&dev_priv->res_lru[i]); 680 } 681 682 init_waitqueue_head(&dev_priv->fence_queue); 683 init_waitqueue_head(&dev_priv->fifo_queue); 684 dev_priv->fence_queue_waiters = 0; 685 dev_priv->fifo_queue_waiters = 0; 686 687 dev_priv->used_memory_size = 0; 688 689 dev_priv->io_start = pci_resource_start(dev->pdev, 0); 690 dev_priv->vram_start = pci_resource_start(dev->pdev, 1); 691 dev_priv->mmio_start = pci_resource_start(dev->pdev, 2); 692 693 dev_priv->assume_16bpp = !!vmw_assume_16bpp; 694 695 dev_priv->enable_fb = enable_fbdev; 696 697 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 698 svga_id = vmw_read(dev_priv, SVGA_REG_ID); 699 if (svga_id != SVGA_ID_2) { 700 ret = -ENOSYS; 701 DRM_ERROR("Unsupported SVGA ID 0x%x\n", svga_id); 702 goto out_err0; 703 } 704 705 dev_priv->capabilities = vmw_read(dev_priv, SVGA_REG_CAPABILITIES); 706 707 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) { 708 dev_priv->capabilities2 = vmw_read(dev_priv, SVGA_REG_CAP2); 709 } 710 711 712 ret = vmw_dma_select_mode(dev_priv); 713 if (unlikely(ret != 0)) { 714 DRM_INFO("Restricting capabilities since DMA not available.\n"); 715 refuse_dma = true; 716 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) 717 DRM_INFO("Disabling 3D acceleration.\n"); 718 } 719 720 dev_priv->vram_size = vmw_read(dev_priv, SVGA_REG_VRAM_SIZE); 721 dev_priv->mmio_size = vmw_read(dev_priv, SVGA_REG_MEM_SIZE); 722 dev_priv->fb_max_width = vmw_read(dev_priv, SVGA_REG_MAX_WIDTH); 723 dev_priv->fb_max_height = vmw_read(dev_priv, SVGA_REG_MAX_HEIGHT); 724 725 vmw_get_initial_size(dev_priv); 726 727 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 728 dev_priv->max_gmr_ids = 729 vmw_read(dev_priv, SVGA_REG_GMR_MAX_IDS); 730 dev_priv->max_gmr_pages = 731 vmw_read(dev_priv, SVGA_REG_GMRS_MAX_PAGES); 732 dev_priv->memory_size = 733 vmw_read(dev_priv, SVGA_REG_MEMORY_SIZE); 734 dev_priv->memory_size -= dev_priv->vram_size; 735 } else { 736 /* 737 * An arbitrary limit of 512MiB on surface 738 * memory. But all HWV8 hardware supports GMR2. 739 */ 740 dev_priv->memory_size = 512*1024*1024; 741 } 742 dev_priv->max_mob_pages = 0; 743 dev_priv->max_mob_size = 0; 744 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) { 745 uint64_t mem_size; 746 747 if (dev_priv->capabilities2 & SVGA_CAP2_GB_MEMSIZE_2) 748 mem_size = vmw_read(dev_priv, 749 SVGA_REG_GBOBJECT_MEM_SIZE_KB); 750 else 751 mem_size = 752 vmw_read(dev_priv, 753 SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB); 754 755 /* 756 * Workaround for low memory 2D VMs to compensate for the 757 * allocation taken by fbdev 758 */ 759 if (!(dev_priv->capabilities & SVGA_CAP_3D)) 760 mem_size *= 3; 761 762 dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE; 763 dev_priv->prim_bb_mem = 764 vmw_read(dev_priv, 765 SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM); 766 dev_priv->max_mob_size = 767 vmw_read(dev_priv, SVGA_REG_MOB_MAX_SIZE); 768 dev_priv->stdu_max_width = 769 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_WIDTH); 770 dev_priv->stdu_max_height = 771 vmw_read(dev_priv, SVGA_REG_SCREENTARGET_MAX_HEIGHT); 772 773 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 774 SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH); 775 dev_priv->texture_max_width = vmw_read(dev_priv, 776 SVGA_REG_DEV_CAP); 777 vmw_write(dev_priv, SVGA_REG_DEV_CAP, 778 SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT); 779 dev_priv->texture_max_height = vmw_read(dev_priv, 780 SVGA_REG_DEV_CAP); 781 } else { 782 dev_priv->texture_max_width = 8192; 783 dev_priv->texture_max_height = 8192; 784 dev_priv->prim_bb_mem = dev_priv->vram_size; 785 } 786 787 vmw_print_capabilities(dev_priv->capabilities); 788 if (dev_priv->capabilities & SVGA_CAP_CAP2_REGISTER) 789 vmw_print_capabilities2(dev_priv->capabilities2); 790 791 ret = vmw_dma_masks(dev_priv); 792 if (unlikely(ret != 0)) 793 goto out_err0; 794 795 dma_set_max_seg_size(dev->dev, min_t(unsigned int, U32_MAX & PAGE_MASK, 796 SCATTERLIST_MAX_SEGMENT)); 797 798 if (dev_priv->capabilities & SVGA_CAP_GMR2) { 799 DRM_INFO("Max GMR ids is %u\n", 800 (unsigned)dev_priv->max_gmr_ids); 801 DRM_INFO("Max number of GMR pages is %u\n", 802 (unsigned)dev_priv->max_gmr_pages); 803 DRM_INFO("Max dedicated hypervisor surface memory is %u kiB\n", 804 (unsigned)dev_priv->memory_size / 1024); 805 } 806 DRM_INFO("Maximum display memory size is %u kiB\n", 807 dev_priv->prim_bb_mem / 1024); 808 DRM_INFO("VRAM at 0x%08x size is %u kiB\n", 809 dev_priv->vram_start, dev_priv->vram_size / 1024); 810 DRM_INFO("MMIO at 0x%08x size is %u kiB\n", 811 dev_priv->mmio_start, dev_priv->mmio_size / 1024); 812 813 dev_priv->mmio_virt = memremap(dev_priv->mmio_start, 814 dev_priv->mmio_size, MEMREMAP_WB); 815 816 if (unlikely(dev_priv->mmio_virt == NULL)) { 817 ret = -ENOMEM; 818 DRM_ERROR("Failed mapping MMIO.\n"); 819 goto out_err0; 820 } 821 822 /* Need mmio memory to check for fifo pitchlock cap. */ 823 if (!(dev_priv->capabilities & SVGA_CAP_DISPLAY_TOPOLOGY) && 824 !(dev_priv->capabilities & SVGA_CAP_PITCHLOCK) && 825 !vmw_fifo_have_pitchlock(dev_priv)) { 826 ret = -ENOSYS; 827 DRM_ERROR("Hardware has no pitchlock\n"); 828 goto out_err4; 829 } 830 831 dev_priv->tdev = ttm_object_device_init(&ttm_mem_glob, 12, 832 &vmw_prime_dmabuf_ops); 833 834 if (unlikely(dev_priv->tdev == NULL)) { 835 DRM_ERROR("Unable to initialize TTM object management.\n"); 836 ret = -ENOMEM; 837 goto out_err4; 838 } 839 840 dev->dev_private = dev_priv; 841 842 ret = pci_request_regions(dev->pdev, "vmwgfx probe"); 843 dev_priv->stealth = (ret != 0); 844 if (dev_priv->stealth) { 845 /** 846 * Request at least the mmio PCI resource. 847 */ 848 849 DRM_INFO("It appears like vesafb is loaded. " 850 "Ignore above error if any.\n"); 851 ret = pci_request_region(dev->pdev, 2, "vmwgfx stealth probe"); 852 if (unlikely(ret != 0)) { 853 DRM_ERROR("Failed reserving the SVGA MMIO resource.\n"); 854 goto out_no_device; 855 } 856 } 857 858 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) { 859 ret = vmw_irq_install(dev, dev->pdev->irq); 860 if (ret != 0) { 861 DRM_ERROR("Failed installing irq: %d\n", ret); 862 goto out_no_irq; 863 } 864 } 865 866 dev_priv->fman = vmw_fence_manager_init(dev_priv); 867 if (unlikely(dev_priv->fman == NULL)) { 868 ret = -ENOMEM; 869 goto out_no_fman; 870 } 871 872 drm_vma_offset_manager_init(&dev_priv->vma_manager, 873 DRM_FILE_PAGE_OFFSET_START, 874 DRM_FILE_PAGE_OFFSET_SIZE); 875 ret = ttm_bo_device_init(&dev_priv->bdev, 876 &vmw_bo_driver, 877 dev->anon_inode->i_mapping, 878 &dev_priv->vma_manager, 879 false); 880 if (unlikely(ret != 0)) { 881 DRM_ERROR("Failed initializing TTM buffer object driver.\n"); 882 goto out_no_bdev; 883 } 884 885 /* 886 * Enable VRAM, but initially don't use it until SVGA is enabled and 887 * unhidden. 888 */ 889 890 ret = vmw_vram_manager_init(dev_priv); 891 if (unlikely(ret != 0)) { 892 DRM_ERROR("Failed initializing memory manager for VRAM.\n"); 893 goto out_no_vram; 894 } 895 896 /* 897 * "Guest Memory Regions" is an aperture like feature with 898 * one slot per bo. There is an upper limit of the number of 899 * slots as well as the bo size. 900 */ 901 dev_priv->has_gmr = true; 902 /* TODO: This is most likely not correct */ 903 if (((dev_priv->capabilities & (SVGA_CAP_GMR | SVGA_CAP_GMR2)) == 0) || 904 refuse_dma || 905 vmw_gmrid_man_init(dev_priv, VMW_PL_GMR) != 0) { 906 DRM_INFO("No GMR memory available. " 907 "Graphics memory resources are very limited.\n"); 908 dev_priv->has_gmr = false; 909 } 910 911 if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS && !refuse_dma) { 912 dev_priv->has_mob = true; 913 914 if (vmw_gmrid_man_init(dev_priv, VMW_PL_MOB) != 0) { 915 DRM_INFO("No MOB memory available. " 916 "3D will be disabled.\n"); 917 dev_priv->has_mob = false; 918 } 919 } 920 921 if (dev_priv->has_mob && (dev_priv->capabilities & SVGA_CAP_DX)) { 922 spin_lock(&dev_priv->cap_lock); 923 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_DXCONTEXT); 924 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 925 dev_priv->sm_type = VMW_SM_4; 926 spin_unlock(&dev_priv->cap_lock); 927 } 928 929 vmw_validation_mem_init_ttm(dev_priv, VMWGFX_VALIDATION_MEM_GRAN); 930 931 /* SVGA_CAP2_DX2 (DefineGBSurface_v3) is needed for SM4_1 support */ 932 if (has_sm4_context(dev_priv) && 933 (dev_priv->capabilities2 & SVGA_CAP2_DX2)) { 934 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM41); 935 936 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 937 dev_priv->sm_type = VMW_SM_4_1; 938 939 if (has_sm4_1_context(dev_priv) && 940 (dev_priv->capabilities2 & SVGA_CAP2_DX3)) { 941 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_SM5); 942 if (vmw_read(dev_priv, SVGA_REG_DEV_CAP)) 943 dev_priv->sm_type = VMW_SM_5; 944 } 945 } 946 947 ret = vmw_kms_init(dev_priv); 948 if (unlikely(ret != 0)) 949 goto out_no_kms; 950 vmw_overlay_init(dev_priv); 951 952 ret = vmw_request_device(dev_priv); 953 if (ret) 954 goto out_no_fifo; 955 956 DRM_INFO("Atomic: %s\n", (dev->driver->driver_features & DRIVER_ATOMIC) 957 ? "yes." : "no."); 958 if (dev_priv->sm_type == VMW_SM_5) 959 DRM_INFO("SM5 support available.\n"); 960 if (dev_priv->sm_type == VMW_SM_4_1) 961 DRM_INFO("SM4_1 support available.\n"); 962 if (dev_priv->sm_type == VMW_SM_4) 963 DRM_INFO("SM4 support available.\n"); 964 965 snprintf(host_log, sizeof(host_log), "vmwgfx: %s-%s", 966 VMWGFX_REPO, VMWGFX_GIT_VERSION); 967 vmw_host_log(host_log); 968 969 memset(host_log, 0, sizeof(host_log)); 970 snprintf(host_log, sizeof(host_log), "vmwgfx: Module Version: %d.%d.%d", 971 VMWGFX_DRIVER_MAJOR, VMWGFX_DRIVER_MINOR, 972 VMWGFX_DRIVER_PATCHLEVEL); 973 vmw_host_log(host_log); 974 975 if (dev_priv->enable_fb) { 976 vmw_fifo_resource_inc(dev_priv); 977 vmw_svga_enable(dev_priv); 978 vmw_fb_init(dev_priv); 979 } 980 981 dev_priv->pm_nb.notifier_call = vmwgfx_pm_notifier; 982 register_pm_notifier(&dev_priv->pm_nb); 983 984 return 0; 985 986out_no_fifo: 987 vmw_overlay_close(dev_priv); 988 vmw_kms_close(dev_priv); 989out_no_kms: 990 if (dev_priv->has_mob) 991 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 992 if (dev_priv->has_gmr) 993 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 994 vmw_vram_manager_fini(dev_priv); 995out_no_vram: 996 (void)ttm_bo_device_release(&dev_priv->bdev); 997out_no_bdev: 998 vmw_fence_manager_takedown(dev_priv->fman); 999out_no_fman: 1000 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1001 vmw_irq_uninstall(dev_priv->dev); 1002out_no_irq: 1003 if (dev_priv->stealth) 1004 pci_release_region(dev->pdev, 2); 1005 else 1006 pci_release_regions(dev->pdev); 1007out_no_device: 1008 ttm_object_device_release(&dev_priv->tdev); 1009out_err4: 1010 memunmap(dev_priv->mmio_virt); 1011out_err0: 1012 for (i = vmw_res_context; i < vmw_res_max; ++i) 1013 idr_destroy(&dev_priv->res_idr[i]); 1014 1015 if (dev_priv->ctx.staged_bindings) 1016 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1017 kfree(dev_priv); 1018 return ret; 1019} 1020 1021static void vmw_driver_unload(struct drm_device *dev) 1022{ 1023 struct vmw_private *dev_priv = vmw_priv(dev); 1024 enum vmw_res_type i; 1025 1026 unregister_pm_notifier(&dev_priv->pm_nb); 1027 1028 if (dev_priv->ctx.res_ht_initialized) 1029 drm_ht_remove(&dev_priv->ctx.res_ht); 1030 vfree(dev_priv->ctx.cmd_bounce); 1031 if (dev_priv->enable_fb) { 1032 vmw_fb_off(dev_priv); 1033 vmw_fb_close(dev_priv); 1034 vmw_fifo_resource_dec(dev_priv); 1035 vmw_svga_disable(dev_priv); 1036 } 1037 1038 vmw_kms_close(dev_priv); 1039 vmw_overlay_close(dev_priv); 1040 1041 if (dev_priv->has_gmr) 1042 vmw_gmrid_man_fini(dev_priv, VMW_PL_GMR); 1043 1044 vmw_release_device_early(dev_priv); 1045 if (dev_priv->has_mob) 1046 vmw_gmrid_man_fini(dev_priv, VMW_PL_MOB); 1047 vmw_vram_manager_fini(dev_priv); 1048 (void) ttm_bo_device_release(&dev_priv->bdev); 1049 drm_vma_offset_manager_destroy(&dev_priv->vma_manager); 1050 vmw_release_device_late(dev_priv); 1051 vmw_fence_manager_takedown(dev_priv->fman); 1052 if (dev_priv->capabilities & SVGA_CAP_IRQMASK) 1053 vmw_irq_uninstall(dev_priv->dev); 1054 if (dev_priv->stealth) 1055 pci_release_region(dev->pdev, 2); 1056 else 1057 pci_release_regions(dev->pdev); 1058 1059 ttm_object_device_release(&dev_priv->tdev); 1060 memunmap(dev_priv->mmio_virt); 1061 if (dev_priv->ctx.staged_bindings) 1062 vmw_binding_state_free(dev_priv->ctx.staged_bindings); 1063 1064 for (i = vmw_res_context; i < vmw_res_max; ++i) 1065 idr_destroy(&dev_priv->res_idr[i]); 1066 1067 kfree(dev_priv); 1068} 1069 1070static void vmw_postclose(struct drm_device *dev, 1071 struct drm_file *file_priv) 1072{ 1073 struct vmw_fpriv *vmw_fp = vmw_fpriv(file_priv); 1074 1075 ttm_object_file_release(&vmw_fp->tfile); 1076 kfree(vmw_fp); 1077} 1078 1079static int vmw_driver_open(struct drm_device *dev, struct drm_file *file_priv) 1080{ 1081 struct vmw_private *dev_priv = vmw_priv(dev); 1082 struct vmw_fpriv *vmw_fp; 1083 int ret = -ENOMEM; 1084 1085 vmw_fp = kzalloc(sizeof(*vmw_fp), GFP_KERNEL); 1086 if (unlikely(!vmw_fp)) 1087 return ret; 1088 1089 vmw_fp->tfile = ttm_object_file_init(dev_priv->tdev, 10); 1090 if (unlikely(vmw_fp->tfile == NULL)) 1091 goto out_no_tfile; 1092 1093 file_priv->driver_priv = vmw_fp; 1094 1095 return 0; 1096 1097out_no_tfile: 1098 kfree(vmw_fp); 1099 return ret; 1100} 1101 1102static long vmw_generic_ioctl(struct file *filp, unsigned int cmd, 1103 unsigned long arg, 1104 long (*ioctl_func)(struct file *, unsigned int, 1105 unsigned long)) 1106{ 1107 struct drm_file *file_priv = filp->private_data; 1108 struct drm_device *dev = file_priv->minor->dev; 1109 unsigned int nr = DRM_IOCTL_NR(cmd); 1110 unsigned int flags; 1111 1112 /* 1113 * Do extra checking on driver private ioctls. 1114 */ 1115 1116 if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END) 1117 && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) { 1118 const struct drm_ioctl_desc *ioctl = 1119 &vmw_ioctls[nr - DRM_COMMAND_BASE]; 1120 1121 if (nr == DRM_COMMAND_BASE + DRM_VMW_EXECBUF) { 1122 return ioctl_func(filp, cmd, arg); 1123 } else if (nr == DRM_COMMAND_BASE + DRM_VMW_UPDATE_LAYOUT) { 1124 if (!drm_is_current_master(file_priv) && 1125 !capable(CAP_SYS_ADMIN)) 1126 return -EACCES; 1127 } 1128 1129 if (unlikely(ioctl->cmd != cmd)) 1130 goto out_io_encoding; 1131 1132 flags = ioctl->flags; 1133 } else if (!drm_ioctl_flags(nr, &flags)) 1134 return -EINVAL; 1135 1136 return ioctl_func(filp, cmd, arg); 1137 1138out_io_encoding: 1139 DRM_ERROR("Invalid command format, ioctl %d\n", 1140 nr - DRM_COMMAND_BASE); 1141 1142 return -EINVAL; 1143} 1144 1145static long vmw_unlocked_ioctl(struct file *filp, unsigned int cmd, 1146 unsigned long arg) 1147{ 1148 return vmw_generic_ioctl(filp, cmd, arg, &drm_ioctl); 1149} 1150 1151#ifdef CONFIG_COMPAT 1152static long vmw_compat_ioctl(struct file *filp, unsigned int cmd, 1153 unsigned long arg) 1154{ 1155 return vmw_generic_ioctl(filp, cmd, arg, &drm_compat_ioctl); 1156} 1157#endif 1158 1159static void vmw_master_set(struct drm_device *dev, 1160 struct drm_file *file_priv, 1161 bool from_open) 1162{ 1163 /* 1164 * Inform a new master that the layout may have changed while 1165 * it was gone. 1166 */ 1167 if (!from_open) 1168 drm_sysfs_hotplug_event(dev); 1169} 1170 1171static void vmw_master_drop(struct drm_device *dev, 1172 struct drm_file *file_priv) 1173{ 1174 struct vmw_private *dev_priv = vmw_priv(dev); 1175 1176 vmw_kms_legacy_hotspot_clear(dev_priv); 1177 if (!dev_priv->enable_fb) 1178 vmw_svga_disable(dev_priv); 1179} 1180 1181/** 1182 * __vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1183 * 1184 * @dev_priv: Pointer to device private struct. 1185 * Needs the reservation sem to be held in non-exclusive mode. 1186 */ 1187static void __vmw_svga_enable(struct vmw_private *dev_priv) 1188{ 1189 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1190 1191 spin_lock(&dev_priv->svga_lock); 1192 if (!ttm_resource_manager_used(man)) { 1193 vmw_write(dev_priv, SVGA_REG_ENABLE, SVGA_REG_ENABLE); 1194 ttm_resource_manager_set_used(man, true); 1195 } 1196 spin_unlock(&dev_priv->svga_lock); 1197} 1198 1199/** 1200 * vmw_svga_enable - Enable SVGA mode, FIFO and use of VRAM. 1201 * 1202 * @dev_priv: Pointer to device private struct. 1203 */ 1204void vmw_svga_enable(struct vmw_private *dev_priv) 1205{ 1206 (void) ttm_read_lock(&dev_priv->reservation_sem, false); 1207 __vmw_svga_enable(dev_priv); 1208 ttm_read_unlock(&dev_priv->reservation_sem); 1209} 1210 1211/** 1212 * __vmw_svga_disable - Disable SVGA mode and use of VRAM. 1213 * 1214 * @dev_priv: Pointer to device private struct. 1215 * Needs the reservation sem to be held in exclusive mode. 1216 * Will not empty VRAM. VRAM must be emptied by caller. 1217 */ 1218static void __vmw_svga_disable(struct vmw_private *dev_priv) 1219{ 1220 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1221 1222 spin_lock(&dev_priv->svga_lock); 1223 if (ttm_resource_manager_used(man)) { 1224 ttm_resource_manager_set_used(man, false); 1225 vmw_write(dev_priv, SVGA_REG_ENABLE, 1226 SVGA_REG_ENABLE_HIDE | 1227 SVGA_REG_ENABLE_ENABLE); 1228 } 1229 spin_unlock(&dev_priv->svga_lock); 1230} 1231 1232/** 1233 * vmw_svga_disable - Disable SVGA_MODE, and use of VRAM. Keep the fifo 1234 * running. 1235 * 1236 * @dev_priv: Pointer to device private struct. 1237 * Will empty VRAM. 1238 */ 1239void vmw_svga_disable(struct vmw_private *dev_priv) 1240{ 1241 struct ttm_resource_manager *man = ttm_manager_type(&dev_priv->bdev, TTM_PL_VRAM); 1242 /* 1243 * Disabling SVGA will turn off device modesetting capabilities, so 1244 * notify KMS about that so that it doesn't cache atomic state that 1245 * isn't valid anymore, for example crtcs turned on. 1246 * Strictly we'd want to do this under the SVGA lock (or an SVGA mutex), 1247 * but vmw_kms_lost_device() takes the reservation sem and thus we'll 1248 * end up with lock order reversal. Thus, a master may actually perform 1249 * a new modeset just after we call vmw_kms_lost_device() and race with 1250 * vmw_svga_disable(), but that should at worst cause atomic KMS state 1251 * to be inconsistent with the device, causing modesetting problems. 1252 * 1253 */ 1254 vmw_kms_lost_device(dev_priv->dev); 1255 ttm_write_lock(&dev_priv->reservation_sem, false); 1256 spin_lock(&dev_priv->svga_lock); 1257 if (ttm_resource_manager_used(man)) { 1258 ttm_resource_manager_set_used(man, false); 1259 spin_unlock(&dev_priv->svga_lock); 1260 if (ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_VRAM)) 1261 DRM_ERROR("Failed evicting VRAM buffers.\n"); 1262 vmw_write(dev_priv, SVGA_REG_ENABLE, 1263 SVGA_REG_ENABLE_HIDE | 1264 SVGA_REG_ENABLE_ENABLE); 1265 } else 1266 spin_unlock(&dev_priv->svga_lock); 1267 ttm_write_unlock(&dev_priv->reservation_sem); 1268} 1269 1270static void vmw_remove(struct pci_dev *pdev) 1271{ 1272 struct drm_device *dev = pci_get_drvdata(pdev); 1273 1274 drm_dev_unregister(dev); 1275 vmw_driver_unload(dev); 1276 drm_dev_put(dev); 1277 pci_disable_device(pdev); 1278} 1279 1280static unsigned long 1281vmw_get_unmapped_area(struct file *file, unsigned long uaddr, 1282 unsigned long len, unsigned long pgoff, 1283 unsigned long flags) 1284{ 1285 struct drm_file *file_priv = file->private_data; 1286 struct vmw_private *dev_priv = vmw_priv(file_priv->minor->dev); 1287 1288 return drm_get_unmapped_area(file, uaddr, len, pgoff, flags, 1289 &dev_priv->vma_manager); 1290} 1291 1292static int vmwgfx_pm_notifier(struct notifier_block *nb, unsigned long val, 1293 void *ptr) 1294{ 1295 struct vmw_private *dev_priv = 1296 container_of(nb, struct vmw_private, pm_nb); 1297 1298 switch (val) { 1299 case PM_HIBERNATION_PREPARE: 1300 /* 1301 * Take the reservation sem in write mode, which will make sure 1302 * there are no other processes holding a buffer object 1303 * reservation, meaning we should be able to evict all buffer 1304 * objects if needed. 1305 * Once user-space processes have been frozen, we can release 1306 * the lock again. 1307 */ 1308 ttm_suspend_lock(&dev_priv->reservation_sem); 1309 dev_priv->suspend_locked = true; 1310 break; 1311 case PM_POST_HIBERNATION: 1312 case PM_POST_RESTORE: 1313 if (READ_ONCE(dev_priv->suspend_locked)) { 1314 dev_priv->suspend_locked = false; 1315 ttm_suspend_unlock(&dev_priv->reservation_sem); 1316 } 1317 break; 1318 default: 1319 break; 1320 } 1321 return 0; 1322} 1323 1324static int vmw_pci_suspend(struct pci_dev *pdev, pm_message_t state) 1325{ 1326 struct drm_device *dev = pci_get_drvdata(pdev); 1327 struct vmw_private *dev_priv = vmw_priv(dev); 1328 1329 if (dev_priv->refuse_hibernation) 1330 return -EBUSY; 1331 1332 pci_save_state(pdev); 1333 pci_disable_device(pdev); 1334 pci_set_power_state(pdev, PCI_D3hot); 1335 return 0; 1336} 1337 1338static int vmw_pci_resume(struct pci_dev *pdev) 1339{ 1340 pci_set_power_state(pdev, PCI_D0); 1341 pci_restore_state(pdev); 1342 return pci_enable_device(pdev); 1343} 1344 1345static int vmw_pm_suspend(struct device *kdev) 1346{ 1347 struct pci_dev *pdev = to_pci_dev(kdev); 1348 struct pm_message dummy; 1349 1350 dummy.event = 0; 1351 1352 return vmw_pci_suspend(pdev, dummy); 1353} 1354 1355static int vmw_pm_resume(struct device *kdev) 1356{ 1357 struct pci_dev *pdev = to_pci_dev(kdev); 1358 1359 return vmw_pci_resume(pdev); 1360} 1361 1362static int vmw_pm_freeze(struct device *kdev) 1363{ 1364 struct pci_dev *pdev = to_pci_dev(kdev); 1365 struct drm_device *dev = pci_get_drvdata(pdev); 1366 struct vmw_private *dev_priv = vmw_priv(dev); 1367 int ret; 1368 1369 /* 1370 * Unlock for vmw_kms_suspend. 1371 * No user-space processes should be running now. 1372 */ 1373 ttm_suspend_unlock(&dev_priv->reservation_sem); 1374 ret = vmw_kms_suspend(dev_priv->dev); 1375 if (ret) { 1376 ttm_suspend_lock(&dev_priv->reservation_sem); 1377 DRM_ERROR("Failed to freeze modesetting.\n"); 1378 return ret; 1379 } 1380 if (dev_priv->enable_fb) 1381 vmw_fb_off(dev_priv); 1382 1383 ttm_suspend_lock(&dev_priv->reservation_sem); 1384 vmw_execbuf_release_pinned_bo(dev_priv); 1385 vmw_resource_evict_all(dev_priv); 1386 vmw_release_device_early(dev_priv); 1387 ttm_bo_swapout_all(); 1388 if (dev_priv->enable_fb) 1389 vmw_fifo_resource_dec(dev_priv); 1390 if (atomic_read(&dev_priv->num_fifo_resources) != 0) { 1391 DRM_ERROR("Can't hibernate while 3D resources are active.\n"); 1392 if (dev_priv->enable_fb) 1393 vmw_fifo_resource_inc(dev_priv); 1394 WARN_ON(vmw_request_device_late(dev_priv)); 1395 dev_priv->suspend_locked = false; 1396 ttm_suspend_unlock(&dev_priv->reservation_sem); 1397 if (dev_priv->suspend_state) 1398 vmw_kms_resume(dev); 1399 if (dev_priv->enable_fb) 1400 vmw_fb_on(dev_priv); 1401 return -EBUSY; 1402 } 1403 1404 vmw_fence_fifo_down(dev_priv->fman); 1405 __vmw_svga_disable(dev_priv); 1406 1407 vmw_release_device_late(dev_priv); 1408 return 0; 1409} 1410 1411static int vmw_pm_restore(struct device *kdev) 1412{ 1413 struct pci_dev *pdev = to_pci_dev(kdev); 1414 struct drm_device *dev = pci_get_drvdata(pdev); 1415 struct vmw_private *dev_priv = vmw_priv(dev); 1416 int ret; 1417 1418 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); 1419 (void) vmw_read(dev_priv, SVGA_REG_ID); 1420 1421 if (dev_priv->enable_fb) 1422 vmw_fifo_resource_inc(dev_priv); 1423 1424 ret = vmw_request_device(dev_priv); 1425 if (ret) 1426 return ret; 1427 1428 if (dev_priv->enable_fb) 1429 __vmw_svga_enable(dev_priv); 1430 1431 vmw_fence_fifo_up(dev_priv->fman); 1432 dev_priv->suspend_locked = false; 1433 ttm_suspend_unlock(&dev_priv->reservation_sem); 1434 if (dev_priv->suspend_state) 1435 vmw_kms_resume(dev_priv->dev); 1436 1437 if (dev_priv->enable_fb) 1438 vmw_fb_on(dev_priv); 1439 1440 return 0; 1441} 1442 1443static const struct dev_pm_ops vmw_pm_ops = { 1444 .freeze = vmw_pm_freeze, 1445 .thaw = vmw_pm_restore, 1446 .restore = vmw_pm_restore, 1447 .suspend = vmw_pm_suspend, 1448 .resume = vmw_pm_resume, 1449}; 1450 1451static const struct file_operations vmwgfx_driver_fops = { 1452 .owner = THIS_MODULE, 1453 .open = drm_open, 1454 .release = drm_release, 1455 .unlocked_ioctl = vmw_unlocked_ioctl, 1456 .mmap = vmw_mmap, 1457 .poll = vmw_fops_poll, 1458 .read = vmw_fops_read, 1459#if defined(CONFIG_COMPAT) 1460 .compat_ioctl = vmw_compat_ioctl, 1461#endif 1462 .llseek = noop_llseek, 1463 .get_unmapped_area = vmw_get_unmapped_area, 1464}; 1465 1466static struct drm_driver driver = { 1467 .driver_features = 1468 DRIVER_MODESET | DRIVER_RENDER | DRIVER_ATOMIC, 1469 .ioctls = vmw_ioctls, 1470 .num_ioctls = ARRAY_SIZE(vmw_ioctls), 1471 .master_set = vmw_master_set, 1472 .master_drop = vmw_master_drop, 1473 .open = vmw_driver_open, 1474 .postclose = vmw_postclose, 1475 1476 .dumb_create = vmw_dumb_create, 1477 .dumb_map_offset = vmw_dumb_map_offset, 1478 .dumb_destroy = vmw_dumb_destroy, 1479 1480 .prime_fd_to_handle = vmw_prime_fd_to_handle, 1481 .prime_handle_to_fd = vmw_prime_handle_to_fd, 1482 1483 .fops = &vmwgfx_driver_fops, 1484 .name = VMWGFX_DRIVER_NAME, 1485 .desc = VMWGFX_DRIVER_DESC, 1486 .date = VMWGFX_DRIVER_DATE, 1487 .major = VMWGFX_DRIVER_MAJOR, 1488 .minor = VMWGFX_DRIVER_MINOR, 1489 .patchlevel = VMWGFX_DRIVER_PATCHLEVEL 1490}; 1491 1492static struct pci_driver vmw_pci_driver = { 1493 .name = VMWGFX_DRIVER_NAME, 1494 .id_table = vmw_pci_id_list, 1495 .probe = vmw_probe, 1496 .remove = vmw_remove, 1497 .driver = { 1498 .pm = &vmw_pm_ops 1499 } 1500}; 1501 1502static int vmw_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1503{ 1504 struct drm_device *dev; 1505 int ret; 1506 1507 ret = pci_enable_device(pdev); 1508 if (ret) 1509 return ret; 1510 1511 dev = drm_dev_alloc(&driver, &pdev->dev); 1512 if (IS_ERR(dev)) { 1513 ret = PTR_ERR(dev); 1514 goto err_pci_disable_device; 1515 } 1516 1517 dev->pdev = pdev; 1518 pci_set_drvdata(pdev, dev); 1519 1520 ret = vmw_driver_load(dev, ent->driver_data); 1521 if (ret) 1522 goto err_drm_dev_put; 1523 1524 ret = drm_dev_register(dev, ent->driver_data); 1525 if (ret) 1526 goto err_vmw_driver_unload; 1527 1528 return 0; 1529 1530err_vmw_driver_unload: 1531 vmw_driver_unload(dev); 1532err_drm_dev_put: 1533 drm_dev_put(dev); 1534err_pci_disable_device: 1535 pci_disable_device(pdev); 1536 return ret; 1537} 1538 1539static int __init vmwgfx_init(void) 1540{ 1541 int ret; 1542 1543 if (vgacon_text_force()) 1544 return -EINVAL; 1545 1546 ret = pci_register_driver(&vmw_pci_driver); 1547 if (ret) 1548 DRM_ERROR("Failed initializing DRM.\n"); 1549 return ret; 1550} 1551 1552static void __exit vmwgfx_exit(void) 1553{ 1554 pci_unregister_driver(&vmw_pci_driver); 1555} 1556 1557module_init(vmwgfx_init); 1558module_exit(vmwgfx_exit); 1559 1560MODULE_AUTHOR("VMware Inc. and others"); 1561MODULE_DESCRIPTION("Standalone drm driver for the VMware SVGA device"); 1562MODULE_LICENSE("GPL and additional rights"); 1563MODULE_VERSION(__stringify(VMWGFX_DRIVER_MAJOR) "." 1564 __stringify(VMWGFX_DRIVER_MINOR) "." 1565 __stringify(VMWGFX_DRIVER_PATCHLEVEL) "." 1566 "0"); 1567