1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright © 2018 Broadcom
4 *
5 * Authors:
6 *	Eric Anholt <eric@anholt.net>
7 *	Boris Brezillon <boris.brezillon@bootlin.com>
8 */
9
10#include <linux/clk.h>
11#include <linux/component.h>
12#include <linux/of_graph.h>
13#include <linux/of_platform.h>
14#include <linux/pm_runtime.h>
15
16#include <drm/drm_atomic_helper.h>
17#include <drm/drm_edid.h>
18#include <drm/drm_fb_cma_helper.h>
19#include <drm/drm_fourcc.h>
20#include <drm/drm_panel.h>
21#include <drm/drm_probe_helper.h>
22#include <drm/drm_vblank.h>
23#include <drm/drm_writeback.h>
24
25#include "vc4_drv.h"
26#include "vc4_regs.h"
27
28/* Base address of the output.  Raster formats must be 4-byte aligned,
29 * T and LT must be 16-byte aligned or maybe utile-aligned (docs are
30 * inconsistent, but probably utile).
31 */
32#define TXP_DST_PTR		0x00
33
34/* Pitch in bytes for raster images, 16-byte aligned.  For tiled, it's
35 * the width in tiles.
36 */
37#define TXP_DST_PITCH		0x04
38/* For T-tiled imgaes, DST_PITCH should be the number of tiles wide,
39 * shifted up.
40 */
41# define TXP_T_TILE_WIDTH_SHIFT		7
42/* For LT-tiled images, DST_PITCH should be the number of utiles wide,
43 * shifted up.
44 */
45# define TXP_LT_TILE_WIDTH_SHIFT	4
46
47/* Pre-rotation width/height of the image.  Must match HVS config.
48 *
49 * If TFORMAT and 32-bit, limit is 1920 for 32-bit and 3840 to 16-bit
50 * and width/height must be tile or utile-aligned as appropriate.  If
51 * transposing (rotating), width is limited to 1920.
52 *
53 * Height is limited to various numbers between 4088 and 4095.  I'd
54 * just use 4088 to be safe.
55 */
56#define TXP_DIM			0x08
57# define TXP_HEIGHT_SHIFT		16
58# define TXP_HEIGHT_MASK		GENMASK(31, 16)
59# define TXP_WIDTH_SHIFT		0
60# define TXP_WIDTH_MASK			GENMASK(15, 0)
61
62#define TXP_DST_CTRL		0x0c
63/* These bits are set to 0x54 */
64#define TXP_PILOT_SHIFT			24
65#define TXP_PILOT_MASK			GENMASK(31, 24)
66/* Bits 22-23 are set to 0x01 */
67#define TXP_VERSION_SHIFT		22
68#define TXP_VERSION_MASK		GENMASK(23, 22)
69
70/* Powers down the internal memory. */
71# define TXP_POWERDOWN			BIT(21)
72
73/* Enables storing the alpha component in 8888/4444, instead of
74 * filling with ~ALPHA_INVERT.
75 */
76# define TXP_ALPHA_ENABLE		BIT(20)
77
78/* 4 bits, each enables stores for a channel in each set of 4 bytes.
79 * Set to 0xf for normal operation.
80 */
81# define TXP_BYTE_ENABLE_SHIFT		16
82# define TXP_BYTE_ENABLE_MASK		GENMASK(19, 16)
83
84/* Debug: Generate VSTART again at EOF. */
85# define TXP_VSTART_AT_EOF		BIT(15)
86
87/* Debug: Terminate the current frame immediately.  Stops AXI
88 * writes.
89 */
90# define TXP_ABORT			BIT(14)
91
92# define TXP_DITHER			BIT(13)
93
94/* Inverts alpha if TXP_ALPHA_ENABLE, chooses fill value for
95 * !TXP_ALPHA_ENABLE.
96 */
97# define TXP_ALPHA_INVERT		BIT(12)
98
99/* Note: I've listed the channels here in high bit (in byte 3/2/1) to
100 * low bit (in byte 0) order.
101 */
102# define TXP_FORMAT_SHIFT		8
103# define TXP_FORMAT_MASK		GENMASK(11, 8)
104# define TXP_FORMAT_ABGR4444		0
105# define TXP_FORMAT_ARGB4444		1
106# define TXP_FORMAT_BGRA4444		2
107# define TXP_FORMAT_RGBA4444		3
108# define TXP_FORMAT_BGR565		6
109# define TXP_FORMAT_RGB565		7
110/* 888s are non-rotated, raster-only */
111# define TXP_FORMAT_BGR888		8
112# define TXP_FORMAT_RGB888		9
113# define TXP_FORMAT_ABGR8888		12
114# define TXP_FORMAT_ARGB8888		13
115# define TXP_FORMAT_BGRA8888		14
116# define TXP_FORMAT_RGBA8888		15
117
118/* If TFORMAT is set, generates LT instead of T format. */
119# define TXP_LINEAR_UTILE		BIT(7)
120
121/* Rotate output by 90 degrees. */
122# define TXP_TRANSPOSE			BIT(6)
123
124/* Generate a tiled format for V3D. */
125# define TXP_TFORMAT			BIT(5)
126
127/* Generates some undefined test mode output. */
128# define TXP_TEST_MODE			BIT(4)
129
130/* Request odd field from HVS. */
131# define TXP_FIELD			BIT(3)
132
133/* Raise interrupt when idle. */
134# define TXP_EI				BIT(2)
135
136/* Set when generating a frame, clears when idle. */
137# define TXP_BUSY			BIT(1)
138
139/* Starts a frame.  Self-clearing. */
140# define TXP_GO				BIT(0)
141
142/* Number of lines received and committed to memory. */
143#define TXP_PROGRESS		0x10
144
145#define TXP_READ(offset) readl(txp->regs + (offset))
146#define TXP_WRITE(offset, val) writel(val, txp->regs + (offset))
147
148struct vc4_txp {
149	struct vc4_crtc	base;
150
151	struct platform_device *pdev;
152
153	struct drm_writeback_connector connector;
154
155	void __iomem *regs;
156	struct debugfs_regset32 regset;
157};
158
159static inline struct vc4_txp *encoder_to_vc4_txp(struct drm_encoder *encoder)
160{
161	return container_of(encoder, struct vc4_txp, connector.encoder);
162}
163
164static inline struct vc4_txp *connector_to_vc4_txp(struct drm_connector *conn)
165{
166	return container_of(conn, struct vc4_txp, connector.base);
167}
168
169static const struct debugfs_reg32 txp_regs[] = {
170	VC4_REG32(TXP_DST_PTR),
171	VC4_REG32(TXP_DST_PITCH),
172	VC4_REG32(TXP_DIM),
173	VC4_REG32(TXP_DST_CTRL),
174	VC4_REG32(TXP_PROGRESS),
175};
176
177static int vc4_txp_connector_get_modes(struct drm_connector *connector)
178{
179	struct drm_device *dev = connector->dev;
180
181	return drm_add_modes_noedid(connector, dev->mode_config.max_width,
182				    dev->mode_config.max_height);
183}
184
185static enum drm_mode_status
186vc4_txp_connector_mode_valid(struct drm_connector *connector,
187			     struct drm_display_mode *mode)
188{
189	struct drm_device *dev = connector->dev;
190	struct drm_mode_config *mode_config = &dev->mode_config;
191	int w = mode->hdisplay, h = mode->vdisplay;
192
193	if (w < mode_config->min_width || w > mode_config->max_width)
194		return MODE_BAD_HVALUE;
195
196	if (h < mode_config->min_height || h > mode_config->max_height)
197		return MODE_BAD_VVALUE;
198
199	return MODE_OK;
200}
201
202static const u32 drm_fmts[] = {
203	DRM_FORMAT_RGB888,
204	DRM_FORMAT_BGR888,
205	DRM_FORMAT_XRGB8888,
206	DRM_FORMAT_XBGR8888,
207	DRM_FORMAT_ARGB8888,
208	DRM_FORMAT_ABGR8888,
209	DRM_FORMAT_RGBX8888,
210	DRM_FORMAT_BGRX8888,
211	DRM_FORMAT_RGBA8888,
212	DRM_FORMAT_BGRA8888,
213};
214
215static const u32 txp_fmts[] = {
216	TXP_FORMAT_RGB888,
217	TXP_FORMAT_BGR888,
218	TXP_FORMAT_ARGB8888,
219	TXP_FORMAT_ABGR8888,
220	TXP_FORMAT_ARGB8888,
221	TXP_FORMAT_ABGR8888,
222	TXP_FORMAT_RGBA8888,
223	TXP_FORMAT_BGRA8888,
224	TXP_FORMAT_RGBA8888,
225	TXP_FORMAT_BGRA8888,
226};
227
228static void vc4_txp_armed(struct drm_crtc_state *state)
229{
230	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
231
232	vc4_state->txp_armed = true;
233}
234
235static int vc4_txp_connector_atomic_check(struct drm_connector *conn,
236					  struct drm_atomic_state *state)
237{
238	struct drm_connector_state *conn_state;
239	struct drm_crtc_state *crtc_state;
240	struct drm_framebuffer *fb;
241	int i;
242
243	conn_state = drm_atomic_get_new_connector_state(state, conn);
244	if (!conn_state->writeback_job)
245		return 0;
246
247	crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc);
248
249	fb = conn_state->writeback_job->fb;
250	if (fb->width != crtc_state->mode.hdisplay ||
251	    fb->height != crtc_state->mode.vdisplay) {
252		DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
253			      fb->width, fb->height);
254		return -EINVAL;
255	}
256
257	for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
258		if (fb->format->format == drm_fmts[i])
259			break;
260	}
261
262	if (i == ARRAY_SIZE(drm_fmts))
263		return -EINVAL;
264
265	/* Pitch must be aligned on 16 bytes. */
266	if (fb->pitches[0] & GENMASK(3, 0))
267		return -EINVAL;
268
269	vc4_txp_armed(crtc_state);
270
271	return 0;
272}
273
274static void vc4_txp_connector_atomic_commit(struct drm_connector *conn,
275					struct drm_connector_state *conn_state)
276{
277	struct vc4_txp *txp = connector_to_vc4_txp(conn);
278	struct drm_gem_cma_object *gem;
279	struct drm_display_mode *mode;
280	struct drm_framebuffer *fb;
281	u32 ctrl;
282	int i;
283
284	if (WARN_ON(!conn_state->writeback_job))
285		return;
286
287	mode = &conn_state->crtc->state->adjusted_mode;
288	fb = conn_state->writeback_job->fb;
289
290	for (i = 0; i < ARRAY_SIZE(drm_fmts); i++) {
291		if (fb->format->format == drm_fmts[i])
292			break;
293	}
294
295	if (WARN_ON(i == ARRAY_SIZE(drm_fmts)))
296		return;
297
298	ctrl = TXP_GO | TXP_EI |
299	       VC4_SET_FIELD(0xf, TXP_BYTE_ENABLE) |
300	       VC4_SET_FIELD(txp_fmts[i], TXP_FORMAT);
301
302	if (fb->format->has_alpha)
303		ctrl |= TXP_ALPHA_ENABLE;
304	else
305		/*
306		 * If TXP_ALPHA_ENABLE isn't set and TXP_ALPHA_INVERT is, the
307		 * hardware will force the output padding to be 0xff.
308		 */
309		ctrl |= TXP_ALPHA_INVERT;
310
311	gem = drm_fb_cma_get_gem_obj(fb, 0);
312	TXP_WRITE(TXP_DST_PTR, gem->paddr + fb->offsets[0]);
313	TXP_WRITE(TXP_DST_PITCH, fb->pitches[0]);
314	TXP_WRITE(TXP_DIM,
315		  VC4_SET_FIELD(mode->hdisplay, TXP_WIDTH) |
316		  VC4_SET_FIELD(mode->vdisplay, TXP_HEIGHT));
317
318	TXP_WRITE(TXP_DST_CTRL, ctrl);
319
320	drm_writeback_queue_job(&txp->connector, conn_state);
321}
322
323static const struct drm_connector_helper_funcs vc4_txp_connector_helper_funcs = {
324	.get_modes = vc4_txp_connector_get_modes,
325	.mode_valid = vc4_txp_connector_mode_valid,
326	.atomic_check = vc4_txp_connector_atomic_check,
327	.atomic_commit = vc4_txp_connector_atomic_commit,
328};
329
330static enum drm_connector_status
331vc4_txp_connector_detect(struct drm_connector *connector, bool force)
332{
333	return connector_status_connected;
334}
335
336static void vc4_txp_connector_destroy(struct drm_connector *connector)
337{
338	drm_connector_unregister(connector);
339	drm_connector_cleanup(connector);
340}
341
342static const struct drm_connector_funcs vc4_txp_connector_funcs = {
343	.detect = vc4_txp_connector_detect,
344	.fill_modes = drm_helper_probe_single_connector_modes,
345	.destroy = vc4_txp_connector_destroy,
346	.reset = drm_atomic_helper_connector_reset,
347	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
348	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
349};
350
351static void vc4_txp_encoder_disable(struct drm_encoder *encoder)
352{
353	struct vc4_txp *txp = encoder_to_vc4_txp(encoder);
354
355	if (TXP_READ(TXP_DST_CTRL) & TXP_BUSY) {
356		unsigned long timeout = jiffies + msecs_to_jiffies(1000);
357
358		TXP_WRITE(TXP_DST_CTRL, TXP_ABORT);
359
360		while (TXP_READ(TXP_DST_CTRL) & TXP_BUSY &&
361		       time_before(jiffies, timeout))
362			;
363
364		WARN_ON(TXP_READ(TXP_DST_CTRL) & TXP_BUSY);
365	}
366
367	TXP_WRITE(TXP_DST_CTRL, TXP_POWERDOWN);
368}
369
370static const struct drm_encoder_helper_funcs vc4_txp_encoder_helper_funcs = {
371	.disable = vc4_txp_encoder_disable,
372};
373
374static int vc4_txp_enable_vblank(struct drm_crtc *crtc)
375{
376	return 0;
377}
378
379static void vc4_txp_disable_vblank(struct drm_crtc *crtc) {}
380
381static const struct drm_crtc_funcs vc4_txp_crtc_funcs = {
382	.set_config		= drm_atomic_helper_set_config,
383	.destroy		= vc4_crtc_destroy,
384	.page_flip		= vc4_page_flip,
385	.reset			= vc4_crtc_reset,
386	.atomic_duplicate_state	= vc4_crtc_duplicate_state,
387	.atomic_destroy_state	= vc4_crtc_destroy_state,
388	.gamma_set		= drm_atomic_helper_legacy_gamma_set,
389	.enable_vblank		= vc4_txp_enable_vblank,
390	.disable_vblank		= vc4_txp_disable_vblank,
391};
392
393static int vc4_txp_atomic_check(struct drm_crtc *crtc,
394				struct drm_crtc_state *state)
395{
396	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
397	int ret;
398
399	ret = vc4_hvs_atomic_check(crtc, state);
400	if (ret)
401		return ret;
402
403	state->no_vblank = true;
404	vc4_state->feed_txp = true;
405
406	return 0;
407}
408
409static void vc4_txp_atomic_enable(struct drm_crtc *crtc,
410				  struct drm_crtc_state *old_state)
411{
412	drm_crtc_vblank_on(crtc);
413	vc4_hvs_atomic_enable(crtc, old_state);
414}
415
416static void vc4_txp_atomic_disable(struct drm_crtc *crtc,
417				   struct drm_crtc_state *old_state)
418{
419	struct drm_device *dev = crtc->dev;
420
421	/* Disable vblank irq handling before crtc is disabled. */
422	drm_crtc_vblank_off(crtc);
423
424	vc4_hvs_atomic_disable(crtc, old_state);
425
426	/*
427	 * Make sure we issue a vblank event after disabling the CRTC if
428	 * someone was waiting it.
429	 */
430	if (crtc->state->event) {
431		unsigned long flags;
432
433		spin_lock_irqsave(&dev->event_lock, flags);
434		drm_crtc_send_vblank_event(crtc, crtc->state->event);
435		crtc->state->event = NULL;
436		spin_unlock_irqrestore(&dev->event_lock, flags);
437	}
438}
439
440static const struct drm_crtc_helper_funcs vc4_txp_crtc_helper_funcs = {
441	.atomic_check	= vc4_txp_atomic_check,
442	.atomic_flush	= vc4_hvs_atomic_flush,
443	.atomic_enable	= vc4_txp_atomic_enable,
444	.atomic_disable	= vc4_txp_atomic_disable,
445};
446
447static irqreturn_t vc4_txp_interrupt(int irq, void *data)
448{
449	struct vc4_txp *txp = data;
450	struct vc4_crtc *vc4_crtc = &txp->base;
451
452	TXP_WRITE(TXP_DST_CTRL, TXP_READ(TXP_DST_CTRL) & ~TXP_EI);
453	vc4_crtc_handle_vblank(vc4_crtc);
454	drm_writeback_signal_completion(&txp->connector, 0);
455
456	return IRQ_HANDLED;
457}
458
459static const struct vc4_crtc_data vc4_txp_crtc_data = {
460	.hvs_available_channels = BIT(2),
461	.hvs_output = 2,
462};
463
464static int vc4_txp_bind(struct device *dev, struct device *master, void *data)
465{
466	struct platform_device *pdev = to_platform_device(dev);
467	struct drm_device *drm = dev_get_drvdata(master);
468	struct vc4_dev *vc4 = to_vc4_dev(drm);
469	struct vc4_crtc *vc4_crtc;
470	struct vc4_txp *txp;
471	struct drm_crtc *crtc;
472	struct drm_encoder *encoder;
473	int ret, irq;
474
475	irq = platform_get_irq(pdev, 0);
476	if (irq < 0)
477		return irq;
478
479	txp = devm_kzalloc(dev, sizeof(*txp), GFP_KERNEL);
480	if (!txp)
481		return -ENOMEM;
482	vc4_crtc = &txp->base;
483	crtc = &vc4_crtc->base;
484
485	vc4_crtc->pdev = pdev;
486	vc4_crtc->data = &vc4_txp_crtc_data;
487
488	txp->pdev = pdev;
489
490	txp->regs = vc4_ioremap_regs(pdev, 0);
491	if (IS_ERR(txp->regs))
492		return PTR_ERR(txp->regs);
493	txp->regset.base = txp->regs;
494	txp->regset.regs = txp_regs;
495	txp->regset.nregs = ARRAY_SIZE(txp_regs);
496
497	drm_connector_helper_add(&txp->connector.base,
498				 &vc4_txp_connector_helper_funcs);
499	ret = drm_writeback_connector_init(drm, &txp->connector,
500					   &vc4_txp_connector_funcs,
501					   &vc4_txp_encoder_helper_funcs,
502					   drm_fmts, ARRAY_SIZE(drm_fmts));
503	if (ret)
504		return ret;
505
506	ret = vc4_crtc_init(drm, vc4_crtc,
507			    &vc4_txp_crtc_funcs, &vc4_txp_crtc_helper_funcs);
508	if (ret)
509		return ret;
510
511	encoder = &txp->connector.encoder;
512	encoder->possible_crtcs = drm_crtc_mask(crtc);
513
514	ret = devm_request_irq(dev, irq, vc4_txp_interrupt, 0,
515			       dev_name(dev), txp);
516	if (ret)
517		return ret;
518
519	dev_set_drvdata(dev, txp);
520	vc4->txp = txp;
521
522	vc4_debugfs_add_regset32(drm, "txp_regs", &txp->regset);
523
524	return 0;
525}
526
527static void vc4_txp_unbind(struct device *dev, struct device *master,
528			   void *data)
529{
530	struct drm_device *drm = dev_get_drvdata(master);
531	struct vc4_dev *vc4 = to_vc4_dev(drm);
532	struct vc4_txp *txp = dev_get_drvdata(dev);
533
534	vc4_txp_connector_destroy(&txp->connector.base);
535
536	vc4->txp = NULL;
537}
538
539static const struct component_ops vc4_txp_ops = {
540	.bind   = vc4_txp_bind,
541	.unbind = vc4_txp_unbind,
542};
543
544static int vc4_txp_probe(struct platform_device *pdev)
545{
546	return component_add(&pdev->dev, &vc4_txp_ops);
547}
548
549static int vc4_txp_remove(struct platform_device *pdev)
550{
551	component_del(&pdev->dev, &vc4_txp_ops);
552	return 0;
553}
554
555static const struct of_device_id vc4_txp_dt_match[] = {
556	{ .compatible = "brcm,bcm2835-txp" },
557	{ /* sentinel */ },
558};
559
560struct platform_driver vc4_txp_driver = {
561	.probe = vc4_txp_probe,
562	.remove = vc4_txp_remove,
563	.driver = {
564		.name = "vc4_txp",
565		.of_match_table = vc4_txp_dt_match,
566	},
567};
568