1#ifndef _VC4_HDMI_REGS_H_ 2#define _VC4_HDMI_REGS_H_ 3 4#include "vc4_hdmi.h" 5 6#define VC4_HDMI_PACKET_STRIDE 0x24 7 8enum vc4_hdmi_regs { 9 VC4_INVALID = 0, 10 VC4_HDMI, 11 VC4_HD, 12 VC5_CEC, 13 VC5_CSC, 14 VC5_DVP, 15 VC5_PHY, 16 VC5_RAM, 17 VC5_RM, 18}; 19 20enum vc4_hdmi_field { 21 HDMI_AUDIO_PACKET_CONFIG, 22 HDMI_CEC_CNTRL_1, 23 HDMI_CEC_CNTRL_2, 24 HDMI_CEC_CNTRL_3, 25 HDMI_CEC_CNTRL_4, 26 HDMI_CEC_CNTRL_5, 27 HDMI_CEC_CPU_CLEAR, 28 HDMI_CEC_CPU_MASK_CLEAR, 29 HDMI_CEC_CPU_MASK_SET, 30 HDMI_CEC_CPU_MASK_STATUS, 31 HDMI_CEC_CPU_STATUS, 32 HDMI_CEC_CPU_SET, 33 34 /* 35 * Transmit data, first byte is low byte of the 32-bit reg. 36 * MSB of each byte transmitted first. 37 */ 38 HDMI_CEC_RX_DATA_1, 39 HDMI_CEC_RX_DATA_2, 40 HDMI_CEC_RX_DATA_3, 41 HDMI_CEC_RX_DATA_4, 42 HDMI_CEC_TX_DATA_1, 43 HDMI_CEC_TX_DATA_2, 44 HDMI_CEC_TX_DATA_3, 45 HDMI_CEC_TX_DATA_4, 46 HDMI_CLOCK_STOP, 47 HDMI_CORE_REV, 48 HDMI_CRP_CFG, 49 HDMI_CSC_12_11, 50 HDMI_CSC_14_13, 51 HDMI_CSC_22_21, 52 HDMI_CSC_24_23, 53 HDMI_CSC_32_31, 54 HDMI_CSC_34_33, 55 HDMI_CSC_CTL, 56 57 /* 58 * 20-bit fields containing CTS values to be transmitted if 59 * !EXTERNAL_CTS_EN 60 */ 61 HDMI_CTS_0, 62 HDMI_CTS_1, 63 HDMI_DVP_CTL, 64 HDMI_FIFO_CTL, 65 HDMI_FRAME_COUNT, 66 HDMI_HORZA, 67 HDMI_HORZB, 68 HDMI_HOTPLUG, 69 HDMI_HOTPLUG_INT, 70 71 /* 72 * 3 bits per field, where each field maps from that 73 * corresponding MAI bus channel to the given HDMI channel. 74 */ 75 HDMI_MAI_CHANNEL_MAP, 76 HDMI_MAI_CONFIG, 77 HDMI_MAI_CTL, 78 79 /* 80 * Register for DMAing in audio data to be transported over 81 * the MAI bus to the Falcon core. 82 */ 83 HDMI_MAI_DATA, 84 85 /* Format header to be placed on the MAI data. Unused. */ 86 HDMI_MAI_FMT, 87 88 /* Last received format word on the MAI bus. */ 89 HDMI_MAI_FORMAT, 90 HDMI_MAI_SMP, 91 HDMI_MAI_THR, 92 HDMI_M_CTL, 93 HDMI_RAM_PACKET_CONFIG, 94 HDMI_RAM_PACKET_START, 95 HDMI_RAM_PACKET_STATUS, 96 HDMI_RM_CONTROL, 97 HDMI_RM_FORMAT, 98 HDMI_RM_OFFSET, 99 HDMI_SCHEDULER_CONTROL, 100 HDMI_SW_RESET_CONTROL, 101 HDMI_TX_PHY_CHANNEL_SWAP, 102 HDMI_TX_PHY_CLK_DIV, 103 HDMI_TX_PHY_CTL_0, 104 HDMI_TX_PHY_CTL_1, 105 HDMI_TX_PHY_CTL_2, 106 HDMI_TX_PHY_CTL_3, 107 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 108 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 109 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 110 HDMI_TX_PHY_PLL_CFG, 111 HDMI_TX_PHY_PLL_CTL_0, 112 HDMI_TX_PHY_PLL_CTL_1, 113 HDMI_TX_PHY_POWERDOWN_CTL, 114 HDMI_TX_PHY_RESET_CTL, 115 HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 116 HDMI_VEC_INTERFACE_XBAR, 117 HDMI_VERTA0, 118 HDMI_VERTA1, 119 HDMI_VERTB0, 120 HDMI_VERTB1, 121 HDMI_VID_CTL, 122}; 123 124struct vc4_hdmi_register { 125 char *name; 126 enum vc4_hdmi_regs reg; 127 unsigned int offset; 128}; 129 130#define _VC4_REG(_base, _reg, _offset) \ 131 [_reg] = { \ 132 .name = #_reg, \ 133 .reg = _base, \ 134 .offset = _offset, \ 135 } 136 137#define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset) 138#define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset) 139#define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset) 140#define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset) 141#define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset) 142#define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset) 143#define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset) 144#define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset) 145 146static const struct vc4_hdmi_register vc4_hdmi_fields[] = { 147 VC4_HD_REG(HDMI_M_CTL, 0x000c), 148 VC4_HD_REG(HDMI_MAI_CTL, 0x0014), 149 VC4_HD_REG(HDMI_MAI_THR, 0x0018), 150 VC4_HD_REG(HDMI_MAI_FMT, 0x001c), 151 VC4_HD_REG(HDMI_MAI_DATA, 0x0020), 152 VC4_HD_REG(HDMI_MAI_SMP, 0x002c), 153 VC4_HD_REG(HDMI_VID_CTL, 0x0038), 154 VC4_HD_REG(HDMI_CSC_CTL, 0x0040), 155 VC4_HD_REG(HDMI_CSC_12_11, 0x0044), 156 VC4_HD_REG(HDMI_CSC_14_13, 0x0048), 157 VC4_HD_REG(HDMI_CSC_22_21, 0x004c), 158 VC4_HD_REG(HDMI_CSC_24_23, 0x0050), 159 VC4_HD_REG(HDMI_CSC_32_31, 0x0054), 160 VC4_HD_REG(HDMI_CSC_34_33, 0x0058), 161 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068), 162 163 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000), 164 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004), 165 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008), 166 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c), 167 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c), 168 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090), 169 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094), 170 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098), 171 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c), 172 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0), 173 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4), 174 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8), 175 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac), 176 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0), 177 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0), 178 VC4_HDMI_REG(HDMI_HORZA, 0x00c4), 179 VC4_HDMI_REG(HDMI_HORZB, 0x00c8), 180 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc), 181 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0), 182 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4), 183 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8), 184 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8), 185 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec), 186 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0), 187 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4), 188 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8), 189 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc), 190 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100), 191 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104), 192 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108), 193 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c), 194 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110), 195 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114), 196 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118), 197 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0), 198 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4), 199 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340), 200 VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344), 201 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348), 202 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c), 203 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350), 204 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354), 205 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400), 206}; 207 208static const struct vc4_hdmi_register vc5_hdmi_hdmi0_fields[] = { 209 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 210 VC4_HD_REG(HDMI_MAI_CTL, 0x0010), 211 VC4_HD_REG(HDMI_MAI_THR, 0x0014), 212 VC4_HD_REG(HDMI_MAI_FMT, 0x0018), 213 VC4_HD_REG(HDMI_MAI_DATA, 0x001c), 214 VC4_HD_REG(HDMI_MAI_SMP, 0x0020), 215 VC4_HD_REG(HDMI_VID_CTL, 0x0044), 216 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060), 217 218 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 219 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 220 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 221 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 222 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 223 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 224 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 225 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 226 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 227 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 228 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 229 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 230 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 231 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 232 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 233 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 234 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 235 236 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 237 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 238 239 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 240 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 241 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 242 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 243 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 244 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 245 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 246 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 247 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 248 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 249 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 250 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 251 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 252 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 253 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 254 255 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 256 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 257 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 258 259 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 260 261 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 262 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 263 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 264 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 265 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 266 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 267 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 268 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 269 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 270 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 271 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 272 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 273 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 274 275 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 276 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 277 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 278 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 279 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 280 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 281 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 282}; 283 284static const struct vc4_hdmi_register vc5_hdmi_hdmi1_fields[] = { 285 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 286 VC4_HD_REG(HDMI_MAI_CTL, 0x0030), 287 VC4_HD_REG(HDMI_MAI_THR, 0x0034), 288 VC4_HD_REG(HDMI_MAI_FMT, 0x0038), 289 VC4_HD_REG(HDMI_MAI_DATA, 0x003c), 290 VC4_HD_REG(HDMI_MAI_SMP, 0x0040), 291 VC4_HD_REG(HDMI_VID_CTL, 0x0048), 292 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064), 293 294 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 295 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 296 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 297 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 298 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 299 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 300 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 301 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 302 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 303 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 304 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 305 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 306 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 307 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 308 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 309 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 310 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 311 312 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 313 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 314 315 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 316 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 317 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 318 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 319 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 320 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 321 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 322 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 323 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 324 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 325 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 326 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 327 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 328 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 329 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 330 331 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 332 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 333 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 334 335 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 336 337 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 338 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 339 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 340 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 341 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 342 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 343 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 344 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 345 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 346 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 347 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 348 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 349 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 350 351 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 352 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 353 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 354 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 355 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 356 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 357 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 358}; 359 360static inline 361void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi, 362 enum vc4_hdmi_regs reg) 363{ 364 switch (reg) { 365 case VC4_HD: 366 return hdmi->hd_regs; 367 368 case VC4_HDMI: 369 return hdmi->hdmicore_regs; 370 371 case VC5_CSC: 372 return hdmi->csc_regs; 373 374 case VC5_CEC: 375 return hdmi->cec_regs; 376 377 case VC5_DVP: 378 return hdmi->dvp_regs; 379 380 case VC5_PHY: 381 return hdmi->phy_regs; 382 383 case VC5_RAM: 384 return hdmi->ram_regs; 385 386 case VC5_RM: 387 return hdmi->rm_regs; 388 389 default: 390 return NULL; 391 } 392 393 return NULL; 394} 395 396static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi, 397 enum vc4_hdmi_field reg) 398{ 399 const struct vc4_hdmi_register *field; 400 const struct vc4_hdmi_variant *variant = hdmi->variant; 401 void __iomem *base; 402 403 if (reg >= variant->num_registers) { 404 dev_warn(&hdmi->pdev->dev, 405 "Invalid register ID %u\n", reg); 406 return 0; 407 } 408 409 field = &variant->registers[reg]; 410 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 411 if (!base) { 412 dev_warn(&hdmi->pdev->dev, 413 "Unknown register ID %u\n", reg); 414 return 0; 415 } 416 417 return readl(base + field->offset); 418} 419#define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg) 420 421static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi, 422 enum vc4_hdmi_field reg, 423 u32 value) 424{ 425 const struct vc4_hdmi_register *field; 426 const struct vc4_hdmi_variant *variant = hdmi->variant; 427 void __iomem *base; 428 429 if (reg >= variant->num_registers) { 430 dev_warn(&hdmi->pdev->dev, 431 "Invalid register ID %u\n", reg); 432 return; 433 } 434 435 field = &variant->registers[reg]; 436 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 437 if (!base) 438 return; 439 440 writel(value, base + field->offset); 441} 442#define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val) 443 444#endif /* _VC4_HDMI_REGS_H_ */ 445