1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9/** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34#include <drm/drm_atomic_helper.h> 35#include <drm/drm_edid.h> 36#include <drm/drm_probe_helper.h> 37#include <drm/drm_simple_kms_helper.h> 38#include <linux/clk.h> 39#include <linux/component.h> 40#include <linux/i2c.h> 41#include <linux/of_address.h> 42#include <linux/of_gpio.h> 43#include <linux/of_platform.h> 44#include <linux/pm_runtime.h> 45#include <linux/rational.h> 46#include <linux/reset.h> 47#include <sound/dmaengine_pcm.h> 48#include <sound/pcm_drm_eld.h> 49#include <sound/pcm_params.h> 50#include <sound/soc.h> 51#include "media/cec.h" 52#include "vc4_drv.h" 53#include "vc4_hdmi.h" 54#include "vc4_hdmi_regs.h" 55#include "vc4_regs.h" 56 57#define VC5_HDMI_HORZA_HFP_SHIFT 16 58#define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 59#define VC5_HDMI_HORZA_VPOS BIT(15) 60#define VC5_HDMI_HORZA_HPOS BIT(14) 61#define VC5_HDMI_HORZA_HAP_SHIFT 0 62#define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 63 64#define VC5_HDMI_HORZB_HBP_SHIFT 16 65#define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 66#define VC5_HDMI_HORZB_HSP_SHIFT 0 67#define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 68 69#define VC5_HDMI_VERTA_VSP_SHIFT 24 70#define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 71#define VC5_HDMI_VERTA_VFP_SHIFT 16 72#define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 73#define VC5_HDMI_VERTA_VAL_SHIFT 0 74#define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 75 76#define VC5_HDMI_VERTB_VSPO_SHIFT 16 77#define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 78 79# define VC4_HD_M_SW_RST BIT(2) 80# define VC4_HD_M_ENABLE BIT(0) 81 82#define HSM_MIN_CLOCK_FREQ 120000000 83#define CEC_CLOCK_FREQ 40000 84#define VC4_HSM_MID_CLOCK 149985000 85 86#define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 87 88static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 89{ 90 struct drm_info_node *node = (struct drm_info_node *)m->private; 91 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 92 struct drm_printer p = drm_seq_file_printer(m); 93 94 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 95 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 96 97 return 0; 98} 99 100static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 101{ 102 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 103 udelay(1); 104 HDMI_WRITE(HDMI_M_CTL, 0); 105 106 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 107 108 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 109 VC4_HDMI_SW_RESET_HDMI | 110 VC4_HDMI_SW_RESET_FORMAT_DETECT); 111 112 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 113} 114 115static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 116{ 117 reset_control_reset(vc4_hdmi->reset); 118 119 HDMI_WRITE(HDMI_DVP_CTL, 0); 120 121 HDMI_WRITE(HDMI_CLOCK_STOP, 122 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 123} 124 125#ifdef CONFIG_DRM_VC4_HDMI_CEC 126static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 127{ 128 u16 clk_cnt; 129 u32 value; 130 131 value = HDMI_READ(HDMI_CEC_CNTRL_1); 132 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 133 134 /* 135 * Set the clock divider: the hsm_clock rate and this divider 136 * setting will give a 40 kHz CEC clock. 137 */ 138 clk_cnt = clk_get_rate(vc4_hdmi->hsm_clock) / CEC_CLOCK_FREQ; 139 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 140 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 141} 142#else 143static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 144#endif 145 146static enum drm_connector_status 147vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 148{ 149 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 150 bool connected = false; 151 152 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 153 154 if (vc4_hdmi->hpd_gpio) { 155 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^ 156 vc4_hdmi->hpd_active_low) 157 connected = true; 158 } else if (drm_probe_ddc(vc4_hdmi->ddc)) { 159 connected = true; 160 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) { 161 connected = true; 162 } 163 164 if (connected) { 165 if (connector->status != connector_status_connected) { 166 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 167 168 if (edid) { 169 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 170 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 171 kfree(edid); 172 } 173 } 174 175 pm_runtime_put(&vc4_hdmi->pdev->dev); 176 return connector_status_connected; 177 } 178 179 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 180 pm_runtime_put(&vc4_hdmi->pdev->dev); 181 return connector_status_disconnected; 182} 183 184static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 185{ 186 drm_connector_unregister(connector); 187 drm_connector_cleanup(connector); 188} 189 190static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 191{ 192 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 193 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 194 int ret = 0; 195 struct edid *edid; 196 197 edid = drm_get_edid(connector, vc4_hdmi->ddc); 198 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 199 if (!edid) 200 return -ENODEV; 201 202 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 203 204 drm_connector_update_edid_property(connector, edid); 205 ret = drm_add_edid_modes(connector, edid); 206 kfree(edid); 207 208 return ret; 209} 210 211static void vc4_hdmi_connector_reset(struct drm_connector *connector) 212{ 213 drm_atomic_helper_connector_reset(connector); 214 215 if (connector->state) 216 drm_atomic_helper_connector_tv_reset(connector); 217} 218 219static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 220 .detect = vc4_hdmi_connector_detect, 221 .fill_modes = drm_helper_probe_single_connector_modes, 222 .destroy = vc4_hdmi_connector_destroy, 223 .reset = vc4_hdmi_connector_reset, 224 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 225 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 226}; 227 228static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 229 .get_modes = vc4_hdmi_connector_get_modes, 230}; 231 232static int vc4_hdmi_connector_init(struct drm_device *dev, 233 struct vc4_hdmi *vc4_hdmi) 234{ 235 struct drm_connector *connector = &vc4_hdmi->connector; 236 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 237 int ret; 238 239 drm_connector_init_with_ddc(dev, connector, 240 &vc4_hdmi_connector_funcs, 241 DRM_MODE_CONNECTOR_HDMIA, 242 vc4_hdmi->ddc); 243 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 244 245 /* Create and attach TV margin props to this connector. */ 246 ret = drm_mode_create_tv_margin_properties(dev); 247 if (ret) 248 return ret; 249 250 drm_connector_attach_tv_margin_properties(connector); 251 252 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 253 DRM_CONNECTOR_POLL_DISCONNECT); 254 255 connector->interlace_allowed = 1; 256 connector->doublescan_allowed = 0; 257 258 drm_connector_attach_encoder(connector, encoder); 259 260 return 0; 261} 262 263static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 264 enum hdmi_infoframe_type type) 265{ 266 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 267 u32 packet_id = type - 0x80; 268 269 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 270 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 271 272 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 273 BIT(packet_id)), 100); 274} 275 276static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 277 union hdmi_infoframe *frame) 278{ 279 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 280 u32 packet_id = frame->any.type - 0x80; 281 const struct vc4_hdmi_register *ram_packet_start = 282 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 283 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 284 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 285 ram_packet_start->reg); 286 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 287 ssize_t len, i; 288 int ret; 289 290 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 291 VC4_HDMI_RAM_PACKET_ENABLE), 292 "Packet RAM has to be on to store the packet."); 293 294 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 295 if (len < 0) 296 return; 297 298 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 299 if (ret) { 300 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 301 return; 302 } 303 304 for (i = 0; i < len; i += 7) { 305 writel(buffer[i + 0] << 0 | 306 buffer[i + 1] << 8 | 307 buffer[i + 2] << 16, 308 base + packet_reg); 309 packet_reg += 4; 310 311 writel(buffer[i + 3] << 0 | 312 buffer[i + 4] << 8 | 313 buffer[i + 5] << 16 | 314 buffer[i + 6] << 24, 315 base + packet_reg); 316 packet_reg += 4; 317 } 318 319 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 320 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 321 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 322 BIT(packet_id)), 100); 323 if (ret) 324 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 325} 326 327static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 328{ 329 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 330 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 331 struct drm_connector *connector = &vc4_hdmi->connector; 332 struct drm_connector_state *cstate = connector->state; 333 struct drm_crtc *crtc = encoder->crtc; 334 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 335 union hdmi_infoframe frame; 336 int ret; 337 338 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 339 connector, mode); 340 if (ret < 0) { 341 DRM_ERROR("couldn't fill AVI infoframe\n"); 342 return; 343 } 344 345 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 346 connector, mode, 347 vc4_encoder->limited_rgb_range ? 348 HDMI_QUANTIZATION_RANGE_LIMITED : 349 HDMI_QUANTIZATION_RANGE_FULL); 350 351 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 352 353 vc4_hdmi_write_infoframe(encoder, &frame); 354} 355 356static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 357{ 358 union hdmi_infoframe frame; 359 int ret; 360 361 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 362 if (ret < 0) { 363 DRM_ERROR("couldn't fill SPD infoframe\n"); 364 return; 365 } 366 367 frame.spd.sdi = HDMI_SPD_SDI_PC; 368 369 vc4_hdmi_write_infoframe(encoder, &frame); 370} 371 372static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 373{ 374 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 375 union hdmi_infoframe frame; 376 int ret; 377 378 ret = hdmi_audio_infoframe_init(&frame.audio); 379 380 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 381 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 382 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 383 frame.audio.channels = vc4_hdmi->audio.channels; 384 385 vc4_hdmi_write_infoframe(encoder, &frame); 386} 387 388static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 389{ 390 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 391 392 vc4_hdmi_set_avi_infoframe(encoder); 393 vc4_hdmi_set_spd_infoframe(encoder); 394 /* 395 * If audio was streaming, then we need to reenabled the audio 396 * infoframe here during encoder_enable. 397 */ 398 if (vc4_hdmi->audio.streaming) 399 vc4_hdmi_set_audio_infoframe(encoder); 400} 401 402static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder) 403{ 404 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 405 406 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 407 408 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 409 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC); 410 411 HDMI_WRITE(HDMI_VID_CTL, 412 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 413} 414 415static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder) 416{ 417 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 418 int ret; 419 420 if (vc4_hdmi->variant->phy_disable) 421 vc4_hdmi->variant->phy_disable(vc4_hdmi); 422 423 HDMI_WRITE(HDMI_VID_CTL, 424 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 425 426 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 427 clk_disable_unprepare(vc4_hdmi->pixel_clock); 428 429 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 430 if (ret < 0) 431 DRM_ERROR("Failed to release power domain: %d\n", ret); 432} 433 434static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 435{ 436} 437 438static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 439{ 440 u32 csc_ctl; 441 442 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 443 VC4_HD_CSC_CTL_ORDER); 444 445 if (enable) { 446 /* CEA VICs other than #1 requre limited range RGB 447 * output unless overridden by an AVI infoframe. 448 * Apply a colorspace conversion to squash 0-255 down 449 * to 16-235. The matrix here is: 450 * 451 * [ 0 0 0.8594 16] 452 * [ 0 0.8594 0 16] 453 * [ 0.8594 0 0 16] 454 * [ 0 0 0 1] 455 */ 456 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 457 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 458 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 459 VC4_HD_CSC_CTL_MODE); 460 461 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 462 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 463 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 464 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 465 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 466 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 467 } 468 469 /* The RGB order applies even when CSC is disabled. */ 470 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 471} 472 473static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 474{ 475 u32 csc_ctl; 476 477 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 478 479 if (enable) { 480 /* CEA VICs other than #1 requre limited range RGB 481 * output unless overridden by an AVI infoframe. 482 * Apply a colorspace conversion to squash 0-255 down 483 * to 16-235. The matrix here is: 484 * 485 * [ 0.8594 0 0 16] 486 * [ 0 0.8594 0 16] 487 * [ 0 0 0.8594 16] 488 * [ 0 0 0 1] 489 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 490 */ 491 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 492 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 493 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 494 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 495 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 496 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 497 } else { 498 /* Still use the matrix for full range, but make it unity. 499 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 500 */ 501 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 502 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 503 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 504 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 505 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 506 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 507 } 508 509 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 510} 511 512static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 513 struct drm_display_mode *mode) 514{ 515 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 516 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 517 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 518 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 519 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 520 VC4_HDMI_VERTA_VSP) | 521 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 522 VC4_HDMI_VERTA_VFP) | 523 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 524 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 525 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 526 interlaced, 527 VC4_HDMI_VERTB_VBP)); 528 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 529 VC4_SET_FIELD(mode->crtc_vtotal - 530 mode->crtc_vsync_end, 531 VC4_HDMI_VERTB_VBP)); 532 533 HDMI_WRITE(HDMI_HORZA, 534 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 535 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 536 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 537 VC4_HDMI_HORZA_HAP)); 538 539 HDMI_WRITE(HDMI_HORZB, 540 VC4_SET_FIELD((mode->htotal - 541 mode->hsync_end) * pixel_rep, 542 VC4_HDMI_HORZB_HBP) | 543 VC4_SET_FIELD((mode->hsync_end - 544 mode->hsync_start) * pixel_rep, 545 VC4_HDMI_HORZB_HSP) | 546 VC4_SET_FIELD((mode->hsync_start - 547 mode->hdisplay) * pixel_rep, 548 VC4_HDMI_HORZB_HFP)); 549 550 HDMI_WRITE(HDMI_VERTA0, verta); 551 HDMI_WRITE(HDMI_VERTA1, verta); 552 553 HDMI_WRITE(HDMI_VERTB0, vertb_even); 554 HDMI_WRITE(HDMI_VERTB1, vertb); 555} 556static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 557 struct drm_display_mode *mode) 558{ 559 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 560 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 561 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 562 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 563 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 564 VC5_HDMI_VERTA_VSP) | 565 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 566 VC5_HDMI_VERTA_VFP) | 567 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 568 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 569 VC5_HDMI_VERTB_VSPO) | 570 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 571 interlaced, 572 VC4_HDMI_VERTB_VBP)); 573 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 574 VC4_SET_FIELD(mode->crtc_vtotal - 575 mode->crtc_vsync_end, 576 VC4_HDMI_VERTB_VBP)); 577 578 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 579 HDMI_WRITE(HDMI_HORZA, 580 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 581 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 582 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 583 VC5_HDMI_HORZA_HAP) | 584 VC4_SET_FIELD((mode->hsync_start - 585 mode->hdisplay) * pixel_rep, 586 VC5_HDMI_HORZA_HFP)); 587 588 HDMI_WRITE(HDMI_HORZB, 589 VC4_SET_FIELD((mode->htotal - 590 mode->hsync_end) * pixel_rep, 591 VC5_HDMI_HORZB_HBP) | 592 VC4_SET_FIELD((mode->hsync_end - 593 mode->hsync_start) * pixel_rep, 594 VC5_HDMI_HORZB_HSP)); 595 596 HDMI_WRITE(HDMI_VERTA0, verta); 597 HDMI_WRITE(HDMI_VERTA1, verta); 598 599 HDMI_WRITE(HDMI_VERTB0, vertb_even); 600 HDMI_WRITE(HDMI_VERTB1, vertb); 601 602 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 603} 604 605static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 606{ 607 u32 drift; 608 int ret; 609 610 drift = HDMI_READ(HDMI_FIFO_CTL); 611 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 612 613 HDMI_WRITE(HDMI_FIFO_CTL, 614 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 615 HDMI_WRITE(HDMI_FIFO_CTL, 616 drift | VC4_HDMI_FIFO_CTL_RECENTER); 617 usleep_range(1000, 1100); 618 HDMI_WRITE(HDMI_FIFO_CTL, 619 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 620 HDMI_WRITE(HDMI_FIFO_CTL, 621 drift | VC4_HDMI_FIFO_CTL_RECENTER); 622 623 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 624 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 625 WARN_ONCE(ret, "Timeout waiting for " 626 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 627} 628 629static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder) 630{ 631 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 632 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 633 unsigned long pixel_rate, hsm_rate; 634 int ret; 635 636 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 637 if (ret < 0) { 638 DRM_ERROR("Failed to retain power domain: %d\n", ret); 639 return; 640 } 641 642 pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1); 643 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 644 if (ret) { 645 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 646 return; 647 } 648 649 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 650 if (ret) { 651 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 652 return; 653 } 654 655 /* 656 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 657 * be faster than pixel clock, infinitesimally faster, tested in 658 * simulation. Otherwise, exact value is unimportant for HDMI 659 * operation." This conflicts with bcm2835's vc4 documentation, which 660 * states HSM's clock has to be at least 108% of the pixel clock. 661 * 662 * Real life tests reveal that vc4's firmware statement holds up, and 663 * users are able to use pixel clocks closer to HSM's, namely for 664 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 665 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 666 * 162MHz. 667 * 668 * Additionally, the AXI clock needs to be at least 25% of 669 * pixel clock, but HSM ends up being the limiting factor. 670 */ 671 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 672 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 673 if (ret) { 674 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 675 return; 676 } 677 678 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 679 680 /* 681 * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup 682 * at 300MHz. 683 */ 684 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, 685 (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); 686 if (ret) { 687 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 688 clk_disable_unprepare(vc4_hdmi->pixel_clock); 689 return; 690 } 691 692 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 693 if (ret) { 694 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 695 clk_disable_unprepare(vc4_hdmi->pixel_clock); 696 return; 697 } 698 699 if (vc4_hdmi->variant->phy_init) 700 vc4_hdmi->variant->phy_init(vc4_hdmi, mode); 701 702 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 703 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 704 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 705 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 706 707 if (vc4_hdmi->variant->set_timings) 708 vc4_hdmi->variant->set_timings(vc4_hdmi, mode); 709} 710 711static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder) 712{ 713 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 714 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 715 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 716 717 if (vc4_encoder->hdmi_monitor && 718 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 719 if (vc4_hdmi->variant->csc_setup) 720 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 721 722 vc4_encoder->limited_rgb_range = true; 723 } else { 724 if (vc4_hdmi->variant->csc_setup) 725 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 726 727 vc4_encoder->limited_rgb_range = false; 728 } 729 730 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 731} 732 733static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder) 734{ 735 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 736 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 737 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 738 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 739 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 740 int ret; 741 742 HDMI_WRITE(HDMI_VID_CTL, 743 VC4_HD_VID_CTL_ENABLE | 744 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 745 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 746 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 747 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 748 749 HDMI_WRITE(HDMI_VID_CTL, 750 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 751 752 if (vc4_encoder->hdmi_monitor) { 753 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 754 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 755 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 756 757 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 758 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 759 WARN_ONCE(ret, "Timeout waiting for " 760 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 761 } else { 762 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 763 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 764 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 765 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 766 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 767 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 768 769 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 770 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 771 WARN_ONCE(ret, "Timeout waiting for " 772 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 773 } 774 775 if (vc4_encoder->hdmi_monitor) { 776 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 777 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 778 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 779 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 780 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 781 782 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 783 VC4_HDMI_RAM_PACKET_ENABLE); 784 785 vc4_hdmi_set_infoframes(encoder); 786 } 787 788 vc4_hdmi_recenter_fifo(vc4_hdmi); 789} 790 791static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 792{ 793} 794 795#define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 796#define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 797 798static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 799 struct drm_crtc_state *crtc_state, 800 struct drm_connector_state *conn_state) 801{ 802 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 803 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 804 unsigned long long pixel_rate = mode->clock * 1000; 805 unsigned long long tmds_rate; 806 807 if (vc4_hdmi->variant->unsupported_odd_h_timings && 808 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 809 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 810 (mode->hsync_end % 2) || (mode->htotal % 2))) 811 return -EINVAL; 812 813 /* 814 * The 1440p@60 pixel rate is in the same range than the first 815 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 816 * bandwidth). Slightly lower the frequency to bring it out of 817 * the WiFi range. 818 */ 819 tmds_rate = pixel_rate * 10; 820 if (vc4_hdmi->disable_wifi_frequencies && 821 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 822 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 823 mode->clock = 238560; 824 pixel_rate = mode->clock * 1000; 825 } 826 827 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 828 pixel_rate = pixel_rate * 2; 829 830 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 831 return -EINVAL; 832 833 return 0; 834} 835 836static enum drm_mode_status 837vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 838 const struct drm_display_mode *mode) 839{ 840 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 841 842 if (vc4_hdmi->variant->unsupported_odd_h_timings && 843 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 844 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 845 (mode->hsync_end % 2) || (mode->htotal % 2))) 846 return MODE_H_ILLEGAL; 847 848 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 849 return MODE_CLOCK_HIGH; 850 851 return MODE_OK; 852} 853 854static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 855 .atomic_check = vc4_hdmi_encoder_atomic_check, 856 .mode_valid = vc4_hdmi_encoder_mode_valid, 857 .disable = vc4_hdmi_encoder_disable, 858 .enable = vc4_hdmi_encoder_enable, 859}; 860 861static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 862{ 863 int i; 864 u32 channel_map = 0; 865 866 for (i = 0; i < 8; i++) { 867 if (channel_mask & BIT(i)) 868 channel_map |= i << (3 * i); 869 } 870 return channel_map; 871} 872 873static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 874{ 875 int i; 876 u32 channel_map = 0; 877 878 for (i = 0; i < 8; i++) { 879 if (channel_mask & BIT(i)) 880 channel_map |= i << (4 * i); 881 } 882 return channel_map; 883} 884 885/* HDMI audio codec callbacks */ 886static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi) 887{ 888 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 889 unsigned long n, m; 890 891 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate, 892 VC4_HD_MAI_SMP_N_MASK >> 893 VC4_HD_MAI_SMP_N_SHIFT, 894 (VC4_HD_MAI_SMP_M_MASK >> 895 VC4_HD_MAI_SMP_M_SHIFT) + 1, 896 &n, &m); 897 898 HDMI_WRITE(HDMI_MAI_SMP, 899 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 900 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 901} 902 903static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) 904{ 905 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 906 struct drm_crtc *crtc = encoder->crtc; 907 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 908 u32 samplerate = vc4_hdmi->audio.samplerate; 909 u32 n, cts; 910 u64 tmp; 911 912 n = 128 * samplerate / 1000; 913 tmp = (u64)(mode->clock * 1000) * n; 914 do_div(tmp, 128 * samplerate); 915 cts = tmp; 916 917 HDMI_WRITE(HDMI_CRP_CFG, 918 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 919 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 920 921 /* 922 * We could get slightly more accurate clocks in some cases by 923 * providing a CTS_1 value. The two CTS values are alternated 924 * between based on the period fields 925 */ 926 HDMI_WRITE(HDMI_CTS_0, cts); 927 HDMI_WRITE(HDMI_CTS_1, cts); 928} 929 930static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 931{ 932 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 933 934 return snd_soc_card_get_drvdata(card); 935} 936 937static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 938 struct snd_soc_dai *dai) 939{ 940 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 941 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 942 struct drm_connector *connector = &vc4_hdmi->connector; 943 int ret; 944 945 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream) 946 return -EINVAL; 947 948 vc4_hdmi->audio.substream = substream; 949 950 /* 951 * If the HDMI encoder hasn't probed, or the encoder is 952 * currently in DVI mode, treat the codec dai as missing. 953 */ 954 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 955 VC4_HDMI_RAM_PACKET_ENABLE)) 956 return -ENODEV; 957 958 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld); 959 if (ret) 960 return ret; 961 962 return 0; 963} 964 965static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 966{ 967 return 0; 968} 969 970static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 971{ 972 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 973 struct device *dev = &vc4_hdmi->pdev->dev; 974 int ret; 975 976 vc4_hdmi->audio.streaming = false; 977 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 978 if (ret) 979 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 980 981 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 982 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 983 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 984} 985 986static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 987 struct snd_soc_dai *dai) 988{ 989 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 990 991 if (substream != vc4_hdmi->audio.substream) 992 return; 993 994 vc4_hdmi_audio_reset(vc4_hdmi); 995 996 vc4_hdmi->audio.substream = NULL; 997} 998 999/* HDMI audio codec callbacks */ 1000static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 1001 struct snd_pcm_hw_params *params, 1002 struct snd_soc_dai *dai) 1003{ 1004 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1005 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1006 struct device *dev = &vc4_hdmi->pdev->dev; 1007 u32 audio_packet_config, channel_mask; 1008 u32 channel_map; 1009 1010 if (substream != vc4_hdmi->audio.substream) 1011 return -EINVAL; 1012 1013 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1014 params_rate(params), params_width(params), 1015 params_channels(params)); 1016 1017 vc4_hdmi->audio.channels = params_channels(params); 1018 vc4_hdmi->audio.samplerate = params_rate(params); 1019 1020 HDMI_WRITE(HDMI_MAI_CTL, 1021 VC4_HD_MAI_CTL_RESET | 1022 VC4_HD_MAI_CTL_FLUSH | 1023 VC4_HD_MAI_CTL_DLATE | 1024 VC4_HD_MAI_CTL_ERRORE | 1025 VC4_HD_MAI_CTL_ERRORF); 1026 1027 vc4_hdmi_audio_set_mai_clock(vc4_hdmi); 1028 1029 /* The B frame identifier should match the value used by alsa-lib (8) */ 1030 audio_packet_config = 1031 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1032 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1033 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1034 1035 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0); 1036 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1037 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1038 1039 /* Set the MAI threshold */ 1040 HDMI_WRITE(HDMI_MAI_THR, 1041 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 1042 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 1043 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 1044 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 1045 1046 HDMI_WRITE(HDMI_MAI_CONFIG, 1047 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1048 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1049 1050 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1051 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1052 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1053 vc4_hdmi_set_n_cts(vc4_hdmi); 1054 1055 vc4_hdmi_set_audio_infoframe(encoder); 1056 1057 return 0; 1058} 1059 1060static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 1061 struct snd_soc_dai *dai) 1062{ 1063 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1064 1065 switch (cmd) { 1066 case SNDRV_PCM_TRIGGER_START: 1067 vc4_hdmi->audio.streaming = true; 1068 1069 if (vc4_hdmi->variant->phy_rng_enable) 1070 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1071 1072 HDMI_WRITE(HDMI_MAI_CTL, 1073 VC4_SET_FIELD(vc4_hdmi->audio.channels, 1074 VC4_HD_MAI_CTL_CHNUM) | 1075 VC4_HD_MAI_CTL_WHOLSMP | 1076 VC4_HD_MAI_CTL_CHALIGN | 1077 VC4_HD_MAI_CTL_ENABLE); 1078 break; 1079 case SNDRV_PCM_TRIGGER_STOP: 1080 HDMI_WRITE(HDMI_MAI_CTL, 1081 VC4_HD_MAI_CTL_DLATE | 1082 VC4_HD_MAI_CTL_ERRORE | 1083 VC4_HD_MAI_CTL_ERRORF); 1084 1085 if (vc4_hdmi->variant->phy_rng_disable) 1086 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1087 1088 vc4_hdmi->audio.streaming = false; 1089 1090 break; 1091 default: 1092 break; 1093 } 1094 1095 return 0; 1096} 1097 1098static inline struct vc4_hdmi * 1099snd_component_to_hdmi(struct snd_soc_component *component) 1100{ 1101 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 1102 1103 return snd_soc_card_get_drvdata(card); 1104} 1105 1106static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 1107 struct snd_ctl_elem_info *uinfo) 1108{ 1109 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1110 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1111 struct drm_connector *connector = &vc4_hdmi->connector; 1112 1113 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1114 uinfo->count = sizeof(connector->eld); 1115 1116 return 0; 1117} 1118 1119static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 1120 struct snd_ctl_elem_value *ucontrol) 1121{ 1122 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1123 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1124 struct drm_connector *connector = &vc4_hdmi->connector; 1125 1126 memcpy(ucontrol->value.bytes.data, connector->eld, 1127 sizeof(connector->eld)); 1128 1129 return 0; 1130} 1131 1132static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 1133 { 1134 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1135 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1136 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1137 .name = "ELD", 1138 .info = vc4_hdmi_audio_eld_ctl_info, 1139 .get = vc4_hdmi_audio_eld_ctl_get, 1140 }, 1141}; 1142 1143static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 1144 SND_SOC_DAPM_OUTPUT("TX"), 1145}; 1146 1147static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 1148 { "TX", NULL, "Playback" }, 1149}; 1150 1151static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 1152 .name = "vc4-hdmi-codec-dai-component", 1153 .controls = vc4_hdmi_audio_controls, 1154 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 1155 .dapm_widgets = vc4_hdmi_audio_widgets, 1156 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 1157 .dapm_routes = vc4_hdmi_audio_routes, 1158 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1159 .idle_bias_on = 1, 1160 .use_pmdown_time = 1, 1161 .endianness = 1, 1162 .non_legacy_dai_naming = 1, 1163}; 1164 1165static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1166 .startup = vc4_hdmi_audio_startup, 1167 .shutdown = vc4_hdmi_audio_shutdown, 1168 .hw_params = vc4_hdmi_audio_hw_params, 1169 .set_fmt = vc4_hdmi_audio_set_fmt, 1170 .trigger = vc4_hdmi_audio_trigger, 1171}; 1172 1173static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1174 .name = "vc4-hdmi-hifi", 1175 .playback = { 1176 .stream_name = "Playback", 1177 .channels_min = 2, 1178 .channels_max = 8, 1179 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1180 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1181 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1182 SNDRV_PCM_RATE_192000, 1183 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1184 }, 1185}; 1186 1187static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1188 .name = "vc4-hdmi-cpu-dai-component", 1189}; 1190 1191static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1192{ 1193 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1194 1195 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1196 1197 return 0; 1198} 1199 1200static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1201 .name = "vc4-hdmi-cpu-dai", 1202 .probe = vc4_hdmi_audio_cpu_dai_probe, 1203 .playback = { 1204 .stream_name = "Playback", 1205 .channels_min = 1, 1206 .channels_max = 8, 1207 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1208 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1209 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1210 SNDRV_PCM_RATE_192000, 1211 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1212 }, 1213 .ops = &vc4_hdmi_audio_dai_ops, 1214}; 1215 1216static const struct snd_dmaengine_pcm_config pcm_conf = { 1217 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1218 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1219}; 1220 1221static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1222{ 1223 const struct vc4_hdmi_register *mai_data = 1224 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1225 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1226 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1227 struct device *dev = &vc4_hdmi->pdev->dev; 1228 const __be32 *addr; 1229 int index, len; 1230 int ret; 1231 1232 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 1233 dev_warn(dev, 1234 "'dmas' DT property is missing or empty, no HDMI audio\n"); 1235 return 0; 1236 } 1237 1238 if (mai_data->reg != VC4_HD) { 1239 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1240 return -EINVAL; 1241 } 1242 1243 /* 1244 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1245 * the bus address specified in the DT, because the physical address 1246 * (the one returned by platform_get_resource()) is not appropriate 1247 * for DMA transfers. 1248 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1249 */ 1250 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1251 /* Before BCM2711, we don't have a named register range */ 1252 if (index < 0) 1253 index = 1; 1254 1255 addr = of_get_address(dev->of_node, index, NULL, NULL); 1256 1257 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1258 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1259 vc4_hdmi->audio.dma_data.maxburst = 2; 1260 1261 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1262 if (ret) { 1263 dev_err(dev, "Could not register PCM component: %d\n", ret); 1264 return ret; 1265 } 1266 1267 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1268 &vc4_hdmi_audio_cpu_dai_drv, 1); 1269 if (ret) { 1270 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1271 return ret; 1272 } 1273 1274 /* register component and codec dai */ 1275 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1276 &vc4_hdmi_audio_codec_dai_drv, 1); 1277 if (ret) { 1278 dev_err(dev, "Could not register component: %d\n", ret); 1279 return ret; 1280 } 1281 1282 dai_link->cpus = &vc4_hdmi->audio.cpu; 1283 dai_link->codecs = &vc4_hdmi->audio.codec; 1284 dai_link->platforms = &vc4_hdmi->audio.platform; 1285 1286 dai_link->num_cpus = 1; 1287 dai_link->num_codecs = 1; 1288 dai_link->num_platforms = 1; 1289 1290 dai_link->name = "MAI"; 1291 dai_link->stream_name = "MAI PCM"; 1292 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1293 dai_link->cpus->dai_name = dev_name(dev); 1294 dai_link->codecs->name = dev_name(dev); 1295 dai_link->platforms->name = dev_name(dev); 1296 1297 card->dai_link = dai_link; 1298 card->num_links = 1; 1299 card->name = vc4_hdmi->variant->card_name; 1300 card->driver_name = "vc4-hdmi"; 1301 card->dev = dev; 1302 card->owner = THIS_MODULE; 1303 1304 /* 1305 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1306 * stores a pointer to the snd card object in dev->driver_data. This 1307 * means we cannot use it for something else. The hdmi back-pointer is 1308 * now stored in card->drvdata and should be retrieved with 1309 * snd_soc_card_get_drvdata() if needed. 1310 */ 1311 snd_soc_card_set_drvdata(card, vc4_hdmi); 1312 ret = devm_snd_soc_register_card(dev, card); 1313 if (ret) 1314 dev_err(dev, "Could not register sound card: %d\n", ret); 1315 1316 return ret; 1317 1318} 1319 1320#ifdef CONFIG_DRM_VC4_HDMI_CEC 1321static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1322{ 1323 struct vc4_hdmi *vc4_hdmi = priv; 1324 1325 if (vc4_hdmi->cec_irq_was_rx) { 1326 if (vc4_hdmi->cec_rx_msg.len) 1327 cec_received_msg(vc4_hdmi->cec_adap, 1328 &vc4_hdmi->cec_rx_msg); 1329 } else if (vc4_hdmi->cec_tx_ok) { 1330 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1331 0, 0, 0, 0); 1332 } else { 1333 /* 1334 * This CEC implementation makes 1 retry, so if we 1335 * get a NACK, then that means it made 2 attempts. 1336 */ 1337 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1338 0, 2, 0, 0); 1339 } 1340 return IRQ_HANDLED; 1341} 1342 1343static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1344{ 1345 struct drm_device *dev = vc4_hdmi->connector.dev; 1346 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1347 unsigned int i; 1348 1349 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1350 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1351 1352 if (msg->len > 16) { 1353 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1354 return; 1355 } 1356 1357 for (i = 0; i < msg->len; i += 4) { 1358 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1359 1360 msg->msg[i] = val & 0xff; 1361 msg->msg[i + 1] = (val >> 8) & 0xff; 1362 msg->msg[i + 2] = (val >> 16) & 0xff; 1363 msg->msg[i + 3] = (val >> 24) & 0xff; 1364 } 1365} 1366 1367static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1368{ 1369 struct vc4_hdmi *vc4_hdmi = priv; 1370 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1371 u32 cntrl1, cntrl5; 1372 1373 if (!(stat & VC4_HDMI_CPU_CEC)) 1374 return IRQ_NONE; 1375 vc4_hdmi->cec_rx_msg.len = 0; 1376 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1377 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1378 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1379 if (vc4_hdmi->cec_irq_was_rx) { 1380 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1381 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1382 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1383 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1384 } else { 1385 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1386 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1387 } 1388 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1389 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1390 1391 return IRQ_WAKE_THREAD; 1392} 1393 1394static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1395{ 1396 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1397 /* clock period in microseconds */ 1398 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1399 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5); 1400 1401 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1402 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1403 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1404 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1405 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1406 1407 if (enable) { 1408 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1409 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1410 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 1411 HDMI_WRITE(HDMI_CEC_CNTRL_2, 1412 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1413 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1414 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1415 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1416 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1417 HDMI_WRITE(HDMI_CEC_CNTRL_3, 1418 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1419 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1420 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1421 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1422 HDMI_WRITE(HDMI_CEC_CNTRL_4, 1423 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1424 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1425 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1426 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1427 1428 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1429 } else { 1430 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1431 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1432 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1433 } 1434 return 0; 1435} 1436 1437static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1438{ 1439 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1440 1441 HDMI_WRITE(HDMI_CEC_CNTRL_1, 1442 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1443 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1444 return 0; 1445} 1446 1447static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1448 u32 signal_free_time, struct cec_msg *msg) 1449{ 1450 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1451 struct drm_device *dev = vc4_hdmi->connector.dev; 1452 u32 val; 1453 unsigned int i; 1454 1455 if (msg->len > 16) { 1456 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 1457 return -ENOMEM; 1458 } 1459 1460 for (i = 0; i < msg->len; i += 4) 1461 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 1462 (msg->msg[i]) | 1463 (msg->msg[i + 1] << 8) | 1464 (msg->msg[i + 2] << 16) | 1465 (msg->msg[i + 3] << 24)); 1466 1467 val = HDMI_READ(HDMI_CEC_CNTRL_1); 1468 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1469 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1470 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1471 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1472 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1473 1474 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1475 return 0; 1476} 1477 1478static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1479 .adap_enable = vc4_hdmi_cec_adap_enable, 1480 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1481 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1482}; 1483 1484static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1485{ 1486 struct cec_connector_info conn_info; 1487 struct platform_device *pdev = vc4_hdmi->pdev; 1488 u32 value; 1489 int ret; 1490 1491 if (!vc4_hdmi->variant->cec_available) 1492 return 0; 1493 1494 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1495 vc4_hdmi, 1496 vc4_hdmi->variant->card_name, 1497 CEC_CAP_DEFAULTS | 1498 CEC_CAP_CONNECTOR_INFO, 1); 1499 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 1500 if (ret < 0) 1501 return ret; 1502 1503 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 1504 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 1505 1506 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 1507 1508 value = HDMI_READ(HDMI_CEC_CNTRL_1); 1509 /* Set the logical address to Unregistered */ 1510 value |= VC4_HDMI_CEC_ADDR_MASK; 1511 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 1512 1513 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1514 1515 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0), 1516 vc4_cec_irq_handler, 1517 vc4_cec_irq_handler_thread, 0, 1518 "vc4 hdmi cec", vc4_hdmi); 1519 if (ret) 1520 goto err_delete_cec_adap; 1521 1522 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 1523 if (ret < 0) 1524 goto err_delete_cec_adap; 1525 1526 return 0; 1527 1528err_delete_cec_adap: 1529 cec_delete_adapter(vc4_hdmi->cec_adap); 1530 1531 return ret; 1532} 1533 1534static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 1535{ 1536 cec_unregister_adapter(vc4_hdmi->cec_adap); 1537} 1538#else 1539static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1540{ 1541 return 0; 1542} 1543 1544static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 1545 1546#endif 1547 1548static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 1549 struct debugfs_regset32 *regset, 1550 enum vc4_hdmi_regs reg) 1551{ 1552 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1553 struct debugfs_reg32 *regs, *new_regs; 1554 unsigned int count = 0; 1555 unsigned int i; 1556 1557 regs = kcalloc(variant->num_registers, sizeof(*regs), 1558 GFP_KERNEL); 1559 if (!regs) 1560 return -ENOMEM; 1561 1562 for (i = 0; i < variant->num_registers; i++) { 1563 const struct vc4_hdmi_register *field = &variant->registers[i]; 1564 1565 if (field->reg != reg) 1566 continue; 1567 1568 regs[count].name = field->name; 1569 regs[count].offset = field->offset; 1570 count++; 1571 } 1572 1573 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 1574 if (!new_regs) 1575 return -ENOMEM; 1576 1577 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 1578 regset->regs = new_regs; 1579 regset->nregs = count; 1580 1581 return 0; 1582} 1583 1584static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1585{ 1586 struct platform_device *pdev = vc4_hdmi->pdev; 1587 struct device *dev = &pdev->dev; 1588 int ret; 1589 1590 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1591 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 1592 return PTR_ERR(vc4_hdmi->hdmicore_regs); 1593 1594 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1595 if (IS_ERR(vc4_hdmi->hd_regs)) 1596 return PTR_ERR(vc4_hdmi->hd_regs); 1597 1598 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 1599 if (ret) 1600 return ret; 1601 1602 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 1603 if (ret) 1604 return ret; 1605 1606 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1607 if (IS_ERR(vc4_hdmi->pixel_clock)) { 1608 ret = PTR_ERR(vc4_hdmi->pixel_clock); 1609 if (ret != -EPROBE_DEFER) 1610 DRM_ERROR("Failed to get pixel clock\n"); 1611 return ret; 1612 } 1613 1614 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1615 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1616 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1617 return PTR_ERR(vc4_hdmi->hsm_clock); 1618 } 1619 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 1620 1621 return 0; 1622} 1623 1624static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1625{ 1626 struct platform_device *pdev = vc4_hdmi->pdev; 1627 struct device *dev = &pdev->dev; 1628 struct resource *res; 1629 1630 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 1631 if (!res) 1632 return -ENODEV; 1633 1634 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 1635 resource_size(res)); 1636 if (!vc4_hdmi->hdmicore_regs) 1637 return -ENOMEM; 1638 1639 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 1640 if (!res) 1641 return -ENODEV; 1642 1643 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 1644 if (!vc4_hdmi->hd_regs) 1645 return -ENOMEM; 1646 1647 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 1648 if (!res) 1649 return -ENODEV; 1650 1651 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 1652 if (!vc4_hdmi->cec_regs) 1653 return -ENOMEM; 1654 1655 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 1656 if (!res) 1657 return -ENODEV; 1658 1659 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 1660 if (!vc4_hdmi->csc_regs) 1661 return -ENOMEM; 1662 1663 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 1664 if (!res) 1665 return -ENODEV; 1666 1667 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 1668 if (!vc4_hdmi->dvp_regs) 1669 return -ENOMEM; 1670 1671 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 1672 if (!res) 1673 return -ENODEV; 1674 1675 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 1676 if (!vc4_hdmi->phy_regs) 1677 return -ENOMEM; 1678 1679 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 1680 if (!res) 1681 return -ENODEV; 1682 1683 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 1684 if (!vc4_hdmi->ram_regs) 1685 return -ENOMEM; 1686 1687 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 1688 if (!res) 1689 return -ENODEV; 1690 1691 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 1692 if (!vc4_hdmi->rm_regs) 1693 return -ENOMEM; 1694 1695 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1696 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1697 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1698 return PTR_ERR(vc4_hdmi->hsm_clock); 1699 } 1700 1701 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 1702 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 1703 DRM_ERROR("Failed to get pixel bvb clock\n"); 1704 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 1705 } 1706 1707 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 1708 if (IS_ERR(vc4_hdmi->audio_clock)) { 1709 DRM_ERROR("Failed to get audio clock\n"); 1710 return PTR_ERR(vc4_hdmi->audio_clock); 1711 } 1712 1713 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 1714 if (IS_ERR(vc4_hdmi->reset)) { 1715 DRM_ERROR("Failed to get HDMI reset line\n"); 1716 return PTR_ERR(vc4_hdmi->reset); 1717 } 1718 1719 return 0; 1720} 1721 1722#ifdef CONFIG_PM 1723static int vc4_hdmi_runtime_suspend(struct device *dev) 1724{ 1725 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1726 1727 clk_disable_unprepare(vc4_hdmi->hsm_clock); 1728 1729 return 0; 1730} 1731 1732static int vc4_hdmi_runtime_resume(struct device *dev) 1733{ 1734 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1735 int ret; 1736 1737 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 1738 if (ret) 1739 return ret; 1740 1741 return 0; 1742} 1743#endif 1744 1745static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1746{ 1747 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 1748 struct platform_device *pdev = to_platform_device(dev); 1749 struct drm_device *drm = dev_get_drvdata(master); 1750 struct vc4_hdmi *vc4_hdmi; 1751 struct drm_encoder *encoder; 1752 struct device_node *ddc_node; 1753 u32 value; 1754 int ret; 1755 1756 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 1757 if (!vc4_hdmi) 1758 return -ENOMEM; 1759 1760 dev_set_drvdata(dev, vc4_hdmi); 1761 encoder = &vc4_hdmi->encoder.base.base; 1762 vc4_hdmi->encoder.base.type = variant->encoder_type; 1763 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 1764 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 1765 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 1766 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 1767 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 1768 vc4_hdmi->pdev = pdev; 1769 vc4_hdmi->variant = variant; 1770 1771 ret = variant->init_resources(vc4_hdmi); 1772 if (ret) 1773 return ret; 1774 1775 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1776 if (!ddc_node) { 1777 DRM_ERROR("Failed to find ddc node in device tree\n"); 1778 return -ENODEV; 1779 } 1780 1781 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1782 of_node_put(ddc_node); 1783 if (!vc4_hdmi->ddc) { 1784 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1785 return -EPROBE_DEFER; 1786 } 1787 1788 /* Only use the GPIO HPD pin if present in the DT, otherwise 1789 * we'll use the HDMI core's register. 1790 */ 1791 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1792 enum of_gpio_flags hpd_gpio_flags; 1793 1794 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1795 "hpd-gpios", 0, 1796 &hpd_gpio_flags); 1797 if (vc4_hdmi->hpd_gpio < 0) { 1798 ret = vc4_hdmi->hpd_gpio; 1799 goto err_put_ddc; 1800 } 1801 1802 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1803 } 1804 1805 vc4_hdmi->disable_wifi_frequencies = 1806 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 1807 1808 /* 1809 * If we boot without any cable connected to the HDMI connector, 1810 * the firmware will skip the HSM initialization and leave it 1811 * with a rate of 0, resulting in a bus lockup when we're 1812 * accessing the registers even if it's enabled. 1813 * 1814 * Let's put a sensible default at runtime_resume so that we 1815 * don't end up in this situation. 1816 */ 1817 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 1818 if (ret) 1819 goto err_put_ddc; 1820 1821 if (vc4_hdmi->variant->reset) 1822 vc4_hdmi->variant->reset(vc4_hdmi); 1823 1824 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 1825 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 1826 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 1827 clk_prepare_enable(vc4_hdmi->pixel_clock); 1828 clk_prepare_enable(vc4_hdmi->hsm_clock); 1829 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1830 } 1831 1832 pm_runtime_enable(dev); 1833 1834 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 1835 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 1836 1837 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 1838 if (ret) 1839 goto err_destroy_encoder; 1840 1841 ret = vc4_hdmi_cec_init(vc4_hdmi); 1842 if (ret) 1843 goto err_destroy_conn; 1844 1845 ret = vc4_hdmi_audio_init(vc4_hdmi); 1846 if (ret) 1847 goto err_free_cec; 1848 1849 vc4_debugfs_add_file(drm, variant->debugfs_name, 1850 vc4_hdmi_debugfs_regs, 1851 vc4_hdmi); 1852 1853 return 0; 1854 1855err_free_cec: 1856 vc4_hdmi_cec_exit(vc4_hdmi); 1857err_destroy_conn: 1858 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 1859err_destroy_encoder: 1860 drm_encoder_cleanup(encoder); 1861 pm_runtime_disable(dev); 1862err_put_ddc: 1863 put_device(&vc4_hdmi->ddc->dev); 1864 1865 return ret; 1866} 1867 1868static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1869 void *data) 1870{ 1871 struct vc4_hdmi *vc4_hdmi; 1872 1873 /* 1874 * ASoC makes it a bit hard to retrieve a pointer to the 1875 * vc4_hdmi structure. Registering the card will overwrite our 1876 * device drvdata with a pointer to the snd_soc_card structure, 1877 * which can then be used to retrieve whatever drvdata we want 1878 * to associate. 1879 * 1880 * However, that doesn't fly in the case where we wouldn't 1881 * register an ASoC card (because of an old DT that is missing 1882 * the dmas properties for example), then the card isn't 1883 * registered and the device drvdata wouldn't be set. 1884 * 1885 * We can deal with both cases by making sure a snd_soc_card 1886 * pointer and a vc4_hdmi structure are pointing to the same 1887 * memory address, so we can treat them indistinctly without any 1888 * issue. 1889 */ 1890 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 1891 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 1892 vc4_hdmi = dev_get_drvdata(dev); 1893 1894 kfree(vc4_hdmi->hdmi_regset.regs); 1895 kfree(vc4_hdmi->hd_regset.regs); 1896 1897 vc4_hdmi_cec_exit(vc4_hdmi); 1898 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 1899 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 1900 1901 pm_runtime_disable(dev); 1902 1903 put_device(&vc4_hdmi->ddc->dev); 1904} 1905 1906static const struct component_ops vc4_hdmi_ops = { 1907 .bind = vc4_hdmi_bind, 1908 .unbind = vc4_hdmi_unbind, 1909}; 1910 1911static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1912{ 1913 return component_add(&pdev->dev, &vc4_hdmi_ops); 1914} 1915 1916static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1917{ 1918 component_del(&pdev->dev, &vc4_hdmi_ops); 1919 return 0; 1920} 1921 1922static const struct vc4_hdmi_variant bcm2835_variant = { 1923 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 1924 .debugfs_name = "hdmi_regs", 1925 .card_name = "vc4-hdmi", 1926 .max_pixel_clock = 162000000, 1927 .cec_available = true, 1928 .registers = vc4_hdmi_fields, 1929 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 1930 1931 .init_resources = vc4_hdmi_init_resources, 1932 .csc_setup = vc4_hdmi_csc_setup, 1933 .reset = vc4_hdmi_reset, 1934 .set_timings = vc4_hdmi_set_timings, 1935 .phy_init = vc4_hdmi_phy_init, 1936 .phy_disable = vc4_hdmi_phy_disable, 1937 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 1938 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 1939 .channel_map = vc4_hdmi_channel_map, 1940}; 1941 1942static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 1943 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 1944 .debugfs_name = "hdmi0_regs", 1945 .card_name = "vc4-hdmi-0", 1946 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 1947 .registers = vc5_hdmi_hdmi0_fields, 1948 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 1949 .phy_lane_mapping = { 1950 PHY_LANE_0, 1951 PHY_LANE_1, 1952 PHY_LANE_2, 1953 PHY_LANE_CK, 1954 }, 1955 .unsupported_odd_h_timings = true, 1956 1957 .init_resources = vc5_hdmi_init_resources, 1958 .csc_setup = vc5_hdmi_csc_setup, 1959 .reset = vc5_hdmi_reset, 1960 .set_timings = vc5_hdmi_set_timings, 1961 .phy_init = vc5_hdmi_phy_init, 1962 .phy_disable = vc5_hdmi_phy_disable, 1963 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 1964 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 1965 .channel_map = vc5_hdmi_channel_map, 1966}; 1967 1968static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 1969 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 1970 .debugfs_name = "hdmi1_regs", 1971 .card_name = "vc4-hdmi-1", 1972 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 1973 .registers = vc5_hdmi_hdmi1_fields, 1974 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 1975 .phy_lane_mapping = { 1976 PHY_LANE_1, 1977 PHY_LANE_0, 1978 PHY_LANE_CK, 1979 PHY_LANE_2, 1980 }, 1981 .unsupported_odd_h_timings = true, 1982 1983 .init_resources = vc5_hdmi_init_resources, 1984 .csc_setup = vc5_hdmi_csc_setup, 1985 .reset = vc5_hdmi_reset, 1986 .set_timings = vc5_hdmi_set_timings, 1987 .phy_init = vc5_hdmi_phy_init, 1988 .phy_disable = vc5_hdmi_phy_disable, 1989 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 1990 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 1991 .channel_map = vc5_hdmi_channel_map, 1992}; 1993 1994static const struct of_device_id vc4_hdmi_dt_match[] = { 1995 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 1996 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 1997 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 1998 {} 1999}; 2000 2001static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2002 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2003 vc4_hdmi_runtime_resume, 2004 NULL) 2005}; 2006 2007struct platform_driver vc4_hdmi_driver = { 2008 .probe = vc4_hdmi_dev_probe, 2009 .remove = vc4_hdmi_dev_remove, 2010 .driver = { 2011 .name = "vc4_hdmi", 2012 .of_match_table = vc4_hdmi_dt_match, 2013 .pm = &vc4_hdmi_pm_ops, 2014 }, 2015}; 2016