1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (C) 2015 Broadcom 4 */ 5#ifndef _VC4_DRV_H_ 6#define _VC4_DRV_H_ 7 8#include <linux/delay.h> 9#include <linux/refcount.h> 10#include <linux/uaccess.h> 11 12#include <drm/drm_atomic.h> 13#include <drm/drm_debugfs.h> 14#include <drm/drm_device.h> 15#include <drm/drm_encoder.h> 16#include <drm/drm_gem_cma_helper.h> 17#include <drm/drm_managed.h> 18#include <drm/drm_mm.h> 19#include <drm/drm_modeset_lock.h> 20 21#include "uapi/drm/vc4_drm.h" 22 23struct drm_device; 24struct drm_gem_object; 25 26/* Don't forget to update vc4_bo.c: bo_type_names[] when adding to 27 * this. 28 */ 29enum vc4_kernel_bo_type { 30 /* Any kernel allocation (gem_create_object hook) before it 31 * gets another type set. 32 */ 33 VC4_BO_TYPE_KERNEL, 34 VC4_BO_TYPE_V3D, 35 VC4_BO_TYPE_V3D_SHADER, 36 VC4_BO_TYPE_DUMB, 37 VC4_BO_TYPE_BIN, 38 VC4_BO_TYPE_RCL, 39 VC4_BO_TYPE_BCL, 40 VC4_BO_TYPE_KERNEL_CACHE, 41 VC4_BO_TYPE_COUNT 42}; 43 44/* Performance monitor object. The perform lifetime is controlled by userspace 45 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 46 * request, and when this is the case, HW perf counters will be activated just 47 * before the submit_cl is submitted to the GPU and disabled when the job is 48 * done. This way, only events related to a specific job will be counted. 49 */ 50struct vc4_perfmon { 51 /* Tracks the number of users of the perfmon, when this counter reaches 52 * zero the perfmon is destroyed. 53 */ 54 refcount_t refcnt; 55 56 /* Number of counters activated in this perfmon instance 57 * (should be less than DRM_VC4_MAX_PERF_COUNTERS). 58 */ 59 u8 ncounters; 60 61 /* Events counted by the HW perf counters. */ 62 u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 63 64 /* Storage for counter values. Counters are incremented by the HW 65 * perf counter values every time the perfmon is attached to a GPU job. 66 * This way, perfmon users don't have to retrieve the results after 67 * each job if they want to track events covering several submissions. 68 * Note that counter values can't be reset, but you can fake a reset by 69 * destroying the perfmon and creating a new one. 70 */ 71 u64 counters[]; 72}; 73 74struct vc4_dev { 75 struct drm_device base; 76 77 struct vc4_hvs *hvs; 78 struct vc4_v3d *v3d; 79 struct vc4_dpi *dpi; 80 struct vc4_vec *vec; 81 struct vc4_txp *txp; 82 83 struct vc4_hang_state *hang_state; 84 85 /* The kernel-space BO cache. Tracks buffers that have been 86 * unreferenced by all other users (refcounts of 0!) but not 87 * yet freed, so we can do cheap allocations. 88 */ 89 struct vc4_bo_cache { 90 /* Array of list heads for entries in the BO cache, 91 * based on number of pages, so we can do O(1) lookups 92 * in the cache when allocating. 93 */ 94 struct list_head *size_list; 95 uint32_t size_list_size; 96 97 /* List of all BOs in the cache, ordered by age, so we 98 * can do O(1) lookups when trying to free old 99 * buffers. 100 */ 101 struct list_head time_list; 102 struct work_struct time_work; 103 struct timer_list time_timer; 104 } bo_cache; 105 106 u32 num_labels; 107 struct vc4_label { 108 const char *name; 109 u32 num_allocated; 110 u32 size_allocated; 111 } *bo_labels; 112 113 /* Protects bo_cache and bo_labels. */ 114 struct mutex bo_lock; 115 116 /* Purgeable BO pool. All BOs in this pool can have their memory 117 * reclaimed if the driver is unable to allocate new BOs. We also 118 * keep stats related to the purge mechanism here. 119 */ 120 struct { 121 struct list_head list; 122 unsigned int num; 123 size_t size; 124 unsigned int purged_num; 125 size_t purged_size; 126 struct mutex lock; 127 } purgeable; 128 129 uint64_t dma_fence_context; 130 131 /* Sequence number for the last job queued in bin_job_list. 132 * Starts at 0 (no jobs emitted). 133 */ 134 uint64_t emit_seqno; 135 136 /* Sequence number for the last completed job on the GPU. 137 * Starts at 0 (no jobs completed). 138 */ 139 uint64_t finished_seqno; 140 141 /* List of all struct vc4_exec_info for jobs to be executed in 142 * the binner. The first job in the list is the one currently 143 * programmed into ct0ca for execution. 144 */ 145 struct list_head bin_job_list; 146 147 /* List of all struct vc4_exec_info for jobs that have 148 * completed binning and are ready for rendering. The first 149 * job in the list is the one currently programmed into ct1ca 150 * for execution. 151 */ 152 struct list_head render_job_list; 153 154 /* List of the finished vc4_exec_infos waiting to be freed by 155 * job_done_work. 156 */ 157 struct list_head job_done_list; 158 /* Spinlock used to synchronize the job_list and seqno 159 * accesses between the IRQ handler and GEM ioctls. 160 */ 161 spinlock_t job_lock; 162 wait_queue_head_t job_wait_queue; 163 struct work_struct job_done_work; 164 165 /* Used to track the active perfmon if any. Access to this field is 166 * protected by job_lock. 167 */ 168 struct vc4_perfmon *active_perfmon; 169 170 /* List of struct vc4_seqno_cb for callbacks to be made from a 171 * workqueue when the given seqno is passed. 172 */ 173 struct list_head seqno_cb_list; 174 175 /* The memory used for storing binner tile alloc, tile state, 176 * and overflow memory allocations. This is freed when V3D 177 * powers down. 178 */ 179 struct vc4_bo *bin_bo; 180 181 /* Size of blocks allocated within bin_bo. */ 182 uint32_t bin_alloc_size; 183 184 /* Bitmask of the bin_alloc_size chunks in bin_bo that are 185 * used. 186 */ 187 uint32_t bin_alloc_used; 188 189 /* Bitmask of the current bin_alloc used for overflow memory. */ 190 uint32_t bin_alloc_overflow; 191 192 /* Incremented when an underrun error happened after an atomic commit. 193 * This is particularly useful to detect when a specific modeset is too 194 * demanding in term of memory or HVS bandwidth which is hard to guess 195 * at atomic check time. 196 */ 197 atomic_t underrun; 198 199 struct work_struct overflow_mem_work; 200 201 int power_refcount; 202 203 /* Set to true when the load tracker is supported. */ 204 bool load_tracker_available; 205 206 /* Set to true when the load tracker is active. */ 207 bool load_tracker_enabled; 208 209 /* Mutex controlling the power refcount. */ 210 struct mutex power_lock; 211 212 struct { 213 struct timer_list timer; 214 struct work_struct reset_work; 215 } hangcheck; 216 217 struct semaphore async_modeset; 218 219 struct drm_modeset_lock ctm_state_lock; 220 struct drm_private_obj ctm_manager; 221 struct drm_private_obj hvs_channels; 222 struct drm_private_obj load_tracker; 223 224 /* List of vc4_debugfs_info_entry for adding to debugfs once 225 * the minor is available (after drm_dev_register()). 226 */ 227 struct list_head debugfs_list; 228 229 /* Mutex for binner bo allocation. */ 230 struct mutex bin_bo_lock; 231 /* Reference count for our binner bo. */ 232 struct kref bin_bo_kref; 233}; 234 235static inline struct vc4_dev * 236to_vc4_dev(struct drm_device *dev) 237{ 238 return container_of(dev, struct vc4_dev, base); 239} 240 241struct vc4_bo { 242 struct drm_gem_cma_object base; 243 244 /* seqno of the last job to render using this BO. */ 245 uint64_t seqno; 246 247 /* seqno of the last job to use the RCL to write to this BO. 248 * 249 * Note that this doesn't include binner overflow memory 250 * writes. 251 */ 252 uint64_t write_seqno; 253 254 bool t_format; 255 256 /* List entry for the BO's position in either 257 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 258 */ 259 struct list_head unref_head; 260 261 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 262 unsigned long free_time; 263 264 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 265 struct list_head size_head; 266 267 /* Struct for shader validation state, if created by 268 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 269 */ 270 struct vc4_validated_shader_info *validated_shader; 271 272 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i 273 * for user-allocated labels. 274 */ 275 int label; 276 277 /* Count the number of active users. This is needed to determine 278 * whether we can move the BO to the purgeable list or not (when the BO 279 * is used by the GPU or the display engine we can't purge it). 280 */ 281 refcount_t usecnt; 282 283 /* Store purgeable/purged state here */ 284 u32 madv; 285 struct mutex madv_lock; 286}; 287 288static inline struct vc4_bo * 289to_vc4_bo(struct drm_gem_object *bo) 290{ 291 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base); 292} 293 294struct vc4_fence { 295 struct dma_fence base; 296 struct drm_device *dev; 297 /* vc4 seqno for signaled() test */ 298 uint64_t seqno; 299}; 300 301static inline struct vc4_fence * 302to_vc4_fence(struct dma_fence *fence) 303{ 304 return container_of(fence, struct vc4_fence, base); 305} 306 307struct vc4_seqno_cb { 308 struct work_struct work; 309 uint64_t seqno; 310 void (*func)(struct vc4_seqno_cb *cb); 311}; 312 313struct vc4_v3d { 314 struct vc4_dev *vc4; 315 struct platform_device *pdev; 316 void __iomem *regs; 317 struct clk *clk; 318 struct debugfs_regset32 regset; 319}; 320 321struct vc4_hvs { 322 struct platform_device *pdev; 323 void __iomem *regs; 324 u32 __iomem *dlist; 325 326 struct clk *core_clk; 327 328 /* Memory manager for CRTCs to allocate space in the display 329 * list. Units are dwords. 330 */ 331 struct drm_mm dlist_mm; 332 /* Memory manager for the LBM memory used by HVS scaling. */ 333 struct drm_mm lbm_mm; 334 spinlock_t mm_lock; 335 336 struct drm_mm_node mitchell_netravali_filter; 337 338 struct debugfs_regset32 regset; 339 340 /* HVS version 5 flag, therefore requires updated dlist structures */ 341 bool hvs5; 342}; 343 344struct vc4_plane { 345 struct drm_plane base; 346}; 347 348static inline struct vc4_plane * 349to_vc4_plane(struct drm_plane *plane) 350{ 351 return container_of(plane, struct vc4_plane, base); 352} 353 354enum vc4_scaling_mode { 355 VC4_SCALING_NONE, 356 VC4_SCALING_TPZ, 357 VC4_SCALING_PPF, 358}; 359 360struct vc4_plane_state { 361 struct drm_plane_state base; 362 /* System memory copy of the display list for this element, computed 363 * at atomic_check time. 364 */ 365 u32 *dlist; 366 u32 dlist_size; /* Number of dwords allocated for the display list */ 367 u32 dlist_count; /* Number of used dwords in the display list. */ 368 369 /* Offset in the dlist to various words, for pageflip or 370 * cursor updates. 371 */ 372 u32 pos0_offset; 373 u32 pos2_offset; 374 u32 ptr0_offset; 375 u32 lbm_offset; 376 377 /* Offset where the plane's dlist was last stored in the 378 * hardware at vc4_crtc_atomic_flush() time. 379 */ 380 u32 __iomem *hw_dlist; 381 382 /* Clipped coordinates of the plane on the display. */ 383 int crtc_x, crtc_y, crtc_w, crtc_h; 384 /* Clipped area being scanned from in the FB. */ 385 u32 src_x, src_y; 386 387 u32 src_w[2], src_h[2]; 388 389 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */ 390 enum vc4_scaling_mode x_scaling[2], y_scaling[2]; 391 bool is_unity; 392 bool is_yuv; 393 394 /* Offset to start scanning out from the start of the plane's 395 * BO. 396 */ 397 u32 offsets[3]; 398 399 /* Our allocation in LBM for temporary storage during scaling. */ 400 struct drm_mm_node lbm; 401 402 /* Set when the plane has per-pixel alpha content or does not cover 403 * the entire screen. This is a hint to the CRTC that it might need 404 * to enable background color fill. 405 */ 406 bool needs_bg_fill; 407 408 /* Mark the dlist as initialized. Useful to avoid initializing it twice 409 * when async update is not possible. 410 */ 411 bool dlist_initialized; 412 413 /* Load of this plane on the HVS block. The load is expressed in HVS 414 * cycles/sec. 415 */ 416 u64 hvs_load; 417 418 /* Memory bandwidth needed for this plane. This is expressed in 419 * bytes/sec. 420 */ 421 u64 membus_load; 422}; 423 424static inline struct vc4_plane_state * 425to_vc4_plane_state(struct drm_plane_state *state) 426{ 427 return container_of(state, struct vc4_plane_state, base); 428} 429 430enum vc4_encoder_type { 431 VC4_ENCODER_TYPE_NONE, 432 VC4_ENCODER_TYPE_HDMI0, 433 VC4_ENCODER_TYPE_HDMI1, 434 VC4_ENCODER_TYPE_VEC, 435 VC4_ENCODER_TYPE_DSI0, 436 VC4_ENCODER_TYPE_DSI1, 437 VC4_ENCODER_TYPE_SMI, 438 VC4_ENCODER_TYPE_DPI, 439}; 440 441struct vc4_encoder { 442 struct drm_encoder base; 443 enum vc4_encoder_type type; 444 u32 clock_select; 445 446 void (*pre_crtc_configure)(struct drm_encoder *encoder); 447 void (*pre_crtc_enable)(struct drm_encoder *encoder); 448 void (*post_crtc_enable)(struct drm_encoder *encoder); 449 450 void (*post_crtc_disable)(struct drm_encoder *encoder); 451 void (*post_crtc_powerdown)(struct drm_encoder *encoder); 452}; 453 454static inline struct vc4_encoder * 455to_vc4_encoder(struct drm_encoder *encoder) 456{ 457 return container_of(encoder, struct vc4_encoder, base); 458} 459 460struct vc4_crtc_data { 461 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */ 462 unsigned int hvs_available_channels; 463 464 /* Which output of the HVS this pixelvalve sources from. */ 465 int hvs_output; 466}; 467 468struct vc4_pv_data { 469 struct vc4_crtc_data base; 470 471 /* Depth of the PixelValve FIFO in bytes */ 472 unsigned int fifo_depth; 473 474 /* Number of pixels output per clock period */ 475 u8 pixels_per_clock; 476 477 enum vc4_encoder_type encoder_types[4]; 478 const char *debugfs_name; 479 480}; 481 482struct vc4_crtc { 483 struct drm_crtc base; 484 struct platform_device *pdev; 485 const struct vc4_crtc_data *data; 486 void __iomem *regs; 487 488 /* Timestamp at start of vblank irq - unaffected by lock delays. */ 489 ktime_t t_vblank; 490 491 u8 lut_r[256]; 492 u8 lut_g[256]; 493 u8 lut_b[256]; 494 495 struct drm_pending_vblank_event *event; 496 497 struct debugfs_regset32 regset; 498}; 499 500static inline struct vc4_crtc * 501to_vc4_crtc(struct drm_crtc *crtc) 502{ 503 return container_of(crtc, struct vc4_crtc, base); 504} 505 506static inline const struct vc4_crtc_data * 507vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc) 508{ 509 return crtc->data; 510} 511 512static inline const struct vc4_pv_data * 513vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc) 514{ 515 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc); 516 517 return container_of(data, struct vc4_pv_data, base); 518} 519 520struct vc4_crtc_state { 521 struct drm_crtc_state base; 522 /* Dlist area for this CRTC configuration. */ 523 struct drm_mm_node mm; 524 bool feed_txp; 525 bool txp_armed; 526 unsigned int assigned_channel; 527 528 struct { 529 unsigned int left; 530 unsigned int right; 531 unsigned int top; 532 unsigned int bottom; 533 } margins; 534 535 /* Transitional state below, only valid during atomic commits */ 536 bool update_muxing; 537}; 538 539#define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1) 540 541static inline struct vc4_crtc_state * 542to_vc4_crtc_state(struct drm_crtc_state *crtc_state) 543{ 544 return container_of(crtc_state, struct vc4_crtc_state, base); 545} 546 547#define V3D_READ(offset) readl(vc4->v3d->regs + offset) 548#define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 549#define HVS_READ(offset) readl(vc4->hvs->regs + offset) 550#define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 551 552#define VC4_REG32(reg) { .name = #reg, .offset = reg } 553 554struct vc4_exec_info { 555 /* Sequence number for this bin/render job. */ 556 uint64_t seqno; 557 558 /* Latest write_seqno of any BO that binning depends on. */ 559 uint64_t bin_dep_seqno; 560 561 struct dma_fence *fence; 562 563 /* Last current addresses the hardware was processing when the 564 * hangcheck timer checked on us. 565 */ 566 uint32_t last_ct0ca, last_ct1ca; 567 568 /* Kernel-space copy of the ioctl arguments */ 569 struct drm_vc4_submit_cl *args; 570 571 /* This is the array of BOs that were looked up at the start of exec. 572 * Command validation will use indices into this array. 573 */ 574 struct drm_gem_cma_object **bo; 575 uint32_t bo_count; 576 577 /* List of BOs that are being written by the RCL. Other than 578 * the binner temporary storage, this is all the BOs written 579 * by the job. 580 */ 581 struct drm_gem_cma_object *rcl_write_bo[4]; 582 uint32_t rcl_write_bo_count; 583 584 /* Pointers for our position in vc4->job_list */ 585 struct list_head head; 586 587 /* List of other BOs used in the job that need to be released 588 * once the job is complete. 589 */ 590 struct list_head unref_list; 591 592 /* Current unvalidated indices into @bo loaded by the non-hardware 593 * VC4_PACKET_GEM_HANDLES. 594 */ 595 uint32_t bo_index[2]; 596 597 /* This is the BO where we store the validated command lists, shader 598 * records, and uniforms. 599 */ 600 struct drm_gem_cma_object *exec_bo; 601 602 /** 603 * This tracks the per-shader-record state (packet 64) that 604 * determines the length of the shader record and the offset 605 * it's expected to be found at. It gets read in from the 606 * command lists. 607 */ 608 struct vc4_shader_state { 609 uint32_t addr; 610 /* Maximum vertex index referenced by any primitive using this 611 * shader state. 612 */ 613 uint32_t max_index; 614 } *shader_state; 615 616 /** How many shader states the user declared they were using. */ 617 uint32_t shader_state_size; 618 /** How many shader state records the validator has seen. */ 619 uint32_t shader_state_count; 620 621 bool found_tile_binning_mode_config_packet; 622 bool found_start_tile_binning_packet; 623 bool found_increment_semaphore_packet; 624 bool found_flush; 625 uint8_t bin_tiles_x, bin_tiles_y; 626 /* Physical address of the start of the tile alloc array 627 * (where each tile's binned CL will start) 628 */ 629 uint32_t tile_alloc_offset; 630 /* Bitmask of which binner slots are freed when this job completes. */ 631 uint32_t bin_slots; 632 633 /** 634 * Computed addresses pointing into exec_bo where we start the 635 * bin thread (ct0) and render thread (ct1). 636 */ 637 uint32_t ct0ca, ct0ea; 638 uint32_t ct1ca, ct1ea; 639 640 /* Pointer to the unvalidated bin CL (if present). */ 641 void *bin_u; 642 643 /* Pointers to the shader recs. These paddr gets incremented as CL 644 * packets are relocated in validate_gl_shader_state, and the vaddrs 645 * (u and v) get incremented and size decremented as the shader recs 646 * themselves are validated. 647 */ 648 void *shader_rec_u; 649 void *shader_rec_v; 650 uint32_t shader_rec_p; 651 uint32_t shader_rec_size; 652 653 /* Pointers to the uniform data. These pointers are incremented, and 654 * size decremented, as each batch of uniforms is uploaded. 655 */ 656 void *uniforms_u; 657 void *uniforms_v; 658 uint32_t uniforms_p; 659 uint32_t uniforms_size; 660 661 /* Pointer to a performance monitor object if the user requested it, 662 * NULL otherwise. 663 */ 664 struct vc4_perfmon *perfmon; 665 666 /* Whether the exec has taken a reference to the binner BO, which should 667 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet. 668 */ 669 bool bin_bo_used; 670}; 671 672/* Per-open file private data. Any driver-specific resource that has to be 673 * released when the DRM file is closed should be placed here. 674 */ 675struct vc4_file { 676 struct { 677 struct idr idr; 678 struct mutex lock; 679 } perfmon; 680 681 bool bin_bo_used; 682}; 683 684static inline struct vc4_exec_info * 685vc4_first_bin_job(struct vc4_dev *vc4) 686{ 687 return list_first_entry_or_null(&vc4->bin_job_list, 688 struct vc4_exec_info, head); 689} 690 691static inline struct vc4_exec_info * 692vc4_first_render_job(struct vc4_dev *vc4) 693{ 694 return list_first_entry_or_null(&vc4->render_job_list, 695 struct vc4_exec_info, head); 696} 697 698static inline struct vc4_exec_info * 699vc4_last_render_job(struct vc4_dev *vc4) 700{ 701 if (list_empty(&vc4->render_job_list)) 702 return NULL; 703 return list_last_entry(&vc4->render_job_list, 704 struct vc4_exec_info, head); 705} 706 707/** 708 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 709 * setup parameters. 710 * 711 * This will be used at draw time to relocate the reference to the texture 712 * contents in p0, and validate that the offset combined with 713 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 714 * Note that the hardware treats unprovided config parameters as 0, so not all 715 * of them need to be set up for every texure sample, and we'll store ~0 as 716 * the offset to mark the unused ones. 717 * 718 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 719 * Setup") for definitions of the texture parameters. 720 */ 721struct vc4_texture_sample_info { 722 bool is_direct; 723 uint32_t p_offset[4]; 724}; 725 726/** 727 * struct vc4_validated_shader_info - information about validated shaders that 728 * needs to be used from command list validation. 729 * 730 * For a given shader, each time a shader state record references it, we need 731 * to verify that the shader doesn't read more uniforms than the shader state 732 * record's uniform BO pointer can provide, and we need to apply relocations 733 * and validate the shader state record's uniforms that define the texture 734 * samples. 735 */ 736struct vc4_validated_shader_info { 737 uint32_t uniforms_size; 738 uint32_t uniforms_src_size; 739 uint32_t num_texture_samples; 740 struct vc4_texture_sample_info *texture_samples; 741 742 uint32_t num_uniform_addr_offsets; 743 uint32_t *uniform_addr_offsets; 744 745 bool is_threaded; 746}; 747 748/** 749 * __wait_for - magic wait macro 750 * 751 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 752 * important that we check the condition again after having timed out, since the 753 * timeout could be due to preemption or similar and we've never had a chance to 754 * check the condition before the timeout. 755 */ 756#define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 757 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 758 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 759 int ret__; \ 760 might_sleep(); \ 761 for (;;) { \ 762 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 763 OP; \ 764 /* Guarantee COND check prior to timeout */ \ 765 barrier(); \ 766 if (COND) { \ 767 ret__ = 0; \ 768 break; \ 769 } \ 770 if (expired__) { \ 771 ret__ = -ETIMEDOUT; \ 772 break; \ 773 } \ 774 usleep_range(wait__, wait__ * 2); \ 775 if (wait__ < (Wmax)) \ 776 wait__ <<= 1; \ 777 } \ 778 ret__; \ 779}) 780 781#define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 782 (Wmax)) 783#define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 784 785/* vc4_bo.c */ 786struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 787void vc4_free_object(struct drm_gem_object *gem_obj); 788struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 789 bool from_cache, enum vc4_kernel_bo_type type); 790int vc4_dumb_create(struct drm_file *file_priv, 791 struct drm_device *dev, 792 struct drm_mode_create_dumb *args); 793struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags); 794int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 795 struct drm_file *file_priv); 796int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 797 struct drm_file *file_priv); 798int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 799 struct drm_file *file_priv); 800int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, 801 struct drm_file *file_priv); 802int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, 803 struct drm_file *file_priv); 804int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 805 struct drm_file *file_priv); 806int vc4_label_bo_ioctl(struct drm_device *dev, void *data, 807 struct drm_file *file_priv); 808vm_fault_t vc4_fault(struct vm_fault *vmf); 809int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 810int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 811struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev, 812 struct dma_buf_attachment *attach, 813 struct sg_table *sgt); 814void *vc4_prime_vmap(struct drm_gem_object *obj); 815int vc4_bo_cache_init(struct drm_device *dev); 816int vc4_bo_inc_usecnt(struct vc4_bo *bo); 817void vc4_bo_dec_usecnt(struct vc4_bo *bo); 818void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo); 819void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo); 820 821/* vc4_crtc.c */ 822extern struct platform_driver vc4_crtc_driver; 823int vc4_crtc_disable_at_boot(struct drm_crtc *crtc); 824int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 825 const struct drm_crtc_funcs *crtc_funcs, 826 const struct drm_crtc_helper_funcs *crtc_helper_funcs); 827void vc4_crtc_destroy(struct drm_crtc *crtc); 828int vc4_page_flip(struct drm_crtc *crtc, 829 struct drm_framebuffer *fb, 830 struct drm_pending_vblank_event *event, 831 uint32_t flags, 832 struct drm_modeset_acquire_ctx *ctx); 833struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc); 834void vc4_crtc_destroy_state(struct drm_crtc *crtc, 835 struct drm_crtc_state *state); 836void vc4_crtc_reset(struct drm_crtc *crtc); 837void vc4_crtc_handle_vblank(struct vc4_crtc *crtc); 838void vc4_crtc_get_margins(struct drm_crtc_state *state, 839 unsigned int *left, unsigned int *right, 840 unsigned int *top, unsigned int *bottom); 841 842/* vc4_debugfs.c */ 843void vc4_debugfs_init(struct drm_minor *minor); 844#ifdef CONFIG_DEBUG_FS 845void vc4_debugfs_add_file(struct drm_device *drm, 846 const char *filename, 847 int (*show)(struct seq_file*, void*), 848 void *data); 849void vc4_debugfs_add_regset32(struct drm_device *drm, 850 const char *filename, 851 struct debugfs_regset32 *regset); 852#else 853static inline void vc4_debugfs_add_file(struct drm_device *drm, 854 const char *filename, 855 int (*show)(struct seq_file*, void*), 856 void *data) 857{ 858} 859 860static inline void vc4_debugfs_add_regset32(struct drm_device *drm, 861 const char *filename, 862 struct debugfs_regset32 *regset) 863{ 864} 865#endif 866 867/* vc4_drv.c */ 868void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 869 870/* vc4_dpi.c */ 871extern struct platform_driver vc4_dpi_driver; 872 873/* vc4_dsi.c */ 874extern struct platform_driver vc4_dsi_driver; 875 876/* vc4_fence.c */ 877extern const struct dma_fence_ops vc4_fence_ops; 878 879/* vc4_gem.c */ 880int vc4_gem_init(struct drm_device *dev); 881int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 882 struct drm_file *file_priv); 883int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 884 struct drm_file *file_priv); 885int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 886 struct drm_file *file_priv); 887void vc4_submit_next_bin_job(struct drm_device *dev); 888void vc4_submit_next_render_job(struct drm_device *dev); 889void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 890int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 891 uint64_t timeout_ns, bool interruptible); 892void vc4_job_handle_completed(struct vc4_dev *vc4); 893int vc4_queue_seqno_cb(struct drm_device *dev, 894 struct vc4_seqno_cb *cb, uint64_t seqno, 895 void (*func)(struct vc4_seqno_cb *cb)); 896int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data, 897 struct drm_file *file_priv); 898 899/* vc4_hdmi.c */ 900extern struct platform_driver vc4_hdmi_driver; 901 902/* vc4_vec.c */ 903extern struct platform_driver vc4_vec_driver; 904 905/* vc4_txp.c */ 906extern struct platform_driver vc4_txp_driver; 907 908/* vc4_irq.c */ 909irqreturn_t vc4_irq(int irq, void *arg); 910void vc4_irq_preinstall(struct drm_device *dev); 911int vc4_irq_postinstall(struct drm_device *dev); 912void vc4_irq_uninstall(struct drm_device *dev); 913void vc4_irq_reset(struct drm_device *dev); 914 915/* vc4_hvs.c */ 916extern struct platform_driver vc4_hvs_driver; 917void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output); 918int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output); 919int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state); 920void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); 921void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); 922void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state); 923void vc4_hvs_dump_state(struct drm_device *dev); 924void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel); 925void vc4_hvs_mask_underrun(struct drm_device *dev, int channel); 926 927/* vc4_kms.c */ 928int vc4_kms_load(struct drm_device *dev); 929 930/* vc4_plane.c */ 931struct drm_plane *vc4_plane_init(struct drm_device *dev, 932 enum drm_plane_type type); 933int vc4_plane_create_additional_planes(struct drm_device *dev); 934u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 935u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 936void vc4_plane_async_set_fb(struct drm_plane *plane, 937 struct drm_framebuffer *fb); 938 939/* vc4_v3d.c */ 940extern struct platform_driver vc4_v3d_driver; 941extern const struct of_device_id vc4_v3d_dt_match[]; 942int vc4_v3d_get_bin_slot(struct vc4_dev *vc4); 943int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used); 944void vc4_v3d_bin_bo_put(struct vc4_dev *vc4); 945int vc4_v3d_pm_get(struct vc4_dev *vc4); 946void vc4_v3d_pm_put(struct vc4_dev *vc4); 947 948/* vc4_validate.c */ 949int 950vc4_validate_bin_cl(struct drm_device *dev, 951 void *validated, 952 void *unvalidated, 953 struct vc4_exec_info *exec); 954 955int 956vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 957 958struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 959 uint32_t hindex); 960 961int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 962 963bool vc4_check_tex_size(struct vc4_exec_info *exec, 964 struct drm_gem_cma_object *fbo, 965 uint32_t offset, uint8_t tiling_format, 966 uint32_t width, uint32_t height, uint8_t cpp); 967 968/* vc4_validate_shader.c */ 969struct vc4_validated_shader_info * 970vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 971 972/* vc4_perfmon.c */ 973void vc4_perfmon_get(struct vc4_perfmon *perfmon); 974void vc4_perfmon_put(struct vc4_perfmon *perfmon); 975void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon); 976void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon, 977 bool capture); 978struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id); 979void vc4_perfmon_open_file(struct vc4_file *vc4file); 980void vc4_perfmon_close_file(struct vc4_file *vc4file); 981int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data, 982 struct drm_file *file_priv); 983int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 984 struct drm_file *file_priv); 985int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 986 struct drm_file *file_priv); 987 988#endif /* _VC4_DRV_H_ */ 989