1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6/** 7 * DOC: VC4 CRTC module 8 * 9 * In VC4, the Pixel Valve is what most closely corresponds to the 10 * DRM's concept of a CRTC. The PV generates video timings from the 11 * encoder's clock plus its configuration. It pulls scaled pixels from 12 * the HVS at that timing, and feeds it to the encoder. 13 * 14 * However, the DRM CRTC also collects the configuration of all the 15 * DRM planes attached to it. As a result, the CRTC is also 16 * responsible for writing the display list for the HVS channel that 17 * the CRTC will use. 18 * 19 * The 2835 has 3 different pixel valves. pv0 in the audio power 20 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the 21 * image domain can feed either HDMI or the SDTV controller. The 22 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for 23 * SDTV, etc.) according to which output type is chosen in the mux. 24 * 25 * For power management, the pixel valve's registers are all clocked 26 * by the AXI clock, while the timings and FIFOs make use of the 27 * output-specific clock. Since the encoders also directly consume 28 * the CPRMAN clocks, and know what timings they need, they are the 29 * ones that set the clock. 30 */ 31 32#include <linux/clk.h> 33#include <linux/component.h> 34#include <linux/of_device.h> 35 36#include <drm/drm_atomic.h> 37#include <drm/drm_atomic_helper.h> 38#include <drm/drm_atomic_uapi.h> 39#include <drm/drm_fb_cma_helper.h> 40#include <drm/drm_print.h> 41#include <drm/drm_probe_helper.h> 42#include <drm/drm_vblank.h> 43 44#include "vc4_drv.h" 45#include "vc4_regs.h" 46 47#define HVS_FIFO_LATENCY_PIX 6 48 49#define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) 50#define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) 51 52static const struct debugfs_reg32 crtc_regs[] = { 53 VC4_REG32(PV_CONTROL), 54 VC4_REG32(PV_V_CONTROL), 55 VC4_REG32(PV_VSYNCD_EVEN), 56 VC4_REG32(PV_HORZA), 57 VC4_REG32(PV_HORZB), 58 VC4_REG32(PV_VERTA), 59 VC4_REG32(PV_VERTB), 60 VC4_REG32(PV_VERTA_EVEN), 61 VC4_REG32(PV_VERTB_EVEN), 62 VC4_REG32(PV_INTEN), 63 VC4_REG32(PV_INTSTAT), 64 VC4_REG32(PV_STAT), 65 VC4_REG32(PV_HACT_ACT), 66}; 67 68static unsigned int 69vc4_crtc_get_cob_allocation(struct vc4_dev *vc4, unsigned int channel) 70{ 71 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel)); 72 /* Top/base are supposed to be 4-pixel aligned, but the 73 * Raspberry Pi firmware fills the low bits (which are 74 * presumably ignored). 75 */ 76 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; 77 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; 78 79 return top - base + 4; 80} 81 82static bool vc4_crtc_get_scanout_position(struct drm_crtc *crtc, 83 bool in_vblank_irq, 84 int *vpos, int *hpos, 85 ktime_t *stime, ktime_t *etime, 86 const struct drm_display_mode *mode) 87{ 88 struct drm_device *dev = crtc->dev; 89 struct vc4_dev *vc4 = to_vc4_dev(dev); 90 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 91 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 92 unsigned int cob_size; 93 u32 val; 94 int fifo_lines; 95 int vblank_lines; 96 bool ret = false; 97 98 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 99 100 /* Get optional system timestamp before query. */ 101 if (stime) 102 *stime = ktime_get(); 103 104 /* 105 * Read vertical scanline which is currently composed for our 106 * pixelvalve by the HVS, and also the scaler status. 107 */ 108 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); 109 110 /* Get optional system timestamp after query. */ 111 if (etime) 112 *etime = ktime_get(); 113 114 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 115 116 /* Vertical position of hvs composed scanline. */ 117 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); 118 *hpos = 0; 119 120 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 121 *vpos /= 2; 122 123 /* Use hpos to correct for field offset in interlaced mode. */ 124 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) 125 *hpos += mode->crtc_htotal / 2; 126 } 127 128 cob_size = vc4_crtc_get_cob_allocation(vc4, vc4_crtc_state->assigned_channel); 129 /* This is the offset we need for translating hvs -> pv scanout pos. */ 130 fifo_lines = cob_size / mode->crtc_hdisplay; 131 132 if (fifo_lines > 0) 133 ret = true; 134 135 /* HVS more than fifo_lines into frame for compositing? */ 136 if (*vpos > fifo_lines) { 137 /* 138 * We are in active scanout and can get some meaningful results 139 * from HVS. The actual PV scanout can not trail behind more 140 * than fifo_lines as that is the fifo's capacity. Assume that 141 * in active scanout the HVS and PV work in lockstep wrt. HVS 142 * refilling the fifo and PV consuming from the fifo, ie. 143 * whenever the PV consumes and frees up a scanline in the 144 * fifo, the HVS will immediately refill it, therefore 145 * incrementing vpos. Therefore we choose HVS read position - 146 * fifo size in scanlines as a estimate of the real scanout 147 * position of the PV. 148 */ 149 *vpos -= fifo_lines + 1; 150 151 return ret; 152 } 153 154 /* 155 * Less: This happens when we are in vblank and the HVS, after getting 156 * the VSTART restart signal from the PV, just started refilling its 157 * fifo with new lines from the top-most lines of the new framebuffers. 158 * The PV does not scan out in vblank, so does not remove lines from 159 * the fifo, so the fifo will be full quickly and the HVS has to pause. 160 * We can't get meaningful readings wrt. scanline position of the PV 161 * and need to make things up in a approximative but consistent way. 162 */ 163 vblank_lines = mode->vtotal - mode->vdisplay; 164 165 if (in_vblank_irq) { 166 /* 167 * Assume the irq handler got called close to first 168 * line of vblank, so PV has about a full vblank 169 * scanlines to go, and as a base timestamp use the 170 * one taken at entry into vblank irq handler, so it 171 * is not affected by random delays due to lock 172 * contention on event_lock or vblank_time lock in 173 * the core. 174 */ 175 *vpos = -vblank_lines; 176 177 if (stime) 178 *stime = vc4_crtc->t_vblank; 179 if (etime) 180 *etime = vc4_crtc->t_vblank; 181 182 /* 183 * If the HVS fifo is not yet full then we know for certain 184 * we are at the very beginning of vblank, as the hvs just 185 * started refilling, and the stime and etime timestamps 186 * truly correspond to start of vblank. 187 * 188 * Unfortunately there's no way to report this to upper levels 189 * and make it more useful. 190 */ 191 } else { 192 /* 193 * No clue where we are inside vblank. Return a vpos of zero, 194 * which will cause calling code to just return the etime 195 * timestamp uncorrected. At least this is no worse than the 196 * standard fallback. 197 */ 198 *vpos = 0; 199 } 200 201 return ret; 202} 203 204void vc4_crtc_destroy(struct drm_crtc *crtc) 205{ 206 drm_crtc_cleanup(crtc); 207} 208 209static u32 vc4_get_fifo_full_level(struct vc4_crtc *vc4_crtc, u32 format) 210{ 211 const struct vc4_crtc_data *crtc_data = vc4_crtc_to_vc4_crtc_data(vc4_crtc); 212 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 213 struct vc4_dev *vc4 = to_vc4_dev(vc4_crtc->base.dev); 214 u32 fifo_len_bytes = pv_data->fifo_depth; 215 216 /* 217 * Pixels are pulled from the HVS if the number of bytes is 218 * lower than the FIFO full level. 219 * 220 * The latency of the pixel fetch mechanism is 6 pixels, so we 221 * need to convert those 6 pixels in bytes, depending on the 222 * format, and then subtract that from the length of the FIFO 223 * to make sure we never end up in a situation where the FIFO 224 * is full. 225 */ 226 switch (format) { 227 case PV_CONTROL_FORMAT_DSIV_16: 228 case PV_CONTROL_FORMAT_DSIC_16: 229 return fifo_len_bytes - 2 * HVS_FIFO_LATENCY_PIX; 230 case PV_CONTROL_FORMAT_DSIV_18: 231 return fifo_len_bytes - 14; 232 case PV_CONTROL_FORMAT_24: 233 case PV_CONTROL_FORMAT_DSIV_24: 234 default: 235 /* 236 * For some reason, the pixelvalve4 doesn't work with 237 * the usual formula and will only work with 32. 238 */ 239 if (crtc_data->hvs_output == 5) 240 return 32; 241 242 /* 243 * It looks like in some situations, we will overflow 244 * the PixelValve FIFO (with the bit 10 of PV stat being 245 * set) and stall the HVS / PV, eventually resulting in 246 * a page flip timeout. 247 * 248 * Displaying the video overlay during a playback with 249 * Kodi on an RPi3 seems to be a great solution with a 250 * failure rate around 50%. 251 * 252 * Removing 1 from the FIFO full level however 253 * seems to completely remove that issue. 254 */ 255 if (!vc4->hvs->hvs5) 256 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX - 1; 257 258 return fifo_len_bytes - 3 * HVS_FIFO_LATENCY_PIX; 259 } 260} 261 262static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc, 263 u32 format) 264{ 265 u32 level = vc4_get_fifo_full_level(vc4_crtc, format); 266 u32 ret = 0; 267 268 ret |= VC4_SET_FIELD((level >> 6), 269 PV5_CONTROL_FIFO_LEVEL_HIGH); 270 271 return ret | VC4_SET_FIELD(level & 0x3f, 272 PV_CONTROL_FIFO_LEVEL); 273} 274 275/* 276 * Returns the encoder attached to the CRTC. 277 * 278 * VC4 can only scan out to one encoder at a time, while the DRM core 279 * allows drivers to push pixels to more than one encoder from the 280 * same CRTC. 281 */ 282static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) 283{ 284 struct drm_connector *connector; 285 struct drm_connector_list_iter conn_iter; 286 287 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 288 drm_for_each_connector_iter(connector, &conn_iter) { 289 if (connector->state->crtc == crtc) { 290 drm_connector_list_iter_end(&conn_iter); 291 return connector->encoder; 292 } 293 } 294 drm_connector_list_iter_end(&conn_iter); 295 296 return NULL; 297} 298 299static void vc4_crtc_pixelvalve_reset(struct drm_crtc *crtc) 300{ 301 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 302 303 /* The PV needs to be disabled before it can be flushed */ 304 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) & ~PV_CONTROL_EN); 305 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR); 306} 307 308static void vc4_crtc_config_pv(struct drm_crtc *crtc) 309{ 310 struct drm_device *dev = crtc->dev; 311 struct vc4_dev *vc4 = to_vc4_dev(dev); 312 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); 313 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 314 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 315 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 316 struct drm_crtc_state *state = crtc->state; 317 struct drm_display_mode *mode = &state->adjusted_mode; 318 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 319 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 320 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || 321 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); 322 bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1; 323 u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; 324 u8 ppc = pv_data->pixels_per_clock; 325 bool debug_dump_regs = false; 326 327 if (debug_dump_regs) { 328 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 329 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs before:\n", 330 drm_crtc_index(crtc)); 331 drm_print_regset32(&p, &vc4_crtc->regset); 332 } 333 334 vc4_crtc_pixelvalve_reset(crtc); 335 336 CRTC_WRITE(PV_HORZA, 337 VC4_SET_FIELD((mode->htotal - mode->hsync_end) * pixel_rep / ppc, 338 PV_HORZA_HBP) | 339 VC4_SET_FIELD((mode->hsync_end - mode->hsync_start) * pixel_rep / ppc, 340 PV_HORZA_HSYNC)); 341 342 CRTC_WRITE(PV_HORZB, 343 VC4_SET_FIELD((mode->hsync_start - mode->hdisplay) * pixel_rep / ppc, 344 PV_HORZB_HFP) | 345 VC4_SET_FIELD(mode->hdisplay * pixel_rep / ppc, 346 PV_HORZB_HACTIVE)); 347 348 CRTC_WRITE(PV_VERTA, 349 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 350 interlace, 351 PV_VERTA_VBP) | 352 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 353 PV_VERTA_VSYNC)); 354 CRTC_WRITE(PV_VERTB, 355 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 356 PV_VERTB_VFP) | 357 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 358 359 if (interlace) { 360 CRTC_WRITE(PV_VERTA_EVEN, 361 VC4_SET_FIELD(mode->crtc_vtotal - 362 mode->crtc_vsync_end, 363 PV_VERTA_VBP) | 364 VC4_SET_FIELD(mode->crtc_vsync_end - 365 mode->crtc_vsync_start, 366 PV_VERTA_VSYNC)); 367 CRTC_WRITE(PV_VERTB_EVEN, 368 VC4_SET_FIELD(mode->crtc_vsync_start - 369 mode->crtc_vdisplay, 370 PV_VERTB_VFP) | 371 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 372 373 /* We set up first field even mode for HDMI. VEC's 374 * NTSC mode would want first field odd instead, once 375 * we support it (to do so, set ODD_FIRST and put the 376 * delay in VSYNCD_EVEN instead). 377 */ 378 CRTC_WRITE(PV_V_CONTROL, 379 PV_VCONTROL_CONTINUOUS | 380 (is_dsi ? PV_VCONTROL_DSI : 0) | 381 PV_VCONTROL_INTERLACE | 382 VC4_SET_FIELD(mode->htotal * pixel_rep / (2 * ppc), 383 PV_VCONTROL_ODD_DELAY)); 384 CRTC_WRITE(PV_VSYNCD_EVEN, 0); 385 } else { 386 CRTC_WRITE(PV_V_CONTROL, 387 PV_VCONTROL_CONTINUOUS | 388 (is_dsi ? PV_VCONTROL_DSI : 0)); 389 } 390 391 if (is_dsi) 392 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); 393 394 if (vc4->hvs->hvs5) 395 CRTC_WRITE(PV_MUX_CFG, 396 VC4_SET_FIELD(PV_MUX_CFG_RGB_PIXEL_MUX_MODE_NO_SWAP, 397 PV_MUX_CFG_RGB_PIXEL_MUX_MODE)); 398 399 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | 400 vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) | 401 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | 402 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | 403 PV_CONTROL_CLR_AT_START | 404 PV_CONTROL_TRIGGER_UNDERFLOW | 405 PV_CONTROL_WAIT_HSTART | 406 VC4_SET_FIELD(vc4_encoder->clock_select, 407 PV_CONTROL_CLK_SELECT)); 408 409 if (debug_dump_regs) { 410 struct drm_printer p = drm_info_printer(&vc4_crtc->pdev->dev); 411 dev_info(&vc4_crtc->pdev->dev, "CRTC %d regs after:\n", 412 drm_crtc_index(crtc)); 413 drm_print_regset32(&p, &vc4_crtc->regset); 414 } 415} 416 417static void require_hvs_enabled(struct drm_device *dev) 418{ 419 struct vc4_dev *vc4 = to_vc4_dev(dev); 420 421 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != 422 SCALER_DISPCTRL_ENABLE); 423} 424 425static int vc4_crtc_disable(struct drm_crtc *crtc, unsigned int channel) 426{ 427 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); 428 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 429 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 430 struct drm_device *dev = crtc->dev; 431 int ret; 432 433 CRTC_WRITE(PV_V_CONTROL, 434 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); 435 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); 436 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); 437 438 /* 439 * This delay is needed to avoid to get a pixel stuck in an 440 * unflushable FIFO between the pixelvalve and the HDMI 441 * controllers on the BCM2711. 442 * 443 * Timing is fairly sensitive here, so mdelay is the safest 444 * approach. 445 * 446 * If it was to be reworked, the stuck pixel happens on a 447 * BCM2711 when changing mode with a good probability, so a 448 * script that changes mode on a regular basis should trigger 449 * the bug after less than 10 attempts. It manifests itself with 450 * every pixels being shifted by one to the right, and thus the 451 * last pixel of a line actually being displayed as the first 452 * pixel on the next line. 453 */ 454 mdelay(20); 455 456 if (vc4_encoder && vc4_encoder->post_crtc_disable) 457 vc4_encoder->post_crtc_disable(encoder); 458 459 vc4_crtc_pixelvalve_reset(crtc); 460 vc4_hvs_stop_channel(dev, channel); 461 462 if (vc4_encoder && vc4_encoder->post_crtc_powerdown) 463 vc4_encoder->post_crtc_powerdown(encoder); 464 465 return 0; 466} 467 468int vc4_crtc_disable_at_boot(struct drm_crtc *crtc) 469{ 470 struct drm_device *drm = crtc->dev; 471 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 472 int channel; 473 474 if (!(of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 475 "brcm,bcm2711-pixelvalve2") || 476 of_device_is_compatible(vc4_crtc->pdev->dev.of_node, 477 "brcm,bcm2711-pixelvalve4"))) 478 return 0; 479 480 if (!(CRTC_READ(PV_CONTROL) & PV_CONTROL_EN)) 481 return 0; 482 483 if (!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN)) 484 return 0; 485 486 channel = vc4_hvs_get_fifo_from_output(drm, vc4_crtc->data->hvs_output); 487 if (channel < 0) 488 return 0; 489 490 return vc4_crtc_disable(crtc, channel); 491} 492 493static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, 494 struct drm_crtc_state *old_state) 495{ 496 struct vc4_crtc_state *old_vc4_state = to_vc4_crtc_state(old_state); 497 struct drm_device *dev = crtc->dev; 498 499 require_hvs_enabled(dev); 500 501 /* Disable vblank irq handling before crtc is disabled. */ 502 drm_crtc_vblank_off(crtc); 503 504 vc4_crtc_disable(crtc, old_vc4_state->assigned_channel); 505 506 /* 507 * Make sure we issue a vblank event after disabling the CRTC if 508 * someone was waiting it. 509 */ 510 if (crtc->state->event) { 511 unsigned long flags; 512 513 spin_lock_irqsave(&dev->event_lock, flags); 514 drm_crtc_send_vblank_event(crtc, crtc->state->event); 515 crtc->state->event = NULL; 516 spin_unlock_irqrestore(&dev->event_lock, flags); 517 } 518} 519 520static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 521 struct drm_crtc_state *old_state) 522{ 523 struct drm_device *dev = crtc->dev; 524 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 525 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); 526 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 527 528 require_hvs_enabled(dev); 529 530 /* Enable vblank irq handling before crtc is started otherwise 531 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). 532 */ 533 drm_crtc_vblank_on(crtc); 534 535 vc4_hvs_atomic_enable(crtc, old_state); 536 537 if (vc4_encoder->pre_crtc_configure) 538 vc4_encoder->pre_crtc_configure(encoder); 539 540 vc4_crtc_config_pv(crtc); 541 542 CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN); 543 544 if (vc4_encoder->pre_crtc_enable) 545 vc4_encoder->pre_crtc_enable(encoder); 546 547 /* When feeding the transposer block the pixelvalve is unneeded and 548 * should not be enabled. 549 */ 550 CRTC_WRITE(PV_V_CONTROL, 551 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); 552 553 if (vc4_encoder->post_crtc_enable) 554 vc4_encoder->post_crtc_enable(encoder); 555} 556 557static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, 558 const struct drm_display_mode *mode) 559{ 560 /* Do not allow doublescan modes from user space */ 561 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 562 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", 563 crtc->base.id); 564 return MODE_NO_DBLESCAN; 565 } 566 567 return MODE_OK; 568} 569 570void vc4_crtc_get_margins(struct drm_crtc_state *state, 571 unsigned int *left, unsigned int *right, 572 unsigned int *top, unsigned int *bottom) 573{ 574 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 575 struct drm_connector_state *conn_state; 576 struct drm_connector *conn; 577 int i; 578 579 *left = vc4_state->margins.left; 580 *right = vc4_state->margins.right; 581 *top = vc4_state->margins.top; 582 *bottom = vc4_state->margins.bottom; 583 584 /* We have to interate over all new connector states because 585 * vc4_crtc_get_margins() might be called before 586 * vc4_crtc_atomic_check() which means margins info in vc4_crtc_state 587 * might be outdated. 588 */ 589 for_each_new_connector_in_state(state->state, conn, conn_state, i) { 590 if (conn_state->crtc != state->crtc) 591 continue; 592 593 *left = conn_state->tv.margins.left; 594 *right = conn_state->tv.margins.right; 595 *top = conn_state->tv.margins.top; 596 *bottom = conn_state->tv.margins.bottom; 597 break; 598 } 599} 600 601static int vc4_crtc_atomic_check(struct drm_crtc *crtc, 602 struct drm_crtc_state *state) 603{ 604 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 605 struct drm_connector *conn; 606 struct drm_connector_state *conn_state; 607 int ret, i; 608 609 ret = vc4_hvs_atomic_check(crtc, state); 610 if (ret) 611 return ret; 612 613 for_each_new_connector_in_state(state->state, conn, conn_state, i) { 614 if (conn_state->crtc != crtc) 615 continue; 616 617 vc4_state->margins.left = conn_state->tv.margins.left; 618 vc4_state->margins.right = conn_state->tv.margins.right; 619 vc4_state->margins.top = conn_state->tv.margins.top; 620 vc4_state->margins.bottom = conn_state->tv.margins.bottom; 621 break; 622 } 623 624 return 0; 625} 626 627static int vc4_enable_vblank(struct drm_crtc *crtc) 628{ 629 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 630 631 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); 632 633 return 0; 634} 635 636static void vc4_disable_vblank(struct drm_crtc *crtc) 637{ 638 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 639 640 CRTC_WRITE(PV_INTEN, 0); 641} 642 643static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) 644{ 645 struct drm_crtc *crtc = &vc4_crtc->base; 646 struct drm_device *dev = crtc->dev; 647 struct vc4_dev *vc4 = to_vc4_dev(dev); 648 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 649 u32 chan = vc4_state->assigned_channel; 650 unsigned long flags; 651 652 spin_lock_irqsave(&dev->event_lock, flags); 653 if (vc4_crtc->event && 654 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) || 655 vc4_state->feed_txp)) { 656 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); 657 vc4_crtc->event = NULL; 658 drm_crtc_vblank_put(crtc); 659 660 /* Wait for the page flip to unmask the underrun to ensure that 661 * the display list was updated by the hardware. Before that 662 * happens, the HVS will be using the previous display list with 663 * the CRTC and encoder already reconfigured, leading to 664 * underruns. This can be seen when reconfiguring the CRTC. 665 */ 666 vc4_hvs_unmask_underrun(dev, chan); 667 } 668 spin_unlock_irqrestore(&dev->event_lock, flags); 669} 670 671void vc4_crtc_handle_vblank(struct vc4_crtc *crtc) 672{ 673 crtc->t_vblank = ktime_get(); 674 drm_crtc_handle_vblank(&crtc->base); 675 vc4_crtc_handle_page_flip(crtc); 676} 677 678static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) 679{ 680 struct vc4_crtc *vc4_crtc = data; 681 u32 stat = CRTC_READ(PV_INTSTAT); 682 irqreturn_t ret = IRQ_NONE; 683 684 if (stat & PV_INT_VFP_START) { 685 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 686 vc4_crtc_handle_vblank(vc4_crtc); 687 ret = IRQ_HANDLED; 688 } 689 690 return ret; 691} 692 693struct vc4_async_flip_state { 694 struct drm_crtc *crtc; 695 struct drm_framebuffer *fb; 696 struct drm_framebuffer *old_fb; 697 struct drm_pending_vblank_event *event; 698 699 struct vc4_seqno_cb cb; 700}; 701 702/* Called when the V3D execution for the BO being flipped to is done, so that 703 * we can actually update the plane's address to point to it. 704 */ 705static void 706vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) 707{ 708 struct vc4_async_flip_state *flip_state = 709 container_of(cb, struct vc4_async_flip_state, cb); 710 struct drm_crtc *crtc = flip_state->crtc; 711 struct drm_device *dev = crtc->dev; 712 struct vc4_dev *vc4 = to_vc4_dev(dev); 713 struct drm_plane *plane = crtc->primary; 714 715 vc4_plane_async_set_fb(plane, flip_state->fb); 716 if (flip_state->event) { 717 unsigned long flags; 718 719 spin_lock_irqsave(&dev->event_lock, flags); 720 drm_crtc_send_vblank_event(crtc, flip_state->event); 721 spin_unlock_irqrestore(&dev->event_lock, flags); 722 } 723 724 drm_crtc_vblank_put(crtc); 725 drm_framebuffer_put(flip_state->fb); 726 727 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced 728 * when the planes are updated through the async update path. 729 * FIXME: we should move to generic async-page-flip when it's 730 * available, so that we can get rid of this hand-made cleanup_fb() 731 * logic. 732 */ 733 if (flip_state->old_fb) { 734 struct drm_gem_cma_object *cma_bo; 735 struct vc4_bo *bo; 736 737 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0); 738 bo = to_vc4_bo(&cma_bo->base); 739 vc4_bo_dec_usecnt(bo); 740 drm_framebuffer_put(flip_state->old_fb); 741 } 742 743 kfree(flip_state); 744 745 up(&vc4->async_modeset); 746} 747 748/* Implements async (non-vblank-synced) page flips. 749 * 750 * The page flip ioctl needs to return immediately, so we grab the 751 * modeset semaphore on the pipe, and queue the address update for 752 * when V3D is done with the BO being flipped to. 753 */ 754static int vc4_async_page_flip(struct drm_crtc *crtc, 755 struct drm_framebuffer *fb, 756 struct drm_pending_vblank_event *event, 757 uint32_t flags) 758{ 759 struct drm_device *dev = crtc->dev; 760 struct vc4_dev *vc4 = to_vc4_dev(dev); 761 struct drm_plane *plane = crtc->primary; 762 int ret = 0; 763 struct vc4_async_flip_state *flip_state; 764 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); 765 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); 766 767 /* Increment the BO usecnt here, so that we never end up with an 768 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the 769 * plane is later updated through the non-async path. 770 * FIXME: we should move to generic async-page-flip when it's 771 * available, so that we can get rid of this hand-made prepare_fb() 772 * logic. 773 */ 774 ret = vc4_bo_inc_usecnt(bo); 775 if (ret) 776 return ret; 777 778 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); 779 if (!flip_state) { 780 vc4_bo_dec_usecnt(bo); 781 return -ENOMEM; 782 } 783 784 drm_framebuffer_get(fb); 785 flip_state->fb = fb; 786 flip_state->crtc = crtc; 787 flip_state->event = event; 788 789 /* Make sure all other async modesetes have landed. */ 790 ret = down_interruptible(&vc4->async_modeset); 791 if (ret) { 792 drm_framebuffer_put(fb); 793 vc4_bo_dec_usecnt(bo); 794 kfree(flip_state); 795 return ret; 796 } 797 798 /* Save the current FB before it's replaced by the new one in 799 * drm_atomic_set_fb_for_plane(). We'll need the old FB in 800 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep 801 * it consistent. 802 * FIXME: we should move to generic async-page-flip when it's 803 * available, so that we can get rid of this hand-made cleanup_fb() 804 * logic. 805 */ 806 flip_state->old_fb = plane->state->fb; 807 if (flip_state->old_fb) 808 drm_framebuffer_get(flip_state->old_fb); 809 810 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 811 812 /* Immediately update the plane's legacy fb pointer, so that later 813 * modeset prep sees the state that will be present when the semaphore 814 * is released. 815 */ 816 drm_atomic_set_fb_for_plane(plane->state, fb); 817 818 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, 819 vc4_async_page_flip_complete); 820 821 /* Driver takes ownership of state on successful async commit. */ 822 return 0; 823} 824 825int vc4_page_flip(struct drm_crtc *crtc, 826 struct drm_framebuffer *fb, 827 struct drm_pending_vblank_event *event, 828 uint32_t flags, 829 struct drm_modeset_acquire_ctx *ctx) 830{ 831 if (flags & DRM_MODE_PAGE_FLIP_ASYNC) 832 return vc4_async_page_flip(crtc, fb, event, flags); 833 else 834 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx); 835} 836 837struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) 838{ 839 struct vc4_crtc_state *vc4_state, *old_vc4_state; 840 841 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 842 if (!vc4_state) 843 return NULL; 844 845 old_vc4_state = to_vc4_crtc_state(crtc->state); 846 vc4_state->feed_txp = old_vc4_state->feed_txp; 847 vc4_state->margins = old_vc4_state->margins; 848 vc4_state->assigned_channel = old_vc4_state->assigned_channel; 849 850 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); 851 return &vc4_state->base; 852} 853 854void vc4_crtc_destroy_state(struct drm_crtc *crtc, 855 struct drm_crtc_state *state) 856{ 857 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); 858 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 859 860 if (drm_mm_node_allocated(&vc4_state->mm)) { 861 unsigned long flags; 862 863 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 864 drm_mm_remove_node(&vc4_state->mm); 865 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 866 867 } 868 869 drm_atomic_helper_crtc_destroy_state(crtc, state); 870} 871 872void vc4_crtc_reset(struct drm_crtc *crtc) 873{ 874 struct vc4_crtc_state *vc4_crtc_state; 875 876 if (crtc->state) 877 vc4_crtc_destroy_state(crtc, crtc->state); 878 879 vc4_crtc_state = kzalloc(sizeof(*vc4_crtc_state), GFP_KERNEL); 880 if (!vc4_crtc_state) { 881 crtc->state = NULL; 882 return; 883 } 884 885 vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; 886 __drm_atomic_helper_crtc_reset(crtc, &vc4_crtc_state->base); 887} 888 889static const struct drm_crtc_funcs vc4_crtc_funcs = { 890 .set_config = drm_atomic_helper_set_config, 891 .destroy = vc4_crtc_destroy, 892 .page_flip = vc4_page_flip, 893 .set_property = NULL, 894 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ 895 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ 896 .reset = vc4_crtc_reset, 897 .atomic_duplicate_state = vc4_crtc_duplicate_state, 898 .atomic_destroy_state = vc4_crtc_destroy_state, 899 .gamma_set = drm_atomic_helper_legacy_gamma_set, 900 .enable_vblank = vc4_enable_vblank, 901 .disable_vblank = vc4_disable_vblank, 902 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, 903}; 904 905static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { 906 .mode_valid = vc4_crtc_mode_valid, 907 .atomic_check = vc4_crtc_atomic_check, 908 .atomic_flush = vc4_hvs_atomic_flush, 909 .atomic_enable = vc4_crtc_atomic_enable, 910 .atomic_disable = vc4_crtc_atomic_disable, 911 .get_scanout_position = vc4_crtc_get_scanout_position, 912}; 913 914static const struct vc4_pv_data bcm2835_pv0_data = { 915 .base = { 916 .hvs_available_channels = BIT(0), 917 .hvs_output = 0, 918 }, 919 .debugfs_name = "crtc0_regs", 920 .fifo_depth = 64, 921 .pixels_per_clock = 1, 922 .encoder_types = { 923 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, 924 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, 925 }, 926}; 927 928static const struct vc4_pv_data bcm2835_pv1_data = { 929 .base = { 930 .hvs_available_channels = BIT(2), 931 .hvs_output = 2, 932 }, 933 .debugfs_name = "crtc1_regs", 934 .fifo_depth = 64, 935 .pixels_per_clock = 1, 936 .encoder_types = { 937 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, 938 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, 939 }, 940}; 941 942static const struct vc4_pv_data bcm2835_pv2_data = { 943 .base = { 944 .hvs_available_channels = BIT(1), 945 .hvs_output = 1, 946 }, 947 .debugfs_name = "crtc2_regs", 948 .fifo_depth = 64, 949 .pixels_per_clock = 1, 950 .encoder_types = { 951 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI0, 952 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 953 }, 954}; 955 956static const struct vc4_pv_data bcm2711_pv0_data = { 957 .base = { 958 .hvs_available_channels = BIT(0), 959 .hvs_output = 0, 960 }, 961 .debugfs_name = "crtc0_regs", 962 .fifo_depth = 64, 963 .pixels_per_clock = 1, 964 .encoder_types = { 965 [0] = VC4_ENCODER_TYPE_DSI0, 966 [1] = VC4_ENCODER_TYPE_DPI, 967 }, 968}; 969 970static const struct vc4_pv_data bcm2711_pv1_data = { 971 .base = { 972 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 973 .hvs_output = 3, 974 }, 975 .debugfs_name = "crtc1_regs", 976 .fifo_depth = 64, 977 .pixels_per_clock = 1, 978 .encoder_types = { 979 [0] = VC4_ENCODER_TYPE_DSI1, 980 [1] = VC4_ENCODER_TYPE_SMI, 981 }, 982}; 983 984static const struct vc4_pv_data bcm2711_pv2_data = { 985 .base = { 986 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 987 .hvs_output = 4, 988 }, 989 .debugfs_name = "crtc2_regs", 990 .fifo_depth = 256, 991 .pixels_per_clock = 2, 992 .encoder_types = { 993 [0] = VC4_ENCODER_TYPE_HDMI0, 994 }, 995}; 996 997static const struct vc4_pv_data bcm2711_pv3_data = { 998 .base = { 999 .hvs_available_channels = BIT(1), 1000 .hvs_output = 1, 1001 }, 1002 .debugfs_name = "crtc3_regs", 1003 .fifo_depth = 64, 1004 .pixels_per_clock = 1, 1005 .encoder_types = { 1006 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 1007 }, 1008}; 1009 1010static const struct vc4_pv_data bcm2711_pv4_data = { 1011 .base = { 1012 .hvs_available_channels = BIT(0) | BIT(1) | BIT(2), 1013 .hvs_output = 5, 1014 }, 1015 .debugfs_name = "crtc4_regs", 1016 .fifo_depth = 64, 1017 .pixels_per_clock = 2, 1018 .encoder_types = { 1019 [0] = VC4_ENCODER_TYPE_HDMI1, 1020 }, 1021}; 1022 1023static const struct of_device_id vc4_crtc_dt_match[] = { 1024 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &bcm2835_pv0_data }, 1025 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &bcm2835_pv1_data }, 1026 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &bcm2835_pv2_data }, 1027 { .compatible = "brcm,bcm2711-pixelvalve0", .data = &bcm2711_pv0_data }, 1028 { .compatible = "brcm,bcm2711-pixelvalve1", .data = &bcm2711_pv1_data }, 1029 { .compatible = "brcm,bcm2711-pixelvalve2", .data = &bcm2711_pv2_data }, 1030 { .compatible = "brcm,bcm2711-pixelvalve3", .data = &bcm2711_pv3_data }, 1031 { .compatible = "brcm,bcm2711-pixelvalve4", .data = &bcm2711_pv4_data }, 1032 {} 1033}; 1034 1035static void vc4_set_crtc_possible_masks(struct drm_device *drm, 1036 struct drm_crtc *crtc) 1037{ 1038 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 1039 const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc); 1040 const enum vc4_encoder_type *encoder_types = pv_data->encoder_types; 1041 struct drm_encoder *encoder; 1042 1043 drm_for_each_encoder(encoder, drm) { 1044 struct vc4_encoder *vc4_encoder; 1045 int i; 1046 1047 if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL) 1048 continue; 1049 1050 vc4_encoder = to_vc4_encoder(encoder); 1051 for (i = 0; i < ARRAY_SIZE(pv_data->encoder_types); i++) { 1052 if (vc4_encoder->type == encoder_types[i]) { 1053 vc4_encoder->clock_select = i; 1054 encoder->possible_crtcs |= drm_crtc_mask(crtc); 1055 break; 1056 } 1057 } 1058 } 1059} 1060 1061int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 1062 const struct drm_crtc_funcs *crtc_funcs, 1063 const struct drm_crtc_helper_funcs *crtc_helper_funcs) 1064{ 1065 struct vc4_dev *vc4 = to_vc4_dev(drm); 1066 struct drm_crtc *crtc = &vc4_crtc->base; 1067 struct drm_plane *primary_plane; 1068 unsigned int i; 1069 1070 /* For now, we create just the primary and the legacy cursor 1071 * planes. We should be able to stack more planes on easily, 1072 * but to do that we would need to compute the bandwidth 1073 * requirement of the plane configuration, and reject ones 1074 * that will take too much. 1075 */ 1076 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); 1077 if (IS_ERR(primary_plane)) { 1078 dev_err(drm->dev, "failed to construct primary plane\n"); 1079 return PTR_ERR(primary_plane); 1080 } 1081 1082 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1083 crtc_funcs, NULL); 1084 drm_crtc_helper_add(crtc, crtc_helper_funcs); 1085 1086 if (!vc4->hvs->hvs5) { 1087 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); 1088 1089 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); 1090 1091 /* We support CTM, but only for one CRTC at a time. It's therefore 1092 * implemented as private driver state in vc4_kms, not here. 1093 */ 1094 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); 1095 } 1096 1097 for (i = 0; i < crtc->gamma_size; i++) { 1098 vc4_crtc->lut_r[i] = i; 1099 vc4_crtc->lut_g[i] = i; 1100 vc4_crtc->lut_b[i] = i; 1101 } 1102 1103 return 0; 1104} 1105 1106static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) 1107{ 1108 struct platform_device *pdev = to_platform_device(dev); 1109 struct drm_device *drm = dev_get_drvdata(master); 1110 const struct vc4_pv_data *pv_data; 1111 struct vc4_crtc *vc4_crtc; 1112 struct drm_crtc *crtc; 1113 struct drm_plane *destroy_plane, *temp; 1114 int ret; 1115 1116 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); 1117 if (!vc4_crtc) 1118 return -ENOMEM; 1119 crtc = &vc4_crtc->base; 1120 1121 pv_data = of_device_get_match_data(dev); 1122 if (!pv_data) 1123 return -ENODEV; 1124 vc4_crtc->data = &pv_data->base; 1125 vc4_crtc->pdev = pdev; 1126 1127 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); 1128 if (IS_ERR(vc4_crtc->regs)) 1129 return PTR_ERR(vc4_crtc->regs); 1130 1131 vc4_crtc->regset.base = vc4_crtc->regs; 1132 vc4_crtc->regset.regs = crtc_regs; 1133 vc4_crtc->regset.nregs = ARRAY_SIZE(crtc_regs); 1134 1135 ret = vc4_crtc_init(drm, vc4_crtc, 1136 &vc4_crtc_funcs, &vc4_crtc_helper_funcs); 1137 if (ret) 1138 return ret; 1139 vc4_set_crtc_possible_masks(drm, crtc); 1140 1141 CRTC_WRITE(PV_INTEN, 0); 1142 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 1143 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1144 vc4_crtc_irq_handler, 1145 IRQF_SHARED, 1146 "vc4 crtc", vc4_crtc); 1147 if (ret) 1148 goto err_destroy_planes; 1149 1150 platform_set_drvdata(pdev, vc4_crtc); 1151 1152 vc4_debugfs_add_regset32(drm, pv_data->debugfs_name, 1153 &vc4_crtc->regset); 1154 1155 return 0; 1156 1157err_destroy_planes: 1158 list_for_each_entry_safe(destroy_plane, temp, 1159 &drm->mode_config.plane_list, head) { 1160 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc)) 1161 destroy_plane->funcs->destroy(destroy_plane); 1162 } 1163 1164 return ret; 1165} 1166 1167static void vc4_crtc_unbind(struct device *dev, struct device *master, 1168 void *data) 1169{ 1170 struct platform_device *pdev = to_platform_device(dev); 1171 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); 1172 1173 vc4_crtc_destroy(&vc4_crtc->base); 1174 1175 CRTC_WRITE(PV_INTEN, 0); 1176 1177 platform_set_drvdata(pdev, NULL); 1178} 1179 1180static const struct component_ops vc4_crtc_ops = { 1181 .bind = vc4_crtc_bind, 1182 .unbind = vc4_crtc_unbind, 1183}; 1184 1185static int vc4_crtc_dev_probe(struct platform_device *pdev) 1186{ 1187 return component_add(&pdev->dev, &vc4_crtc_ops); 1188} 1189 1190static int vc4_crtc_dev_remove(struct platform_device *pdev) 1191{ 1192 component_del(&pdev->dev, &vc4_crtc_ops); 1193 return 0; 1194} 1195 1196struct platform_driver vc4_crtc_driver = { 1197 .probe = vc4_crtc_dev_probe, 1198 .remove = vc4_crtc_dev_remove, 1199 .driver = { 1200 .name = "vc4_crtc", 1201 .of_match_table = vc4_crtc_dt_match, 1202 }, 1203}; 1204