18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: MIT */
28c2ecf20Sopenharmony_ci/*
38c2ecf20Sopenharmony_ci * Copyright (C) 2013-2019 NVIDIA Corporation.
48c2ecf20Sopenharmony_ci * Copyright (C) 2015 Rob Clark
58c2ecf20Sopenharmony_ci */
68c2ecf20Sopenharmony_ci
78c2ecf20Sopenharmony_ci#ifndef DRM_TEGRA_DP_H
88c2ecf20Sopenharmony_ci#define DRM_TEGRA_DP_H 1
98c2ecf20Sopenharmony_ci
108c2ecf20Sopenharmony_ci#include <linux/types.h>
118c2ecf20Sopenharmony_ci
128c2ecf20Sopenharmony_cistruct drm_display_info;
138c2ecf20Sopenharmony_cistruct drm_display_mode;
148c2ecf20Sopenharmony_cistruct drm_dp_aux;
158c2ecf20Sopenharmony_cistruct drm_dp_link;
168c2ecf20Sopenharmony_ci
178c2ecf20Sopenharmony_ci/**
188c2ecf20Sopenharmony_ci * struct drm_dp_link_caps - DP link capabilities
198c2ecf20Sopenharmony_ci */
208c2ecf20Sopenharmony_cistruct drm_dp_link_caps {
218c2ecf20Sopenharmony_ci	/**
228c2ecf20Sopenharmony_ci	 * @enhanced_framing:
238c2ecf20Sopenharmony_ci	 *
248c2ecf20Sopenharmony_ci	 * enhanced framing capability (mandatory as of DP 1.2)
258c2ecf20Sopenharmony_ci	 */
268c2ecf20Sopenharmony_ci	bool enhanced_framing;
278c2ecf20Sopenharmony_ci
288c2ecf20Sopenharmony_ci	/**
298c2ecf20Sopenharmony_ci	 * tps3_supported:
308c2ecf20Sopenharmony_ci	 *
318c2ecf20Sopenharmony_ci	 * training pattern sequence 3 supported for equalization
328c2ecf20Sopenharmony_ci	 */
338c2ecf20Sopenharmony_ci	bool tps3_supported;
348c2ecf20Sopenharmony_ci
358c2ecf20Sopenharmony_ci	/**
368c2ecf20Sopenharmony_ci	 * @fast_training:
378c2ecf20Sopenharmony_ci	 *
388c2ecf20Sopenharmony_ci	 * AUX CH handshake not required for link training
398c2ecf20Sopenharmony_ci	 */
408c2ecf20Sopenharmony_ci	bool fast_training;
418c2ecf20Sopenharmony_ci
428c2ecf20Sopenharmony_ci	/**
438c2ecf20Sopenharmony_ci	 * @channel_coding:
448c2ecf20Sopenharmony_ci	 *
458c2ecf20Sopenharmony_ci	 * ANSI 8B/10B channel coding capability
468c2ecf20Sopenharmony_ci	 */
478c2ecf20Sopenharmony_ci	bool channel_coding;
488c2ecf20Sopenharmony_ci
498c2ecf20Sopenharmony_ci	/**
508c2ecf20Sopenharmony_ci	 * @alternate_scrambler_reset:
518c2ecf20Sopenharmony_ci	 *
528c2ecf20Sopenharmony_ci	 * eDP alternate scrambler reset capability
538c2ecf20Sopenharmony_ci	 */
548c2ecf20Sopenharmony_ci	bool alternate_scrambler_reset;
558c2ecf20Sopenharmony_ci};
568c2ecf20Sopenharmony_ci
578c2ecf20Sopenharmony_civoid drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
588c2ecf20Sopenharmony_ci			   const struct drm_dp_link_caps *src);
598c2ecf20Sopenharmony_ci
608c2ecf20Sopenharmony_ci/**
618c2ecf20Sopenharmony_ci * struct drm_dp_link_ops - DP link operations
628c2ecf20Sopenharmony_ci */
638c2ecf20Sopenharmony_cistruct drm_dp_link_ops {
648c2ecf20Sopenharmony_ci	/**
658c2ecf20Sopenharmony_ci	 * @apply_training:
668c2ecf20Sopenharmony_ci	 */
678c2ecf20Sopenharmony_ci	int (*apply_training)(struct drm_dp_link *link);
688c2ecf20Sopenharmony_ci
698c2ecf20Sopenharmony_ci	/**
708c2ecf20Sopenharmony_ci	 * @configure:
718c2ecf20Sopenharmony_ci	 */
728c2ecf20Sopenharmony_ci	int (*configure)(struct drm_dp_link *link);
738c2ecf20Sopenharmony_ci};
748c2ecf20Sopenharmony_ci
758c2ecf20Sopenharmony_ci#define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
768c2ecf20Sopenharmony_ci#define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
778c2ecf20Sopenharmony_ci#define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
788c2ecf20Sopenharmony_ci
798c2ecf20Sopenharmony_ci/**
808c2ecf20Sopenharmony_ci * struct drm_dp_link_train_set - link training settings
818c2ecf20Sopenharmony_ci * @voltage_swing: per-lane voltage swing
828c2ecf20Sopenharmony_ci * @pre_emphasis: per-lane pre-emphasis
838c2ecf20Sopenharmony_ci * @post_cursor: per-lane post-cursor
848c2ecf20Sopenharmony_ci */
858c2ecf20Sopenharmony_cistruct drm_dp_link_train_set {
868c2ecf20Sopenharmony_ci	unsigned int voltage_swing[4];
878c2ecf20Sopenharmony_ci	unsigned int pre_emphasis[4];
888c2ecf20Sopenharmony_ci	unsigned int post_cursor[4];
898c2ecf20Sopenharmony_ci};
908c2ecf20Sopenharmony_ci
918c2ecf20Sopenharmony_ci/**
928c2ecf20Sopenharmony_ci * struct drm_dp_link_train - link training state information
938c2ecf20Sopenharmony_ci * @request: currently requested settings
948c2ecf20Sopenharmony_ci * @adjust: adjustments requested by sink
958c2ecf20Sopenharmony_ci * @pattern: currently requested training pattern
968c2ecf20Sopenharmony_ci * @clock_recovered: flag to track if clock recovery has completed
978c2ecf20Sopenharmony_ci * @channel_equalized: flag to track if channel equalization has completed
988c2ecf20Sopenharmony_ci */
998c2ecf20Sopenharmony_cistruct drm_dp_link_train {
1008c2ecf20Sopenharmony_ci	struct drm_dp_link_train_set request;
1018c2ecf20Sopenharmony_ci	struct drm_dp_link_train_set adjust;
1028c2ecf20Sopenharmony_ci
1038c2ecf20Sopenharmony_ci	unsigned int pattern;
1048c2ecf20Sopenharmony_ci
1058c2ecf20Sopenharmony_ci	bool clock_recovered;
1068c2ecf20Sopenharmony_ci	bool channel_equalized;
1078c2ecf20Sopenharmony_ci};
1088c2ecf20Sopenharmony_ci
1098c2ecf20Sopenharmony_ci/**
1108c2ecf20Sopenharmony_ci * struct drm_dp_link - DP link capabilities and configuration
1118c2ecf20Sopenharmony_ci * @revision: DP specification revision supported on the link
1128c2ecf20Sopenharmony_ci * @max_rate: maximum clock rate supported on the link
1138c2ecf20Sopenharmony_ci * @max_lanes: maximum number of lanes supported on the link
1148c2ecf20Sopenharmony_ci * @caps: capabilities supported on the link (see &drm_dp_link_caps)
1158c2ecf20Sopenharmony_ci * @aux_rd_interval: AUX read interval to use for training (in microseconds)
1168c2ecf20Sopenharmony_ci * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
1178c2ecf20Sopenharmony_ci * @rate: currently configured link rate
1188c2ecf20Sopenharmony_ci * @lanes: currently configured number of lanes
1198c2ecf20Sopenharmony_ci * @rates: additional supported link rates in kHz (eDP 1.4)
1208c2ecf20Sopenharmony_ci * @num_rates: number of additional supported link rates (eDP 1.4)
1218c2ecf20Sopenharmony_ci */
1228c2ecf20Sopenharmony_cistruct drm_dp_link {
1238c2ecf20Sopenharmony_ci	unsigned char revision;
1248c2ecf20Sopenharmony_ci	unsigned int max_rate;
1258c2ecf20Sopenharmony_ci	unsigned int max_lanes;
1268c2ecf20Sopenharmony_ci
1278c2ecf20Sopenharmony_ci	struct drm_dp_link_caps caps;
1288c2ecf20Sopenharmony_ci
1298c2ecf20Sopenharmony_ci	/**
1308c2ecf20Sopenharmony_ci	 * @cr: clock recovery read interval
1318c2ecf20Sopenharmony_ci	 * @ce: channel equalization read interval
1328c2ecf20Sopenharmony_ci	 */
1338c2ecf20Sopenharmony_ci	struct {
1348c2ecf20Sopenharmony_ci		unsigned int cr;
1358c2ecf20Sopenharmony_ci		unsigned int ce;
1368c2ecf20Sopenharmony_ci	} aux_rd_interval;
1378c2ecf20Sopenharmony_ci
1388c2ecf20Sopenharmony_ci	unsigned char edp;
1398c2ecf20Sopenharmony_ci
1408c2ecf20Sopenharmony_ci	unsigned int rate;
1418c2ecf20Sopenharmony_ci	unsigned int lanes;
1428c2ecf20Sopenharmony_ci
1438c2ecf20Sopenharmony_ci	unsigned long rates[DP_MAX_SUPPORTED_RATES];
1448c2ecf20Sopenharmony_ci	unsigned int num_rates;
1458c2ecf20Sopenharmony_ci
1468c2ecf20Sopenharmony_ci	/**
1478c2ecf20Sopenharmony_ci	 * @ops: DP link operations
1488c2ecf20Sopenharmony_ci	 */
1498c2ecf20Sopenharmony_ci	const struct drm_dp_link_ops *ops;
1508c2ecf20Sopenharmony_ci
1518c2ecf20Sopenharmony_ci	/**
1528c2ecf20Sopenharmony_ci	 * @aux: DP AUX channel
1538c2ecf20Sopenharmony_ci	 */
1548c2ecf20Sopenharmony_ci	struct drm_dp_aux *aux;
1558c2ecf20Sopenharmony_ci
1568c2ecf20Sopenharmony_ci	/**
1578c2ecf20Sopenharmony_ci	 * @train: DP link training state
1588c2ecf20Sopenharmony_ci	 */
1598c2ecf20Sopenharmony_ci	struct drm_dp_link_train train;
1608c2ecf20Sopenharmony_ci};
1618c2ecf20Sopenharmony_ci
1628c2ecf20Sopenharmony_ciint drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
1638c2ecf20Sopenharmony_ciint drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
1648c2ecf20Sopenharmony_civoid drm_dp_link_update_rates(struct drm_dp_link *link);
1658c2ecf20Sopenharmony_ci
1668c2ecf20Sopenharmony_ciint drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
1678c2ecf20Sopenharmony_ciint drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
1688c2ecf20Sopenharmony_ciint drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
1698c2ecf20Sopenharmony_ciint drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
1708c2ecf20Sopenharmony_ciint drm_dp_link_choose(struct drm_dp_link *link,
1718c2ecf20Sopenharmony_ci		       const struct drm_display_mode *mode,
1728c2ecf20Sopenharmony_ci		       const struct drm_display_info *info);
1738c2ecf20Sopenharmony_ci
1748c2ecf20Sopenharmony_civoid drm_dp_link_train_init(struct drm_dp_link_train *train);
1758c2ecf20Sopenharmony_ciint drm_dp_link_train(struct drm_dp_link *link);
1768c2ecf20Sopenharmony_ci
1778c2ecf20Sopenharmony_ci#endif
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