1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) STMicroelectronics SA 2014 4 * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics. 5 */ 6 7#include <linux/clk.h> 8#include <linux/component.h> 9#include <linux/debugfs.h> 10#include <linux/hdmi.h> 11#include <linux/module.h> 12#include <linux/io.h> 13#include <linux/platform_device.h> 14#include <linux/reset.h> 15 16#include <drm/drm_atomic_helper.h> 17#include <drm/drm_bridge.h> 18#include <drm/drm_debugfs.h> 19#include <drm/drm_drv.h> 20#include <drm/drm_edid.h> 21#include <drm/drm_file.h> 22#include <drm/drm_print.h> 23#include <drm/drm_probe_helper.h> 24 25#include <sound/hdmi-codec.h> 26 27#include "sti_hdmi.h" 28#include "sti_hdmi_tx3g4c28phy.h" 29#include "sti_vtg.h" 30 31#define HDMI_CFG 0x0000 32#define HDMI_INT_EN 0x0004 33#define HDMI_INT_STA 0x0008 34#define HDMI_INT_CLR 0x000C 35#define HDMI_STA 0x0010 36#define HDMI_ACTIVE_VID_XMIN 0x0100 37#define HDMI_ACTIVE_VID_XMAX 0x0104 38#define HDMI_ACTIVE_VID_YMIN 0x0108 39#define HDMI_ACTIVE_VID_YMAX 0x010C 40#define HDMI_DFLT_CHL0_DAT 0x0110 41#define HDMI_DFLT_CHL1_DAT 0x0114 42#define HDMI_DFLT_CHL2_DAT 0x0118 43#define HDMI_AUDIO_CFG 0x0200 44#define HDMI_SPDIF_FIFO_STATUS 0x0204 45#define HDMI_SW_DI_1_HEAD_WORD 0x0210 46#define HDMI_SW_DI_1_PKT_WORD0 0x0214 47#define HDMI_SW_DI_1_PKT_WORD1 0x0218 48#define HDMI_SW_DI_1_PKT_WORD2 0x021C 49#define HDMI_SW_DI_1_PKT_WORD3 0x0220 50#define HDMI_SW_DI_1_PKT_WORD4 0x0224 51#define HDMI_SW_DI_1_PKT_WORD5 0x0228 52#define HDMI_SW_DI_1_PKT_WORD6 0x022C 53#define HDMI_SW_DI_CFG 0x0230 54#define HDMI_SAMPLE_FLAT_MASK 0x0244 55#define HDMI_AUDN 0x0400 56#define HDMI_AUD_CTS 0x0404 57#define HDMI_SW_DI_2_HEAD_WORD 0x0600 58#define HDMI_SW_DI_2_PKT_WORD0 0x0604 59#define HDMI_SW_DI_2_PKT_WORD1 0x0608 60#define HDMI_SW_DI_2_PKT_WORD2 0x060C 61#define HDMI_SW_DI_2_PKT_WORD3 0x0610 62#define HDMI_SW_DI_2_PKT_WORD4 0x0614 63#define HDMI_SW_DI_2_PKT_WORD5 0x0618 64#define HDMI_SW_DI_2_PKT_WORD6 0x061C 65#define HDMI_SW_DI_3_HEAD_WORD 0x0620 66#define HDMI_SW_DI_3_PKT_WORD0 0x0624 67#define HDMI_SW_DI_3_PKT_WORD1 0x0628 68#define HDMI_SW_DI_3_PKT_WORD2 0x062C 69#define HDMI_SW_DI_3_PKT_WORD3 0x0630 70#define HDMI_SW_DI_3_PKT_WORD4 0x0634 71#define HDMI_SW_DI_3_PKT_WORD5 0x0638 72#define HDMI_SW_DI_3_PKT_WORD6 0x063C 73 74#define HDMI_IFRAME_SLOT_AVI 1 75#define HDMI_IFRAME_SLOT_AUDIO 2 76#define HDMI_IFRAME_SLOT_VENDOR 3 77 78#define XCAT(prefix, x, suffix) prefix ## x ## suffix 79#define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD) 80#define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0) 81#define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1) 82#define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2) 83#define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3) 84#define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4) 85#define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5) 86#define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6) 87 88#define HDMI_SW_DI_MAX_WORD 7 89 90#define HDMI_IFRAME_DISABLED 0x0 91#define HDMI_IFRAME_SINGLE_SHOT 0x1 92#define HDMI_IFRAME_FIELD 0x2 93#define HDMI_IFRAME_FRAME 0x3 94#define HDMI_IFRAME_MASK 0x3 95#define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */ 96 97#define HDMI_CFG_DEVICE_EN BIT(0) 98#define HDMI_CFG_HDMI_NOT_DVI BIT(1) 99#define HDMI_CFG_HDCP_EN BIT(2) 100#define HDMI_CFG_ESS_NOT_OESS BIT(3) 101#define HDMI_CFG_H_SYNC_POL_NEG BIT(4) 102#define HDMI_CFG_V_SYNC_POL_NEG BIT(6) 103#define HDMI_CFG_422_EN BIT(8) 104#define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12) 105#define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13) 106#define HDMI_CFG_SW_RST_EN BIT(31) 107 108#define HDMI_INT_GLOBAL BIT(0) 109#define HDMI_INT_SW_RST BIT(1) 110#define HDMI_INT_PIX_CAP BIT(3) 111#define HDMI_INT_HOT_PLUG BIT(4) 112#define HDMI_INT_DLL_LCK BIT(5) 113#define HDMI_INT_NEW_FRAME BIT(6) 114#define HDMI_INT_GENCTRL_PKT BIT(7) 115#define HDMI_INT_AUDIO_FIFO_XRUN BIT(8) 116#define HDMI_INT_SINK_TERM_PRESENT BIT(11) 117 118#define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \ 119 | HDMI_INT_DLL_LCK \ 120 | HDMI_INT_HOT_PLUG \ 121 | HDMI_INT_GLOBAL) 122 123#define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \ 124 | HDMI_INT_AUDIO_FIFO_XRUN \ 125 | HDMI_INT_GENCTRL_PKT \ 126 | HDMI_INT_NEW_FRAME \ 127 | HDMI_INT_DLL_LCK \ 128 | HDMI_INT_HOT_PLUG \ 129 | HDMI_INT_PIX_CAP \ 130 | HDMI_INT_SW_RST \ 131 | HDMI_INT_GLOBAL) 132 133#define HDMI_STA_SW_RST BIT(1) 134 135#define HDMI_AUD_CFG_8CH BIT(0) 136#define HDMI_AUD_CFG_SPDIF_DIV_2 BIT(1) 137#define HDMI_AUD_CFG_SPDIF_DIV_3 BIT(2) 138#define HDMI_AUD_CFG_SPDIF_CLK_DIV_4 (BIT(1) | BIT(2)) 139#define HDMI_AUD_CFG_CTS_CLK_256FS BIT(12) 140#define HDMI_AUD_CFG_DTS_INVALID BIT(16) 141#define HDMI_AUD_CFG_ONE_BIT_INVALID (BIT(18) | BIT(19) | BIT(20) | BIT(21)) 142#define HDMI_AUD_CFG_CH12_VALID BIT(28) 143#define HDMI_AUD_CFG_CH34_VALID BIT(29) 144#define HDMI_AUD_CFG_CH56_VALID BIT(30) 145#define HDMI_AUD_CFG_CH78_VALID BIT(31) 146 147/* sample flat mask */ 148#define HDMI_SAMPLE_FLAT_NO 0 149#define HDMI_SAMPLE_FLAT_SP0 BIT(0) 150#define HDMI_SAMPLE_FLAT_SP1 BIT(1) 151#define HDMI_SAMPLE_FLAT_SP2 BIT(2) 152#define HDMI_SAMPLE_FLAT_SP3 BIT(3) 153#define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\ 154 HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3) 155 156#define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0) 157#define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8) 158#define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16) 159 160struct sti_hdmi_connector { 161 struct drm_connector drm_connector; 162 struct drm_encoder *encoder; 163 struct sti_hdmi *hdmi; 164 struct drm_property *colorspace_property; 165}; 166 167#define to_sti_hdmi_connector(x) \ 168 container_of(x, struct sti_hdmi_connector, drm_connector) 169 170u32 hdmi_read(struct sti_hdmi *hdmi, int offset) 171{ 172 return readl(hdmi->regs + offset); 173} 174 175void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset) 176{ 177 writel(val, hdmi->regs + offset); 178} 179 180/** 181 * HDMI interrupt handler threaded 182 * 183 * @irq: irq number 184 * @arg: connector structure 185 */ 186static irqreturn_t hdmi_irq_thread(int irq, void *arg) 187{ 188 struct sti_hdmi *hdmi = arg; 189 190 /* Hot plug/unplug IRQ */ 191 if (hdmi->irq_status & HDMI_INT_HOT_PLUG) { 192 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; 193 if (hdmi->drm_dev) 194 drm_helper_hpd_irq_event(hdmi->drm_dev); 195 } 196 197 /* Sw reset and PLL lock are exclusive so we can use the same 198 * event to signal them 199 */ 200 if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) { 201 hdmi->event_received = true; 202 wake_up_interruptible(&hdmi->wait_event); 203 } 204 205 /* Audio FIFO underrun IRQ */ 206 if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN) 207 DRM_INFO("Warning: audio FIFO underrun occurs!\n"); 208 209 return IRQ_HANDLED; 210} 211 212/** 213 * HDMI interrupt handler 214 * 215 * @irq: irq number 216 * @arg: connector structure 217 */ 218static irqreturn_t hdmi_irq(int irq, void *arg) 219{ 220 struct sti_hdmi *hdmi = arg; 221 222 /* read interrupt status */ 223 hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA); 224 225 /* clear interrupt status */ 226 hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR); 227 228 /* force sync bus write */ 229 hdmi_read(hdmi, HDMI_INT_STA); 230 231 return IRQ_WAKE_THREAD; 232} 233 234/** 235 * Set hdmi active area depending on the drm display mode selected 236 * 237 * @hdmi: pointer on the hdmi internal structure 238 */ 239static void hdmi_active_area(struct sti_hdmi *hdmi) 240{ 241 u32 xmin, xmax; 242 u32 ymin, ymax; 243 244 xmin = sti_vtg_get_pixel_number(hdmi->mode, 1); 245 xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay); 246 ymin = sti_vtg_get_line_number(hdmi->mode, 0); 247 ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1); 248 249 hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN); 250 hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX); 251 hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN); 252 hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX); 253} 254 255/** 256 * Overall hdmi configuration 257 * 258 * @hdmi: pointer on the hdmi internal structure 259 */ 260static void hdmi_config(struct sti_hdmi *hdmi) 261{ 262 u32 conf; 263 264 DRM_DEBUG_DRIVER("\n"); 265 266 /* Clear overrun and underrun fifo */ 267 conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR; 268 269 /* Select encryption type and the framing mode */ 270 conf |= HDMI_CFG_ESS_NOT_OESS; 271 if (hdmi->hdmi_monitor) 272 conf |= HDMI_CFG_HDMI_NOT_DVI; 273 274 /* Set Hsync polarity */ 275 if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) { 276 DRM_DEBUG_DRIVER("H Sync Negative\n"); 277 conf |= HDMI_CFG_H_SYNC_POL_NEG; 278 } 279 280 /* Set Vsync polarity */ 281 if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) { 282 DRM_DEBUG_DRIVER("V Sync Negative\n"); 283 conf |= HDMI_CFG_V_SYNC_POL_NEG; 284 } 285 286 /* Enable HDMI */ 287 conf |= HDMI_CFG_DEVICE_EN; 288 289 hdmi_write(hdmi, conf, HDMI_CFG); 290} 291 292/* 293 * Helper to reset info frame 294 * 295 * @hdmi: pointer on the hdmi internal structure 296 * @slot: infoframe to reset 297 */ 298static void hdmi_infoframe_reset(struct sti_hdmi *hdmi, 299 u32 slot) 300{ 301 u32 val, i; 302 u32 head_offset, pack_offset; 303 304 switch (slot) { 305 case HDMI_IFRAME_SLOT_AVI: 306 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); 307 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); 308 break; 309 case HDMI_IFRAME_SLOT_AUDIO: 310 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); 311 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); 312 break; 313 case HDMI_IFRAME_SLOT_VENDOR: 314 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); 315 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); 316 break; 317 default: 318 DRM_ERROR("unsupported infoframe slot: %#x\n", slot); 319 return; 320 } 321 322 /* Disable transmission for the selected slot */ 323 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 324 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); 325 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 326 327 /* Reset info frame registers */ 328 hdmi_write(hdmi, 0x0, head_offset); 329 for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32)) 330 hdmi_write(hdmi, 0x0, pack_offset + i); 331} 332 333/** 334 * Helper to concatenate infoframe in 32 bits word 335 * 336 * @ptr: pointer on the hdmi internal structure 337 * @size: size to write 338 */ 339static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size) 340{ 341 unsigned long value = 0; 342 size_t i; 343 344 for (i = size; i > 0; i--) 345 value = (value << 8) | ptr[i - 1]; 346 347 return value; 348} 349 350/** 351 * Helper to write info frame 352 * 353 * @hdmi: pointer on the hdmi internal structure 354 * @data: infoframe to write 355 * @size: size to write 356 */ 357static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi, 358 const u8 *data, 359 size_t size) 360{ 361 const u8 *ptr = data; 362 u32 val, slot, mode, i; 363 u32 head_offset, pack_offset; 364 365 switch (*ptr) { 366 case HDMI_INFOFRAME_TYPE_AVI: 367 slot = HDMI_IFRAME_SLOT_AVI; 368 mode = HDMI_IFRAME_FIELD; 369 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI); 370 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI); 371 break; 372 case HDMI_INFOFRAME_TYPE_AUDIO: 373 slot = HDMI_IFRAME_SLOT_AUDIO; 374 mode = HDMI_IFRAME_FRAME; 375 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO); 376 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO); 377 break; 378 case HDMI_INFOFRAME_TYPE_VENDOR: 379 slot = HDMI_IFRAME_SLOT_VENDOR; 380 mode = HDMI_IFRAME_FRAME; 381 head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR); 382 pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR); 383 break; 384 default: 385 DRM_ERROR("unsupported infoframe type: %#x\n", *ptr); 386 return; 387 } 388 389 /* Disable transmission slot for updated infoframe */ 390 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 391 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot); 392 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 393 394 val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++); 395 val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++); 396 val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++); 397 writel(val, hdmi->regs + head_offset); 398 399 /* 400 * Each subpack contains 4 bytes 401 * The First Bytes of the first subpacket must contain the checksum 402 * Packet size is increase by one. 403 */ 404 size = size - HDMI_INFOFRAME_HEADER_SIZE + 1; 405 for (i = 0; i < size; i += sizeof(u32)) { 406 size_t num; 407 408 num = min_t(size_t, size - i, sizeof(u32)); 409 val = hdmi_infoframe_subpack(ptr, num); 410 ptr += sizeof(u32); 411 writel(val, hdmi->regs + pack_offset + i); 412 } 413 414 /* Enable transmission slot for updated infoframe */ 415 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 416 val |= HDMI_IFRAME_CFG_DI_N(mode, slot); 417 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 418} 419 420/** 421 * Prepare and configure the AVI infoframe 422 * 423 * AVI infoframe are transmitted at least once per two video field and 424 * contains information about HDMI transmission mode such as color space, 425 * colorimetry, ... 426 * 427 * @hdmi: pointer on the hdmi internal structure 428 * 429 * Return negative value if error occurs 430 */ 431static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi) 432{ 433 struct drm_display_mode *mode = &hdmi->mode; 434 struct hdmi_avi_infoframe infoframe; 435 u8 buffer[HDMI_INFOFRAME_SIZE(AVI)]; 436 int ret; 437 438 DRM_DEBUG_DRIVER("\n"); 439 440 ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, 441 hdmi->drm_connector, mode); 442 if (ret < 0) { 443 DRM_ERROR("failed to setup AVI infoframe: %d\n", ret); 444 return ret; 445 } 446 447 /* fixed infoframe configuration not linked to the mode */ 448 infoframe.colorspace = hdmi->colorspace; 449 infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 450 infoframe.colorimetry = HDMI_COLORIMETRY_NONE; 451 452 ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer)); 453 if (ret < 0) { 454 DRM_ERROR("failed to pack AVI infoframe: %d\n", ret); 455 return ret; 456 } 457 458 hdmi_infoframe_write_infopack(hdmi, buffer, ret); 459 460 return 0; 461} 462 463/** 464 * Prepare and configure the AUDIO infoframe 465 * 466 * AUDIO infoframe are transmitted once per frame and 467 * contains information about HDMI transmission mode such as audio codec, 468 * sample size, ... 469 * 470 * @hdmi: pointer on the hdmi internal structure 471 * 472 * Return negative value if error occurs 473 */ 474static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi) 475{ 476 struct hdmi_audio_params *audio = &hdmi->audio; 477 u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)]; 478 int ret, val; 479 480 DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__, 481 audio->enabled ? "enable" : "disable"); 482 if (audio->enabled) { 483 /* set audio parameters stored*/ 484 ret = hdmi_audio_infoframe_pack(&audio->cea, buffer, 485 sizeof(buffer)); 486 if (ret < 0) { 487 DRM_ERROR("failed to pack audio infoframe: %d\n", ret); 488 return ret; 489 } 490 hdmi_infoframe_write_infopack(hdmi, buffer, ret); 491 } else { 492 /*disable audio info frame transmission */ 493 val = hdmi_read(hdmi, HDMI_SW_DI_CFG); 494 val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 495 HDMI_IFRAME_SLOT_AUDIO); 496 hdmi_write(hdmi, val, HDMI_SW_DI_CFG); 497 } 498 499 return 0; 500} 501 502/* 503 * Prepare and configure the VS infoframe 504 * 505 * Vendor Specific infoframe are transmitted once per frame and 506 * contains vendor specific information. 507 * 508 * @hdmi: pointer on the hdmi internal structure 509 * 510 * Return negative value if error occurs 511 */ 512#define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6 513static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi) 514{ 515 struct drm_display_mode *mode = &hdmi->mode; 516 struct hdmi_vendor_infoframe infoframe; 517 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE]; 518 int ret; 519 520 DRM_DEBUG_DRIVER("\n"); 521 522 ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe, 523 hdmi->drm_connector, 524 mode); 525 if (ret < 0) { 526 /* 527 * Going into that statement does not means vendor infoframe 528 * fails. It just informed us that vendor infoframe is not 529 * needed for the selected mode. Only 4k or stereoscopic 3D 530 * mode requires vendor infoframe. So just simply return 0. 531 */ 532 return 0; 533 } 534 535 ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer)); 536 if (ret < 0) { 537 DRM_ERROR("failed to pack VS infoframe: %d\n", ret); 538 return ret; 539 } 540 541 hdmi_infoframe_write_infopack(hdmi, buffer, ret); 542 543 return 0; 544} 545 546#define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */ 547 548/** 549 * Software reset of the hdmi subsystem 550 * 551 * @hdmi: pointer on the hdmi internal structure 552 * 553 */ 554static void hdmi_swreset(struct sti_hdmi *hdmi) 555{ 556 u32 val; 557 558 DRM_DEBUG_DRIVER("\n"); 559 560 /* Enable hdmi_audio clock only during hdmi reset */ 561 if (clk_prepare_enable(hdmi->clk_audio)) 562 DRM_INFO("Failed to prepare/enable hdmi_audio clk\n"); 563 564 /* Sw reset */ 565 hdmi->event_received = false; 566 567 val = hdmi_read(hdmi, HDMI_CFG); 568 val |= HDMI_CFG_SW_RST_EN; 569 hdmi_write(hdmi, val, HDMI_CFG); 570 571 /* Wait reset completed */ 572 wait_event_interruptible_timeout(hdmi->wait_event, 573 hdmi->event_received, 574 msecs_to_jiffies 575 (HDMI_TIMEOUT_SWRESET)); 576 577 /* 578 * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is 579 * set to '1' and clk_audio is running. 580 */ 581 if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0) 582 DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n"); 583 584 val = hdmi_read(hdmi, HDMI_CFG); 585 val &= ~HDMI_CFG_SW_RST_EN; 586 hdmi_write(hdmi, val, HDMI_CFG); 587 588 /* Disable hdmi_audio clock. Not used anymore for drm purpose */ 589 clk_disable_unprepare(hdmi->clk_audio); 590} 591 592#define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2) 593#define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2) 594#define DBGFS_DUMP(str, reg) seq_printf(s, "%s %-25s 0x%08X", str, #reg, \ 595 hdmi_read(hdmi, reg)) 596#define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot)) 597 598static void hdmi_dbg_cfg(struct seq_file *s, int val) 599{ 600 int tmp; 601 602 seq_putc(s, '\t'); 603 tmp = val & HDMI_CFG_HDMI_NOT_DVI; 604 DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI"); 605 seq_puts(s, "\t\t\t\t\t"); 606 tmp = val & HDMI_CFG_HDCP_EN; 607 DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable"); 608 seq_puts(s, "\t\t\t\t\t"); 609 tmp = val & HDMI_CFG_ESS_NOT_OESS; 610 DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable"); 611 seq_puts(s, "\t\t\t\t\t"); 612 tmp = val & HDMI_CFG_H_SYNC_POL_NEG; 613 DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal"); 614 seq_puts(s, "\t\t\t\t\t"); 615 tmp = val & HDMI_CFG_V_SYNC_POL_NEG; 616 DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal"); 617 seq_puts(s, "\t\t\t\t\t"); 618 tmp = val & HDMI_CFG_422_EN; 619 DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable"); 620} 621 622static void hdmi_dbg_sta(struct seq_file *s, int val) 623{ 624 int tmp; 625 626 seq_putc(s, '\t'); 627 tmp = (val & HDMI_STA_DLL_LCK); 628 DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked"); 629 seq_puts(s, "\t\t\t\t\t"); 630 tmp = (val & HDMI_STA_HOT_PLUG); 631 DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected"); 632} 633 634static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val) 635{ 636 int tmp; 637 char *const en_di[] = {"no transmission", 638 "single transmission", 639 "once every field", 640 "once every frame"}; 641 642 seq_putc(s, '\t'); 643 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1)); 644 DBGFS_PRINT_STR("Data island 1:", en_di[tmp]); 645 seq_puts(s, "\t\t\t\t\t"); 646 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4; 647 DBGFS_PRINT_STR("Data island 2:", en_di[tmp]); 648 seq_puts(s, "\t\t\t\t\t"); 649 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8; 650 DBGFS_PRINT_STR("Data island 3:", en_di[tmp]); 651 seq_puts(s, "\t\t\t\t\t"); 652 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12; 653 DBGFS_PRINT_STR("Data island 4:", en_di[tmp]); 654 seq_puts(s, "\t\t\t\t\t"); 655 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16; 656 DBGFS_PRINT_STR("Data island 5:", en_di[tmp]); 657 seq_puts(s, "\t\t\t\t\t"); 658 tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20; 659 DBGFS_PRINT_STR("Data island 6:", en_di[tmp]); 660} 661 662static int hdmi_dbg_show(struct seq_file *s, void *data) 663{ 664 struct drm_info_node *node = s->private; 665 struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data; 666 667 seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs); 668 DBGFS_DUMP("\n", HDMI_CFG); 669 hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG)); 670 DBGFS_DUMP("", HDMI_INT_EN); 671 DBGFS_DUMP("\n", HDMI_STA); 672 hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA)); 673 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN); 674 seq_putc(s, '\t'); 675 DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN)); 676 DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX); 677 seq_putc(s, '\t'); 678 DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX)); 679 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN); 680 seq_putc(s, '\t'); 681 DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN)); 682 DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX); 683 seq_putc(s, '\t'); 684 DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX)); 685 DBGFS_DUMP("", HDMI_SW_DI_CFG); 686 hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG)); 687 688 DBGFS_DUMP("\n", HDMI_AUDIO_CFG); 689 DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS); 690 DBGFS_DUMP("\n", HDMI_AUDN); 691 692 seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):", 693 HDMI_IFRAME_SLOT_AVI); 694 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI); 695 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI); 696 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI); 697 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI); 698 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI); 699 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI); 700 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI); 701 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI); 702 seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):", 703 HDMI_IFRAME_SLOT_AUDIO); 704 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO); 705 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO); 706 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO); 707 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO); 708 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO); 709 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO); 710 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO); 711 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO); 712 seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):", 713 HDMI_IFRAME_SLOT_VENDOR); 714 DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR); 715 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR); 716 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR); 717 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR); 718 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR); 719 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR); 720 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR); 721 DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR); 722 seq_putc(s, '\n'); 723 return 0; 724} 725 726static struct drm_info_list hdmi_debugfs_files[] = { 727 { "hdmi", hdmi_dbg_show, 0, NULL }, 728}; 729 730static void hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor) 731{ 732 unsigned int i; 733 734 for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++) 735 hdmi_debugfs_files[i].data = hdmi; 736 737 drm_debugfs_create_files(hdmi_debugfs_files, 738 ARRAY_SIZE(hdmi_debugfs_files), 739 minor->debugfs_root, minor); 740} 741 742static void sti_hdmi_disable(struct drm_bridge *bridge) 743{ 744 struct sti_hdmi *hdmi = bridge->driver_private; 745 746 u32 val = hdmi_read(hdmi, HDMI_CFG); 747 748 if (!hdmi->enabled) 749 return; 750 751 DRM_DEBUG_DRIVER("\n"); 752 753 /* Disable HDMI */ 754 val &= ~HDMI_CFG_DEVICE_EN; 755 hdmi_write(hdmi, val, HDMI_CFG); 756 757 hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR); 758 759 /* Stop the phy */ 760 hdmi->phy_ops->stop(hdmi); 761 762 /* Reset info frame transmission */ 763 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI); 764 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO); 765 hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR); 766 767 /* Set the default channel data to be a dark red */ 768 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT); 769 hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT); 770 hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT); 771 772 /* Disable/unprepare hdmi clock */ 773 clk_disable_unprepare(hdmi->clk_phy); 774 clk_disable_unprepare(hdmi->clk_tmds); 775 clk_disable_unprepare(hdmi->clk_pix); 776 777 hdmi->enabled = false; 778 779 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID); 780} 781 782/** 783 * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent 784 * clocks. None-coherent clocks means that audio and TMDS clocks have not the 785 * same source (drifts between clocks). In this case assumption is that CTS is 786 * automatically calculated by hardware. 787 * 788 * @audio_fs: audio frame clock frequency in Hz 789 * 790 * Values computed are based on table described in HDMI specification 1.4b 791 * 792 * Returns n value. 793 */ 794static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs) 795{ 796 unsigned int n; 797 798 switch (audio_fs) { 799 case 32000: 800 n = 4096; 801 break; 802 case 44100: 803 n = 6272; 804 break; 805 case 48000: 806 n = 6144; 807 break; 808 case 88200: 809 n = 6272 * 2; 810 break; 811 case 96000: 812 n = 6144 * 2; 813 break; 814 case 176400: 815 n = 6272 * 4; 816 break; 817 case 192000: 818 n = 6144 * 4; 819 break; 820 default: 821 /* Not pre-defined, recommended value: 128 * fs / 1000 */ 822 n = (audio_fs * 128) / 1000; 823 } 824 825 return n; 826} 827 828static int hdmi_audio_configure(struct sti_hdmi *hdmi) 829{ 830 int audio_cfg, n; 831 struct hdmi_audio_params *params = &hdmi->audio; 832 struct hdmi_audio_infoframe *info = ¶ms->cea; 833 834 DRM_DEBUG_DRIVER("\n"); 835 836 if (!hdmi->enabled) 837 return 0; 838 839 /* update N parameter */ 840 n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate); 841 842 DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n", 843 params->sample_rate, hdmi->mode.clock * 1000, n); 844 hdmi_write(hdmi, n, HDMI_AUDN); 845 846 /* update HDMI registers according to configuration */ 847 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | 848 HDMI_AUD_CFG_ONE_BIT_INVALID; 849 850 switch (info->channels) { 851 case 8: 852 audio_cfg |= HDMI_AUD_CFG_CH78_VALID; 853 fallthrough; 854 case 6: 855 audio_cfg |= HDMI_AUD_CFG_CH56_VALID; 856 fallthrough; 857 case 4: 858 audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH; 859 fallthrough; 860 case 2: 861 audio_cfg |= HDMI_AUD_CFG_CH12_VALID; 862 break; 863 default: 864 DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n", 865 info->channels); 866 return -EINVAL; 867 } 868 869 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); 870 871 return hdmi_audio_infoframe_config(hdmi); 872} 873 874static void sti_hdmi_pre_enable(struct drm_bridge *bridge) 875{ 876 struct sti_hdmi *hdmi = bridge->driver_private; 877 878 DRM_DEBUG_DRIVER("\n"); 879 880 if (hdmi->enabled) 881 return; 882 883 /* Prepare/enable clocks */ 884 if (clk_prepare_enable(hdmi->clk_pix)) 885 DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n"); 886 if (clk_prepare_enable(hdmi->clk_tmds)) 887 DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n"); 888 if (clk_prepare_enable(hdmi->clk_phy)) 889 DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n"); 890 891 hdmi->enabled = true; 892 893 /* Program hdmi serializer and start phy */ 894 if (!hdmi->phy_ops->start(hdmi)) { 895 DRM_ERROR("Unable to start hdmi phy\n"); 896 return; 897 } 898 899 /* Program hdmi active area */ 900 hdmi_active_area(hdmi); 901 902 /* Enable working interrupts */ 903 hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN); 904 905 /* Program hdmi config */ 906 hdmi_config(hdmi); 907 908 /* Program AVI infoframe */ 909 if (hdmi_avi_infoframe_config(hdmi)) 910 DRM_ERROR("Unable to configure AVI infoframe\n"); 911 912 if (hdmi->audio.enabled) { 913 if (hdmi_audio_configure(hdmi)) 914 DRM_ERROR("Unable to configure audio\n"); 915 } else { 916 hdmi_audio_infoframe_config(hdmi); 917 } 918 919 /* Program VS infoframe */ 920 if (hdmi_vendor_infoframe_config(hdmi)) 921 DRM_ERROR("Unable to configure VS infoframe\n"); 922 923 /* Sw reset */ 924 hdmi_swreset(hdmi); 925} 926 927static void sti_hdmi_set_mode(struct drm_bridge *bridge, 928 const struct drm_display_mode *mode, 929 const struct drm_display_mode *adjusted_mode) 930{ 931 struct sti_hdmi *hdmi = bridge->driver_private; 932 int ret; 933 934 DRM_DEBUG_DRIVER("\n"); 935 936 /* Copy the drm display mode in the connector local structure */ 937 drm_mode_copy(&hdmi->mode, mode); 938 939 /* Update clock framerate according to the selected mode */ 940 ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000); 941 if (ret < 0) { 942 DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n", 943 mode->clock * 1000); 944 return; 945 } 946 ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000); 947 if (ret < 0) { 948 DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n", 949 mode->clock * 1000); 950 return; 951 } 952} 953 954static void sti_hdmi_bridge_nope(struct drm_bridge *bridge) 955{ 956 /* do nothing */ 957} 958 959static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = { 960 .pre_enable = sti_hdmi_pre_enable, 961 .enable = sti_hdmi_bridge_nope, 962 .disable = sti_hdmi_disable, 963 .post_disable = sti_hdmi_bridge_nope, 964 .mode_set = sti_hdmi_set_mode, 965}; 966 967static int sti_hdmi_connector_get_modes(struct drm_connector *connector) 968{ 969 struct sti_hdmi_connector *hdmi_connector 970 = to_sti_hdmi_connector(connector); 971 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 972 struct edid *edid; 973 int count; 974 975 DRM_DEBUG_DRIVER("\n"); 976 977 edid = drm_get_edid(connector, hdmi->ddc_adapt); 978 if (!edid) 979 goto fail; 980 981 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid); 982 DRM_DEBUG_KMS("%s : %dx%d cm\n", 983 (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"), 984 edid->width_cm, edid->height_cm); 985 cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid); 986 987 count = drm_add_edid_modes(connector, edid); 988 drm_connector_update_edid_property(connector, edid); 989 990 kfree(edid); 991 return count; 992 993fail: 994 DRM_ERROR("Can't read HDMI EDID\n"); 995 return 0; 996} 997 998#define CLK_TOLERANCE_HZ 50 999 1000static enum drm_mode_status 1001sti_hdmi_connector_mode_valid(struct drm_connector *connector, 1002 struct drm_display_mode *mode) 1003{ 1004 int target = mode->clock * 1000; 1005 int target_min = target - CLK_TOLERANCE_HZ; 1006 int target_max = target + CLK_TOLERANCE_HZ; 1007 int result; 1008 struct sti_hdmi_connector *hdmi_connector 1009 = to_sti_hdmi_connector(connector); 1010 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1011 1012 1013 result = clk_round_rate(hdmi->clk_pix, target); 1014 1015 DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n", 1016 target, result); 1017 1018 if ((result < target_min) || (result > target_max)) { 1019 DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target); 1020 return MODE_BAD; 1021 } 1022 1023 return MODE_OK; 1024} 1025 1026static const 1027struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = { 1028 .get_modes = sti_hdmi_connector_get_modes, 1029 .mode_valid = sti_hdmi_connector_mode_valid, 1030}; 1031 1032/* get detection status of display device */ 1033static enum drm_connector_status 1034sti_hdmi_connector_detect(struct drm_connector *connector, bool force) 1035{ 1036 struct sti_hdmi_connector *hdmi_connector 1037 = to_sti_hdmi_connector(connector); 1038 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1039 1040 DRM_DEBUG_DRIVER("\n"); 1041 1042 if (hdmi->hpd) { 1043 DRM_DEBUG_DRIVER("hdmi cable connected\n"); 1044 return connector_status_connected; 1045 } 1046 1047 DRM_DEBUG_DRIVER("hdmi cable disconnected\n"); 1048 cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID); 1049 return connector_status_disconnected; 1050} 1051 1052static void sti_hdmi_connector_init_property(struct drm_device *drm_dev, 1053 struct drm_connector *connector) 1054{ 1055 struct sti_hdmi_connector *hdmi_connector 1056 = to_sti_hdmi_connector(connector); 1057 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1058 struct drm_property *prop; 1059 1060 /* colorspace property */ 1061 hdmi->colorspace = DEFAULT_COLORSPACE_MODE; 1062 prop = drm_property_create_enum(drm_dev, 0, "colorspace", 1063 colorspace_mode_names, 1064 ARRAY_SIZE(colorspace_mode_names)); 1065 if (!prop) { 1066 DRM_ERROR("fails to create colorspace property\n"); 1067 return; 1068 } 1069 hdmi_connector->colorspace_property = prop; 1070 drm_object_attach_property(&connector->base, prop, hdmi->colorspace); 1071} 1072 1073static int 1074sti_hdmi_connector_set_property(struct drm_connector *connector, 1075 struct drm_connector_state *state, 1076 struct drm_property *property, 1077 uint64_t val) 1078{ 1079 struct sti_hdmi_connector *hdmi_connector 1080 = to_sti_hdmi_connector(connector); 1081 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1082 1083 if (property == hdmi_connector->colorspace_property) { 1084 hdmi->colorspace = val; 1085 return 0; 1086 } 1087 1088 DRM_ERROR("failed to set hdmi connector property\n"); 1089 return -EINVAL; 1090} 1091 1092static int 1093sti_hdmi_connector_get_property(struct drm_connector *connector, 1094 const struct drm_connector_state *state, 1095 struct drm_property *property, 1096 uint64_t *val) 1097{ 1098 struct sti_hdmi_connector *hdmi_connector 1099 = to_sti_hdmi_connector(connector); 1100 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1101 1102 if (property == hdmi_connector->colorspace_property) { 1103 *val = hdmi->colorspace; 1104 return 0; 1105 } 1106 1107 DRM_ERROR("failed to get hdmi connector property\n"); 1108 return -EINVAL; 1109} 1110 1111static int sti_hdmi_late_register(struct drm_connector *connector) 1112{ 1113 struct sti_hdmi_connector *hdmi_connector 1114 = to_sti_hdmi_connector(connector); 1115 struct sti_hdmi *hdmi = hdmi_connector->hdmi; 1116 1117 hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary); 1118 1119 return 0; 1120} 1121 1122static const struct drm_connector_funcs sti_hdmi_connector_funcs = { 1123 .fill_modes = drm_helper_probe_single_connector_modes, 1124 .detect = sti_hdmi_connector_detect, 1125 .destroy = drm_connector_cleanup, 1126 .reset = drm_atomic_helper_connector_reset, 1127 .atomic_set_property = sti_hdmi_connector_set_property, 1128 .atomic_get_property = sti_hdmi_connector_get_property, 1129 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1130 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1131 .late_register = sti_hdmi_late_register, 1132}; 1133 1134static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev) 1135{ 1136 struct drm_encoder *encoder; 1137 1138 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1139 if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) 1140 return encoder; 1141 } 1142 1143 return NULL; 1144} 1145 1146static void hdmi_audio_shutdown(struct device *dev, void *data) 1147{ 1148 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1149 int audio_cfg; 1150 1151 DRM_DEBUG_DRIVER("\n"); 1152 1153 /* disable audio */ 1154 audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID | 1155 HDMI_AUD_CFG_ONE_BIT_INVALID; 1156 hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG); 1157 1158 hdmi->audio.enabled = false; 1159 hdmi_audio_infoframe_config(hdmi); 1160} 1161 1162static int hdmi_audio_hw_params(struct device *dev, 1163 void *data, 1164 struct hdmi_codec_daifmt *daifmt, 1165 struct hdmi_codec_params *params) 1166{ 1167 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1168 int ret; 1169 1170 DRM_DEBUG_DRIVER("\n"); 1171 1172 if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv || 1173 daifmt->frame_clk_inv || daifmt->bit_clk_master || 1174 daifmt->frame_clk_master) { 1175 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1176 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1177 daifmt->bit_clk_master, 1178 daifmt->frame_clk_master); 1179 return -EINVAL; 1180 } 1181 1182 hdmi->audio.sample_width = params->sample_width; 1183 hdmi->audio.sample_rate = params->sample_rate; 1184 hdmi->audio.cea = params->cea; 1185 1186 hdmi->audio.enabled = true; 1187 1188 ret = hdmi_audio_configure(hdmi); 1189 if (ret < 0) 1190 return ret; 1191 1192 return 0; 1193} 1194 1195static int hdmi_audio_mute(struct device *dev, void *data, 1196 bool enable, int direction) 1197{ 1198 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1199 1200 DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable"); 1201 1202 if (enable) 1203 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK); 1204 else 1205 hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK); 1206 1207 return 0; 1208} 1209 1210static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len) 1211{ 1212 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1213 struct drm_connector *connector = hdmi->drm_connector; 1214 1215 DRM_DEBUG_DRIVER("\n"); 1216 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1217 1218 return 0; 1219} 1220 1221static const struct hdmi_codec_ops audio_codec_ops = { 1222 .hw_params = hdmi_audio_hw_params, 1223 .audio_shutdown = hdmi_audio_shutdown, 1224 .mute_stream = hdmi_audio_mute, 1225 .get_eld = hdmi_audio_get_eld, 1226 .no_capture_mute = 1, 1227}; 1228 1229static int sti_hdmi_register_audio_driver(struct device *dev, 1230 struct sti_hdmi *hdmi) 1231{ 1232 struct hdmi_codec_pdata codec_data = { 1233 .ops = &audio_codec_ops, 1234 .max_i2s_channels = 8, 1235 .i2s = 1, 1236 }; 1237 1238 DRM_DEBUG_DRIVER("\n"); 1239 1240 hdmi->audio.enabled = false; 1241 1242 hdmi->audio_pdev = platform_device_register_data( 1243 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1244 &codec_data, sizeof(codec_data)); 1245 1246 if (IS_ERR(hdmi->audio_pdev)) 1247 return PTR_ERR(hdmi->audio_pdev); 1248 1249 DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev)); 1250 1251 return 0; 1252} 1253 1254static int sti_hdmi_bind(struct device *dev, struct device *master, void *data) 1255{ 1256 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1257 struct drm_device *drm_dev = data; 1258 struct drm_encoder *encoder; 1259 struct sti_hdmi_connector *connector; 1260 struct cec_connector_info conn_info; 1261 struct drm_connector *drm_connector; 1262 struct drm_bridge *bridge; 1263 int err; 1264 1265 /* Set the drm device handle */ 1266 hdmi->drm_dev = drm_dev; 1267 1268 encoder = sti_hdmi_find_encoder(drm_dev); 1269 if (!encoder) 1270 return -EINVAL; 1271 1272 connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL); 1273 if (!connector) 1274 return -EINVAL; 1275 1276 connector->hdmi = hdmi; 1277 1278 bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL); 1279 if (!bridge) 1280 return -EINVAL; 1281 1282 bridge->driver_private = hdmi; 1283 bridge->funcs = &sti_hdmi_bridge_funcs; 1284 drm_bridge_attach(encoder, bridge, NULL, 0); 1285 1286 connector->encoder = encoder; 1287 1288 drm_connector = (struct drm_connector *)connector; 1289 1290 drm_connector->polled = DRM_CONNECTOR_POLL_HPD; 1291 1292 drm_connector_init_with_ddc(drm_dev, drm_connector, 1293 &sti_hdmi_connector_funcs, 1294 DRM_MODE_CONNECTOR_HDMIA, 1295 hdmi->ddc_adapt); 1296 drm_connector_helper_add(drm_connector, 1297 &sti_hdmi_connector_helper_funcs); 1298 1299 /* initialise property */ 1300 sti_hdmi_connector_init_property(drm_dev, drm_connector); 1301 1302 hdmi->drm_connector = drm_connector; 1303 1304 err = drm_connector_attach_encoder(drm_connector, encoder); 1305 if (err) { 1306 DRM_ERROR("Failed to attach a connector to a encoder\n"); 1307 goto err_sysfs; 1308 } 1309 1310 err = sti_hdmi_register_audio_driver(dev, hdmi); 1311 if (err) { 1312 DRM_ERROR("Failed to attach an audio codec\n"); 1313 goto err_sysfs; 1314 } 1315 1316 /* Initialize audio infoframe */ 1317 err = hdmi_audio_infoframe_init(&hdmi->audio.cea); 1318 if (err) { 1319 DRM_ERROR("Failed to init audio infoframe\n"); 1320 goto err_sysfs; 1321 } 1322 1323 cec_fill_conn_info_from_drm(&conn_info, drm_connector); 1324 hdmi->notifier = cec_notifier_conn_register(&hdmi->dev, NULL, 1325 &conn_info); 1326 if (!hdmi->notifier) { 1327 hdmi->drm_connector = NULL; 1328 return -ENOMEM; 1329 } 1330 1331 /* Enable default interrupts */ 1332 hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN); 1333 1334 return 0; 1335 1336err_sysfs: 1337 hdmi->drm_connector = NULL; 1338 return -EINVAL; 1339} 1340 1341static void sti_hdmi_unbind(struct device *dev, 1342 struct device *master, void *data) 1343{ 1344 struct sti_hdmi *hdmi = dev_get_drvdata(dev); 1345 1346 cec_notifier_conn_unregister(hdmi->notifier); 1347} 1348 1349static const struct component_ops sti_hdmi_ops = { 1350 .bind = sti_hdmi_bind, 1351 .unbind = sti_hdmi_unbind, 1352}; 1353 1354static const struct of_device_id hdmi_of_match[] = { 1355 { 1356 .compatible = "st,stih407-hdmi", 1357 .data = &tx3g4c28phy_ops, 1358 }, { 1359 /* end node */ 1360 } 1361}; 1362MODULE_DEVICE_TABLE(of, hdmi_of_match); 1363 1364static int sti_hdmi_probe(struct platform_device *pdev) 1365{ 1366 struct device *dev = &pdev->dev; 1367 struct sti_hdmi *hdmi; 1368 struct device_node *np = dev->of_node; 1369 struct resource *res; 1370 struct device_node *ddc; 1371 int ret; 1372 1373 DRM_INFO("%s\n", __func__); 1374 1375 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1376 if (!hdmi) 1377 return -ENOMEM; 1378 1379 ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0); 1380 if (ddc) { 1381 hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc); 1382 of_node_put(ddc); 1383 if (!hdmi->ddc_adapt) 1384 return -EPROBE_DEFER; 1385 } 1386 1387 hdmi->dev = pdev->dev; 1388 1389 /* Get resources */ 1390 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg"); 1391 if (!res) { 1392 DRM_ERROR("Invalid hdmi resource\n"); 1393 ret = -ENOMEM; 1394 goto release_adapter; 1395 } 1396 hdmi->regs = devm_ioremap(dev, res->start, resource_size(res)); 1397 if (!hdmi->regs) { 1398 ret = -ENOMEM; 1399 goto release_adapter; 1400 } 1401 1402 hdmi->phy_ops = (struct hdmi_phy_ops *) 1403 of_match_node(hdmi_of_match, np)->data; 1404 1405 /* Get clock resources */ 1406 hdmi->clk_pix = devm_clk_get(dev, "pix"); 1407 if (IS_ERR(hdmi->clk_pix)) { 1408 DRM_ERROR("Cannot get hdmi_pix clock\n"); 1409 ret = PTR_ERR(hdmi->clk_pix); 1410 goto release_adapter; 1411 } 1412 1413 hdmi->clk_tmds = devm_clk_get(dev, "tmds"); 1414 if (IS_ERR(hdmi->clk_tmds)) { 1415 DRM_ERROR("Cannot get hdmi_tmds clock\n"); 1416 ret = PTR_ERR(hdmi->clk_tmds); 1417 goto release_adapter; 1418 } 1419 1420 hdmi->clk_phy = devm_clk_get(dev, "phy"); 1421 if (IS_ERR(hdmi->clk_phy)) { 1422 DRM_ERROR("Cannot get hdmi_phy clock\n"); 1423 ret = PTR_ERR(hdmi->clk_phy); 1424 goto release_adapter; 1425 } 1426 1427 hdmi->clk_audio = devm_clk_get(dev, "audio"); 1428 if (IS_ERR(hdmi->clk_audio)) { 1429 DRM_ERROR("Cannot get hdmi_audio clock\n"); 1430 ret = PTR_ERR(hdmi->clk_audio); 1431 goto release_adapter; 1432 } 1433 1434 hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG; 1435 1436 init_waitqueue_head(&hdmi->wait_event); 1437 1438 hdmi->irq = platform_get_irq_byname(pdev, "irq"); 1439 if (hdmi->irq < 0) { 1440 DRM_ERROR("Cannot get HDMI irq\n"); 1441 ret = hdmi->irq; 1442 goto release_adapter; 1443 } 1444 1445 ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq, 1446 hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi); 1447 if (ret) { 1448 DRM_ERROR("Failed to register HDMI interrupt\n"); 1449 goto release_adapter; 1450 } 1451 1452 hdmi->reset = devm_reset_control_get(dev, "hdmi"); 1453 /* Take hdmi out of reset */ 1454 if (!IS_ERR(hdmi->reset)) 1455 reset_control_deassert(hdmi->reset); 1456 1457 platform_set_drvdata(pdev, hdmi); 1458 1459 return component_add(&pdev->dev, &sti_hdmi_ops); 1460 1461 release_adapter: 1462 i2c_put_adapter(hdmi->ddc_adapt); 1463 1464 return ret; 1465} 1466 1467static int sti_hdmi_remove(struct platform_device *pdev) 1468{ 1469 struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev); 1470 1471 i2c_put_adapter(hdmi->ddc_adapt); 1472 if (hdmi->audio_pdev) 1473 platform_device_unregister(hdmi->audio_pdev); 1474 component_del(&pdev->dev, &sti_hdmi_ops); 1475 1476 return 0; 1477} 1478 1479struct platform_driver sti_hdmi_driver = { 1480 .driver = { 1481 .name = "sti-hdmi", 1482 .owner = THIS_MODULE, 1483 .of_match_table = hdmi_of_match, 1484 }, 1485 .probe = sti_hdmi_probe, 1486 .remove = sti_hdmi_remove, 1487}; 1488 1489MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>"); 1490MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver"); 1491MODULE_LICENSE("GPL"); 1492