18c2ecf20Sopenharmony_ci1. stiH display hardware IP 28c2ecf20Sopenharmony_ci--------------------------- 38c2ecf20Sopenharmony_ciThe STMicroelectronics stiH SoCs use a common chain of HW display IP blocks: 48c2ecf20Sopenharmony_ci- The High Quality Video Display Processor (HQVDP) gets video frames from a 58c2ecf20Sopenharmony_ci video decoder and does high quality video processing, including scaling. 68c2ecf20Sopenharmony_ci 78c2ecf20Sopenharmony_ci- The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It 88c2ecf20Sopenharmony_ci has several inputs: 98c2ecf20Sopenharmony_ci - The graphics planes are internally processed by the Generic Display 108c2ecf20Sopenharmony_ci Pipeline (GDP). 118c2ecf20Sopenharmony_ci - The video plug (VID) connects to the HQVDP output. 128c2ecf20Sopenharmony_ci - The cursor handles ... a cursor. 138c2ecf20Sopenharmony_ci- The TV OUT pre-formats (convert, clip, round) the compositor output data 148c2ecf20Sopenharmony_ci- The HDMI / DVO / HD Analog / SD analog IP builds the video signals 158c2ecf20Sopenharmony_ci - DVO (Digital Video Output) handles a 24bits parallel signal 168c2ecf20Sopenharmony_ci - The HD analog signal is typically driven by a YCbCr cable, supporting up to 178c2ecf20Sopenharmony_ci 1080i mode. 188c2ecf20Sopenharmony_ci - The SD analog signal is typically used for legacy TV 198c2ecf20Sopenharmony_ci- The VTG (Video Timing Generators) build Vsync signals used by the other HW IP 208c2ecf20Sopenharmony_ciNote that some stiH drivers support only a subset of thee HW IP. 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_ci .-------------. .-----------. .-----------. 238c2ecf20Sopenharmony_ciGPU >-------------+GDP Main | | +---+ HDMI +--> HDMI 248c2ecf20Sopenharmony_ciGPU >-------------+GDP mixer+---+ | :===========: 258c2ecf20Sopenharmony_ciGPU >-------------+Cursor | | +---+ DVO +--> 24b// 268c2ecf20Sopenharmony_ci ------- | COMPOSITOR | | TV OUT | :===========: 278c2ecf20Sopenharmony_ci | | | | | +---+ HD analog +--> YCbCr 288c2ecf20Sopenharmony_ciVid >--+ HQVDP +--+VID Aux +---+ | :===========: 298c2ecf20Sopenharmony_cidec | | | mixer| | +---+ SD analog +--> CVBS 308c2ecf20Sopenharmony_ci '-------' '-------------' '-----------' '-----------' 318c2ecf20Sopenharmony_ci .-----------. 328c2ecf20Sopenharmony_ci | main+--> Vsync 338c2ecf20Sopenharmony_ci | VTG | 348c2ecf20Sopenharmony_ci | aux+--> Vsync 358c2ecf20Sopenharmony_ci '-----------' 368c2ecf20Sopenharmony_ci 378c2ecf20Sopenharmony_ci2. DRM / HW mapping 388c2ecf20Sopenharmony_ci------------------- 398c2ecf20Sopenharmony_ciThese IP are mapped to the DRM objects as following: 408c2ecf20Sopenharmony_ci- The CRTCs are mapped to the Compositor Main and Aux Mixers 418c2ecf20Sopenharmony_ci- The Framebuffers and planes are mapped to the Compositor GDP (non video 428c2ecf20Sopenharmony_ci buffers) and to HQVDP+VID (video buffers) 438c2ecf20Sopenharmony_ci- The Cursor is mapped to the Compositor Cursor 448c2ecf20Sopenharmony_ci- The Encoders are mapped to the TVOut 458c2ecf20Sopenharmony_ci- The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog 468c2ecf20Sopenharmony_ci 478c2ecf20Sopenharmony_ciFB & planes Cursor CRTC Encoders Bridges/Connectors 488c2ecf20Sopenharmony_ci | | | | | 498c2ecf20Sopenharmony_ci | | | | | 508c2ecf20Sopenharmony_ci | .-------------. | .-----------. .-----------. | 518c2ecf20Sopenharmony_ci +------------> |GDP | Main | | | +-> | | HDMI | <-+ 528c2ecf20Sopenharmony_ci +------------> |GDP v mixer|<+ | | | :===========: | 538c2ecf20Sopenharmony_ci | |Cursor | | | +-> | | DVO | <-+ 548c2ecf20Sopenharmony_ci | ------- | COMPOSITOR | | |TV OUT | | :===========: | 558c2ecf20Sopenharmony_ci | | | | | | | +-> | | HD analog | <-+ 568c2ecf20Sopenharmony_ci +-> | HQVDP | |VID Aux |<+ | | | :===========: | 578c2ecf20Sopenharmony_ci | | | mixer| | +-> | | SD analog | <-+ 588c2ecf20Sopenharmony_ci '-------' '-------------' '-----------' '-----------' 59