1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd 4 * Author: 5 * Chris Zhong <zyw@rock-chips.com> 6 * Nickey Yang <nickey.yang@rock-chips.com> 7 */ 8 9#include <linux/clk.h> 10#include <linux/iopoll.h> 11#include <linux/math64.h> 12#include <linux/mfd/syscon.h> 13#include <linux/module.h> 14#include <linux/of_device.h> 15#include <linux/phy/phy.h> 16#include <linux/pm_runtime.h> 17#include <linux/regmap.h> 18 19#include <video/mipi_display.h> 20 21#include <drm/bridge/dw_mipi_dsi.h> 22#include <drm/drm_mipi_dsi.h> 23#include <drm/drm_of.h> 24#include <drm/drm_simple_kms_helper.h> 25 26#include "rockchip_drm_drv.h" 27#include "rockchip_drm_vop.h" 28 29#define DSI_PHY_RSTZ 0xa0 30#define PHY_DISFORCEPLL 0 31#define PHY_ENFORCEPLL BIT(3) 32#define PHY_DISABLECLK 0 33#define PHY_ENABLECLK BIT(2) 34#define PHY_RSTZ 0 35#define PHY_UNRSTZ BIT(1) 36#define PHY_SHUTDOWNZ 0 37#define PHY_UNSHUTDOWNZ BIT(0) 38 39#define DSI_PHY_IF_CFG 0xa4 40#define N_LANES(n) ((((n) - 1) & 0x3) << 0) 41#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 42 43#define DSI_PHY_STATUS 0xb0 44#define LOCK BIT(0) 45#define STOP_STATE_CLK_LANE BIT(2) 46 47#define DSI_PHY_TST_CTRL0 0xb4 48#define PHY_TESTCLK BIT(1) 49#define PHY_UNTESTCLK 0 50#define PHY_TESTCLR BIT(0) 51#define PHY_UNTESTCLR 0 52 53#define DSI_PHY_TST_CTRL1 0xb8 54#define PHY_TESTEN BIT(16) 55#define PHY_UNTESTEN 0 56#define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 57#define PHY_TESTDIN(n) (((n) & 0xff) << 0) 58 59#define DSI_INT_ST0 0xbc 60#define DSI_INT_ST1 0xc0 61#define DSI_INT_MSK0 0xc4 62#define DSI_INT_MSK1 0xc8 63 64#define PHY_STATUS_TIMEOUT_US 10000 65#define CMD_PKT_STATUS_TIMEOUT_US 20000 66 67#define BYPASS_VCO_RANGE BIT(7) 68#define VCO_RANGE_CON_SEL(val) (((val) & 0x7) << 3) 69#define VCO_IN_CAP_CON_DEFAULT (0x0 << 1) 70#define VCO_IN_CAP_CON_LOW (0x1 << 1) 71#define VCO_IN_CAP_CON_HIGH (0x2 << 1) 72#define REF_BIAS_CUR_SEL BIT(0) 73 74#define CP_CURRENT_3UA 0x1 75#define CP_CURRENT_4_5UA 0x2 76#define CP_CURRENT_7_5UA 0x6 77#define CP_CURRENT_6UA 0x9 78#define CP_CURRENT_12UA 0xb 79#define CP_CURRENT_SEL(val) ((val) & 0xf) 80#define CP_PROGRAM_EN BIT(7) 81 82#define LPF_RESISTORS_15_5KOHM 0x1 83#define LPF_RESISTORS_13KOHM 0x2 84#define LPF_RESISTORS_11_5KOHM 0x4 85#define LPF_RESISTORS_10_5KOHM 0x8 86#define LPF_RESISTORS_8KOHM 0x10 87#define LPF_PROGRAM_EN BIT(6) 88#define LPF_RESISTORS_SEL(val) ((val) & 0x3f) 89 90#define HSFREQRANGE_SEL(val) (((val) & 0x3f) << 1) 91 92#define INPUT_DIVIDER(val) (((val) - 1) & 0x7f) 93#define LOW_PROGRAM_EN 0 94#define HIGH_PROGRAM_EN BIT(7) 95#define LOOP_DIV_LOW_SEL(val) (((val) - 1) & 0x1f) 96#define LOOP_DIV_HIGH_SEL(val) ((((val) - 1) >> 5) & 0xf) 97#define PLL_LOOP_DIV_EN BIT(5) 98#define PLL_INPUT_DIV_EN BIT(4) 99 100#define POWER_CONTROL BIT(6) 101#define INTERNAL_REG_CURRENT BIT(3) 102#define BIAS_BLOCK_ON BIT(2) 103#define BANDGAP_ON BIT(0) 104 105#define TER_RESISTOR_HIGH BIT(7) 106#define TER_RESISTOR_LOW 0 107#define LEVEL_SHIFTERS_ON BIT(6) 108#define TER_CAL_DONE BIT(5) 109#define SETRD_MAX (0x7 << 2) 110#define POWER_MANAGE BIT(1) 111#define TER_RESISTORS_ON BIT(0) 112 113#define BIASEXTR_SEL(val) ((val) & 0x7) 114#define BANDGAP_SEL(val) ((val) & 0x7) 115#define TLP_PROGRAM_EN BIT(7) 116#define THS_PRE_PROGRAM_EN BIT(7) 117#define THS_ZERO_PROGRAM_EN BIT(6) 118 119#define PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL 0x10 120#define PLL_CP_CONTROL_PLL_LOCK_BYPASS 0x11 121#define PLL_LPF_AND_CP_CONTROL 0x12 122#define PLL_INPUT_DIVIDER_RATIO 0x17 123#define PLL_LOOP_DIVIDER_RATIO 0x18 124#define PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL 0x19 125#define BANDGAP_AND_BIAS_CONTROL 0x20 126#define TERMINATION_RESISTER_CONTROL 0x21 127#define AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY 0x22 128#define HS_RX_CONTROL_OF_LANE_0 0x44 129#define HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL 0x60 130#define HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL 0x61 131#define HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL 0x62 132#define HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL 0x63 133#define HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL 0x64 134#define HS_TX_CLOCK_LANE_POST_TIME_CONTROL 0x65 135#define HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL 0x70 136#define HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL 0x71 137#define HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL 0x72 138#define HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL 0x73 139#define HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL 0x74 140 141#define DW_MIPI_NEEDS_PHY_CFG_CLK BIT(0) 142#define DW_MIPI_NEEDS_GRF_CLK BIT(1) 143 144#define PX30_GRF_PD_VO_CON1 0x0438 145#define PX30_DSI_FORCETXSTOPMODE (0xf << 7) 146#define PX30_DSI_FORCERXMODE BIT(6) 147#define PX30_DSI_TURNDISABLE BIT(5) 148#define PX30_DSI_LCDC_SEL BIT(0) 149 150#define RK3288_GRF_SOC_CON6 0x025c 151#define RK3288_DSI0_LCDC_SEL BIT(6) 152#define RK3288_DSI1_LCDC_SEL BIT(9) 153 154#define RK3399_GRF_SOC_CON20 0x6250 155#define RK3399_DSI0_LCDC_SEL BIT(0) 156#define RK3399_DSI1_LCDC_SEL BIT(4) 157 158#define RK3399_GRF_SOC_CON22 0x6258 159#define RK3399_DSI0_TURNREQUEST (0xf << 12) 160#define RK3399_DSI0_TURNDISABLE (0xf << 8) 161#define RK3399_DSI0_FORCETXSTOPMODE (0xf << 4) 162#define RK3399_DSI0_FORCERXMODE (0xf << 0) 163 164#define RK3399_GRF_SOC_CON23 0x625c 165#define RK3399_DSI1_TURNDISABLE (0xf << 12) 166#define RK3399_DSI1_FORCETXSTOPMODE (0xf << 8) 167#define RK3399_DSI1_FORCERXMODE (0xf << 4) 168#define RK3399_DSI1_ENABLE (0xf << 0) 169 170#define RK3399_GRF_SOC_CON24 0x6260 171#define RK3399_TXRX_MASTERSLAVEZ BIT(7) 172#define RK3399_TXRX_ENABLECLK BIT(6) 173#define RK3399_TXRX_BASEDIR BIT(5) 174 175#define HIWORD_UPDATE(val, mask) (val | (mask) << 16) 176 177#define to_dsi(nm) container_of(nm, struct dw_mipi_dsi_rockchip, nm) 178 179enum { 180 BANDGAP_97_07, 181 BANDGAP_98_05, 182 BANDGAP_99_02, 183 BANDGAP_100_00, 184 BANDGAP_93_17, 185 BANDGAP_94_15, 186 BANDGAP_95_12, 187 BANDGAP_96_10, 188}; 189 190enum { 191 BIASEXTR_87_1, 192 BIASEXTR_91_5, 193 BIASEXTR_95_9, 194 BIASEXTR_100, 195 BIASEXTR_105_94, 196 BIASEXTR_111_88, 197 BIASEXTR_118_8, 198 BIASEXTR_127_7, 199}; 200 201struct rockchip_dw_dsi_chip_data { 202 u32 reg; 203 204 u32 lcdsel_grf_reg; 205 u32 lcdsel_big; 206 u32 lcdsel_lit; 207 208 u32 enable_grf_reg; 209 u32 enable; 210 211 u32 lanecfg1_grf_reg; 212 u32 lanecfg1; 213 u32 lanecfg2_grf_reg; 214 u32 lanecfg2; 215 216 unsigned int flags; 217 unsigned int max_data_lanes; 218}; 219 220struct dw_mipi_dsi_rockchip { 221 struct device *dev; 222 struct drm_encoder encoder; 223 void __iomem *base; 224 225 struct regmap *grf_regmap; 226 struct clk *pllref_clk; 227 struct clk *grf_clk; 228 struct clk *phy_cfg_clk; 229 230 /* dual-channel */ 231 bool is_slave; 232 struct dw_mipi_dsi_rockchip *slave; 233 234 /* optional external dphy */ 235 struct phy *phy; 236 union phy_configure_opts phy_opts; 237 238 unsigned int lane_mbps; /* per lane */ 239 u16 input_div; 240 u16 feedback_div; 241 u32 format; 242 243 struct dw_mipi_dsi *dmd; 244 const struct rockchip_dw_dsi_chip_data *cdata; 245 struct dw_mipi_dsi_plat_data pdata; 246}; 247 248struct dphy_pll_parameter_map { 249 unsigned int max_mbps; 250 u8 hsfreqrange; 251 u8 icpctrl; 252 u8 lpfctrl; 253}; 254 255/* The table is based on 27MHz DPHY pll reference clock. */ 256static const struct dphy_pll_parameter_map dppa_map[] = { 257 { 89, 0x00, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 258 { 99, 0x10, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 259 { 109, 0x20, CP_CURRENT_3UA, LPF_RESISTORS_13KOHM }, 260 { 129, 0x01, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 261 { 139, 0x11, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 262 { 149, 0x21, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 263 { 169, 0x02, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 264 { 179, 0x12, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 265 { 199, 0x22, CP_CURRENT_6UA, LPF_RESISTORS_13KOHM }, 266 { 219, 0x03, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 267 { 239, 0x13, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 268 { 249, 0x23, CP_CURRENT_4_5UA, LPF_RESISTORS_13KOHM }, 269 { 269, 0x04, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 270 { 299, 0x14, CP_CURRENT_6UA, LPF_RESISTORS_11_5KOHM }, 271 { 329, 0x05, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 272 { 359, 0x15, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 273 { 399, 0x25, CP_CURRENT_3UA, LPF_RESISTORS_15_5KOHM }, 274 { 449, 0x06, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 275 { 499, 0x16, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 276 { 549, 0x07, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 277 { 599, 0x17, CP_CURRENT_7_5UA, LPF_RESISTORS_10_5KOHM }, 278 { 649, 0x08, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 279 { 699, 0x18, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 280 { 749, 0x09, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 281 { 799, 0x19, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 282 { 849, 0x29, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 283 { 899, 0x39, CP_CURRENT_7_5UA, LPF_RESISTORS_11_5KOHM }, 284 { 949, 0x0a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 285 { 999, 0x1a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 286 {1049, 0x2a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 287 {1099, 0x3a, CP_CURRENT_12UA, LPF_RESISTORS_8KOHM }, 288 {1149, 0x0b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 289 {1199, 0x1b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 290 {1249, 0x2b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 291 {1299, 0x3b, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 292 {1349, 0x0c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 293 {1399, 0x1c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 294 {1449, 0x2c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM }, 295 {1500, 0x3c, CP_CURRENT_12UA, LPF_RESISTORS_10_5KOHM } 296}; 297 298static int max_mbps_to_parameter(unsigned int max_mbps) 299{ 300 int i; 301 302 for (i = 0; i < ARRAY_SIZE(dppa_map); i++) 303 if (dppa_map[i].max_mbps >= max_mbps) 304 return i; 305 306 return -EINVAL; 307} 308 309static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) 310{ 311 writel(val, dsi->base + reg); 312} 313 314static inline u32 dsi_read(struct dw_mipi_dsi_rockchip *dsi, u32 reg) 315{ 316 return readl(dsi->base + reg); 317} 318 319static inline void dsi_set(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 mask) 320{ 321 dsi_write(dsi, reg, dsi_read(dsi, reg) | mask); 322} 323 324static inline void dsi_update_bits(struct dw_mipi_dsi_rockchip *dsi, u32 reg, 325 u32 mask, u32 val) 326{ 327 dsi_write(dsi, reg, (dsi_read(dsi, reg) & ~mask) | val); 328} 329 330static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, 331 u8 test_code, 332 u8 test_data) 333{ 334 /* 335 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 336 * is latched internally as the current test code. Test data is 337 * programmed internally by rising edge on TESTCLK. 338 */ 339 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 340 341 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | 342 PHY_TESTDIN(test_code)); 343 344 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); 345 346 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | 347 PHY_TESTDIN(test_data)); 348 349 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); 350} 351 352/** 353 * ns2bc - Nanoseconds to byte clock cycles 354 */ 355static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) 356{ 357 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); 358} 359 360/** 361 * ns2ui - Nanoseconds to UI time periods 362 */ 363static inline unsigned int ns2ui(struct dw_mipi_dsi_rockchip *dsi, int ns) 364{ 365 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); 366} 367 368static int dw_mipi_dsi_phy_init(void *priv_data) 369{ 370 struct dw_mipi_dsi_rockchip *dsi = priv_data; 371 int ret, i, vco; 372 373 if (dsi->phy) 374 return 0; 375 376 /* 377 * Get vco from frequency(lane_mbps) 378 * vco frequency table 379 * 000 - between 80 and 200 MHz 380 * 001 - between 200 and 300 MHz 381 * 010 - between 300 and 500 MHz 382 * 011 - between 500 and 700 MHz 383 * 100 - between 700 and 900 MHz 384 * 101 - between 900 and 1100 MHz 385 * 110 - between 1100 and 1300 MHz 386 * 111 - between 1300 and 1500 MHz 387 */ 388 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; 389 390 i = max_mbps_to_parameter(dsi->lane_mbps); 391 if (i < 0) { 392 DRM_DEV_ERROR(dsi->dev, 393 "failed to get parameter for %dmbps clock\n", 394 dsi->lane_mbps); 395 return i; 396 } 397 398 ret = clk_prepare_enable(dsi->phy_cfg_clk); 399 if (ret) { 400 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); 401 return ret; 402 } 403 404 dw_mipi_dsi_phy_write(dsi, PLL_BIAS_CUR_SEL_CAP_VCO_CONTROL, 405 BYPASS_VCO_RANGE | 406 VCO_RANGE_CON_SEL(vco) | 407 VCO_IN_CAP_CON_LOW | 408 REF_BIAS_CUR_SEL); 409 410 dw_mipi_dsi_phy_write(dsi, PLL_CP_CONTROL_PLL_LOCK_BYPASS, 411 CP_CURRENT_SEL(dppa_map[i].icpctrl)); 412 dw_mipi_dsi_phy_write(dsi, PLL_LPF_AND_CP_CONTROL, 413 CP_PROGRAM_EN | LPF_PROGRAM_EN | 414 LPF_RESISTORS_SEL(dppa_map[i].lpfctrl)); 415 416 dw_mipi_dsi_phy_write(dsi, HS_RX_CONTROL_OF_LANE_0, 417 HSFREQRANGE_SEL(dppa_map[i].hsfreqrange)); 418 419 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_DIVIDER_RATIO, 420 INPUT_DIVIDER(dsi->input_div)); 421 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 422 LOOP_DIV_LOW_SEL(dsi->feedback_div) | 423 LOW_PROGRAM_EN); 424 /* 425 * We need set PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL immediately 426 * to make the configured LSB effective according to IP simulation 427 * and lab test results. 428 * Only in this way can we get correct mipi phy pll frequency. 429 */ 430 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 431 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 432 dw_mipi_dsi_phy_write(dsi, PLL_LOOP_DIVIDER_RATIO, 433 LOOP_DIV_HIGH_SEL(dsi->feedback_div) | 434 HIGH_PROGRAM_EN); 435 dw_mipi_dsi_phy_write(dsi, PLL_INPUT_AND_LOOP_DIVIDER_RATIOS_CONTROL, 436 PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); 437 438 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 439 LOW_PROGRAM_EN | BIASEXTR_SEL(BIASEXTR_127_7)); 440 dw_mipi_dsi_phy_write(dsi, AFE_BIAS_BANDGAP_ANALOG_PROGRAMMABILITY, 441 HIGH_PROGRAM_EN | BANDGAP_SEL(BANDGAP_96_10)); 442 443 dw_mipi_dsi_phy_write(dsi, BANDGAP_AND_BIAS_CONTROL, 444 POWER_CONTROL | INTERNAL_REG_CURRENT | 445 BIAS_BLOCK_ON | BANDGAP_ON); 446 447 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 448 TER_RESISTOR_LOW | TER_CAL_DONE | 449 SETRD_MAX | TER_RESISTORS_ON); 450 dw_mipi_dsi_phy_write(dsi, TERMINATION_RESISTER_CONTROL, 451 TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | 452 SETRD_MAX | POWER_MANAGE | 453 TER_RESISTORS_ON); 454 455 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_REQUEST_STATE_TIME_CONTROL, 456 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 457 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_PREPARE_STATE_TIME_CONTROL, 458 THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); 459 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_HS_ZERO_STATE_TIME_CONTROL, 460 THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); 461 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_TRAIL_STATE_TIME_CONTROL, 462 THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); 463 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_EXIT_STATE_TIME_CONTROL, 464 BIT(5) | ns2bc(dsi, 100)); 465 dw_mipi_dsi_phy_write(dsi, HS_TX_CLOCK_LANE_POST_TIME_CONTROL, 466 BIT(5) | (ns2bc(dsi, 60) + 7)); 467 468 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_REQUEST_STATE_TIME_CONTROL, 469 TLP_PROGRAM_EN | ns2bc(dsi, 500)); 470 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_PREPARE_STATE_TIME_CONTROL, 471 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 20)); 472 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_HS_ZERO_STATE_TIME_CONTROL, 473 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); 474 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_TRAIL_STATE_TIME_CONTROL, 475 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); 476 dw_mipi_dsi_phy_write(dsi, HS_TX_DATA_LANE_EXIT_STATE_TIME_CONTROL, 477 BIT(5) | ns2bc(dsi, 100)); 478 479 clk_disable_unprepare(dsi->phy_cfg_clk); 480 481 return ret; 482} 483 484static void dw_mipi_dsi_phy_power_on(void *priv_data) 485{ 486 struct dw_mipi_dsi_rockchip *dsi = priv_data; 487 int ret; 488 489 ret = phy_set_mode(dsi->phy, PHY_MODE_MIPI_DPHY); 490 if (ret) { 491 DRM_DEV_ERROR(dsi->dev, "failed to set phy mode: %d\n", ret); 492 return; 493 } 494 495 phy_configure(dsi->phy, &dsi->phy_opts); 496 phy_power_on(dsi->phy); 497} 498 499static void dw_mipi_dsi_phy_power_off(void *priv_data) 500{ 501 struct dw_mipi_dsi_rockchip *dsi = priv_data; 502 503 phy_power_off(dsi->phy); 504} 505 506static int 507dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode, 508 unsigned long mode_flags, u32 lanes, u32 format, 509 unsigned int *lane_mbps) 510{ 511 struct dw_mipi_dsi_rockchip *dsi = priv_data; 512 int bpp; 513 unsigned long mpclk, tmp; 514 unsigned int target_mbps = 1000; 515 unsigned int max_mbps = dppa_map[ARRAY_SIZE(dppa_map) - 1].max_mbps; 516 unsigned long best_freq = 0; 517 unsigned long fvco_min, fvco_max, fin, fout; 518 unsigned int min_prediv, max_prediv; 519 unsigned int _prediv, best_prediv; 520 unsigned long _fbdiv, best_fbdiv; 521 unsigned long min_delta = ULONG_MAX; 522 523 dsi->format = format; 524 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 525 if (bpp < 0) { 526 DRM_DEV_ERROR(dsi->dev, 527 "failed to get bpp for pixel format %d\n", 528 dsi->format); 529 return bpp; 530 } 531 532 mpclk = DIV_ROUND_UP(mode->clock, MSEC_PER_SEC); 533 if (mpclk) { 534 /* take 1 / 0.8, since mbps must big than bandwidth of RGB */ 535 tmp = mpclk * (bpp / lanes) * 10 / 8; 536 if (tmp < max_mbps) 537 target_mbps = tmp; 538 else 539 DRM_DEV_ERROR(dsi->dev, 540 "DPHY clock frequency is out of range\n"); 541 } 542 543 /* for external phy only a the mipi_dphy_config is necessary */ 544 if (dsi->phy) { 545 phy_mipi_dphy_get_default_config(mode->clock * 1000 * 10 / 8, 546 bpp, lanes, 547 &dsi->phy_opts.mipi_dphy); 548 dsi->lane_mbps = target_mbps; 549 *lane_mbps = dsi->lane_mbps; 550 551 return 0; 552 } 553 554 fin = clk_get_rate(dsi->pllref_clk); 555 fout = target_mbps * USEC_PER_SEC; 556 557 /* constraint: 5Mhz <= Fref / N <= 40MHz */ 558 min_prediv = DIV_ROUND_UP(fin, 40 * USEC_PER_SEC); 559 max_prediv = fin / (5 * USEC_PER_SEC); 560 561 /* constraint: 80MHz <= Fvco <= 1500Mhz */ 562 fvco_min = 80 * USEC_PER_SEC; 563 fvco_max = 1500 * USEC_PER_SEC; 564 565 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 566 u64 tmp; 567 u32 delta; 568 /* Fvco = Fref * M / N */ 569 tmp = (u64)fout * _prediv; 570 do_div(tmp, fin); 571 _fbdiv = tmp; 572 /* 573 * Due to the use of a "by 2 pre-scaler," the range of the 574 * feedback multiplication value M is limited to even division 575 * numbers, and m must be greater than 6, not bigger than 512. 576 */ 577 if (_fbdiv < 6 || _fbdiv > 512) 578 continue; 579 580 _fbdiv += _fbdiv % 2; 581 582 tmp = (u64)_fbdiv * fin; 583 do_div(tmp, _prediv); 584 if (tmp < fvco_min || tmp > fvco_max) 585 continue; 586 587 delta = abs(fout - tmp); 588 if (delta < min_delta) { 589 best_prediv = _prediv; 590 best_fbdiv = _fbdiv; 591 min_delta = delta; 592 best_freq = tmp; 593 } 594 } 595 596 if (best_freq) { 597 dsi->lane_mbps = DIV_ROUND_UP(best_freq, USEC_PER_SEC); 598 *lane_mbps = dsi->lane_mbps; 599 dsi->input_div = best_prediv; 600 dsi->feedback_div = best_fbdiv; 601 } else { 602 DRM_DEV_ERROR(dsi->dev, "Can not find best_freq for DPHY\n"); 603 return -EINVAL; 604 } 605 606 return 0; 607} 608 609struct hstt { 610 unsigned int maxfreq; 611 struct dw_mipi_dsi_dphy_timing timing; 612}; 613 614#define HSTT(_maxfreq, _c_lp2hs, _c_hs2lp, _d_lp2hs, _d_hs2lp) \ 615{ \ 616 .maxfreq = _maxfreq, \ 617 .timing = { \ 618 .clk_lp2hs = _c_lp2hs, \ 619 .clk_hs2lp = _c_hs2lp, \ 620 .data_lp2hs = _d_lp2hs, \ 621 .data_hs2lp = _d_hs2lp, \ 622 } \ 623} 624 625/* Table A-3 High-Speed Transition Times */ 626struct hstt hstt_table[] = { 627 HSTT( 90, 32, 20, 26, 13), 628 HSTT( 100, 35, 23, 28, 14), 629 HSTT( 110, 32, 22, 26, 13), 630 HSTT( 130, 31, 20, 27, 13), 631 HSTT( 140, 33, 22, 26, 14), 632 HSTT( 150, 33, 21, 26, 14), 633 HSTT( 170, 32, 20, 27, 13), 634 HSTT( 180, 36, 23, 30, 15), 635 HSTT( 200, 40, 22, 33, 15), 636 HSTT( 220, 40, 22, 33, 15), 637 HSTT( 240, 44, 24, 36, 16), 638 HSTT( 250, 48, 24, 38, 17), 639 HSTT( 270, 48, 24, 38, 17), 640 HSTT( 300, 50, 27, 41, 18), 641 HSTT( 330, 56, 28, 45, 18), 642 HSTT( 360, 59, 28, 48, 19), 643 HSTT( 400, 61, 30, 50, 20), 644 HSTT( 450, 67, 31, 55, 21), 645 HSTT( 500, 73, 31, 59, 22), 646 HSTT( 550, 79, 36, 63, 24), 647 HSTT( 600, 83, 37, 68, 25), 648 HSTT( 650, 90, 38, 73, 27), 649 HSTT( 700, 95, 40, 77, 28), 650 HSTT( 750, 102, 40, 84, 28), 651 HSTT( 800, 106, 42, 87, 30), 652 HSTT( 850, 113, 44, 93, 31), 653 HSTT( 900, 118, 47, 98, 32), 654 HSTT( 950, 124, 47, 102, 34), 655 HSTT(1000, 130, 49, 107, 35), 656 HSTT(1050, 135, 51, 111, 37), 657 HSTT(1100, 139, 51, 114, 38), 658 HSTT(1150, 146, 54, 120, 40), 659 HSTT(1200, 153, 57, 125, 41), 660 HSTT(1250, 158, 58, 130, 42), 661 HSTT(1300, 163, 58, 135, 44), 662 HSTT(1350, 168, 60, 140, 45), 663 HSTT(1400, 172, 64, 144, 47), 664 HSTT(1450, 176, 65, 148, 48), 665 HSTT(1500, 181, 66, 153, 50) 666}; 667 668static int 669dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps, 670 struct dw_mipi_dsi_dphy_timing *timing) 671{ 672 int i; 673 674 for (i = 0; i < ARRAY_SIZE(hstt_table); i++) 675 if (lane_mbps < hstt_table[i].maxfreq) 676 break; 677 678 if (i == ARRAY_SIZE(hstt_table)) 679 i--; 680 681 *timing = hstt_table[i].timing; 682 683 return 0; 684} 685 686static const struct dw_mipi_dsi_phy_ops dw_mipi_dsi_rockchip_phy_ops = { 687 .init = dw_mipi_dsi_phy_init, 688 .power_on = dw_mipi_dsi_phy_power_on, 689 .power_off = dw_mipi_dsi_phy_power_off, 690 .get_lane_mbps = dw_mipi_dsi_get_lane_mbps, 691 .get_timing = dw_mipi_dsi_phy_get_timing, 692}; 693 694static void dw_mipi_dsi_rockchip_config(struct dw_mipi_dsi_rockchip *dsi) 695{ 696 if (dsi->cdata->lanecfg1_grf_reg) 697 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg1_grf_reg, 698 dsi->cdata->lanecfg1); 699 700 if (dsi->cdata->lanecfg2_grf_reg) 701 regmap_write(dsi->grf_regmap, dsi->cdata->lanecfg2_grf_reg, 702 dsi->cdata->lanecfg2); 703 704 if (dsi->cdata->enable_grf_reg) 705 regmap_write(dsi->grf_regmap, dsi->cdata->enable_grf_reg, 706 dsi->cdata->enable); 707} 708 709static void dw_mipi_dsi_rockchip_set_lcdsel(struct dw_mipi_dsi_rockchip *dsi, 710 int mux) 711{ 712 regmap_write(dsi->grf_regmap, dsi->cdata->lcdsel_grf_reg, 713 mux ? dsi->cdata->lcdsel_lit : dsi->cdata->lcdsel_big); 714} 715 716static int 717dw_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder, 718 struct drm_crtc_state *crtc_state, 719 struct drm_connector_state *conn_state) 720{ 721 struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state); 722 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 723 724 switch (dsi->format) { 725 case MIPI_DSI_FMT_RGB888: 726 s->output_mode = ROCKCHIP_OUT_MODE_P888; 727 break; 728 case MIPI_DSI_FMT_RGB666: 729 s->output_mode = ROCKCHIP_OUT_MODE_P666; 730 break; 731 case MIPI_DSI_FMT_RGB565: 732 s->output_mode = ROCKCHIP_OUT_MODE_P565; 733 break; 734 default: 735 WARN_ON(1); 736 return -EINVAL; 737 } 738 739 s->output_type = DRM_MODE_CONNECTOR_DSI; 740 if (dsi->slave) 741 s->output_flags = ROCKCHIP_OUTPUT_DSI_DUAL; 742 743 return 0; 744} 745 746static void dw_mipi_dsi_encoder_enable(struct drm_encoder *encoder) 747{ 748 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 749 int ret, mux; 750 751 mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, 752 &dsi->encoder); 753 if (mux < 0) 754 return; 755 756 pm_runtime_get_sync(dsi->dev); 757 if (dsi->slave) 758 pm_runtime_get_sync(dsi->slave->dev); 759 760 /* 761 * For the RK3399, the clk of grf must be enabled before writing grf 762 * register. And for RK3288 or other soc, this grf_clk must be NULL, 763 * the clk_prepare_enable return true directly. 764 */ 765 ret = clk_prepare_enable(dsi->grf_clk); 766 if (ret) { 767 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 768 return; 769 } 770 771 dw_mipi_dsi_rockchip_set_lcdsel(dsi, mux); 772 if (dsi->slave) 773 dw_mipi_dsi_rockchip_set_lcdsel(dsi->slave, mux); 774 775 clk_disable_unprepare(dsi->grf_clk); 776} 777 778static void dw_mipi_dsi_encoder_disable(struct drm_encoder *encoder) 779{ 780 struct dw_mipi_dsi_rockchip *dsi = to_dsi(encoder); 781 782 if (dsi->slave) 783 pm_runtime_put(dsi->slave->dev); 784 pm_runtime_put(dsi->dev); 785} 786 787static const struct drm_encoder_helper_funcs 788dw_mipi_dsi_encoder_helper_funcs = { 789 .atomic_check = dw_mipi_dsi_encoder_atomic_check, 790 .enable = dw_mipi_dsi_encoder_enable, 791 .disable = dw_mipi_dsi_encoder_disable, 792}; 793 794static int rockchip_dsi_drm_create_encoder(struct dw_mipi_dsi_rockchip *dsi, 795 struct drm_device *drm_dev) 796{ 797 struct drm_encoder *encoder = &dsi->encoder; 798 int ret; 799 800 encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev, 801 dsi->dev->of_node); 802 803 ret = drm_simple_encoder_init(drm_dev, encoder, DRM_MODE_ENCODER_DSI); 804 if (ret) { 805 DRM_ERROR("Failed to initialize encoder with drm\n"); 806 return ret; 807 } 808 809 drm_encoder_helper_add(encoder, &dw_mipi_dsi_encoder_helper_funcs); 810 811 return 0; 812} 813 814static struct device 815*dw_mipi_dsi_rockchip_find_second(struct dw_mipi_dsi_rockchip *dsi) 816{ 817 const struct of_device_id *match; 818 struct device_node *node = NULL, *local; 819 820 match = of_match_device(dsi->dev->driver->of_match_table, dsi->dev); 821 822 local = of_graph_get_remote_node(dsi->dev->of_node, 1, 0); 823 if (!local) 824 return NULL; 825 826 while ((node = of_find_compatible_node(node, NULL, 827 match->compatible))) { 828 struct device_node *remote; 829 830 /* found ourself */ 831 if (node == dsi->dev->of_node) 832 continue; 833 834 remote = of_graph_get_remote_node(node, 1, 0); 835 if (!remote) 836 continue; 837 838 /* same display device in port1-ep0 for both */ 839 if (remote == local) { 840 struct dw_mipi_dsi_rockchip *dsi2; 841 struct platform_device *pdev; 842 843 pdev = of_find_device_by_node(node); 844 845 /* 846 * we have found the second, so will either return it 847 * or return with an error. In any case won't need the 848 * nodes anymore nor continue the loop. 849 */ 850 of_node_put(remote); 851 of_node_put(node); 852 of_node_put(local); 853 854 if (!pdev) 855 return ERR_PTR(-EPROBE_DEFER); 856 857 dsi2 = platform_get_drvdata(pdev); 858 if (!dsi2) { 859 platform_device_put(pdev); 860 return ERR_PTR(-EPROBE_DEFER); 861 } 862 863 return &pdev->dev; 864 } 865 866 of_node_put(remote); 867 } 868 869 of_node_put(local); 870 871 return NULL; 872} 873 874static int dw_mipi_dsi_rockchip_bind(struct device *dev, 875 struct device *master, 876 void *data) 877{ 878 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 879 struct drm_device *drm_dev = data; 880 struct device *second; 881 bool master1, master2; 882 int ret; 883 884 second = dw_mipi_dsi_rockchip_find_second(dsi); 885 if (IS_ERR(second)) 886 return PTR_ERR(second); 887 888 if (second) { 889 master1 = of_property_read_bool(dsi->dev->of_node, 890 "clock-master"); 891 master2 = of_property_read_bool(second->of_node, 892 "clock-master"); 893 894 if (master1 && master2) { 895 DRM_DEV_ERROR(dsi->dev, "only one clock-master allowed\n"); 896 return -EINVAL; 897 } 898 899 if (!master1 && !master2) { 900 DRM_DEV_ERROR(dsi->dev, "no clock-master defined\n"); 901 return -EINVAL; 902 } 903 904 /* we are the slave in dual-DSI */ 905 if (!master1) { 906 dsi->is_slave = true; 907 return 0; 908 } 909 910 dsi->slave = dev_get_drvdata(second); 911 if (!dsi->slave) { 912 DRM_DEV_ERROR(dev, "could not get slaves data\n"); 913 return -ENODEV; 914 } 915 916 dsi->slave->is_slave = true; 917 dw_mipi_dsi_set_slave(dsi->dmd, dsi->slave->dmd); 918 put_device(second); 919 } 920 921 ret = clk_prepare_enable(dsi->pllref_clk); 922 if (ret) { 923 DRM_DEV_ERROR(dev, "Failed to enable pllref_clk: %d\n", ret); 924 return ret; 925 } 926 927 /* 928 * With the GRF clock running, write lane and dual-mode configurations 929 * that won't change immediately. If we waited until enable() to do 930 * this, things like panel preparation would not be able to send 931 * commands over DSI. 932 */ 933 ret = clk_prepare_enable(dsi->grf_clk); 934 if (ret) { 935 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); 936 return ret; 937 } 938 939 dw_mipi_dsi_rockchip_config(dsi); 940 if (dsi->slave) 941 dw_mipi_dsi_rockchip_config(dsi->slave); 942 943 clk_disable_unprepare(dsi->grf_clk); 944 945 ret = rockchip_dsi_drm_create_encoder(dsi, drm_dev); 946 if (ret) { 947 DRM_DEV_ERROR(dev, "Failed to create drm encoder\n"); 948 return ret; 949 } 950 951 ret = dw_mipi_dsi_bind(dsi->dmd, &dsi->encoder); 952 if (ret) { 953 DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret); 954 return ret; 955 } 956 957 return 0; 958} 959 960static void dw_mipi_dsi_rockchip_unbind(struct device *dev, 961 struct device *master, 962 void *data) 963{ 964 struct dw_mipi_dsi_rockchip *dsi = dev_get_drvdata(dev); 965 966 if (dsi->is_slave) 967 return; 968 969 dw_mipi_dsi_unbind(dsi->dmd); 970 971 clk_disable_unprepare(dsi->pllref_clk); 972} 973 974static const struct component_ops dw_mipi_dsi_rockchip_ops = { 975 .bind = dw_mipi_dsi_rockchip_bind, 976 .unbind = dw_mipi_dsi_rockchip_unbind, 977}; 978 979static int dw_mipi_dsi_rockchip_host_attach(void *priv_data, 980 struct mipi_dsi_device *device) 981{ 982 struct dw_mipi_dsi_rockchip *dsi = priv_data; 983 struct device *second; 984 int ret; 985 986 ret = component_add(dsi->dev, &dw_mipi_dsi_rockchip_ops); 987 if (ret) { 988 DRM_DEV_ERROR(dsi->dev, "Failed to register component: %d\n", 989 ret); 990 return ret; 991 } 992 993 second = dw_mipi_dsi_rockchip_find_second(dsi); 994 if (IS_ERR(second)) 995 return PTR_ERR(second); 996 if (second) { 997 ret = component_add(second, &dw_mipi_dsi_rockchip_ops); 998 if (ret) { 999 DRM_DEV_ERROR(second, 1000 "Failed to register component: %d\n", 1001 ret); 1002 return ret; 1003 } 1004 } 1005 1006 return 0; 1007} 1008 1009static int dw_mipi_dsi_rockchip_host_detach(void *priv_data, 1010 struct mipi_dsi_device *device) 1011{ 1012 struct dw_mipi_dsi_rockchip *dsi = priv_data; 1013 struct device *second; 1014 1015 second = dw_mipi_dsi_rockchip_find_second(dsi); 1016 if (second && !IS_ERR(second)) 1017 component_del(second, &dw_mipi_dsi_rockchip_ops); 1018 1019 component_del(dsi->dev, &dw_mipi_dsi_rockchip_ops); 1020 1021 return 0; 1022} 1023 1024static const struct dw_mipi_dsi_host_ops dw_mipi_dsi_rockchip_host_ops = { 1025 .attach = dw_mipi_dsi_rockchip_host_attach, 1026 .detach = dw_mipi_dsi_rockchip_host_detach, 1027}; 1028 1029static int dw_mipi_dsi_rockchip_probe(struct platform_device *pdev) 1030{ 1031 struct device *dev = &pdev->dev; 1032 struct device_node *np = dev->of_node; 1033 struct dw_mipi_dsi_rockchip *dsi; 1034 struct resource *res; 1035 const struct rockchip_dw_dsi_chip_data *cdata = 1036 of_device_get_match_data(dev); 1037 int ret, i; 1038 1039 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1040 if (!dsi) 1041 return -ENOMEM; 1042 1043 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1044 dsi->base = devm_ioremap_resource(dev, res); 1045 if (IS_ERR(dsi->base)) { 1046 DRM_DEV_ERROR(dev, "Unable to get dsi registers\n"); 1047 return PTR_ERR(dsi->base); 1048 } 1049 1050 i = 0; 1051 while (cdata[i].reg) { 1052 if (cdata[i].reg == res->start) { 1053 dsi->cdata = &cdata[i]; 1054 break; 1055 } 1056 1057 i++; 1058 } 1059 1060 if (!dsi->cdata) { 1061 DRM_DEV_ERROR(dev, "no dsi-config for %s node\n", np->name); 1062 return -EINVAL; 1063 } 1064 1065 /* try to get a possible external dphy */ 1066 dsi->phy = devm_phy_optional_get(dev, "dphy"); 1067 if (IS_ERR(dsi->phy)) { 1068 ret = PTR_ERR(dsi->phy); 1069 DRM_DEV_ERROR(dev, "failed to get mipi dphy: %d\n", ret); 1070 return ret; 1071 } 1072 1073 dsi->pllref_clk = devm_clk_get(dev, "ref"); 1074 if (IS_ERR(dsi->pllref_clk)) { 1075 if (dsi->phy) { 1076 /* 1077 * if external phy is present, pll will be 1078 * generated there. 1079 */ 1080 dsi->pllref_clk = NULL; 1081 } else { 1082 ret = PTR_ERR(dsi->pllref_clk); 1083 DRM_DEV_ERROR(dev, 1084 "Unable to get pll reference clock: %d\n", 1085 ret); 1086 return ret; 1087 } 1088 } 1089 1090 if (dsi->cdata->flags & DW_MIPI_NEEDS_PHY_CFG_CLK) { 1091 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); 1092 if (IS_ERR(dsi->phy_cfg_clk)) { 1093 ret = PTR_ERR(dsi->phy_cfg_clk); 1094 DRM_DEV_ERROR(dev, 1095 "Unable to get phy_cfg_clk: %d\n", ret); 1096 return ret; 1097 } 1098 } 1099 1100 if (dsi->cdata->flags & DW_MIPI_NEEDS_GRF_CLK) { 1101 dsi->grf_clk = devm_clk_get(dev, "grf"); 1102 if (IS_ERR(dsi->grf_clk)) { 1103 ret = PTR_ERR(dsi->grf_clk); 1104 DRM_DEV_ERROR(dev, "Unable to get grf_clk: %d\n", ret); 1105 return ret; 1106 } 1107 } 1108 1109 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1110 if (IS_ERR(dsi->grf_regmap)) { 1111 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n"); 1112 return PTR_ERR(dsi->grf_regmap); 1113 } 1114 1115 dsi->dev = dev; 1116 dsi->pdata.base = dsi->base; 1117 dsi->pdata.max_data_lanes = dsi->cdata->max_data_lanes; 1118 dsi->pdata.phy_ops = &dw_mipi_dsi_rockchip_phy_ops; 1119 dsi->pdata.host_ops = &dw_mipi_dsi_rockchip_host_ops; 1120 dsi->pdata.priv_data = dsi; 1121 platform_set_drvdata(pdev, dsi); 1122 1123 dsi->dmd = dw_mipi_dsi_probe(pdev, &dsi->pdata); 1124 if (IS_ERR(dsi->dmd)) { 1125 ret = PTR_ERR(dsi->dmd); 1126 if (ret != -EPROBE_DEFER) 1127 DRM_DEV_ERROR(dev, 1128 "Failed to probe dw_mipi_dsi: %d\n", ret); 1129 goto err_clkdisable; 1130 } 1131 1132 return 0; 1133 1134err_clkdisable: 1135 clk_disable_unprepare(dsi->pllref_clk); 1136 return ret; 1137} 1138 1139static int dw_mipi_dsi_rockchip_remove(struct platform_device *pdev) 1140{ 1141 struct dw_mipi_dsi_rockchip *dsi = platform_get_drvdata(pdev); 1142 1143 dw_mipi_dsi_remove(dsi->dmd); 1144 1145 return 0; 1146} 1147 1148static const struct rockchip_dw_dsi_chip_data px30_chip_data[] = { 1149 { 1150 .reg = 0xff450000, 1151 .lcdsel_grf_reg = PX30_GRF_PD_VO_CON1, 1152 .lcdsel_big = HIWORD_UPDATE(0, PX30_DSI_LCDC_SEL), 1153 .lcdsel_lit = HIWORD_UPDATE(PX30_DSI_LCDC_SEL, 1154 PX30_DSI_LCDC_SEL), 1155 1156 .lanecfg1_grf_reg = PX30_GRF_PD_VO_CON1, 1157 .lanecfg1 = HIWORD_UPDATE(0, PX30_DSI_TURNDISABLE | 1158 PX30_DSI_FORCERXMODE | 1159 PX30_DSI_FORCETXSTOPMODE), 1160 1161 .max_data_lanes = 4, 1162 }, 1163 { /* sentinel */ } 1164}; 1165 1166static const struct rockchip_dw_dsi_chip_data rk3288_chip_data[] = { 1167 { 1168 .reg = 0xff960000, 1169 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1170 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI0_LCDC_SEL), 1171 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI0_LCDC_SEL, RK3288_DSI0_LCDC_SEL), 1172 1173 .max_data_lanes = 4, 1174 }, 1175 { 1176 .reg = 0xff964000, 1177 .lcdsel_grf_reg = RK3288_GRF_SOC_CON6, 1178 .lcdsel_big = HIWORD_UPDATE(0, RK3288_DSI1_LCDC_SEL), 1179 .lcdsel_lit = HIWORD_UPDATE(RK3288_DSI1_LCDC_SEL, RK3288_DSI1_LCDC_SEL), 1180 1181 .max_data_lanes = 4, 1182 }, 1183 { /* sentinel */ } 1184}; 1185 1186static const struct rockchip_dw_dsi_chip_data rk3399_chip_data[] = { 1187 { 1188 .reg = 0xff960000, 1189 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1190 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI0_LCDC_SEL), 1191 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI0_LCDC_SEL, 1192 RK3399_DSI0_LCDC_SEL), 1193 1194 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON22, 1195 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI0_TURNREQUEST | 1196 RK3399_DSI0_TURNDISABLE | 1197 RK3399_DSI0_FORCETXSTOPMODE | 1198 RK3399_DSI0_FORCERXMODE), 1199 1200 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1201 .max_data_lanes = 4, 1202 }, 1203 { 1204 .reg = 0xff968000, 1205 .lcdsel_grf_reg = RK3399_GRF_SOC_CON20, 1206 .lcdsel_big = HIWORD_UPDATE(0, RK3399_DSI1_LCDC_SEL), 1207 .lcdsel_lit = HIWORD_UPDATE(RK3399_DSI1_LCDC_SEL, 1208 RK3399_DSI1_LCDC_SEL), 1209 1210 .lanecfg1_grf_reg = RK3399_GRF_SOC_CON23, 1211 .lanecfg1 = HIWORD_UPDATE(0, RK3399_DSI1_TURNDISABLE | 1212 RK3399_DSI1_FORCETXSTOPMODE | 1213 RK3399_DSI1_FORCERXMODE | 1214 RK3399_DSI1_ENABLE), 1215 1216 .lanecfg2_grf_reg = RK3399_GRF_SOC_CON24, 1217 .lanecfg2 = HIWORD_UPDATE(RK3399_TXRX_MASTERSLAVEZ | 1218 RK3399_TXRX_ENABLECLK, 1219 RK3399_TXRX_MASTERSLAVEZ | 1220 RK3399_TXRX_ENABLECLK | 1221 RK3399_TXRX_BASEDIR), 1222 1223 .enable_grf_reg = RK3399_GRF_SOC_CON23, 1224 .enable = HIWORD_UPDATE(RK3399_DSI1_ENABLE, RK3399_DSI1_ENABLE), 1225 1226 .flags = DW_MIPI_NEEDS_PHY_CFG_CLK | DW_MIPI_NEEDS_GRF_CLK, 1227 .max_data_lanes = 4, 1228 }, 1229 { /* sentinel */ } 1230}; 1231 1232static const struct of_device_id dw_mipi_dsi_rockchip_dt_ids[] = { 1233 { 1234 .compatible = "rockchip,px30-mipi-dsi", 1235 .data = &px30_chip_data, 1236 }, { 1237 .compatible = "rockchip,rk3288-mipi-dsi", 1238 .data = &rk3288_chip_data, 1239 }, { 1240 .compatible = "rockchip,rk3399-mipi-dsi", 1241 .data = &rk3399_chip_data, 1242 }, 1243 { /* sentinel */ } 1244}; 1245MODULE_DEVICE_TABLE(of, dw_mipi_dsi_rockchip_dt_ids); 1246 1247struct platform_driver dw_mipi_dsi_rockchip_driver = { 1248 .probe = dw_mipi_dsi_rockchip_probe, 1249 .remove = dw_mipi_dsi_rockchip_remove, 1250 .driver = { 1251 .of_match_table = dw_mipi_dsi_rockchip_dt_ids, 1252 .name = "dw-mipi-dsi-rockchip", 1253 /* 1254 * For dual-DSI display, one DSI pokes at the other DSI's 1255 * drvdata in dw_mipi_dsi_rockchip_find_second(). This is not 1256 * safe for asynchronous probe. 1257 */ 1258 .probe_type = PROBE_FORCE_SYNCHRONOUS, 1259 }, 1260}; 1261