1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * rcar_du_group.c  --  R-Car Display Unit Channels Pair
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10/*
11 * The R8A7779 DU is split in per-CRTC resources (scan-out engine, blending
12 * unit, timings generator, ...) and device-global resources (start/stop
13 * control, planes, ...) shared between the two CRTCs.
14 *
15 * The R8A7790 introduced a third CRTC with its own set of global resources.
16 * This would be modeled as two separate DU device instances if it wasn't for
17 * a handful or resources that are shared between the three CRTCs (mostly
18 * related to input and output routing). For this reason the R8A7790 DU must be
19 * modeled as a single device with three CRTCs, two sets of "semi-global"
20 * resources, and a few device-global resources.
21 *
22 * The rcar_du_group object is a driver specific object, without any real
23 * counterpart in the DU documentation, that models those semi-global resources.
24 */
25
26#include <linux/clk.h>
27#include <linux/io.h>
28
29#include "rcar_du_drv.h"
30#include "rcar_du_group.h"
31#include "rcar_du_regs.h"
32
33u32 rcar_du_group_read(struct rcar_du_group *rgrp, u32 reg)
34{
35	return rcar_du_read(rgrp->dev, rgrp->mmio_offset + reg);
36}
37
38void rcar_du_group_write(struct rcar_du_group *rgrp, u32 reg, u32 data)
39{
40	rcar_du_write(rgrp->dev, rgrp->mmio_offset + reg, data);
41}
42
43static void rcar_du_group_setup_pins(struct rcar_du_group *rgrp)
44{
45	u32 defr6 = DEFR6_CODE;
46
47	if (rgrp->channels_mask & BIT(0))
48		defr6 |= DEFR6_ODPM02_DISP;
49
50	if (rgrp->channels_mask & BIT(1))
51		defr6 |= DEFR6_ODPM12_DISP;
52
53	rcar_du_group_write(rgrp, DEFR6, defr6);
54}
55
56static void rcar_du_group_setup_defr8(struct rcar_du_group *rgrp)
57{
58	struct rcar_du_device *rcdu = rgrp->dev;
59	u32 defr8 = DEFR8_CODE;
60
61	if (rcdu->info->gen < 3) {
62		defr8 |= DEFR8_DEFE8;
63
64		/*
65		 * On Gen2 the DEFR8 register for the first group also controls
66		 * RGB output routing to DPAD0 and VSPD1 routing to DU0/1/2 for
67		 * DU instances that support it.
68		 */
69		if (rgrp->index == 0) {
70			defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
71			if (rgrp->dev->vspd1_sink == 2)
72				defr8 |= DEFR8_VSCS;
73		}
74	} else {
75		/*
76		 * On Gen3 VSPD routing can't be configured, and DPAD routing
77		 * is set in the group corresponding to the DPAD output (no Gen3
78		 * SoC has multiple DPAD sources belonging to separate groups).
79		 */
80		if (rgrp->index == rcdu->dpad0_source / 2)
81			defr8 |= DEFR8_DRGBS_DU(rcdu->dpad0_source);
82	}
83
84	rcar_du_group_write(rgrp, DEFR8, defr8);
85}
86
87static void rcar_du_group_setup_didsr(struct rcar_du_group *rgrp)
88{
89	struct rcar_du_device *rcdu = rgrp->dev;
90	struct rcar_du_crtc *rcrtc;
91	unsigned int num_crtcs = 0;
92	unsigned int i;
93	u32 didsr;
94
95	/*
96	 * Configure input dot clock routing with a hardcoded configuration. If
97	 * the DU channel can use the LVDS encoder output clock as the dot
98	 * clock, do so. Otherwise route DU_DOTCLKINn signal to DUn.
99	 *
100	 * Each channel can then select between the dot clock configured here
101	 * and the clock provided by the CPG through the ESCR register.
102	 */
103	if (rcdu->info->gen < 3 && rgrp->index == 0) {
104		/*
105		 * On Gen2 a single register in the first group controls dot
106		 * clock selection for all channels.
107		 */
108		rcrtc = rcdu->crtcs;
109		num_crtcs = rcdu->num_crtcs;
110	} else if (rcdu->info->gen == 3 && rgrp->num_crtcs > 1) {
111		/*
112		 * On Gen3 dot clocks are setup through per-group registers,
113		 * only available when the group has two channels.
114		 */
115		rcrtc = &rcdu->crtcs[rgrp->index * 2];
116		num_crtcs = rgrp->num_crtcs;
117	}
118
119	if (!num_crtcs)
120		return;
121
122	didsr = DIDSR_CODE;
123	for (i = 0; i < num_crtcs; ++i, ++rcrtc) {
124		if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index))
125			didsr |= DIDSR_LCDS_LVDS0(i)
126			      |  DIDSR_PDCS_CLK(i, 0);
127		else
128			didsr |= DIDSR_LCDS_DCLKIN(i)
129			      |  DIDSR_PDCS_CLK(i, 0);
130	}
131
132	rcar_du_group_write(rgrp, DIDSR, didsr);
133}
134
135static void rcar_du_group_setup(struct rcar_du_group *rgrp)
136{
137	struct rcar_du_device *rcdu = rgrp->dev;
138	u32 defr7 = DEFR7_CODE;
139
140	/* Enable extended features */
141	rcar_du_group_write(rgrp, DEFR, DEFR_CODE | DEFR_DEFE);
142	if (rcdu->info->gen < 3) {
143		rcar_du_group_write(rgrp, DEFR2, DEFR2_CODE | DEFR2_DEFE2G);
144		rcar_du_group_write(rgrp, DEFR3, DEFR3_CODE | DEFR3_DEFE3);
145		rcar_du_group_write(rgrp, DEFR4, DEFR4_CODE);
146	}
147	rcar_du_group_write(rgrp, DEFR5, DEFR5_CODE | DEFR5_DEFE5);
148
149	rcar_du_group_setup_pins(rgrp);
150
151	/*
152	 * TODO: Handle routing of the DU output to CMM dynamically, as we
153	 * should bypass CMM completely when no color management feature is
154	 * used.
155	 */
156	defr7 |= (rgrp->cmms_mask & BIT(1) ? DEFR7_CMME1 : 0) |
157		 (rgrp->cmms_mask & BIT(0) ? DEFR7_CMME0 : 0);
158	rcar_du_group_write(rgrp, DEFR7, defr7);
159
160	if (rcdu->info->gen >= 2) {
161		rcar_du_group_setup_defr8(rgrp);
162		rcar_du_group_setup_didsr(rgrp);
163	}
164
165	if (rcdu->info->gen >= 3)
166		rcar_du_group_write(rgrp, DEFR10, DEFR10_CODE | DEFR10_DEFE10);
167
168	/*
169	 * Use DS1PR and DS2PR to configure planes priorities and connects the
170	 * superposition 0 to DU0 pins. DU1 pins will be configured dynamically.
171	 */
172	rcar_du_group_write(rgrp, DORCR, DORCR_PG1D_DS1 | DORCR_DPRS);
173
174	/* Apply planes to CRTCs association. */
175	mutex_lock(&rgrp->lock);
176	rcar_du_group_write(rgrp, DPTSR, (rgrp->dptsr_planes << 16) |
177			    rgrp->dptsr_planes);
178	mutex_unlock(&rgrp->lock);
179}
180
181/*
182 * rcar_du_group_get - Acquire a reference to the DU channels group
183 *
184 * Acquiring the first reference setups core registers. A reference must be held
185 * before accessing any hardware registers.
186 *
187 * This function must be called with the DRM mode_config lock held.
188 *
189 * Return 0 in case of success or a negative error code otherwise.
190 */
191int rcar_du_group_get(struct rcar_du_group *rgrp)
192{
193	if (rgrp->use_count)
194		goto done;
195
196	rcar_du_group_setup(rgrp);
197
198done:
199	rgrp->use_count++;
200	return 0;
201}
202
203/*
204 * rcar_du_group_put - Release a reference to the DU
205 *
206 * This function must be called with the DRM mode_config lock held.
207 */
208void rcar_du_group_put(struct rcar_du_group *rgrp)
209{
210	--rgrp->use_count;
211}
212
213static void __rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
214{
215	struct rcar_du_device *rcdu = rgrp->dev;
216
217	/*
218	 * Group start/stop is controlled by the DRES and DEN bits of DSYSR0
219	 * for the first group and DSYSR2 for the second group. On most DU
220	 * instances, this maps to the first CRTC of the group, and we can just
221	 * use rcar_du_crtc_dsysr_clr_set() to access the correct DSYSR. On
222	 * M3-N, however, DU2 doesn't exist, but DSYSR2 does. We thus need to
223	 * access the register directly using group read/write.
224	 */
225	if (rcdu->info->channels_mask & BIT(rgrp->index * 2)) {
226		struct rcar_du_crtc *rcrtc = &rgrp->dev->crtcs[rgrp->index * 2];
227
228		rcar_du_crtc_dsysr_clr_set(rcrtc, DSYSR_DRES | DSYSR_DEN,
229					   start ? DSYSR_DEN : DSYSR_DRES);
230	} else {
231		rcar_du_group_write(rgrp, DSYSR,
232				    start ? DSYSR_DEN : DSYSR_DRES);
233	}
234}
235
236void rcar_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
237{
238	/*
239	 * Many of the configuration bits are only updated when the display
240	 * reset (DRES) bit in DSYSR is set to 1, disabling *both* CRTCs. Some
241	 * of those bits could be pre-configured, but others (especially the
242	 * bits related to plane assignment to display timing controllers) need
243	 * to be modified at runtime.
244	 *
245	 * Restart the display controller if a start is requested. Sorry for the
246	 * flicker. It should be possible to move most of the "DRES-update" bits
247	 * setup to driver initialization time and minimize the number of cases
248	 * when the display controller will have to be restarted.
249	 */
250	if (start) {
251		if (rgrp->used_crtcs++ != 0)
252			__rcar_du_group_start_stop(rgrp, false);
253		__rcar_du_group_start_stop(rgrp, true);
254	} else {
255		if (--rgrp->used_crtcs == 0)
256			__rcar_du_group_start_stop(rgrp, false);
257	}
258}
259
260void rcar_du_group_restart(struct rcar_du_group *rgrp)
261{
262	rgrp->need_restart = false;
263
264	__rcar_du_group_start_stop(rgrp, false);
265	__rcar_du_group_start_stop(rgrp, true);
266}
267
268int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu)
269{
270	struct rcar_du_group *rgrp;
271	struct rcar_du_crtc *crtc;
272	unsigned int index;
273	int ret;
274
275	if (rcdu->info->gen < 2)
276		return 0;
277
278	/*
279	 * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are
280	 * configured in the DEFR8 register of the first group on Gen2 and the
281	 * last group on Gen3. As this function can be called with the DU
282	 * channels of the corresponding CRTCs disabled, we need to enable the
283	 * group clock before accessing the register.
284	 */
285	index = rcdu->info->gen < 3 ? 0 : DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1;
286	rgrp = &rcdu->groups[index];
287	crtc = &rcdu->crtcs[index * 2];
288
289	ret = clk_prepare_enable(crtc->clock);
290	if (ret < 0)
291		return ret;
292
293	rcar_du_group_setup_defr8(rgrp);
294
295	clk_disable_unprepare(crtc->clock);
296
297	return 0;
298}
299
300static void rcar_du_group_set_dpad_levels(struct rcar_du_group *rgrp)
301{
302	static const u32 doflr_values[2] = {
303		DOFLR_HSYCFL0 | DOFLR_VSYCFL0 | DOFLR_ODDFL0 |
304		DOFLR_DISPFL0 | DOFLR_CDEFL0  | DOFLR_RGBFL0,
305		DOFLR_HSYCFL1 | DOFLR_VSYCFL1 | DOFLR_ODDFL1 |
306		DOFLR_DISPFL1 | DOFLR_CDEFL1  | DOFLR_RGBFL1,
307	};
308	static const u32 dpad_mask = BIT(RCAR_DU_OUTPUT_DPAD1)
309				   | BIT(RCAR_DU_OUTPUT_DPAD0);
310	struct rcar_du_device *rcdu = rgrp->dev;
311	u32 doflr = DOFLR_CODE;
312	unsigned int i;
313
314	if (rcdu->info->gen < 2)
315		return;
316
317	/*
318	 * The DPAD outputs can't be controlled directly. However, the parallel
319	 * output of the DU channels routed to DPAD can be set to fixed levels
320	 * through the DOFLR group register. Use this to turn the DPAD on or off
321	 * by driving fixed low-level signals at the output of any DU channel
322	 * not routed to a DPAD output. This doesn't affect the DU output
323	 * signals going to other outputs, such as the internal LVDS and HDMI
324	 * encoders.
325	 */
326
327	for (i = 0; i < rgrp->num_crtcs; ++i) {
328		struct rcar_du_crtc_state *rstate;
329		struct rcar_du_crtc *rcrtc;
330
331		rcrtc = &rcdu->crtcs[rgrp->index * 2 + i];
332		rstate = to_rcar_crtc_state(rcrtc->crtc.state);
333
334		if (!(rstate->outputs & dpad_mask))
335			doflr |= doflr_values[i];
336	}
337
338	rcar_du_group_write(rgrp, DOFLR, doflr);
339}
340
341int rcar_du_group_set_routing(struct rcar_du_group *rgrp)
342{
343	struct rcar_du_device *rcdu = rgrp->dev;
344	u32 dorcr = rcar_du_group_read(rgrp, DORCR);
345
346	dorcr &= ~(DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_MASK);
347
348	/*
349	 * Set the DPAD1 pins sources. Select CRTC 0 if explicitly requested and
350	 * CRTC 1 in all other cases to avoid cloning CRTC 0 to DPAD0 and DPAD1
351	 * by default.
352	 */
353	if (rcdu->dpad1_source == rgrp->index * 2)
354		dorcr |= DORCR_PG2D_DS1;
355	else
356		dorcr |= DORCR_PG2T | DORCR_DK2S | DORCR_PG2D_DS2;
357
358	rcar_du_group_write(rgrp, DORCR, dorcr);
359
360	rcar_du_group_set_dpad_levels(rgrp);
361
362	return rcar_du_set_dpad0_vsp1_routing(rgrp->dev);
363}
364