1/* 2 * Copyright 2013 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#include <linux/math64.h> 25#include <linux/pci.h> 26#include <linux/seq_file.h> 27 28#include "atom.h" 29#include "r600_dpm.h" 30#include "radeon.h" 31#include "radeon_asic.h" 32#include "si_dpm.h" 33#include "sid.h" 34 35#define MC_CG_ARB_FREQ_F0 0x0a 36#define MC_CG_ARB_FREQ_F1 0x0b 37#define MC_CG_ARB_FREQ_F2 0x0c 38#define MC_CG_ARB_FREQ_F3 0x0d 39 40#define SMC_RAM_END 0x20000 41 42#define SCLK_MIN_DEEPSLEEP_FREQ 1350 43 44static const struct si_cac_config_reg cac_weights_tahiti[] = 45{ 46 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND }, 47 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 48 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND }, 49 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND }, 50 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 51 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 52 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 53 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 54 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 55 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND }, 56 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 57 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND }, 58 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND }, 59 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND }, 60 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND }, 61 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 62 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 63 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND }, 64 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 65 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND }, 66 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND }, 67 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND }, 68 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 69 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 70 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 71 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 72 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 73 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 74 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 75 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 76 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND }, 77 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 78 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 79 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 80 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 81 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 82 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 83 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 84 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 85 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND }, 86 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 87 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 88 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 89 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 90 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 91 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 92 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 93 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 94 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 95 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 96 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 97 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 98 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 99 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 100 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 101 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 102 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 103 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 104 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 105 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND }, 106 { 0xFFFFFFFF } 107}; 108 109static const struct si_cac_config_reg lcac_tahiti[] = 110{ 111 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 112 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 113 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 114 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 115 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 116 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 117 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND }, 118 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 119 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 120 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 121 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 122 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 123 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 124 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 125 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 126 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 127 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 128 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 129 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 130 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 131 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 132 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 133 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 134 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 135 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 136 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 137 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 138 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 139 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 140 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 141 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 142 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 143 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 144 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 145 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 146 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 147 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 148 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 149 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 150 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 151 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 152 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 153 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 154 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 155 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 156 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 157 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND }, 158 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 159 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 160 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 161 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 162 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 163 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 164 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 165 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 166 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 167 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 168 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 169 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 170 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 171 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 172 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 173 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 174 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 175 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 176 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 177 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 178 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 179 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 180 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 181 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 182 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 183 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 184 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 185 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 186 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 187 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 188 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 189 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 190 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 191 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 192 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 193 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 194 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 195 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 196 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 197 { 0xFFFFFFFF } 198 199}; 200 201static const struct si_cac_config_reg cac_override_tahiti[] = 202{ 203 { 0xFFFFFFFF } 204}; 205 206static const struct si_powertune_data powertune_data_tahiti = 207{ 208 ((1 << 16) | 27027), 209 6, 210 0, 211 4, 212 95, 213 { 214 0UL, 215 0UL, 216 4521550UL, 217 309631529UL, 218 -1270850L, 219 4513710L, 220 40 221 }, 222 595000000UL, 223 12, 224 { 225 0, 226 0, 227 0, 228 0, 229 0, 230 0, 231 0, 232 0 233 }, 234 true 235}; 236 237static const struct si_dte_data dte_data_tahiti = 238{ 239 { 1159409, 0, 0, 0, 0 }, 240 { 777, 0, 0, 0, 0 }, 241 2, 242 54000, 243 127000, 244 25, 245 2, 246 10, 247 13, 248 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 }, 249 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 }, 250 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 }, 251 85, 252 false 253}; 254 255static const struct si_dte_data dte_data_tahiti_pro = 256{ 257 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 258 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 259 5, 260 45000, 261 100, 262 0xA, 263 1, 264 0, 265 0x10, 266 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 267 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 268 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 269 90, 270 true 271}; 272 273static const struct si_dte_data dte_data_new_zealand = 274{ 275 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 }, 276 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 }, 277 0x5, 278 0xAFC8, 279 0x69, 280 0x32, 281 1, 282 0, 283 0x10, 284 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE }, 285 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 286 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 }, 287 85, 288 true 289}; 290 291static const struct si_dte_data dte_data_aruba_pro = 292{ 293 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 294 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 295 5, 296 45000, 297 100, 298 0xA, 299 1, 300 0, 301 0x10, 302 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 303 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 304 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 305 90, 306 true 307}; 308 309static const struct si_dte_data dte_data_malta = 310{ 311 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 312 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 313 5, 314 45000, 315 100, 316 0xA, 317 1, 318 0, 319 0x10, 320 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 321 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 322 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 323 90, 324 true 325}; 326 327struct si_cac_config_reg cac_weights_pitcairn[] = 328{ 329 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND }, 330 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 331 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 332 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND }, 333 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND }, 334 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 335 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 336 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 337 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 338 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND }, 339 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND }, 340 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND }, 341 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND }, 342 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND }, 343 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 344 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 345 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 346 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND }, 347 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND }, 348 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND }, 349 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND }, 350 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND }, 351 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND }, 352 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 353 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 354 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 355 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND }, 356 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 357 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 358 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 359 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND }, 360 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 361 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND }, 362 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 363 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND }, 364 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND }, 365 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND }, 366 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 367 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND }, 368 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 369 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 370 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 371 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 372 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 373 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 374 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 375 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 376 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 377 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 378 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 379 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 380 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 381 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 382 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 383 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 384 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 385 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 386 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 387 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 388 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND }, 389 { 0xFFFFFFFF } 390}; 391 392static const struct si_cac_config_reg lcac_pitcairn[] = 393{ 394 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 395 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 396 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 397 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 398 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 399 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 400 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 401 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 402 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 403 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 404 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 405 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 406 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 407 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 408 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 409 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 410 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 411 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 412 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 413 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 414 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 415 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 416 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 417 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 418 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 419 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 420 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 421 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 422 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 423 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 424 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 425 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 426 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 427 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 428 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 429 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 430 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 431 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 432 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 433 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 434 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 435 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 436 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 437 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 438 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 439 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 440 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 441 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 442 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 443 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 444 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 445 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 446 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 447 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 448 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 449 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 450 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 451 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 452 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 453 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 454 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 455 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 456 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 457 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 458 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 459 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 460 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 461 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 462 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 463 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 464 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 465 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 466 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 467 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 468 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 469 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 470 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 471 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 472 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 473 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 474 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 475 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 476 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 477 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 478 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 479 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 480 { 0xFFFFFFFF } 481}; 482 483static const struct si_cac_config_reg cac_override_pitcairn[] = 484{ 485 { 0xFFFFFFFF } 486}; 487 488static const struct si_powertune_data powertune_data_pitcairn = 489{ 490 ((1 << 16) | 27027), 491 5, 492 0, 493 6, 494 100, 495 { 496 51600000UL, 497 1800000UL, 498 7194395UL, 499 309631529UL, 500 -1270850L, 501 4513710L, 502 100 503 }, 504 117830498UL, 505 12, 506 { 507 0, 508 0, 509 0, 510 0, 511 0, 512 0, 513 0, 514 0 515 }, 516 true 517}; 518 519static const struct si_dte_data dte_data_pitcairn = 520{ 521 { 0, 0, 0, 0, 0 }, 522 { 0, 0, 0, 0, 0 }, 523 0, 524 0, 525 0, 526 0, 527 0, 528 0, 529 0, 530 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 531 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 532 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 533 0, 534 false 535}; 536 537static const struct si_dte_data dte_data_curacao_xt = 538{ 539 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 540 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 541 5, 542 45000, 543 100, 544 0xA, 545 1, 546 0, 547 0x10, 548 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 549 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 550 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 551 90, 552 true 553}; 554 555static const struct si_dte_data dte_data_curacao_pro = 556{ 557 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 558 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 559 5, 560 45000, 561 100, 562 0xA, 563 1, 564 0, 565 0x10, 566 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 567 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 568 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 569 90, 570 true 571}; 572 573static const struct si_dte_data dte_data_neptune_xt = 574{ 575 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 576 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 577 5, 578 45000, 579 100, 580 0xA, 581 1, 582 0, 583 0x10, 584 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 585 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 586 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 587 90, 588 true 589}; 590 591static const struct si_cac_config_reg cac_weights_chelsea_pro[] = 592{ 593 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 594 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 595 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 596 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 597 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 598 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 599 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 600 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 601 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 602 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 603 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 604 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 605 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 606 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 607 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 608 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 609 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 610 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 611 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 612 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 613 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 614 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 615 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 616 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 617 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 618 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 619 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 620 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 621 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 622 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 623 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 624 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 625 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 626 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 627 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 628 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND }, 629 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 630 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 631 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 632 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 633 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 634 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 635 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 636 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 637 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 638 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 639 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 640 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 641 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 642 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 643 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 644 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 645 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 646 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 647 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 648 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 649 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 650 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 651 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 652 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 653 { 0xFFFFFFFF } 654}; 655 656static const struct si_cac_config_reg cac_weights_chelsea_xt[] = 657{ 658 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 659 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 660 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 661 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 662 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 663 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 664 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 665 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 666 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 667 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 668 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 669 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 670 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 671 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 672 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 673 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 674 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 675 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 676 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 677 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 678 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 679 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 680 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 681 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 682 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 683 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 684 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 685 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 686 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 687 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 688 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 689 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 690 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 691 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 692 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 693 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND }, 694 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 695 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 696 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 697 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 698 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 699 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 700 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 701 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 702 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 703 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 704 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 705 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 706 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 707 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 708 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 709 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 710 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 711 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 712 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 713 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 714 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 715 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 716 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 717 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 718 { 0xFFFFFFFF } 719}; 720 721static const struct si_cac_config_reg cac_weights_heathrow[] = 722{ 723 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 724 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 725 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 726 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 727 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 728 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 729 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 730 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 731 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 732 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 733 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 734 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 735 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 736 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 737 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 738 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 739 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 740 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 741 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 742 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 743 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 744 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 745 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 746 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 747 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 748 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 749 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 750 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 751 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 752 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 753 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 754 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 755 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 756 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 757 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 758 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND }, 759 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 760 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 761 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 762 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 763 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 764 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 765 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 766 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 767 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 768 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 769 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 770 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 771 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 772 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 773 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 774 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 775 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 776 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 777 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 778 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 779 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 780 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 781 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 782 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 783 { 0xFFFFFFFF } 784}; 785 786static const struct si_cac_config_reg cac_weights_cape_verde_pro[] = 787{ 788 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 789 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 790 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 791 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 792 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 793 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 794 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 795 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 796 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 797 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 798 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 799 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 800 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 801 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 802 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 803 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 804 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 805 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 806 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 807 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 808 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 809 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 810 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 811 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 812 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 813 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 814 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 815 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 816 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 817 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 818 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 819 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 820 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 821 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 822 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 823 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND }, 824 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 825 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 826 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 827 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 828 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 829 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 830 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 831 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 832 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 833 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 834 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 835 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 836 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 837 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 838 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 839 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 840 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 841 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 842 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 843 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 844 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 845 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 846 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 847 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 848 { 0xFFFFFFFF } 849}; 850 851static const struct si_cac_config_reg cac_weights_cape_verde[] = 852{ 853 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 854 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 855 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 856 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 857 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 858 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 859 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 860 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 861 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 862 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 863 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 864 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 865 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 866 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 867 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 868 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 869 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 870 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 871 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 872 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 873 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 874 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 875 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 876 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 877 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 878 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 879 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 880 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 881 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 882 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 883 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 884 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 885 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 886 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 887 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 888 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 889 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 890 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 891 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 892 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 893 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 894 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 895 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 896 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 897 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 898 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 899 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 900 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 901 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 902 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 903 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 904 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 905 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 906 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 907 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 908 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 909 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 910 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 911 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 912 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 913 { 0xFFFFFFFF } 914}; 915 916static const struct si_cac_config_reg lcac_cape_verde[] = 917{ 918 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 919 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 920 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 921 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 922 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 923 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 924 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 925 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 926 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 927 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 928 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 929 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 930 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 931 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 932 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 933 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 934 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 935 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 936 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND }, 937 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 938 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 939 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 940 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 941 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 942 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 943 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 944 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 945 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 946 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 947 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 948 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 949 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 950 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 951 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 952 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 953 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 954 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 955 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 956 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 957 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 958 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 959 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 960 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 961 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 962 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 963 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 964 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 965 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 966 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 967 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 968 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 969 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 970 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 971 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 972 { 0xFFFFFFFF } 973}; 974 975static const struct si_cac_config_reg cac_override_cape_verde[] = 976{ 977 { 0xFFFFFFFF } 978}; 979 980static const struct si_powertune_data powertune_data_cape_verde = 981{ 982 ((1 << 16) | 0x6993), 983 5, 984 0, 985 7, 986 105, 987 { 988 0UL, 989 0UL, 990 7194395UL, 991 309631529UL, 992 -1270850L, 993 4513710L, 994 100 995 }, 996 117830498UL, 997 12, 998 { 999 0, 1000 0, 1001 0, 1002 0, 1003 0, 1004 0, 1005 0, 1006 0 1007 }, 1008 true 1009}; 1010 1011static const struct si_dte_data dte_data_cape_verde = 1012{ 1013 { 0, 0, 0, 0, 0 }, 1014 { 0, 0, 0, 0, 0 }, 1015 0, 1016 0, 1017 0, 1018 0, 1019 0, 1020 0, 1021 0, 1022 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1023 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1024 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1025 0, 1026 false 1027}; 1028 1029static const struct si_dte_data dte_data_venus_xtx = 1030{ 1031 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1032 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 }, 1033 5, 1034 55000, 1035 0x69, 1036 0xA, 1037 1, 1038 0, 1039 0x3, 1040 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1041 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1042 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1043 90, 1044 true 1045}; 1046 1047static const struct si_dte_data dte_data_venus_xt = 1048{ 1049 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1050 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 }, 1051 5, 1052 55000, 1053 0x69, 1054 0xA, 1055 1, 1056 0, 1057 0x3, 1058 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1059 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1060 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1061 90, 1062 true 1063}; 1064 1065static const struct si_dte_data dte_data_venus_pro = 1066{ 1067 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1068 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 }, 1069 5, 1070 55000, 1071 0x69, 1072 0xA, 1073 1, 1074 0, 1075 0x3, 1076 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1077 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1078 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1079 90, 1080 true 1081}; 1082 1083struct si_cac_config_reg cac_weights_oland[] = 1084{ 1085 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND }, 1086 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1087 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND }, 1088 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND }, 1089 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1090 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1091 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND }, 1092 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND }, 1093 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND }, 1094 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND }, 1095 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND }, 1096 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND }, 1097 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND }, 1098 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1099 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND }, 1100 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND }, 1101 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND }, 1102 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND }, 1103 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND }, 1104 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND }, 1105 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND }, 1106 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND }, 1107 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND }, 1108 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND }, 1109 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND }, 1110 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1111 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1112 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1113 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1114 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND }, 1115 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1116 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND }, 1117 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND }, 1118 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND }, 1119 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1120 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND }, 1121 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1122 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1123 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1124 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND }, 1125 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND }, 1126 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1127 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1128 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1129 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1130 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1131 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1132 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1133 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1134 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1135 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1136 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1137 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1138 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1139 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1140 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1141 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1142 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1143 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1144 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND }, 1145 { 0xFFFFFFFF } 1146}; 1147 1148static const struct si_cac_config_reg cac_weights_mars_pro[] = 1149{ 1150 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1151 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1152 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1153 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1154 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1155 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1156 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1157 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1158 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1159 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1160 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1161 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1162 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1163 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1164 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1165 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1166 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1167 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1168 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1169 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1170 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1171 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1172 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1173 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1174 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1175 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1176 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1177 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1178 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1179 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1180 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1181 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1182 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1183 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1184 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1185 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND }, 1186 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1187 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1188 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1189 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1190 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1191 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1192 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1193 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1194 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1195 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1196 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1197 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1198 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1199 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1200 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1201 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1202 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1203 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1204 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1205 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1206 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1207 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1208 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1209 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1210 { 0xFFFFFFFF } 1211}; 1212 1213static const struct si_cac_config_reg cac_weights_mars_xt[] = 1214{ 1215 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1216 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1217 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1218 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1219 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1220 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1221 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1222 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1223 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1224 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1225 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1226 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1227 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1228 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1229 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1230 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1231 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1232 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1233 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1234 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1235 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1236 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1237 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1238 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1239 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1240 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1241 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1242 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1243 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1244 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1245 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1246 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1247 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1248 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1249 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1250 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND }, 1251 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1252 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1253 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1254 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1255 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1256 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1257 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1258 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1259 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1260 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1261 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1262 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1263 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1264 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1265 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1266 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1267 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1268 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1269 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1270 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1271 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1272 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1273 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1274 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1275 { 0xFFFFFFFF } 1276}; 1277 1278static const struct si_cac_config_reg cac_weights_oland_pro[] = 1279{ 1280 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1281 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1282 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1283 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1284 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1285 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1286 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1287 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1288 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1289 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1290 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1291 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1292 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1293 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1294 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1295 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1296 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1297 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1298 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1299 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1300 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1301 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1302 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1303 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1304 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1305 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1306 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1307 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1308 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1309 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1310 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1311 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1312 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1313 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1314 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1315 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND }, 1316 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1317 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1318 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1319 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1320 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1321 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1322 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1323 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1324 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1325 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1326 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1327 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1328 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1329 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1330 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1331 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1332 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1333 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1334 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1335 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1336 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1337 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1338 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1339 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1340 { 0xFFFFFFFF } 1341}; 1342 1343static const struct si_cac_config_reg cac_weights_oland_xt[] = 1344{ 1345 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND }, 1346 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1347 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND }, 1348 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND }, 1349 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1350 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1351 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND }, 1352 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND }, 1353 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND }, 1354 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND }, 1355 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND }, 1356 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND }, 1357 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND }, 1358 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND }, 1359 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND }, 1360 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND }, 1361 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND }, 1362 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND }, 1363 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND }, 1364 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND }, 1365 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND }, 1366 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND }, 1367 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND }, 1368 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND }, 1369 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND }, 1370 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND }, 1371 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND }, 1372 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND }, 1373 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1374 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND }, 1375 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND }, 1376 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1377 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND }, 1378 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND }, 1379 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND }, 1380 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND }, 1381 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1382 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND }, 1383 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1384 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND }, 1385 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND }, 1386 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1387 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1388 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1389 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1390 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1391 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND }, 1392 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND }, 1393 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1394 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1395 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND }, 1396 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND }, 1397 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1398 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1399 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1400 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1401 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1402 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1403 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1404 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND }, 1405 { 0xFFFFFFFF } 1406}; 1407 1408static const struct si_cac_config_reg lcac_oland[] = 1409{ 1410 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1411 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1412 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1413 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1414 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1415 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1416 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1417 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1418 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1419 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1420 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND }, 1421 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1422 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1423 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1424 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1425 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1426 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1427 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1428 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1429 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1430 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1431 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1432 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1433 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1434 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1435 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1436 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1437 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1438 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1439 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1440 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1441 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1442 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1443 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1444 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1445 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1446 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1447 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1448 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1449 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1450 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1451 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1452 { 0xFFFFFFFF } 1453}; 1454 1455static const struct si_cac_config_reg lcac_mars_pro[] = 1456{ 1457 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1458 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1459 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1460 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1461 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1462 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1463 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1464 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1465 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND }, 1466 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1467 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1468 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1469 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1470 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1471 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1472 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1473 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1474 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1475 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1476 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1477 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1478 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1479 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1480 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1481 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1482 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1483 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1484 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1485 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND }, 1486 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1487 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1488 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1489 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1490 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1491 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1492 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1493 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1494 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1495 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1496 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1497 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND }, 1498 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND }, 1499 { 0xFFFFFFFF } 1500}; 1501 1502static const struct si_cac_config_reg cac_override_oland[] = 1503{ 1504 { 0xFFFFFFFF } 1505}; 1506 1507static const struct si_powertune_data powertune_data_oland = 1508{ 1509 ((1 << 16) | 0x6993), 1510 5, 1511 0, 1512 7, 1513 105, 1514 { 1515 0UL, 1516 0UL, 1517 7194395UL, 1518 309631529UL, 1519 -1270850L, 1520 4513710L, 1521 100 1522 }, 1523 117830498UL, 1524 12, 1525 { 1526 0, 1527 0, 1528 0, 1529 0, 1530 0, 1531 0, 1532 0, 1533 0 1534 }, 1535 true 1536}; 1537 1538static const struct si_powertune_data powertune_data_mars_pro = 1539{ 1540 ((1 << 16) | 0x6993), 1541 5, 1542 0, 1543 7, 1544 105, 1545 { 1546 0UL, 1547 0UL, 1548 7194395UL, 1549 309631529UL, 1550 -1270850L, 1551 4513710L, 1552 100 1553 }, 1554 117830498UL, 1555 12, 1556 { 1557 0, 1558 0, 1559 0, 1560 0, 1561 0, 1562 0, 1563 0, 1564 0 1565 }, 1566 true 1567}; 1568 1569static const struct si_dte_data dte_data_oland = 1570{ 1571 { 0, 0, 0, 0, 0 }, 1572 { 0, 0, 0, 0, 0 }, 1573 0, 1574 0, 1575 0, 1576 0, 1577 0, 1578 0, 1579 0, 1580 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1581 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1582 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 1583 0, 1584 false 1585}; 1586 1587static const struct si_dte_data dte_data_mars_pro = 1588{ 1589 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1590 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1591 5, 1592 55000, 1593 105, 1594 0xA, 1595 1, 1596 0, 1597 0x10, 1598 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1599 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1600 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1601 90, 1602 true 1603}; 1604 1605static const struct si_dte_data dte_data_sun_xt = 1606{ 1607 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 }, 1608 { 0x0, 0x0, 0x0, 0x0, 0x0 }, 1609 5, 1610 55000, 1611 105, 1612 0xA, 1613 1, 1614 0, 1615 0x10, 1616 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, 1617 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 }, 1618 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }, 1619 90, 1620 true 1621}; 1622 1623 1624static const struct si_cac_config_reg cac_weights_hainan[] = 1625{ 1626 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND }, 1627 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND }, 1628 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND }, 1629 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND }, 1630 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1631 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND }, 1632 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1633 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1634 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1635 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND }, 1636 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND }, 1637 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND }, 1638 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND }, 1639 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1640 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND }, 1641 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1642 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1643 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND }, 1644 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND }, 1645 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND }, 1646 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND }, 1647 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND }, 1648 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND }, 1649 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND }, 1650 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1651 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND }, 1652 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND }, 1653 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1654 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1655 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1656 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND }, 1657 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1658 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1659 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1660 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND }, 1661 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND }, 1662 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND }, 1663 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1664 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1665 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND }, 1666 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1667 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND }, 1668 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1669 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1670 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND }, 1671 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND }, 1672 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1673 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1674 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1675 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1676 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1677 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1678 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1679 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1680 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1681 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1682 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1683 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND }, 1684 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND }, 1685 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND }, 1686 { 0xFFFFFFFF } 1687}; 1688 1689static const struct si_powertune_data powertune_data_hainan = 1690{ 1691 ((1 << 16) | 0x6993), 1692 5, 1693 0, 1694 9, 1695 105, 1696 { 1697 0UL, 1698 0UL, 1699 7194395UL, 1700 309631529UL, 1701 -1270850L, 1702 4513710L, 1703 100 1704 }, 1705 117830498UL, 1706 12, 1707 { 1708 0, 1709 0, 1710 0, 1711 0, 1712 0, 1713 0, 1714 0, 1715 0 1716 }, 1717 true 1718}; 1719 1720struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 1721struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev); 1722struct ni_power_info *ni_get_pi(struct radeon_device *rdev); 1723struct ni_ps *ni_get_ps(struct radeon_ps *rps); 1724 1725extern int si_mc_load_microcode(struct radeon_device *rdev); 1726extern void vce_v1_0_enable_mgcg(struct radeon_device *rdev, bool enable); 1727 1728static int si_populate_voltage_value(struct radeon_device *rdev, 1729 const struct atom_voltage_table *table, 1730 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage); 1731static int si_get_std_voltage_value(struct radeon_device *rdev, 1732 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 1733 u16 *std_voltage); 1734static int si_write_smc_soft_register(struct radeon_device *rdev, 1735 u16 reg_offset, u32 value); 1736static int si_convert_power_level_to_smc(struct radeon_device *rdev, 1737 struct rv7xx_pl *pl, 1738 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level); 1739static int si_calculate_sclk_params(struct radeon_device *rdev, 1740 u32 engine_clock, 1741 SISLANDS_SMC_SCLK_VALUE *sclk); 1742 1743static void si_thermal_start_smc_fan_control(struct radeon_device *rdev); 1744static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev); 1745 1746static struct si_power_info *si_get_pi(struct radeon_device *rdev) 1747{ 1748 struct si_power_info *pi = rdev->pm.dpm.priv; 1749 1750 return pi; 1751} 1752 1753static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff, 1754 u16 v, s32 t, u32 ileakage, u32 *leakage) 1755{ 1756 s64 kt, kv, leakage_w, i_leakage, vddc; 1757 s64 temperature, t_slope, t_intercept, av, bv, t_ref; 1758 s64 tmp; 1759 1760 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1761 vddc = div64_s64(drm_int2fixp(v), 1000); 1762 temperature = div64_s64(drm_int2fixp(t), 1000); 1763 1764 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000); 1765 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000); 1766 av = div64_s64(drm_int2fixp(coeff->av), 100000000); 1767 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000); 1768 t_ref = drm_int2fixp(coeff->t_ref); 1769 1770 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept; 1771 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature)); 1772 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref))); 1773 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc))); 1774 1775 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1776 1777 *leakage = drm_fixp2int(leakage_w * 1000); 1778} 1779 1780static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev, 1781 const struct ni_leakage_coeffients *coeff, 1782 u16 v, 1783 s32 t, 1784 u32 i_leakage, 1785 u32 *leakage) 1786{ 1787 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); 1788} 1789 1790static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff, 1791 const u32 fixed_kt, u16 v, 1792 u32 ileakage, u32 *leakage) 1793{ 1794 s64 kt, kv, leakage_w, i_leakage, vddc; 1795 1796 i_leakage = div64_s64(drm_int2fixp(ileakage), 100); 1797 vddc = div64_s64(drm_int2fixp(v), 1000); 1798 1799 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000); 1800 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000), 1801 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc))); 1802 1803 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc); 1804 1805 *leakage = drm_fixp2int(leakage_w * 1000); 1806} 1807 1808static void si_calculate_leakage_for_v(struct radeon_device *rdev, 1809 const struct ni_leakage_coeffients *coeff, 1810 const u32 fixed_kt, 1811 u16 v, 1812 u32 i_leakage, 1813 u32 *leakage) 1814{ 1815 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage); 1816} 1817 1818 1819static void si_update_dte_from_pl2(struct radeon_device *rdev, 1820 struct si_dte_data *dte_data) 1821{ 1822 u32 p_limit1 = rdev->pm.dpm.tdp_limit; 1823 u32 p_limit2 = rdev->pm.dpm.near_tdp_limit; 1824 u32 k = dte_data->k; 1825 u32 t_max = dte_data->max_t; 1826 u32 t_split[5] = { 10, 15, 20, 25, 30 }; 1827 u32 t_0 = dte_data->t0; 1828 u32 i; 1829 1830 if (p_limit2 != 0 && p_limit2 <= p_limit1) { 1831 dte_data->tdep_count = 3; 1832 1833 for (i = 0; i < k; i++) { 1834 dte_data->r[i] = 1835 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) / 1836 (p_limit2 * (u32)100); 1837 } 1838 1839 dte_data->tdep_r[1] = dte_data->r[4] * 2; 1840 1841 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) { 1842 dte_data->tdep_r[i] = dte_data->r[4]; 1843 } 1844 } else { 1845 DRM_ERROR("Invalid PL2! DTE will not be updated.\n"); 1846 } 1847} 1848 1849static void si_initialize_powertune_defaults(struct radeon_device *rdev) 1850{ 1851 struct ni_power_info *ni_pi = ni_get_pi(rdev); 1852 struct si_power_info *si_pi = si_get_pi(rdev); 1853 bool update_dte_from_pl2 = false; 1854 1855 if (rdev->family == CHIP_TAHITI) { 1856 si_pi->cac_weights = cac_weights_tahiti; 1857 si_pi->lcac_config = lcac_tahiti; 1858 si_pi->cac_override = cac_override_tahiti; 1859 si_pi->powertune_data = &powertune_data_tahiti; 1860 si_pi->dte_data = dte_data_tahiti; 1861 1862 switch (rdev->pdev->device) { 1863 case 0x6798: 1864 si_pi->dte_data.enable_dte_by_default = true; 1865 break; 1866 case 0x6799: 1867 si_pi->dte_data = dte_data_new_zealand; 1868 break; 1869 case 0x6790: 1870 case 0x6791: 1871 case 0x6792: 1872 case 0x679E: 1873 si_pi->dte_data = dte_data_aruba_pro; 1874 update_dte_from_pl2 = true; 1875 break; 1876 case 0x679B: 1877 si_pi->dte_data = dte_data_malta; 1878 update_dte_from_pl2 = true; 1879 break; 1880 case 0x679A: 1881 si_pi->dte_data = dte_data_tahiti_pro; 1882 update_dte_from_pl2 = true; 1883 break; 1884 default: 1885 if (si_pi->dte_data.enable_dte_by_default == true) 1886 DRM_ERROR("DTE is not enabled!\n"); 1887 break; 1888 } 1889 } else if (rdev->family == CHIP_PITCAIRN) { 1890 switch (rdev->pdev->device) { 1891 case 0x6810: 1892 case 0x6818: 1893 si_pi->cac_weights = cac_weights_pitcairn; 1894 si_pi->lcac_config = lcac_pitcairn; 1895 si_pi->cac_override = cac_override_pitcairn; 1896 si_pi->powertune_data = &powertune_data_pitcairn; 1897 si_pi->dte_data = dte_data_curacao_xt; 1898 update_dte_from_pl2 = true; 1899 break; 1900 case 0x6819: 1901 case 0x6811: 1902 si_pi->cac_weights = cac_weights_pitcairn; 1903 si_pi->lcac_config = lcac_pitcairn; 1904 si_pi->cac_override = cac_override_pitcairn; 1905 si_pi->powertune_data = &powertune_data_pitcairn; 1906 si_pi->dte_data = dte_data_curacao_pro; 1907 update_dte_from_pl2 = true; 1908 break; 1909 case 0x6800: 1910 case 0x6806: 1911 si_pi->cac_weights = cac_weights_pitcairn; 1912 si_pi->lcac_config = lcac_pitcairn; 1913 si_pi->cac_override = cac_override_pitcairn; 1914 si_pi->powertune_data = &powertune_data_pitcairn; 1915 si_pi->dte_data = dte_data_neptune_xt; 1916 update_dte_from_pl2 = true; 1917 break; 1918 default: 1919 si_pi->cac_weights = cac_weights_pitcairn; 1920 si_pi->lcac_config = lcac_pitcairn; 1921 si_pi->cac_override = cac_override_pitcairn; 1922 si_pi->powertune_data = &powertune_data_pitcairn; 1923 si_pi->dte_data = dte_data_pitcairn; 1924 break; 1925 } 1926 } else if (rdev->family == CHIP_VERDE) { 1927 si_pi->lcac_config = lcac_cape_verde; 1928 si_pi->cac_override = cac_override_cape_verde; 1929 si_pi->powertune_data = &powertune_data_cape_verde; 1930 1931 switch (rdev->pdev->device) { 1932 case 0x683B: 1933 case 0x683F: 1934 case 0x6829: 1935 case 0x6835: 1936 si_pi->cac_weights = cac_weights_cape_verde_pro; 1937 si_pi->dte_data = dte_data_cape_verde; 1938 break; 1939 case 0x682C: 1940 si_pi->cac_weights = cac_weights_cape_verde_pro; 1941 si_pi->dte_data = dte_data_sun_xt; 1942 update_dte_from_pl2 = true; 1943 break; 1944 case 0x6825: 1945 case 0x6827: 1946 si_pi->cac_weights = cac_weights_heathrow; 1947 si_pi->dte_data = dte_data_cape_verde; 1948 break; 1949 case 0x6824: 1950 case 0x682D: 1951 si_pi->cac_weights = cac_weights_chelsea_xt; 1952 si_pi->dte_data = dte_data_cape_verde; 1953 break; 1954 case 0x682F: 1955 si_pi->cac_weights = cac_weights_chelsea_pro; 1956 si_pi->dte_data = dte_data_cape_verde; 1957 break; 1958 case 0x6820: 1959 si_pi->cac_weights = cac_weights_heathrow; 1960 si_pi->dte_data = dte_data_venus_xtx; 1961 break; 1962 case 0x6821: 1963 si_pi->cac_weights = cac_weights_heathrow; 1964 si_pi->dte_data = dte_data_venus_xt; 1965 break; 1966 case 0x6823: 1967 case 0x682B: 1968 case 0x6822: 1969 case 0x682A: 1970 si_pi->cac_weights = cac_weights_chelsea_pro; 1971 si_pi->dte_data = dte_data_venus_pro; 1972 break; 1973 default: 1974 si_pi->cac_weights = cac_weights_cape_verde; 1975 si_pi->dte_data = dte_data_cape_verde; 1976 break; 1977 } 1978 } else if (rdev->family == CHIP_OLAND) { 1979 switch (rdev->pdev->device) { 1980 case 0x6601: 1981 case 0x6621: 1982 case 0x6603: 1983 case 0x6605: 1984 si_pi->cac_weights = cac_weights_mars_pro; 1985 si_pi->lcac_config = lcac_mars_pro; 1986 si_pi->cac_override = cac_override_oland; 1987 si_pi->powertune_data = &powertune_data_mars_pro; 1988 si_pi->dte_data = dte_data_mars_pro; 1989 update_dte_from_pl2 = true; 1990 break; 1991 case 0x6600: 1992 case 0x6606: 1993 case 0x6620: 1994 case 0x6604: 1995 si_pi->cac_weights = cac_weights_mars_xt; 1996 si_pi->lcac_config = lcac_mars_pro; 1997 si_pi->cac_override = cac_override_oland; 1998 si_pi->powertune_data = &powertune_data_mars_pro; 1999 si_pi->dte_data = dte_data_mars_pro; 2000 update_dte_from_pl2 = true; 2001 break; 2002 case 0x6611: 2003 case 0x6613: 2004 case 0x6608: 2005 si_pi->cac_weights = cac_weights_oland_pro; 2006 si_pi->lcac_config = lcac_mars_pro; 2007 si_pi->cac_override = cac_override_oland; 2008 si_pi->powertune_data = &powertune_data_mars_pro; 2009 si_pi->dte_data = dte_data_mars_pro; 2010 update_dte_from_pl2 = true; 2011 break; 2012 case 0x6610: 2013 si_pi->cac_weights = cac_weights_oland_xt; 2014 si_pi->lcac_config = lcac_mars_pro; 2015 si_pi->cac_override = cac_override_oland; 2016 si_pi->powertune_data = &powertune_data_mars_pro; 2017 si_pi->dte_data = dte_data_mars_pro; 2018 update_dte_from_pl2 = true; 2019 break; 2020 default: 2021 si_pi->cac_weights = cac_weights_oland; 2022 si_pi->lcac_config = lcac_oland; 2023 si_pi->cac_override = cac_override_oland; 2024 si_pi->powertune_data = &powertune_data_oland; 2025 si_pi->dte_data = dte_data_oland; 2026 break; 2027 } 2028 } else if (rdev->family == CHIP_HAINAN) { 2029 si_pi->cac_weights = cac_weights_hainan; 2030 si_pi->lcac_config = lcac_oland; 2031 si_pi->cac_override = cac_override_oland; 2032 si_pi->powertune_data = &powertune_data_hainan; 2033 si_pi->dte_data = dte_data_sun_xt; 2034 update_dte_from_pl2 = true; 2035 } else { 2036 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n"); 2037 return; 2038 } 2039 2040 ni_pi->enable_power_containment = false; 2041 ni_pi->enable_cac = false; 2042 ni_pi->enable_sq_ramping = false; 2043 si_pi->enable_dte = false; 2044 2045 if (si_pi->powertune_data->enable_powertune_by_default) { 2046 ni_pi->enable_power_containment= true; 2047 ni_pi->enable_cac = true; 2048 if (si_pi->dte_data.enable_dte_by_default) { 2049 si_pi->enable_dte = true; 2050 if (update_dte_from_pl2) 2051 si_update_dte_from_pl2(rdev, &si_pi->dte_data); 2052 2053 } 2054 ni_pi->enable_sq_ramping = true; 2055 } 2056 2057 ni_pi->driver_calculate_cac_leakage = true; 2058 ni_pi->cac_configuration_required = true; 2059 2060 if (ni_pi->cac_configuration_required) { 2061 ni_pi->support_cac_long_term_average = true; 2062 si_pi->dyn_powertune_data.l2_lta_window_size = 2063 si_pi->powertune_data->l2_lta_window_size_default; 2064 si_pi->dyn_powertune_data.lts_truncate = 2065 si_pi->powertune_data->lts_truncate_default; 2066 } else { 2067 ni_pi->support_cac_long_term_average = false; 2068 si_pi->dyn_powertune_data.l2_lta_window_size = 0; 2069 si_pi->dyn_powertune_data.lts_truncate = 0; 2070 } 2071 2072 si_pi->dyn_powertune_data.disable_uvd_powertune = false; 2073} 2074 2075static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev) 2076{ 2077 return 1; 2078} 2079 2080static u32 si_calculate_cac_wintime(struct radeon_device *rdev) 2081{ 2082 u32 xclk; 2083 u32 wintime; 2084 u32 cac_window; 2085 u32 cac_window_size; 2086 2087 xclk = radeon_get_xclk(rdev); 2088 2089 if (xclk == 0) 2090 return 0; 2091 2092 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK; 2093 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF); 2094 2095 wintime = (cac_window_size * 100) / xclk; 2096 2097 return wintime; 2098} 2099 2100static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor) 2101{ 2102 return power_in_watts; 2103} 2104 2105static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev, 2106 bool adjust_polarity, 2107 u32 tdp_adjustment, 2108 u32 *tdp_limit, 2109 u32 *near_tdp_limit) 2110{ 2111 u32 adjustment_delta, max_tdp_limit; 2112 2113 if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit) 2114 return -EINVAL; 2115 2116 max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100; 2117 2118 if (adjust_polarity) { 2119 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2120 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit); 2121 } else { 2122 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100; 2123 adjustment_delta = rdev->pm.dpm.tdp_limit - *tdp_limit; 2124 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted) 2125 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta; 2126 else 2127 *near_tdp_limit = 0; 2128 } 2129 2130 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit)) 2131 return -EINVAL; 2132 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit)) 2133 return -EINVAL; 2134 2135 return 0; 2136} 2137 2138static int si_populate_smc_tdp_limits(struct radeon_device *rdev, 2139 struct radeon_ps *radeon_state) 2140{ 2141 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2142 struct si_power_info *si_pi = si_get_pi(rdev); 2143 2144 if (ni_pi->enable_power_containment) { 2145 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2146 PP_SIslands_PAPMParameters *papm_parm; 2147 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table; 2148 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2149 u32 tdp_limit; 2150 u32 near_tdp_limit; 2151 int ret; 2152 2153 if (scaling_factor == 0) 2154 return -EINVAL; 2155 2156 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2157 2158 ret = si_calculate_adjusted_tdp_limits(rdev, 2159 false, /* ??? */ 2160 rdev->pm.dpm.tdp_adjustment, 2161 &tdp_limit, 2162 &near_tdp_limit); 2163 if (ret) 2164 return ret; 2165 2166 smc_table->dpm2Params.TDPLimit = 2167 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000); 2168 smc_table->dpm2Params.NearTDPLimit = 2169 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000); 2170 smc_table->dpm2Params.SafePowerLimit = 2171 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2172 2173 ret = si_copy_bytes_to_smc(rdev, 2174 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2175 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)), 2176 (u8 *)(&(smc_table->dpm2Params.TDPLimit)), 2177 sizeof(u32) * 3, 2178 si_pi->sram_end); 2179 if (ret) 2180 return ret; 2181 2182 if (si_pi->enable_ppm) { 2183 papm_parm = &si_pi->papm_parm; 2184 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters)); 2185 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp); 2186 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max); 2187 papm_parm->dGPU_T_Warning = cpu_to_be32(95); 2188 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5); 2189 papm_parm->PlatformPowerLimit = 0xffffffff; 2190 papm_parm->NearTDPLimitPAPM = 0xffffffff; 2191 2192 ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start, 2193 (u8 *)papm_parm, 2194 sizeof(PP_SIslands_PAPMParameters), 2195 si_pi->sram_end); 2196 if (ret) 2197 return ret; 2198 } 2199 } 2200 return 0; 2201} 2202 2203static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev, 2204 struct radeon_ps *radeon_state) 2205{ 2206 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2207 struct si_power_info *si_pi = si_get_pi(rdev); 2208 2209 if (ni_pi->enable_power_containment) { 2210 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable; 2211 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2212 int ret; 2213 2214 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE)); 2215 2216 smc_table->dpm2Params.NearTDPLimit = 2217 cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000); 2218 smc_table->dpm2Params.SafePowerLimit = 2219 cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000); 2220 2221 ret = si_copy_bytes_to_smc(rdev, 2222 (si_pi->state_table_start + 2223 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) + 2224 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)), 2225 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)), 2226 sizeof(u32) * 2, 2227 si_pi->sram_end); 2228 if (ret) 2229 return ret; 2230 } 2231 2232 return 0; 2233} 2234 2235static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev, 2236 const u16 prev_std_vddc, 2237 const u16 curr_std_vddc) 2238{ 2239 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN; 2240 u64 prev_vddc = (u64)prev_std_vddc; 2241 u64 curr_vddc = (u64)curr_std_vddc; 2242 u64 pwr_efficiency_ratio, n, d; 2243 2244 if ((prev_vddc == 0) || (curr_vddc == 0)) 2245 return 0; 2246 2247 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000); 2248 d = prev_vddc * prev_vddc; 2249 pwr_efficiency_ratio = div64_u64(n, d); 2250 2251 if (pwr_efficiency_ratio > (u64)0xFFFF) 2252 return 0; 2253 2254 return (u16)pwr_efficiency_ratio; 2255} 2256 2257static bool si_should_disable_uvd_powertune(struct radeon_device *rdev, 2258 struct radeon_ps *radeon_state) 2259{ 2260 struct si_power_info *si_pi = si_get_pi(rdev); 2261 2262 if (si_pi->dyn_powertune_data.disable_uvd_powertune && 2263 radeon_state->vclk && radeon_state->dclk) 2264 return true; 2265 2266 return false; 2267} 2268 2269static int si_populate_power_containment_values(struct radeon_device *rdev, 2270 struct radeon_ps *radeon_state, 2271 SISLANDS_SMC_SWSTATE *smc_state) 2272{ 2273 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 2274 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2275 struct ni_ps *state = ni_get_ps(radeon_state); 2276 SISLANDS_SMC_VOLTAGE_VALUE vddc; 2277 u32 prev_sclk; 2278 u32 max_sclk; 2279 u32 min_sclk; 2280 u16 prev_std_vddc; 2281 u16 curr_std_vddc; 2282 int i; 2283 u16 pwr_efficiency_ratio; 2284 u8 max_ps_percent; 2285 bool disable_uvd_power_tune; 2286 int ret; 2287 2288 if (ni_pi->enable_power_containment == false) 2289 return 0; 2290 2291 if (state->performance_level_count == 0) 2292 return -EINVAL; 2293 2294 if (smc_state->levelCount != state->performance_level_count) 2295 return -EINVAL; 2296 2297 disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state); 2298 2299 smc_state->levels[0].dpm2.MaxPS = 0; 2300 smc_state->levels[0].dpm2.NearTDPDec = 0; 2301 smc_state->levels[0].dpm2.AboveSafeInc = 0; 2302 smc_state->levels[0].dpm2.BelowSafeInc = 0; 2303 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0; 2304 2305 for (i = 1; i < state->performance_level_count; i++) { 2306 prev_sclk = state->performance_levels[i-1].sclk; 2307 max_sclk = state->performance_levels[i].sclk; 2308 if (i == 1) 2309 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M; 2310 else 2311 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H; 2312 2313 if (prev_sclk > max_sclk) 2314 return -EINVAL; 2315 2316 if ((max_ps_percent == 0) || 2317 (prev_sclk == max_sclk) || 2318 disable_uvd_power_tune) { 2319 min_sclk = max_sclk; 2320 } else if (i == 1) { 2321 min_sclk = prev_sclk; 2322 } else { 2323 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100; 2324 } 2325 2326 if (min_sclk < state->performance_levels[0].sclk) 2327 min_sclk = state->performance_levels[0].sclk; 2328 2329 if (min_sclk == 0) 2330 return -EINVAL; 2331 2332 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2333 state->performance_levels[i-1].vddc, &vddc); 2334 if (ret) 2335 return ret; 2336 2337 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc); 2338 if (ret) 2339 return ret; 2340 2341 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 2342 state->performance_levels[i].vddc, &vddc); 2343 if (ret) 2344 return ret; 2345 2346 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc); 2347 if (ret) 2348 return ret; 2349 2350 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev, 2351 prev_std_vddc, curr_std_vddc); 2352 2353 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk); 2354 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC; 2355 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC; 2356 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC; 2357 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio); 2358 } 2359 2360 return 0; 2361} 2362 2363static int si_populate_sq_ramping_values(struct radeon_device *rdev, 2364 struct radeon_ps *radeon_state, 2365 SISLANDS_SMC_SWSTATE *smc_state) 2366{ 2367 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2368 struct ni_ps *state = ni_get_ps(radeon_state); 2369 u32 sq_power_throttle, sq_power_throttle2; 2370 bool enable_sq_ramping = ni_pi->enable_sq_ramping; 2371 int i; 2372 2373 if (state->performance_level_count == 0) 2374 return -EINVAL; 2375 2376 if (smc_state->levelCount != state->performance_level_count) 2377 return -EINVAL; 2378 2379 if (rdev->pm.dpm.sq_ramping_threshold == 0) 2380 return -EINVAL; 2381 2382 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT)) 2383 enable_sq_ramping = false; 2384 2385 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT)) 2386 enable_sq_ramping = false; 2387 2388 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT)) 2389 enable_sq_ramping = false; 2390 2391 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT)) 2392 enable_sq_ramping = false; 2393 2394 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT)) 2395 enable_sq_ramping = false; 2396 2397 for (i = 0; i < state->performance_level_count; i++) { 2398 sq_power_throttle = 0; 2399 sq_power_throttle2 = 0; 2400 2401 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) && 2402 enable_sq_ramping) { 2403 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER); 2404 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER); 2405 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA); 2406 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE); 2407 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO); 2408 } else { 2409 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK; 2410 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 2411 } 2412 2413 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle); 2414 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2); 2415 } 2416 2417 return 0; 2418} 2419 2420static int si_enable_power_containment(struct radeon_device *rdev, 2421 struct radeon_ps *radeon_new_state, 2422 bool enable) 2423{ 2424 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2425 PPSMC_Result smc_result; 2426 int ret = 0; 2427 2428 if (ni_pi->enable_power_containment) { 2429 if (enable) { 2430 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2431 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive); 2432 if (smc_result != PPSMC_Result_OK) { 2433 ret = -EINVAL; 2434 ni_pi->pc_enabled = false; 2435 } else { 2436 ni_pi->pc_enabled = true; 2437 } 2438 } 2439 } else { 2440 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive); 2441 if (smc_result != PPSMC_Result_OK) 2442 ret = -EINVAL; 2443 ni_pi->pc_enabled = false; 2444 } 2445 } 2446 2447 return ret; 2448} 2449 2450static int si_initialize_smc_dte_tables(struct radeon_device *rdev) 2451{ 2452 struct si_power_info *si_pi = si_get_pi(rdev); 2453 int ret = 0; 2454 struct si_dte_data *dte_data = &si_pi->dte_data; 2455 Smc_SIslands_DTE_Configuration *dte_tables = NULL; 2456 u32 table_size; 2457 u8 tdep_count; 2458 u32 i; 2459 2460 if (dte_data == NULL) 2461 si_pi->enable_dte = false; 2462 2463 if (si_pi->enable_dte == false) 2464 return 0; 2465 2466 if (dte_data->k <= 0) 2467 return -EINVAL; 2468 2469 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL); 2470 if (dte_tables == NULL) { 2471 si_pi->enable_dte = false; 2472 return -ENOMEM; 2473 } 2474 2475 table_size = dte_data->k; 2476 2477 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES) 2478 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES; 2479 2480 tdep_count = dte_data->tdep_count; 2481 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE) 2482 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; 2483 2484 dte_tables->K = cpu_to_be32(table_size); 2485 dte_tables->T0 = cpu_to_be32(dte_data->t0); 2486 dte_tables->MaxT = cpu_to_be32(dte_data->max_t); 2487 dte_tables->WindowSize = dte_data->window_size; 2488 dte_tables->temp_select = dte_data->temp_select; 2489 dte_tables->DTE_mode = dte_data->dte_mode; 2490 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold); 2491 2492 if (tdep_count > 0) 2493 table_size--; 2494 2495 for (i = 0; i < table_size; i++) { 2496 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]); 2497 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]); 2498 } 2499 2500 dte_tables->Tdep_count = tdep_count; 2501 2502 for (i = 0; i < (u32)tdep_count; i++) { 2503 dte_tables->T_limits[i] = dte_data->t_limits[i]; 2504 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]); 2505 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]); 2506 } 2507 2508 ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables, 2509 sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end); 2510 kfree(dte_tables); 2511 2512 return ret; 2513} 2514 2515static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev, 2516 u16 *max, u16 *min) 2517{ 2518 struct si_power_info *si_pi = si_get_pi(rdev); 2519 struct radeon_cac_leakage_table *table = 2520 &rdev->pm.dpm.dyn_state.cac_leakage_table; 2521 u32 i; 2522 u32 v0_loadline; 2523 2524 2525 if (table == NULL) 2526 return -EINVAL; 2527 2528 *max = 0; 2529 *min = 0xFFFF; 2530 2531 for (i = 0; i < table->count; i++) { 2532 if (table->entries[i].vddc > *max) 2533 *max = table->entries[i].vddc; 2534 if (table->entries[i].vddc < *min) 2535 *min = table->entries[i].vddc; 2536 } 2537 2538 if (si_pi->powertune_data->lkge_lut_v0_percent > 100) 2539 return -EINVAL; 2540 2541 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100; 2542 2543 if (v0_loadline > 0xFFFFUL) 2544 return -EINVAL; 2545 2546 *min = (u16)v0_loadline; 2547 2548 if ((*min > *max) || (*max == 0) || (*min == 0)) 2549 return -EINVAL; 2550 2551 return 0; 2552} 2553 2554static u16 si_get_cac_std_voltage_step(u16 max, u16 min) 2555{ 2556 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) / 2557 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; 2558} 2559 2560static int si_init_dte_leakage_table(struct radeon_device *rdev, 2561 PP_SIslands_CacConfig *cac_tables, 2562 u16 vddc_max, u16 vddc_min, u16 vddc_step, 2563 u16 t0, u16 t_step) 2564{ 2565 struct si_power_info *si_pi = si_get_pi(rdev); 2566 u32 leakage; 2567 unsigned int i, j; 2568 s32 t; 2569 u32 smc_leakage; 2570 u32 scaling_factor; 2571 u16 voltage; 2572 2573 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2574 2575 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) { 2576 t = (1000 * (i * t_step + t0)); 2577 2578 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2579 voltage = vddc_max - (vddc_step * j); 2580 2581 si_calculate_leakage_for_v_and_t(rdev, 2582 &si_pi->powertune_data->leakage_coefficients, 2583 voltage, 2584 t, 2585 si_pi->dyn_powertune_data.cac_leakage, 2586 &leakage); 2587 2588 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2589 2590 if (smc_leakage > 0xFFFF) 2591 smc_leakage = 0xFFFF; 2592 2593 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2594 cpu_to_be16((u16)smc_leakage); 2595 } 2596 } 2597 return 0; 2598} 2599 2600static int si_init_simplified_leakage_table(struct radeon_device *rdev, 2601 PP_SIslands_CacConfig *cac_tables, 2602 u16 vddc_max, u16 vddc_min, u16 vddc_step) 2603{ 2604 struct si_power_info *si_pi = si_get_pi(rdev); 2605 u32 leakage; 2606 unsigned int i, j; 2607 u32 smc_leakage; 2608 u32 scaling_factor; 2609 u16 voltage; 2610 2611 scaling_factor = si_get_smc_power_scaling_factor(rdev); 2612 2613 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) { 2614 voltage = vddc_max - (vddc_step * j); 2615 2616 si_calculate_leakage_for_v(rdev, 2617 &si_pi->powertune_data->leakage_coefficients, 2618 si_pi->powertune_data->fixed_kt, 2619 voltage, 2620 si_pi->dyn_powertune_data.cac_leakage, 2621 &leakage); 2622 2623 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4; 2624 2625 if (smc_leakage > 0xFFFF) 2626 smc_leakage = 0xFFFF; 2627 2628 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) 2629 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] = 2630 cpu_to_be16((u16)smc_leakage); 2631 } 2632 return 0; 2633} 2634 2635static int si_initialize_smc_cac_tables(struct radeon_device *rdev) 2636{ 2637 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2638 struct si_power_info *si_pi = si_get_pi(rdev); 2639 PP_SIslands_CacConfig *cac_tables = NULL; 2640 u16 vddc_max, vddc_min, vddc_step; 2641 u16 t0, t_step; 2642 u32 load_line_slope, reg; 2643 int ret = 0; 2644 u32 ticks_per_us = radeon_get_xclk(rdev) / 100; 2645 2646 if (ni_pi->enable_cac == false) 2647 return 0; 2648 2649 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL); 2650 if (!cac_tables) 2651 return -ENOMEM; 2652 2653 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK; 2654 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window); 2655 WREG32(CG_CAC_CTRL, reg); 2656 2657 si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage; 2658 si_pi->dyn_powertune_data.dc_pwr_value = 2659 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0]; 2660 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev); 2661 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default; 2662 2663 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000; 2664 2665 ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min); 2666 if (ret) 2667 goto done_free; 2668 2669 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min); 2670 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)); 2671 t_step = 4; 2672 t0 = 60; 2673 2674 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage) 2675 ret = si_init_dte_leakage_table(rdev, cac_tables, 2676 vddc_max, vddc_min, vddc_step, 2677 t0, t_step); 2678 else 2679 ret = si_init_simplified_leakage_table(rdev, cac_tables, 2680 vddc_max, vddc_min, vddc_step); 2681 if (ret) 2682 goto done_free; 2683 2684 load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100; 2685 2686 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size); 2687 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate; 2688 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n; 2689 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min); 2690 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step); 2691 cac_tables->R_LL = cpu_to_be32(load_line_slope); 2692 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime); 2693 cac_tables->calculation_repeats = cpu_to_be32(2); 2694 cac_tables->dc_cac = cpu_to_be32(0); 2695 cac_tables->log2_PG_LKG_SCALE = 12; 2696 cac_tables->cac_temp = si_pi->powertune_data->operating_temp; 2697 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0); 2698 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step); 2699 2700 ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables, 2701 sizeof(PP_SIslands_CacConfig), si_pi->sram_end); 2702 2703 if (ret) 2704 goto done_free; 2705 2706 ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us); 2707 2708done_free: 2709 if (ret) { 2710 ni_pi->enable_cac = false; 2711 ni_pi->enable_power_containment = false; 2712 } 2713 2714 kfree(cac_tables); 2715 2716 return 0; 2717} 2718 2719static int si_program_cac_config_registers(struct radeon_device *rdev, 2720 const struct si_cac_config_reg *cac_config_regs) 2721{ 2722 const struct si_cac_config_reg *config_regs = cac_config_regs; 2723 u32 data = 0, offset; 2724 2725 if (!config_regs) 2726 return -EINVAL; 2727 2728 while (config_regs->offset != 0xFFFFFFFF) { 2729 switch (config_regs->type) { 2730 case SISLANDS_CACCONFIG_CGIND: 2731 offset = SMC_CG_IND_START + config_regs->offset; 2732 if (offset < SMC_CG_IND_END) 2733 data = RREG32_SMC(offset); 2734 break; 2735 default: 2736 data = RREG32(config_regs->offset << 2); 2737 break; 2738 } 2739 2740 data &= ~config_regs->mask; 2741 data |= ((config_regs->value << config_regs->shift) & config_regs->mask); 2742 2743 switch (config_regs->type) { 2744 case SISLANDS_CACCONFIG_CGIND: 2745 offset = SMC_CG_IND_START + config_regs->offset; 2746 if (offset < SMC_CG_IND_END) 2747 WREG32_SMC(offset, data); 2748 break; 2749 default: 2750 WREG32(config_regs->offset << 2, data); 2751 break; 2752 } 2753 config_regs++; 2754 } 2755 return 0; 2756} 2757 2758static int si_initialize_hardware_cac_manager(struct radeon_device *rdev) 2759{ 2760 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2761 struct si_power_info *si_pi = si_get_pi(rdev); 2762 int ret; 2763 2764 if ((ni_pi->enable_cac == false) || 2765 (ni_pi->cac_configuration_required == false)) 2766 return 0; 2767 2768 ret = si_program_cac_config_registers(rdev, si_pi->lcac_config); 2769 if (ret) 2770 return ret; 2771 ret = si_program_cac_config_registers(rdev, si_pi->cac_override); 2772 if (ret) 2773 return ret; 2774 ret = si_program_cac_config_registers(rdev, si_pi->cac_weights); 2775 if (ret) 2776 return ret; 2777 2778 return 0; 2779} 2780 2781static int si_enable_smc_cac(struct radeon_device *rdev, 2782 struct radeon_ps *radeon_new_state, 2783 bool enable) 2784{ 2785 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2786 struct si_power_info *si_pi = si_get_pi(rdev); 2787 PPSMC_Result smc_result; 2788 int ret = 0; 2789 2790 if (ni_pi->enable_cac) { 2791 if (enable) { 2792 if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) { 2793 if (ni_pi->support_cac_long_term_average) { 2794 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable); 2795 if (smc_result != PPSMC_Result_OK) 2796 ni_pi->support_cac_long_term_average = false; 2797 } 2798 2799 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac); 2800 if (smc_result != PPSMC_Result_OK) { 2801 ret = -EINVAL; 2802 ni_pi->cac_enabled = false; 2803 } else { 2804 ni_pi->cac_enabled = true; 2805 } 2806 2807 if (si_pi->enable_dte) { 2808 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE); 2809 if (smc_result != PPSMC_Result_OK) 2810 ret = -EINVAL; 2811 } 2812 } 2813 } else if (ni_pi->cac_enabled) { 2814 if (si_pi->enable_dte) 2815 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE); 2816 2817 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac); 2818 2819 ni_pi->cac_enabled = false; 2820 2821 if (ni_pi->support_cac_long_term_average) 2822 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable); 2823 } 2824 } 2825 return ret; 2826} 2827 2828static int si_init_smc_spll_table(struct radeon_device *rdev) 2829{ 2830 struct ni_power_info *ni_pi = ni_get_pi(rdev); 2831 struct si_power_info *si_pi = si_get_pi(rdev); 2832 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table; 2833 SISLANDS_SMC_SCLK_VALUE sclk_params; 2834 u32 fb_div, p_div; 2835 u32 clk_s, clk_v; 2836 u32 sclk = 0; 2837 int ret = 0; 2838 u32 tmp; 2839 int i; 2840 2841 if (si_pi->spll_table_start == 0) 2842 return -EINVAL; 2843 2844 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL); 2845 if (spll_table == NULL) 2846 return -ENOMEM; 2847 2848 for (i = 0; i < 256; i++) { 2849 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params); 2850 if (ret) 2851 break; 2852 2853 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT; 2854 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT; 2855 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT; 2856 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT; 2857 2858 fb_div &= ~0x00001FFF; 2859 fb_div >>= 1; 2860 clk_v >>= 6; 2861 2862 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT)) 2863 ret = -EINVAL; 2864 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT)) 2865 ret = -EINVAL; 2866 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT)) 2867 ret = -EINVAL; 2868 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT)) 2869 ret = -EINVAL; 2870 2871 if (ret) 2872 break; 2873 2874 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) | 2875 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK); 2876 spll_table->freq[i] = cpu_to_be32(tmp); 2877 2878 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) | 2879 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK); 2880 spll_table->ss[i] = cpu_to_be32(tmp); 2881 2882 sclk += 512; 2883 } 2884 2885 2886 if (!ret) 2887 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start, 2888 (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), 2889 si_pi->sram_end); 2890 2891 if (ret) 2892 ni_pi->enable_power_containment = false; 2893 2894 kfree(spll_table); 2895 2896 return ret; 2897} 2898 2899static u16 si_get_lower_of_leakage_and_vce_voltage(struct radeon_device *rdev, 2900 u16 vce_voltage) 2901{ 2902 u16 highest_leakage = 0; 2903 struct si_power_info *si_pi = si_get_pi(rdev); 2904 int i; 2905 2906 for (i = 0; i < si_pi->leakage_voltage.count; i++){ 2907 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage) 2908 highest_leakage = si_pi->leakage_voltage.entries[i].voltage; 2909 } 2910 2911 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage)) 2912 return highest_leakage; 2913 2914 return vce_voltage; 2915} 2916 2917static int si_get_vce_clock_voltage(struct radeon_device *rdev, 2918 u32 evclk, u32 ecclk, u16 *voltage) 2919{ 2920 u32 i; 2921 int ret = -EINVAL; 2922 struct radeon_vce_clock_voltage_dependency_table *table = 2923 &rdev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table; 2924 2925 if (((evclk == 0) && (ecclk == 0)) || 2926 (table && (table->count == 0))) { 2927 *voltage = 0; 2928 return 0; 2929 } 2930 2931 for (i = 0; i < table->count; i++) { 2932 if ((evclk <= table->entries[i].evclk) && 2933 (ecclk <= table->entries[i].ecclk)) { 2934 *voltage = table->entries[i].v; 2935 ret = 0; 2936 break; 2937 } 2938 } 2939 2940 /* if no match return the highest voltage */ 2941 if (ret) 2942 *voltage = table->entries[table->count - 1].v; 2943 2944 *voltage = si_get_lower_of_leakage_and_vce_voltage(rdev, *voltage); 2945 2946 return ret; 2947} 2948 2949static void si_apply_state_adjust_rules(struct radeon_device *rdev, 2950 struct radeon_ps *rps) 2951{ 2952 struct ni_ps *ps = ni_get_ps(rps); 2953 struct radeon_clock_and_voltage_limits *max_limits; 2954 bool disable_mclk_switching = false; 2955 bool disable_sclk_switching = false; 2956 u32 mclk, sclk; 2957 u16 vddc, vddci, min_vce_voltage = 0; 2958 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc; 2959 u32 max_sclk = 0, max_mclk = 0; 2960 int i; 2961 2962 if (rdev->family == CHIP_HAINAN) { 2963 if ((rdev->pdev->revision == 0x81) || 2964 (rdev->pdev->revision == 0xC3) || 2965 (rdev->pdev->device == 0x6664) || 2966 (rdev->pdev->device == 0x6665) || 2967 (rdev->pdev->device == 0x6667)) { 2968 max_sclk = 75000; 2969 } 2970 if ((rdev->pdev->revision == 0xC3) || 2971 (rdev->pdev->device == 0x6665)) { 2972 max_sclk = 60000; 2973 max_mclk = 80000; 2974 } 2975 } else if (rdev->family == CHIP_OLAND) { 2976 if ((rdev->pdev->revision == 0xC7) || 2977 (rdev->pdev->revision == 0x80) || 2978 (rdev->pdev->revision == 0x81) || 2979 (rdev->pdev->revision == 0x83) || 2980 (rdev->pdev->revision == 0x87) || 2981 (rdev->pdev->device == 0x6604) || 2982 (rdev->pdev->device == 0x6605)) { 2983 max_sclk = 75000; 2984 } 2985 2986 if (rdev->pm.dpm.high_pixelclock_count > 1) 2987 disable_sclk_switching = true; 2988 } 2989 2990 if (rps->vce_active) { 2991 rps->evclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].evclk; 2992 rps->ecclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].ecclk; 2993 si_get_vce_clock_voltage(rdev, rps->evclk, rps->ecclk, 2994 &min_vce_voltage); 2995 } else { 2996 rps->evclk = 0; 2997 rps->ecclk = 0; 2998 } 2999 3000 if ((rdev->pm.dpm.new_active_crtc_count > 1) || 3001 ni_dpm_vblank_too_short(rdev)) 3002 disable_mclk_switching = true; 3003 3004 if (rps->vclk || rps->dclk) { 3005 disable_mclk_switching = true; 3006 disable_sclk_switching = true; 3007 } 3008 3009 if (rdev->pm.dpm.ac_power) 3010 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 3011 else 3012 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc; 3013 3014 for (i = ps->performance_level_count - 2; i >= 0; i--) { 3015 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc) 3016 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc; 3017 } 3018 if (rdev->pm.dpm.ac_power == false) { 3019 for (i = 0; i < ps->performance_level_count; i++) { 3020 if (ps->performance_levels[i].mclk > max_limits->mclk) 3021 ps->performance_levels[i].mclk = max_limits->mclk; 3022 if (ps->performance_levels[i].sclk > max_limits->sclk) 3023 ps->performance_levels[i].sclk = max_limits->sclk; 3024 if (ps->performance_levels[i].vddc > max_limits->vddc) 3025 ps->performance_levels[i].vddc = max_limits->vddc; 3026 if (ps->performance_levels[i].vddci > max_limits->vddci) 3027 ps->performance_levels[i].vddci = max_limits->vddci; 3028 } 3029 } 3030 3031 /* limit clocks to max supported clocks based on voltage dependency tables */ 3032 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3033 &max_sclk_vddc); 3034 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3035 &max_mclk_vddci); 3036 btc_get_max_clock_from_voltage_dependency_table(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3037 &max_mclk_vddc); 3038 3039 for (i = 0; i < ps->performance_level_count; i++) { 3040 if (max_sclk_vddc) { 3041 if (ps->performance_levels[i].sclk > max_sclk_vddc) 3042 ps->performance_levels[i].sclk = max_sclk_vddc; 3043 } 3044 if (max_mclk_vddci) { 3045 if (ps->performance_levels[i].mclk > max_mclk_vddci) 3046 ps->performance_levels[i].mclk = max_mclk_vddci; 3047 } 3048 if (max_mclk_vddc) { 3049 if (ps->performance_levels[i].mclk > max_mclk_vddc) 3050 ps->performance_levels[i].mclk = max_mclk_vddc; 3051 } 3052 if (max_mclk) { 3053 if (ps->performance_levels[i].mclk > max_mclk) 3054 ps->performance_levels[i].mclk = max_mclk; 3055 } 3056 if (max_sclk) { 3057 if (ps->performance_levels[i].sclk > max_sclk) 3058 ps->performance_levels[i].sclk = max_sclk; 3059 } 3060 } 3061 3062 /* XXX validate the min clocks required for display */ 3063 3064 if (disable_mclk_switching) { 3065 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk; 3066 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci; 3067 } else { 3068 mclk = ps->performance_levels[0].mclk; 3069 vddci = ps->performance_levels[0].vddci; 3070 } 3071 3072 if (disable_sclk_switching) { 3073 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk; 3074 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc; 3075 } else { 3076 sclk = ps->performance_levels[0].sclk; 3077 vddc = ps->performance_levels[0].vddc; 3078 } 3079 3080 if (rps->vce_active) { 3081 if (sclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk) 3082 sclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].sclk; 3083 if (mclk < rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk) 3084 mclk = rdev->pm.dpm.vce_states[rdev->pm.dpm.vce_level].mclk; 3085 } 3086 3087 /* adjusted low state */ 3088 ps->performance_levels[0].sclk = sclk; 3089 ps->performance_levels[0].mclk = mclk; 3090 ps->performance_levels[0].vddc = vddc; 3091 ps->performance_levels[0].vddci = vddci; 3092 3093 if (disable_sclk_switching) { 3094 sclk = ps->performance_levels[0].sclk; 3095 for (i = 1; i < ps->performance_level_count; i++) { 3096 if (sclk < ps->performance_levels[i].sclk) 3097 sclk = ps->performance_levels[i].sclk; 3098 } 3099 for (i = 0; i < ps->performance_level_count; i++) { 3100 ps->performance_levels[i].sclk = sclk; 3101 ps->performance_levels[i].vddc = vddc; 3102 } 3103 } else { 3104 for (i = 1; i < ps->performance_level_count; i++) { 3105 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk) 3106 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk; 3107 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc) 3108 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc; 3109 } 3110 } 3111 3112 if (disable_mclk_switching) { 3113 mclk = ps->performance_levels[0].mclk; 3114 for (i = 1; i < ps->performance_level_count; i++) { 3115 if (mclk < ps->performance_levels[i].mclk) 3116 mclk = ps->performance_levels[i].mclk; 3117 } 3118 for (i = 0; i < ps->performance_level_count; i++) { 3119 ps->performance_levels[i].mclk = mclk; 3120 ps->performance_levels[i].vddci = vddci; 3121 } 3122 } else { 3123 for (i = 1; i < ps->performance_level_count; i++) { 3124 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk) 3125 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; 3126 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci) 3127 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci; 3128 } 3129 } 3130 3131 for (i = 0; i < ps->performance_level_count; i++) 3132 btc_adjust_clock_combinations(rdev, max_limits, 3133 &ps->performance_levels[i]); 3134 3135 for (i = 0; i < ps->performance_level_count; i++) { 3136 if (ps->performance_levels[i].vddc < min_vce_voltage) 3137 ps->performance_levels[i].vddc = min_vce_voltage; 3138 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk, 3139 ps->performance_levels[i].sclk, 3140 max_limits->vddc, &ps->performance_levels[i].vddc); 3141 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3142 ps->performance_levels[i].mclk, 3143 max_limits->vddci, &ps->performance_levels[i].vddci); 3144 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3145 ps->performance_levels[i].mclk, 3146 max_limits->vddc, &ps->performance_levels[i].vddc); 3147 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk, 3148 rdev->clock.current_dispclk, 3149 max_limits->vddc, &ps->performance_levels[i].vddc); 3150 } 3151 3152 for (i = 0; i < ps->performance_level_count; i++) { 3153 btc_apply_voltage_delta_rules(rdev, 3154 max_limits->vddc, max_limits->vddci, 3155 &ps->performance_levels[i].vddc, 3156 &ps->performance_levels[i].vddci); 3157 } 3158 3159 ps->dc_compatible = true; 3160 for (i = 0; i < ps->performance_level_count; i++) { 3161 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc) 3162 ps->dc_compatible = false; 3163 } 3164} 3165 3166#if 0 3167static int si_read_smc_soft_register(struct radeon_device *rdev, 3168 u16 reg_offset, u32 *value) 3169{ 3170 struct si_power_info *si_pi = si_get_pi(rdev); 3171 3172 return si_read_smc_sram_dword(rdev, 3173 si_pi->soft_regs_start + reg_offset, value, 3174 si_pi->sram_end); 3175} 3176#endif 3177 3178static int si_write_smc_soft_register(struct radeon_device *rdev, 3179 u16 reg_offset, u32 value) 3180{ 3181 struct si_power_info *si_pi = si_get_pi(rdev); 3182 3183 return si_write_smc_sram_dword(rdev, 3184 si_pi->soft_regs_start + reg_offset, 3185 value, si_pi->sram_end); 3186} 3187 3188static bool si_is_special_1gb_platform(struct radeon_device *rdev) 3189{ 3190 bool ret = false; 3191 u32 tmp, width, row, column, bank, density; 3192 bool is_memory_gddr5, is_special; 3193 3194 tmp = RREG32(MC_SEQ_MISC0); 3195 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT)); 3196 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT)) 3197 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT)); 3198 3199 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb); 3200 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32; 3201 3202 tmp = RREG32(MC_ARB_RAMCFG); 3203 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10; 3204 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8; 3205 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2; 3206 3207 density = (1 << (row + column - 20 + bank)) * width; 3208 3209 if ((rdev->pdev->device == 0x6819) && 3210 is_memory_gddr5 && is_special && (density == 0x400)) 3211 ret = true; 3212 3213 return ret; 3214} 3215 3216static void si_get_leakage_vddc(struct radeon_device *rdev) 3217{ 3218 struct si_power_info *si_pi = si_get_pi(rdev); 3219 u16 vddc, count = 0; 3220 int i, ret; 3221 3222 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) { 3223 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i); 3224 3225 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) { 3226 si_pi->leakage_voltage.entries[count].voltage = vddc; 3227 si_pi->leakage_voltage.entries[count].leakage_index = 3228 SISLANDS_LEAKAGE_INDEX0 + i; 3229 count++; 3230 } 3231 } 3232 si_pi->leakage_voltage.count = count; 3233} 3234 3235static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev, 3236 u32 index, u16 *leakage_voltage) 3237{ 3238 struct si_power_info *si_pi = si_get_pi(rdev); 3239 int i; 3240 3241 if (leakage_voltage == NULL) 3242 return -EINVAL; 3243 3244 if ((index & 0xff00) != 0xff00) 3245 return -EINVAL; 3246 3247 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1) 3248 return -EINVAL; 3249 3250 if (index < SISLANDS_LEAKAGE_INDEX0) 3251 return -EINVAL; 3252 3253 for (i = 0; i < si_pi->leakage_voltage.count; i++) { 3254 if (si_pi->leakage_voltage.entries[i].leakage_index == index) { 3255 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage; 3256 return 0; 3257 } 3258 } 3259 return -EAGAIN; 3260} 3261 3262static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources) 3263{ 3264 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3265 bool want_thermal_protection; 3266 enum radeon_dpm_event_src dpm_event_src; 3267 3268 switch (sources) { 3269 case 0: 3270 default: 3271 want_thermal_protection = false; 3272 break; 3273 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL): 3274 want_thermal_protection = true; 3275 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL; 3276 break; 3277 case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL): 3278 want_thermal_protection = true; 3279 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL; 3280 break; 3281 case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) | 3282 (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)): 3283 want_thermal_protection = true; 3284 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL; 3285 break; 3286 } 3287 3288 if (want_thermal_protection) { 3289 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK); 3290 if (pi->thermal_protection) 3291 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3292 } else { 3293 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3294 } 3295} 3296 3297static void si_enable_auto_throttle_source(struct radeon_device *rdev, 3298 enum radeon_dpm_auto_throttle_src source, 3299 bool enable) 3300{ 3301 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3302 3303 if (enable) { 3304 if (!(pi->active_auto_throttle_sources & (1 << source))) { 3305 pi->active_auto_throttle_sources |= 1 << source; 3306 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3307 } 3308 } else { 3309 if (pi->active_auto_throttle_sources & (1 << source)) { 3310 pi->active_auto_throttle_sources &= ~(1 << source); 3311 si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); 3312 } 3313 } 3314} 3315 3316static void si_start_dpm(struct radeon_device *rdev) 3317{ 3318 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); 3319} 3320 3321static void si_stop_dpm(struct radeon_device *rdev) 3322{ 3323 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); 3324} 3325 3326static void si_enable_sclk_control(struct radeon_device *rdev, bool enable) 3327{ 3328 if (enable) 3329 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); 3330 else 3331 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); 3332 3333} 3334 3335#if 0 3336static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev, 3337 u32 thermal_level) 3338{ 3339 PPSMC_Result ret; 3340 3341 if (thermal_level == 0) { 3342 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 3343 if (ret == PPSMC_Result_OK) 3344 return 0; 3345 else 3346 return -EINVAL; 3347 } 3348 return 0; 3349} 3350 3351static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev) 3352{ 3353 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true); 3354} 3355#endif 3356 3357#if 0 3358static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power) 3359{ 3360 if (ac_power) 3361 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ? 3362 0 : -EINVAL; 3363 3364 return 0; 3365} 3366#endif 3367 3368static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev, 3369 PPSMC_Msg msg, u32 parameter) 3370{ 3371 WREG32(SMC_SCRATCH0, parameter); 3372 return si_send_msg_to_smc(rdev, msg); 3373} 3374 3375static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev) 3376{ 3377 if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK) 3378 return -EINVAL; 3379 3380 return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ? 3381 0 : -EINVAL; 3382} 3383 3384int si_dpm_force_performance_level(struct radeon_device *rdev, 3385 enum radeon_dpm_forced_level level) 3386{ 3387 struct radeon_ps *rps = rdev->pm.dpm.current_ps; 3388 struct ni_ps *ps = ni_get_ps(rps); 3389 u32 levels = ps->performance_level_count; 3390 3391 if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { 3392 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3393 return -EINVAL; 3394 3395 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) 3396 return -EINVAL; 3397 } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { 3398 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3399 return -EINVAL; 3400 3401 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK) 3402 return -EINVAL; 3403 } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { 3404 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) 3405 return -EINVAL; 3406 3407 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) 3408 return -EINVAL; 3409 } 3410 3411 rdev->pm.dpm.forced_level = level; 3412 3413 return 0; 3414} 3415 3416#if 0 3417static int si_set_boot_state(struct radeon_device *rdev) 3418{ 3419 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ? 3420 0 : -EINVAL; 3421} 3422#endif 3423 3424static int si_set_sw_state(struct radeon_device *rdev) 3425{ 3426 return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ? 3427 0 : -EINVAL; 3428} 3429 3430static int si_halt_smc(struct radeon_device *rdev) 3431{ 3432 if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK) 3433 return -EINVAL; 3434 3435 return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ? 3436 0 : -EINVAL; 3437} 3438 3439static int si_resume_smc(struct radeon_device *rdev) 3440{ 3441 if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK) 3442 return -EINVAL; 3443 3444 return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ? 3445 0 : -EINVAL; 3446} 3447 3448static void si_dpm_start_smc(struct radeon_device *rdev) 3449{ 3450 si_program_jump_on_start(rdev); 3451 si_start_smc(rdev); 3452 si_start_smc_clock(rdev); 3453} 3454 3455static void si_dpm_stop_smc(struct radeon_device *rdev) 3456{ 3457 si_reset_smc(rdev); 3458 si_stop_smc_clock(rdev); 3459} 3460 3461static int si_process_firmware_header(struct radeon_device *rdev) 3462{ 3463 struct si_power_info *si_pi = si_get_pi(rdev); 3464 u32 tmp; 3465 int ret; 3466 3467 ret = si_read_smc_sram_dword(rdev, 3468 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3469 SISLANDS_SMC_FIRMWARE_HEADER_stateTable, 3470 &tmp, si_pi->sram_end); 3471 if (ret) 3472 return ret; 3473 3474 si_pi->state_table_start = tmp; 3475 3476 ret = si_read_smc_sram_dword(rdev, 3477 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3478 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters, 3479 &tmp, si_pi->sram_end); 3480 if (ret) 3481 return ret; 3482 3483 si_pi->soft_regs_start = tmp; 3484 3485 ret = si_read_smc_sram_dword(rdev, 3486 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3487 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable, 3488 &tmp, si_pi->sram_end); 3489 if (ret) 3490 return ret; 3491 3492 si_pi->mc_reg_table_start = tmp; 3493 3494 ret = si_read_smc_sram_dword(rdev, 3495 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3496 SISLANDS_SMC_FIRMWARE_HEADER_fanTable, 3497 &tmp, si_pi->sram_end); 3498 if (ret) 3499 return ret; 3500 3501 si_pi->fan_table_start = tmp; 3502 3503 ret = si_read_smc_sram_dword(rdev, 3504 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3505 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable, 3506 &tmp, si_pi->sram_end); 3507 if (ret) 3508 return ret; 3509 3510 si_pi->arb_table_start = tmp; 3511 3512 ret = si_read_smc_sram_dword(rdev, 3513 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3514 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable, 3515 &tmp, si_pi->sram_end); 3516 if (ret) 3517 return ret; 3518 3519 si_pi->cac_table_start = tmp; 3520 3521 ret = si_read_smc_sram_dword(rdev, 3522 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3523 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration, 3524 &tmp, si_pi->sram_end); 3525 if (ret) 3526 return ret; 3527 3528 si_pi->dte_table_start = tmp; 3529 3530 ret = si_read_smc_sram_dword(rdev, 3531 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3532 SISLANDS_SMC_FIRMWARE_HEADER_spllTable, 3533 &tmp, si_pi->sram_end); 3534 if (ret) 3535 return ret; 3536 3537 si_pi->spll_table_start = tmp; 3538 3539 ret = si_read_smc_sram_dword(rdev, 3540 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION + 3541 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters, 3542 &tmp, si_pi->sram_end); 3543 if (ret) 3544 return ret; 3545 3546 si_pi->papm_cfg_table_start = tmp; 3547 3548 return ret; 3549} 3550 3551static void si_read_clock_registers(struct radeon_device *rdev) 3552{ 3553 struct si_power_info *si_pi = si_get_pi(rdev); 3554 3555 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL); 3556 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); 3557 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3); 3558 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4); 3559 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM); 3560 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 3561 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); 3562 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); 3563 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); 3564 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); 3565 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); 3566 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); 3567 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); 3568 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); 3569 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); 3570} 3571 3572static void si_enable_thermal_protection(struct radeon_device *rdev, 3573 bool enable) 3574{ 3575 if (enable) 3576 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS); 3577 else 3578 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS); 3579} 3580 3581static void si_enable_acpi_power_management(struct radeon_device *rdev) 3582{ 3583 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN); 3584} 3585 3586#if 0 3587static int si_enter_ulp_state(struct radeon_device *rdev) 3588{ 3589 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower); 3590 3591 udelay(25000); 3592 3593 return 0; 3594} 3595 3596static int si_exit_ulp_state(struct radeon_device *rdev) 3597{ 3598 int i; 3599 3600 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower); 3601 3602 udelay(7000); 3603 3604 for (i = 0; i < rdev->usec_timeout; i++) { 3605 if (RREG32(SMC_RESP_0) == 1) 3606 break; 3607 udelay(1000); 3608 } 3609 3610 return 0; 3611} 3612#endif 3613 3614static int si_notify_smc_display_change(struct radeon_device *rdev, 3615 bool has_display) 3616{ 3617 PPSMC_Msg msg = has_display ? 3618 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay; 3619 3620 return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ? 3621 0 : -EINVAL; 3622} 3623 3624static void si_program_response_times(struct radeon_device *rdev) 3625{ 3626 u32 voltage_response_time, acpi_delay_time, vbi_time_out; 3627 u32 vddc_dly, acpi_dly, vbi_dly; 3628 u32 reference_clock; 3629 3630 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1); 3631 3632 voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time; 3633 3634 if (voltage_response_time == 0) 3635 voltage_response_time = 1000; 3636 3637 acpi_delay_time = 15000; 3638 vbi_time_out = 100000; 3639 3640 reference_clock = radeon_get_xclk(rdev); 3641 3642 vddc_dly = (voltage_response_time * reference_clock) / 100; 3643 acpi_dly = (acpi_delay_time * reference_clock) / 100; 3644 vbi_dly = (vbi_time_out * reference_clock) / 100; 3645 3646 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly); 3647 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly); 3648 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly); 3649 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA); 3650} 3651 3652static void si_program_ds_registers(struct radeon_device *rdev) 3653{ 3654 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3655 u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */ 3656 3657 if (eg_pi->sclk_deep_sleep) { 3658 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK); 3659 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR, 3660 ~AUTOSCALE_ON_SS_CLEAR); 3661 } 3662} 3663 3664static void si_program_display_gap(struct radeon_device *rdev) 3665{ 3666 u32 tmp, pipe; 3667 int i; 3668 3669 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3670 if (rdev->pm.dpm.new_active_crtc_count > 0) 3671 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3672 else 3673 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3674 3675 if (rdev->pm.dpm.new_active_crtc_count > 1) 3676 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM); 3677 else 3678 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE); 3679 3680 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3681 3682 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG); 3683 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT; 3684 3685 if ((rdev->pm.dpm.new_active_crtc_count > 0) && 3686 (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) { 3687 /* find the first active crtc */ 3688 for (i = 0; i < rdev->num_crtc; i++) { 3689 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) 3690 break; 3691 } 3692 if (i == rdev->num_crtc) 3693 pipe = 0; 3694 else 3695 pipe = i; 3696 3697 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK; 3698 tmp |= DCCG_DISP1_SLOW_SELECT(pipe); 3699 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp); 3700 } 3701 3702 /* Setting this to false forces the performance state to low if the crtcs are disabled. 3703 * This can be a problem on PowerXpress systems or if you want to use the card 3704 * for offscreen rendering or compute if there are no crtcs enabled. 3705 */ 3706 si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0); 3707} 3708 3709static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable) 3710{ 3711 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3712 3713 if (enable) { 3714 if (pi->sclk_ss) 3715 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN); 3716 } else { 3717 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN); 3718 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN); 3719 } 3720} 3721 3722static void si_setup_bsp(struct radeon_device *rdev) 3723{ 3724 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3725 u32 xclk = radeon_get_xclk(rdev); 3726 3727 r600_calculate_u_and_p(pi->asi, 3728 xclk, 3729 16, 3730 &pi->bsp, 3731 &pi->bsu); 3732 3733 r600_calculate_u_and_p(pi->pasi, 3734 xclk, 3735 16, 3736 &pi->pbsp, 3737 &pi->pbsu); 3738 3739 3740 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu); 3741 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu); 3742 3743 WREG32(CG_BSP, pi->dsp); 3744} 3745 3746static void si_program_git(struct radeon_device *rdev) 3747{ 3748 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK); 3749} 3750 3751static void si_program_tp(struct radeon_device *rdev) 3752{ 3753 int i; 3754 enum r600_td td = R600_TD_DFLT; 3755 3756 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++) 3757 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i]))); 3758 3759 if (td == R600_TD_AUTO) 3760 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL); 3761 else 3762 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL); 3763 3764 if (td == R600_TD_UP) 3765 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE); 3766 3767 if (td == R600_TD_DOWN) 3768 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE); 3769} 3770 3771static void si_program_tpp(struct radeon_device *rdev) 3772{ 3773 WREG32(CG_TPC, R600_TPC_DFLT); 3774} 3775 3776static void si_program_sstp(struct radeon_device *rdev) 3777{ 3778 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT))); 3779} 3780 3781static void si_enable_display_gap(struct radeon_device *rdev) 3782{ 3783 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL); 3784 3785 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK); 3786 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) | 3787 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE)); 3788 3789 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK); 3790 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) | 3791 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE)); 3792 WREG32(CG_DISPLAY_GAP_CNTL, tmp); 3793} 3794 3795static void si_program_vc(struct radeon_device *rdev) 3796{ 3797 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3798 3799 WREG32(CG_FTV, pi->vrc); 3800} 3801 3802static void si_clear_vc(struct radeon_device *rdev) 3803{ 3804 WREG32(CG_FTV, 0); 3805} 3806 3807u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock) 3808{ 3809 u8 mc_para_index; 3810 3811 if (memory_clock < 10000) 3812 mc_para_index = 0; 3813 else if (memory_clock >= 80000) 3814 mc_para_index = 0x0f; 3815 else 3816 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1); 3817 return mc_para_index; 3818} 3819 3820u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode) 3821{ 3822 u8 mc_para_index; 3823 3824 if (strobe_mode) { 3825 if (memory_clock < 12500) 3826 mc_para_index = 0x00; 3827 else if (memory_clock > 47500) 3828 mc_para_index = 0x0f; 3829 else 3830 mc_para_index = (u8)((memory_clock - 10000) / 2500); 3831 } else { 3832 if (memory_clock < 65000) 3833 mc_para_index = 0x00; 3834 else if (memory_clock > 135000) 3835 mc_para_index = 0x0f; 3836 else 3837 mc_para_index = (u8)((memory_clock - 60000) / 5000); 3838 } 3839 return mc_para_index; 3840} 3841 3842static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk) 3843{ 3844 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3845 bool strobe_mode = false; 3846 u8 result = 0; 3847 3848 if (mclk <= pi->mclk_strobe_mode_threshold) 3849 strobe_mode = true; 3850 3851 if (pi->mem_gddr5) 3852 result = si_get_mclk_frequency_ratio(mclk, strobe_mode); 3853 else 3854 result = si_get_ddr3_mclk_frequency_ratio(mclk); 3855 3856 if (strobe_mode) 3857 result |= SISLANDS_SMC_STROBE_ENABLE; 3858 3859 return result; 3860} 3861 3862static int si_upload_firmware(struct radeon_device *rdev) 3863{ 3864 struct si_power_info *si_pi = si_get_pi(rdev); 3865 int ret; 3866 3867 si_reset_smc(rdev); 3868 si_stop_smc_clock(rdev); 3869 3870 ret = si_load_smc_ucode(rdev, si_pi->sram_end); 3871 3872 return ret; 3873} 3874 3875static bool si_validate_phase_shedding_tables(struct radeon_device *rdev, 3876 const struct atom_voltage_table *table, 3877 const struct radeon_phase_shedding_limits_table *limits) 3878{ 3879 u32 data, num_bits, num_levels; 3880 3881 if ((table == NULL) || (limits == NULL)) 3882 return false; 3883 3884 data = table->mask_low; 3885 3886 num_bits = hweight32(data); 3887 3888 if (num_bits == 0) 3889 return false; 3890 3891 num_levels = (1 << num_bits); 3892 3893 if (table->count != num_levels) 3894 return false; 3895 3896 if (limits->count != (num_levels - 1)) 3897 return false; 3898 3899 return true; 3900} 3901 3902void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev, 3903 u32 max_voltage_steps, 3904 struct atom_voltage_table *voltage_table) 3905{ 3906 unsigned int i, diff; 3907 3908 if (voltage_table->count <= max_voltage_steps) 3909 return; 3910 3911 diff = voltage_table->count - max_voltage_steps; 3912 3913 for (i= 0; i < max_voltage_steps; i++) 3914 voltage_table->entries[i] = voltage_table->entries[i + diff]; 3915 3916 voltage_table->count = max_voltage_steps; 3917} 3918 3919static int si_get_svi2_voltage_table(struct radeon_device *rdev, 3920 struct radeon_clock_voltage_dependency_table *voltage_dependency_table, 3921 struct atom_voltage_table *voltage_table) 3922{ 3923 u32 i; 3924 3925 if (voltage_dependency_table == NULL) 3926 return -EINVAL; 3927 3928 voltage_table->mask_low = 0; 3929 voltage_table->phase_delay = 0; 3930 3931 voltage_table->count = voltage_dependency_table->count; 3932 for (i = 0; i < voltage_table->count; i++) { 3933 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v; 3934 voltage_table->entries[i].smio_low = 0; 3935 } 3936 3937 return 0; 3938} 3939 3940static int si_construct_voltage_tables(struct radeon_device *rdev) 3941{ 3942 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 3943 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 3944 struct si_power_info *si_pi = si_get_pi(rdev); 3945 int ret; 3946 3947 if (pi->voltage_control) { 3948 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 3949 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table); 3950 if (ret) 3951 return ret; 3952 3953 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3954 si_trim_voltage_table_to_fit_state_table(rdev, 3955 SISLANDS_MAX_NO_VREG_STEPS, 3956 &eg_pi->vddc_voltage_table); 3957 } else if (si_pi->voltage_control_svi2) { 3958 ret = si_get_svi2_voltage_table(rdev, 3959 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk, 3960 &eg_pi->vddc_voltage_table); 3961 if (ret) 3962 return ret; 3963 } else { 3964 return -EINVAL; 3965 } 3966 3967 if (eg_pi->vddci_control) { 3968 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI, 3969 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table); 3970 if (ret) 3971 return ret; 3972 3973 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 3974 si_trim_voltage_table_to_fit_state_table(rdev, 3975 SISLANDS_MAX_NO_VREG_STEPS, 3976 &eg_pi->vddci_voltage_table); 3977 } 3978 if (si_pi->vddci_control_svi2) { 3979 ret = si_get_svi2_voltage_table(rdev, 3980 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk, 3981 &eg_pi->vddci_voltage_table); 3982 if (ret) 3983 return ret; 3984 } 3985 3986 if (pi->mvdd_control) { 3987 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC, 3988 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table); 3989 3990 if (ret) { 3991 pi->mvdd_control = false; 3992 return ret; 3993 } 3994 3995 if (si_pi->mvdd_voltage_table.count == 0) { 3996 pi->mvdd_control = false; 3997 return -EINVAL; 3998 } 3999 4000 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS) 4001 si_trim_voltage_table_to_fit_state_table(rdev, 4002 SISLANDS_MAX_NO_VREG_STEPS, 4003 &si_pi->mvdd_voltage_table); 4004 } 4005 4006 if (si_pi->vddc_phase_shed_control) { 4007 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC, 4008 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table); 4009 if (ret) 4010 si_pi->vddc_phase_shed_control = false; 4011 4012 if ((si_pi->vddc_phase_shed_table.count == 0) || 4013 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS)) 4014 si_pi->vddc_phase_shed_control = false; 4015 } 4016 4017 return 0; 4018} 4019 4020static void si_populate_smc_voltage_table(struct radeon_device *rdev, 4021 const struct atom_voltage_table *voltage_table, 4022 SISLANDS_SMC_STATETABLE *table) 4023{ 4024 unsigned int i; 4025 4026 for (i = 0; i < voltage_table->count; i++) 4027 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low); 4028} 4029 4030static int si_populate_smc_voltage_tables(struct radeon_device *rdev, 4031 SISLANDS_SMC_STATETABLE *table) 4032{ 4033 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4034 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4035 struct si_power_info *si_pi = si_get_pi(rdev); 4036 u8 i; 4037 4038 if (si_pi->voltage_control_svi2) { 4039 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc, 4040 si_pi->svc_gpio_id); 4041 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd, 4042 si_pi->svd_gpio_id); 4043 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type, 4044 2); 4045 } else { 4046 if (eg_pi->vddc_voltage_table.count) { 4047 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table); 4048 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] = 4049 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low); 4050 4051 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) { 4052 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) { 4053 table->maxVDDCIndexInPPTable = i; 4054 break; 4055 } 4056 } 4057 } 4058 4059 if (eg_pi->vddci_voltage_table.count) { 4060 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table); 4061 4062 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] = 4063 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low); 4064 } 4065 4066 4067 if (si_pi->mvdd_voltage_table.count) { 4068 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table); 4069 4070 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] = 4071 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low); 4072 } 4073 4074 if (si_pi->vddc_phase_shed_control) { 4075 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table, 4076 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) { 4077 si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table); 4078 4079 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] = 4080 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low); 4081 4082 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay, 4083 (u32)si_pi->vddc_phase_shed_table.phase_delay); 4084 } else { 4085 si_pi->vddc_phase_shed_control = false; 4086 } 4087 } 4088 } 4089 4090 return 0; 4091} 4092 4093static int si_populate_voltage_value(struct radeon_device *rdev, 4094 const struct atom_voltage_table *table, 4095 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4096{ 4097 unsigned int i; 4098 4099 for (i = 0; i < table->count; i++) { 4100 if (value <= table->entries[i].value) { 4101 voltage->index = (u8)i; 4102 voltage->value = cpu_to_be16(table->entries[i].value); 4103 break; 4104 } 4105 } 4106 4107 if (i >= table->count) 4108 return -EINVAL; 4109 4110 return 0; 4111} 4112 4113static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, 4114 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4115{ 4116 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4117 struct si_power_info *si_pi = si_get_pi(rdev); 4118 4119 if (pi->mvdd_control) { 4120 if (mclk <= pi->mvdd_split_frequency) 4121 voltage->index = 0; 4122 else 4123 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1; 4124 4125 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value); 4126 } 4127 return 0; 4128} 4129 4130static int si_get_std_voltage_value(struct radeon_device *rdev, 4131 SISLANDS_SMC_VOLTAGE_VALUE *voltage, 4132 u16 *std_voltage) 4133{ 4134 u16 v_index; 4135 bool voltage_found = false; 4136 *std_voltage = be16_to_cpu(voltage->value); 4137 4138 if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) { 4139 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) { 4140 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL) 4141 return -EINVAL; 4142 4143 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4144 if (be16_to_cpu(voltage->value) == 4145 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4146 voltage_found = true; 4147 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4148 *std_voltage = 4149 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4150 else 4151 *std_voltage = 4152 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4153 break; 4154 } 4155 } 4156 4157 if (!voltage_found) { 4158 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) { 4159 if (be16_to_cpu(voltage->value) <= 4160 (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) { 4161 voltage_found = true; 4162 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4163 *std_voltage = 4164 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc; 4165 else 4166 *std_voltage = 4167 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc; 4168 break; 4169 } 4170 } 4171 } 4172 } else { 4173 if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count) 4174 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc; 4175 } 4176 } 4177 4178 return 0; 4179} 4180 4181static int si_populate_std_voltage_value(struct radeon_device *rdev, 4182 u16 value, u8 index, 4183 SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4184{ 4185 voltage->index = index; 4186 voltage->value = cpu_to_be16(value); 4187 4188 return 0; 4189} 4190 4191static int si_populate_phase_shedding_value(struct radeon_device *rdev, 4192 const struct radeon_phase_shedding_limits_table *limits, 4193 u16 voltage, u32 sclk, u32 mclk, 4194 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage) 4195{ 4196 unsigned int i; 4197 4198 for (i = 0; i < limits->count; i++) { 4199 if ((voltage <= limits->entries[i].voltage) && 4200 (sclk <= limits->entries[i].sclk) && 4201 (mclk <= limits->entries[i].mclk)) 4202 break; 4203 } 4204 4205 smc_voltage->phase_settings = (u8)i; 4206 4207 return 0; 4208} 4209 4210static int si_init_arb_table_index(struct radeon_device *rdev) 4211{ 4212 struct si_power_info *si_pi = si_get_pi(rdev); 4213 u32 tmp; 4214 int ret; 4215 4216 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end); 4217 if (ret) 4218 return ret; 4219 4220 tmp &= 0x00FFFFFF; 4221 tmp |= MC_CG_ARB_FREQ_F1 << 24; 4222 4223 return si_write_smc_sram_dword(rdev, si_pi->arb_table_start, tmp, si_pi->sram_end); 4224} 4225 4226static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev) 4227{ 4228 return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); 4229} 4230 4231static int si_reset_to_default(struct radeon_device *rdev) 4232{ 4233 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ? 4234 0 : -EINVAL; 4235} 4236 4237static int si_force_switch_to_arb_f0(struct radeon_device *rdev) 4238{ 4239 struct si_power_info *si_pi = si_get_pi(rdev); 4240 u32 tmp; 4241 int ret; 4242 4243 ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, 4244 &tmp, si_pi->sram_end); 4245 if (ret) 4246 return ret; 4247 4248 tmp = (tmp >> 24) & 0xff; 4249 4250 if (tmp == MC_CG_ARB_FREQ_F0) 4251 return 0; 4252 4253 return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0); 4254} 4255 4256static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev, 4257 u32 engine_clock) 4258{ 4259 u32 dram_rows; 4260 u32 dram_refresh_rate; 4261 u32 mc_arb_rfsh_rate; 4262 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT; 4263 4264 if (tmp >= 4) 4265 dram_rows = 16384; 4266 else 4267 dram_rows = 1 << (tmp + 10); 4268 4269 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3); 4270 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64; 4271 4272 return mc_arb_rfsh_rate; 4273} 4274 4275static int si_populate_memory_timing_parameters(struct radeon_device *rdev, 4276 struct rv7xx_pl *pl, 4277 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs) 4278{ 4279 u32 dram_timing; 4280 u32 dram_timing2; 4281 u32 burst_time; 4282 4283 arb_regs->mc_arb_rfsh_rate = 4284 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk); 4285 4286 radeon_atom_set_engine_dram_timings(rdev, 4287 pl->sclk, 4288 pl->mclk); 4289 4290 dram_timing = RREG32(MC_ARB_DRAM_TIMING); 4291 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); 4292 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK; 4293 4294 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing); 4295 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2); 4296 arb_regs->mc_arb_burst_time = (u8)burst_time; 4297 4298 return 0; 4299} 4300 4301static int si_do_program_memory_timing_parameters(struct radeon_device *rdev, 4302 struct radeon_ps *radeon_state, 4303 unsigned int first_arb_set) 4304{ 4305 struct si_power_info *si_pi = si_get_pi(rdev); 4306 struct ni_ps *state = ni_get_ps(radeon_state); 4307 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4308 int i, ret = 0; 4309 4310 for (i = 0; i < state->performance_level_count; i++) { 4311 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs); 4312 if (ret) 4313 break; 4314 ret = si_copy_bytes_to_smc(rdev, 4315 si_pi->arb_table_start + 4316 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4317 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i), 4318 (u8 *)&arb_regs, 4319 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4320 si_pi->sram_end); 4321 if (ret) 4322 break; 4323 } 4324 4325 return ret; 4326} 4327 4328static int si_program_memory_timing_parameters(struct radeon_device *rdev, 4329 struct radeon_ps *radeon_new_state) 4330{ 4331 return si_do_program_memory_timing_parameters(rdev, radeon_new_state, 4332 SISLANDS_DRIVER_STATE_ARB_INDEX); 4333} 4334 4335static int si_populate_initial_mvdd_value(struct radeon_device *rdev, 4336 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage) 4337{ 4338 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4339 struct si_power_info *si_pi = si_get_pi(rdev); 4340 4341 if (pi->mvdd_control) 4342 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table, 4343 si_pi->mvdd_bootup_value, voltage); 4344 4345 return 0; 4346} 4347 4348static int si_populate_smc_initial_state(struct radeon_device *rdev, 4349 struct radeon_ps *radeon_initial_state, 4350 SISLANDS_SMC_STATETABLE *table) 4351{ 4352 struct ni_ps *initial_state = ni_get_ps(radeon_initial_state); 4353 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4354 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4355 struct si_power_info *si_pi = si_get_pi(rdev); 4356 u32 reg; 4357 int ret; 4358 4359 table->initialState.levels[0].mclk.vDLL_CNTL = 4360 cpu_to_be32(si_pi->clock_registers.dll_cntl); 4361 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4362 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl); 4363 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4364 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl); 4365 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4366 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl); 4367 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL = 4368 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl); 4369 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4370 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1); 4371 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4372 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2); 4373 table->initialState.levels[0].mclk.vMPLL_SS = 4374 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4375 table->initialState.levels[0].mclk.vMPLL_SS2 = 4376 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4377 4378 table->initialState.levels[0].mclk.mclk_value = 4379 cpu_to_be32(initial_state->performance_levels[0].mclk); 4380 4381 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4382 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl); 4383 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4384 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2); 4385 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4386 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3); 4387 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4388 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4); 4389 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = 4390 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum); 4391 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = 4392 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2); 4393 4394 table->initialState.levels[0].sclk.sclk_value = 4395 cpu_to_be32(initial_state->performance_levels[0].sclk); 4396 4397 table->initialState.levels[0].arbRefreshState = 4398 SISLANDS_INITIAL_STATE_ARB_INDEX; 4399 4400 table->initialState.levels[0].ACIndex = 0; 4401 4402 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4403 initial_state->performance_levels[0].vddc, 4404 &table->initialState.levels[0].vddc); 4405 4406 if (!ret) { 4407 u16 std_vddc; 4408 4409 ret = si_get_std_voltage_value(rdev, 4410 &table->initialState.levels[0].vddc, 4411 &std_vddc); 4412 if (!ret) 4413 si_populate_std_voltage_value(rdev, std_vddc, 4414 table->initialState.levels[0].vddc.index, 4415 &table->initialState.levels[0].std_vddc); 4416 } 4417 4418 if (eg_pi->vddci_control) 4419 si_populate_voltage_value(rdev, 4420 &eg_pi->vddci_voltage_table, 4421 initial_state->performance_levels[0].vddci, 4422 &table->initialState.levels[0].vddci); 4423 4424 if (si_pi->vddc_phase_shed_control) 4425 si_populate_phase_shedding_value(rdev, 4426 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4427 initial_state->performance_levels[0].vddc, 4428 initial_state->performance_levels[0].sclk, 4429 initial_state->performance_levels[0].mclk, 4430 &table->initialState.levels[0].vddc); 4431 4432 si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd); 4433 4434 reg = CG_R(0xffff) | CG_L(0); 4435 table->initialState.levels[0].aT = cpu_to_be32(reg); 4436 4437 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); 4438 4439 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen; 4440 4441 if (pi->mem_gddr5) { 4442 table->initialState.levels[0].strobeMode = 4443 si_get_strobe_mode_settings(rdev, 4444 initial_state->performance_levels[0].mclk); 4445 4446 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold) 4447 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG; 4448 else 4449 table->initialState.levels[0].mcFlags = 0; 4450 } 4451 4452 table->initialState.levelCount = 1; 4453 4454 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; 4455 4456 table->initialState.levels[0].dpm2.MaxPS = 0; 4457 table->initialState.levels[0].dpm2.NearTDPDec = 0; 4458 table->initialState.levels[0].dpm2.AboveSafeInc = 0; 4459 table->initialState.levels[0].dpm2.BelowSafeInc = 0; 4460 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4461 4462 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4463 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4464 4465 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4466 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4467 4468 return 0; 4469} 4470 4471static int si_populate_smc_acpi_state(struct radeon_device *rdev, 4472 SISLANDS_SMC_STATETABLE *table) 4473{ 4474 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4475 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4476 struct si_power_info *si_pi = si_get_pi(rdev); 4477 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4478 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4479 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4480 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4481 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4482 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4483 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4484 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4485 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4486 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4487 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4488 u32 reg; 4489 int ret; 4490 4491 table->ACPIState = table->initialState; 4492 4493 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 4494 4495 if (pi->acpi_vddc) { 4496 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4497 pi->acpi_vddc, &table->ACPIState.levels[0].vddc); 4498 if (!ret) { 4499 u16 std_vddc; 4500 4501 ret = si_get_std_voltage_value(rdev, 4502 &table->ACPIState.levels[0].vddc, &std_vddc); 4503 if (!ret) 4504 si_populate_std_voltage_value(rdev, std_vddc, 4505 table->ACPIState.levels[0].vddc.index, 4506 &table->ACPIState.levels[0].std_vddc); 4507 } 4508 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen; 4509 4510 if (si_pi->vddc_phase_shed_control) { 4511 si_populate_phase_shedding_value(rdev, 4512 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4513 pi->acpi_vddc, 4514 0, 4515 0, 4516 &table->ACPIState.levels[0].vddc); 4517 } 4518 } else { 4519 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table, 4520 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc); 4521 if (!ret) { 4522 u16 std_vddc; 4523 4524 ret = si_get_std_voltage_value(rdev, 4525 &table->ACPIState.levels[0].vddc, &std_vddc); 4526 4527 if (!ret) 4528 si_populate_std_voltage_value(rdev, std_vddc, 4529 table->ACPIState.levels[0].vddc.index, 4530 &table->ACPIState.levels[0].std_vddc); 4531 } 4532 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev, 4533 si_pi->sys_pcie_mask, 4534 si_pi->boot_pcie_gen, 4535 RADEON_PCIE_GEN1); 4536 4537 if (si_pi->vddc_phase_shed_control) 4538 si_populate_phase_shedding_value(rdev, 4539 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 4540 pi->min_vddc_in_table, 4541 0, 4542 0, 4543 &table->ACPIState.levels[0].vddc); 4544 } 4545 4546 if (pi->acpi_vddc) { 4547 if (eg_pi->acpi_vddci) 4548 si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 4549 eg_pi->acpi_vddci, 4550 &table->ACPIState.levels[0].vddci); 4551 } 4552 4553 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET; 4554 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4555 4556 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS); 4557 4558 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4559 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 4560 4561 table->ACPIState.levels[0].mclk.vDLL_CNTL = 4562 cpu_to_be32(dll_cntl); 4563 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL = 4564 cpu_to_be32(mclk_pwrmgt_cntl); 4565 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL = 4566 cpu_to_be32(mpll_ad_func_cntl); 4567 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL = 4568 cpu_to_be32(mpll_dq_func_cntl); 4569 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL = 4570 cpu_to_be32(mpll_func_cntl); 4571 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 = 4572 cpu_to_be32(mpll_func_cntl_1); 4573 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 = 4574 cpu_to_be32(mpll_func_cntl_2); 4575 table->ACPIState.levels[0].mclk.vMPLL_SS = 4576 cpu_to_be32(si_pi->clock_registers.mpll_ss1); 4577 table->ACPIState.levels[0].mclk.vMPLL_SS2 = 4578 cpu_to_be32(si_pi->clock_registers.mpll_ss2); 4579 4580 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = 4581 cpu_to_be32(spll_func_cntl); 4582 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = 4583 cpu_to_be32(spll_func_cntl_2); 4584 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = 4585 cpu_to_be32(spll_func_cntl_3); 4586 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 = 4587 cpu_to_be32(spll_func_cntl_4); 4588 4589 table->ACPIState.levels[0].mclk.mclk_value = 0; 4590 table->ACPIState.levels[0].sclk.sclk_value = 0; 4591 4592 si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 4593 4594 if (eg_pi->dynamic_ac_timing) 4595 table->ACPIState.levels[0].ACIndex = 0; 4596 4597 table->ACPIState.levels[0].dpm2.MaxPS = 0; 4598 table->ACPIState.levels[0].dpm2.NearTDPDec = 0; 4599 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0; 4600 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0; 4601 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0; 4602 4603 reg = MIN_POWER_MASK | MAX_POWER_MASK; 4604 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg); 4605 4606 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK; 4607 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg); 4608 4609 return 0; 4610} 4611 4612static int si_populate_ulv_state(struct radeon_device *rdev, 4613 SISLANDS_SMC_SWSTATE *state) 4614{ 4615 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4616 struct si_power_info *si_pi = si_get_pi(rdev); 4617 struct si_ulv_param *ulv = &si_pi->ulv; 4618 u32 sclk_in_sr = 1350; /* ??? */ 4619 int ret; 4620 4621 ret = si_convert_power_level_to_smc(rdev, &ulv->pl, 4622 &state->levels[0]); 4623 if (!ret) { 4624 if (eg_pi->sclk_deep_sleep) { 4625 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 4626 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 4627 else 4628 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 4629 } 4630 if (ulv->one_pcie_lane_in_ulv) 4631 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1; 4632 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX); 4633 state->levels[0].ACIndex = 1; 4634 state->levels[0].std_vddc = state->levels[0].vddc; 4635 state->levelCount = 1; 4636 4637 state->flags |= PPSMC_SWSTATE_FLAG_DC; 4638 } 4639 4640 return ret; 4641} 4642 4643static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev) 4644{ 4645 struct si_power_info *si_pi = si_get_pi(rdev); 4646 struct si_ulv_param *ulv = &si_pi->ulv; 4647 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 }; 4648 int ret; 4649 4650 ret = si_populate_memory_timing_parameters(rdev, &ulv->pl, 4651 &arb_regs); 4652 if (ret) 4653 return ret; 4654 4655 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay, 4656 ulv->volt_change_delay); 4657 4658 ret = si_copy_bytes_to_smc(rdev, 4659 si_pi->arb_table_start + 4660 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) + 4661 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX, 4662 (u8 *)&arb_regs, 4663 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet), 4664 si_pi->sram_end); 4665 4666 return ret; 4667} 4668 4669static void si_get_mvdd_configuration(struct radeon_device *rdev) 4670{ 4671 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4672 4673 pi->mvdd_split_frequency = 30000; 4674} 4675 4676static int si_init_smc_table(struct radeon_device *rdev) 4677{ 4678 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4679 struct si_power_info *si_pi = si_get_pi(rdev); 4680 struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps; 4681 const struct si_ulv_param *ulv = &si_pi->ulv; 4682 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable; 4683 int ret; 4684 u32 lane_width; 4685 u32 vr_hot_gpio; 4686 4687 si_populate_smc_voltage_tables(rdev, table); 4688 4689 switch (rdev->pm.int_thermal_type) { 4690 case THERMAL_TYPE_SI: 4691 case THERMAL_TYPE_EMC2103_WITH_INTERNAL: 4692 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL; 4693 break; 4694 case THERMAL_TYPE_NONE: 4695 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE; 4696 break; 4697 default: 4698 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL; 4699 break; 4700 } 4701 4702 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC) 4703 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC; 4704 4705 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) { 4706 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819)) 4707 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT; 4708 } 4709 4710 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC) 4711 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC; 4712 4713 if (pi->mem_gddr5) 4714 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5; 4715 4716 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY) 4717 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH; 4718 4719 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) { 4720 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO; 4721 vr_hot_gpio = rdev->pm.dpm.backbias_response_time; 4722 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio, 4723 vr_hot_gpio); 4724 } 4725 4726 ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table); 4727 if (ret) 4728 return ret; 4729 4730 ret = si_populate_smc_acpi_state(rdev, table); 4731 if (ret) 4732 return ret; 4733 4734 table->driverState = table->initialState; 4735 4736 ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state, 4737 SISLANDS_INITIAL_STATE_ARB_INDEX); 4738 if (ret) 4739 return ret; 4740 4741 if (ulv->supported && ulv->pl.vddc) { 4742 ret = si_populate_ulv_state(rdev, &table->ULVState); 4743 if (ret) 4744 return ret; 4745 4746 ret = si_program_ulv_memory_timing_parameters(rdev); 4747 if (ret) 4748 return ret; 4749 4750 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control); 4751 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter); 4752 4753 lane_width = radeon_get_pcie_lanes(rdev); 4754 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 4755 } else { 4756 table->ULVState = table->initialState; 4757 } 4758 4759 return si_copy_bytes_to_smc(rdev, si_pi->state_table_start, 4760 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE), 4761 si_pi->sram_end); 4762} 4763 4764static int si_calculate_sclk_params(struct radeon_device *rdev, 4765 u32 engine_clock, 4766 SISLANDS_SMC_SCLK_VALUE *sclk) 4767{ 4768 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4769 struct si_power_info *si_pi = si_get_pi(rdev); 4770 struct atom_clock_dividers dividers; 4771 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl; 4772 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2; 4773 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3; 4774 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4; 4775 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum; 4776 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2; 4777 u64 tmp; 4778 u32 reference_clock = rdev->clock.spll.reference_freq; 4779 u32 reference_divider; 4780 u32 fbdiv; 4781 int ret; 4782 4783 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 4784 engine_clock, false, ÷rs); 4785 if (ret) 4786 return ret; 4787 4788 reference_divider = 1 + dividers.ref_div; 4789 4790 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 4791 do_div(tmp, reference_clock); 4792 fbdiv = (u32) tmp; 4793 4794 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 4795 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 4796 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 4797 4798 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 4799 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 4800 4801 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 4802 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 4803 spll_func_cntl_3 |= SPLL_DITHEN; 4804 4805 if (pi->sclk_ss) { 4806 struct radeon_atom_ss ss; 4807 u32 vco_freq = engine_clock * dividers.post_div; 4808 4809 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4810 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 4811 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 4812 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 4813 4814 cg_spll_spread_spectrum &= ~CLK_S_MASK; 4815 cg_spll_spread_spectrum |= CLK_S(clk_s); 4816 cg_spll_spread_spectrum |= SSEN; 4817 4818 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 4819 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 4820 } 4821 } 4822 4823 sclk->sclk_value = engine_clock; 4824 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl; 4825 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2; 4826 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3; 4827 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4; 4828 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum; 4829 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2; 4830 4831 return 0; 4832} 4833 4834static int si_populate_sclk_value(struct radeon_device *rdev, 4835 u32 engine_clock, 4836 SISLANDS_SMC_SCLK_VALUE *sclk) 4837{ 4838 SISLANDS_SMC_SCLK_VALUE sclk_tmp; 4839 int ret; 4840 4841 ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp); 4842 if (!ret) { 4843 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value); 4844 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL); 4845 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2); 4846 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3); 4847 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4); 4848 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM); 4849 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2); 4850 } 4851 4852 return ret; 4853} 4854 4855static int si_populate_mclk_value(struct radeon_device *rdev, 4856 u32 engine_clock, 4857 u32 memory_clock, 4858 SISLANDS_SMC_MCLK_VALUE *mclk, 4859 bool strobe_mode, 4860 bool dll_state_on) 4861{ 4862 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4863 struct si_power_info *si_pi = si_get_pi(rdev); 4864 u32 dll_cntl = si_pi->clock_registers.dll_cntl; 4865 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl; 4866 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl; 4867 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl; 4868 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl; 4869 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1; 4870 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2; 4871 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1; 4872 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2; 4873 struct atom_mpll_param mpll_param; 4874 int ret; 4875 4876 ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param); 4877 if (ret) 4878 return ret; 4879 4880 mpll_func_cntl &= ~BWCTRL_MASK; 4881 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl); 4882 4883 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK); 4884 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) | 4885 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode); 4886 4887 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK; 4888 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div); 4889 4890 if (pi->mem_gddr5) { 4891 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK); 4892 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) | 4893 YCLK_POST_DIV(mpll_param.post_div); 4894 } 4895 4896 if (pi->mclk_ss) { 4897 struct radeon_atom_ss ss; 4898 u32 freq_nom; 4899 u32 tmp; 4900 u32 reference_clock = rdev->clock.mpll.reference_freq; 4901 4902 if (pi->mem_gddr5) 4903 freq_nom = memory_clock * 4; 4904 else 4905 freq_nom = memory_clock * 2; 4906 4907 tmp = freq_nom / reference_clock; 4908 tmp = tmp * tmp; 4909 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 4910 ASIC_INTERNAL_MEMORY_SS, freq_nom)) { 4911 u32 clks = reference_clock * 5 / ss.rate; 4912 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom); 4913 4914 mpll_ss1 &= ~CLKV_MASK; 4915 mpll_ss1 |= CLKV(clkv); 4916 4917 mpll_ss2 &= ~CLKS_MASK; 4918 mpll_ss2 |= CLKS(clks); 4919 } 4920 } 4921 4922 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 4923 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed); 4924 4925 if (dll_state_on) 4926 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB; 4927 else 4928 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB); 4929 4930 mclk->mclk_value = cpu_to_be32(memory_clock); 4931 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); 4932 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1); 4933 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2); 4934 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 4935 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 4936 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 4937 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl); 4938 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1); 4939 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2); 4940 4941 return 0; 4942} 4943 4944static void si_populate_smc_sp(struct radeon_device *rdev, 4945 struct radeon_ps *radeon_state, 4946 SISLANDS_SMC_SWSTATE *smc_state) 4947{ 4948 struct ni_ps *ps = ni_get_ps(radeon_state); 4949 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4950 int i; 4951 4952 for (i = 0; i < ps->performance_level_count - 1; i++) 4953 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp); 4954 4955 smc_state->levels[ps->performance_level_count - 1].bSP = 4956 cpu_to_be32(pi->psp); 4957} 4958 4959static int si_convert_power_level_to_smc(struct radeon_device *rdev, 4960 struct rv7xx_pl *pl, 4961 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level) 4962{ 4963 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 4964 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 4965 struct si_power_info *si_pi = si_get_pi(rdev); 4966 int ret; 4967 bool dll_state_on; 4968 u16 std_vddc; 4969 bool gmc_pg = false; 4970 4971 if (eg_pi->pcie_performance_request && 4972 (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID)) 4973 level->gen2PCIE = (u8)si_pi->force_pcie_gen; 4974 else 4975 level->gen2PCIE = (u8)pl->pcie_gen; 4976 4977 ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk); 4978 if (ret) 4979 return ret; 4980 4981 level->mcFlags = 0; 4982 4983 if (pi->mclk_stutter_mode_threshold && 4984 (pl->mclk <= pi->mclk_stutter_mode_threshold) && 4985 !eg_pi->uvd_enabled && 4986 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) && 4987 (rdev->pm.dpm.new_active_crtc_count <= 2)) { 4988 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN; 4989 4990 if (gmc_pg) 4991 level->mcFlags |= SISLANDS_SMC_MC_PG_EN; 4992 } 4993 4994 if (pi->mem_gddr5) { 4995 if (pl->mclk > pi->mclk_edc_enable_threshold) 4996 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG; 4997 4998 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold) 4999 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG; 5000 5001 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk); 5002 5003 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) { 5004 if (si_get_mclk_frequency_ratio(pl->mclk, true) >= 5005 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf)) 5006 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5007 else 5008 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false; 5009 } else { 5010 dll_state_on = false; 5011 } 5012 } else { 5013 level->strobeMode = si_get_strobe_mode_settings(rdev, 5014 pl->mclk); 5015 5016 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false; 5017 } 5018 5019 ret = si_populate_mclk_value(rdev, 5020 pl->sclk, 5021 pl->mclk, 5022 &level->mclk, 5023 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on); 5024 if (ret) 5025 return ret; 5026 5027 ret = si_populate_voltage_value(rdev, 5028 &eg_pi->vddc_voltage_table, 5029 pl->vddc, &level->vddc); 5030 if (ret) 5031 return ret; 5032 5033 5034 ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc); 5035 if (ret) 5036 return ret; 5037 5038 ret = si_populate_std_voltage_value(rdev, std_vddc, 5039 level->vddc.index, &level->std_vddc); 5040 if (ret) 5041 return ret; 5042 5043 if (eg_pi->vddci_control) { 5044 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table, 5045 pl->vddci, &level->vddci); 5046 if (ret) 5047 return ret; 5048 } 5049 5050 if (si_pi->vddc_phase_shed_control) { 5051 ret = si_populate_phase_shedding_value(rdev, 5052 &rdev->pm.dpm.dyn_state.phase_shedding_limits_table, 5053 pl->vddc, 5054 pl->sclk, 5055 pl->mclk, 5056 &level->vddc); 5057 if (ret) 5058 return ret; 5059 } 5060 5061 level->MaxPoweredUpCU = si_pi->max_cu; 5062 5063 ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd); 5064 5065 return ret; 5066} 5067 5068static int si_populate_smc_t(struct radeon_device *rdev, 5069 struct radeon_ps *radeon_state, 5070 SISLANDS_SMC_SWSTATE *smc_state) 5071{ 5072 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5073 struct ni_ps *state = ni_get_ps(radeon_state); 5074 u32 a_t; 5075 u32 t_l, t_h; 5076 u32 high_bsp; 5077 int i, ret; 5078 5079 if (state->performance_level_count >= 9) 5080 return -EINVAL; 5081 5082 if (state->performance_level_count < 2) { 5083 a_t = CG_R(0xffff) | CG_L(0); 5084 smc_state->levels[0].aT = cpu_to_be32(a_t); 5085 return 0; 5086 } 5087 5088 smc_state->levels[0].aT = cpu_to_be32(0); 5089 5090 for (i = 0; i <= state->performance_level_count - 2; i++) { 5091 ret = r600_calculate_at( 5092 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1), 5093 100 * R600_AH_DFLT, 5094 state->performance_levels[i + 1].sclk, 5095 state->performance_levels[i].sclk, 5096 &t_l, 5097 &t_h); 5098 5099 if (ret) { 5100 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT; 5101 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT; 5102 } 5103 5104 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK; 5105 a_t |= CG_R(t_l * pi->bsp / 20000); 5106 smc_state->levels[i].aT = cpu_to_be32(a_t); 5107 5108 high_bsp = (i == state->performance_level_count - 2) ? 5109 pi->pbsp : pi->bsp; 5110 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000); 5111 smc_state->levels[i + 1].aT = cpu_to_be32(a_t); 5112 } 5113 5114 return 0; 5115} 5116 5117static int si_disable_ulv(struct radeon_device *rdev) 5118{ 5119 struct si_power_info *si_pi = si_get_pi(rdev); 5120 struct si_ulv_param *ulv = &si_pi->ulv; 5121 5122 if (ulv->supported) 5123 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ? 5124 0 : -EINVAL; 5125 5126 return 0; 5127} 5128 5129static bool si_is_state_ulv_compatible(struct radeon_device *rdev, 5130 struct radeon_ps *radeon_state) 5131{ 5132 const struct si_power_info *si_pi = si_get_pi(rdev); 5133 const struct si_ulv_param *ulv = &si_pi->ulv; 5134 const struct ni_ps *state = ni_get_ps(radeon_state); 5135 int i; 5136 5137 if (state->performance_levels[0].mclk != ulv->pl.mclk) 5138 return false; 5139 5140 /* XXX validate against display requirements! */ 5141 5142 for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) { 5143 if (rdev->clock.current_dispclk <= 5144 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) { 5145 if (ulv->pl.vddc < 5146 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v) 5147 return false; 5148 } 5149 } 5150 5151 if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0)) 5152 return false; 5153 5154 return true; 5155} 5156 5157static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev, 5158 struct radeon_ps *radeon_new_state) 5159{ 5160 const struct si_power_info *si_pi = si_get_pi(rdev); 5161 const struct si_ulv_param *ulv = &si_pi->ulv; 5162 5163 if (ulv->supported) { 5164 if (si_is_state_ulv_compatible(rdev, radeon_new_state)) 5165 return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ? 5166 0 : -EINVAL; 5167 } 5168 return 0; 5169} 5170 5171static int si_convert_power_state_to_smc(struct radeon_device *rdev, 5172 struct radeon_ps *radeon_state, 5173 SISLANDS_SMC_SWSTATE *smc_state) 5174{ 5175 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5176 struct ni_power_info *ni_pi = ni_get_pi(rdev); 5177 struct si_power_info *si_pi = si_get_pi(rdev); 5178 struct ni_ps *state = ni_get_ps(radeon_state); 5179 int i, ret; 5180 u32 threshold; 5181 u32 sclk_in_sr = 1350; /* ??? */ 5182 5183 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS) 5184 return -EINVAL; 5185 5186 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100; 5187 5188 if (radeon_state->vclk && radeon_state->dclk) { 5189 eg_pi->uvd_enabled = true; 5190 if (eg_pi->smu_uvd_hs) 5191 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD; 5192 } else { 5193 eg_pi->uvd_enabled = false; 5194 } 5195 5196 if (state->dc_compatible) 5197 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC; 5198 5199 smc_state->levelCount = 0; 5200 for (i = 0; i < state->performance_level_count; i++) { 5201 if (eg_pi->sclk_deep_sleep) { 5202 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) { 5203 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ) 5204 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS; 5205 else 5206 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE; 5207 } 5208 } 5209 5210 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i], 5211 &smc_state->levels[i]); 5212 smc_state->levels[i].arbRefreshState = 5213 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i); 5214 5215 if (ret) 5216 return ret; 5217 5218 if (ni_pi->enable_power_containment) 5219 smc_state->levels[i].displayWatermark = 5220 (state->performance_levels[i].sclk < threshold) ? 5221 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5222 else 5223 smc_state->levels[i].displayWatermark = (i < 2) ? 5224 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH; 5225 5226 if (eg_pi->dynamic_ac_timing) 5227 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i; 5228 else 5229 smc_state->levels[i].ACIndex = 0; 5230 5231 smc_state->levelCount++; 5232 } 5233 5234 si_write_smc_soft_register(rdev, 5235 SI_SMC_SOFT_REGISTER_watermark_threshold, 5236 threshold / 512); 5237 5238 si_populate_smc_sp(rdev, radeon_state, smc_state); 5239 5240 ret = si_populate_power_containment_values(rdev, radeon_state, smc_state); 5241 if (ret) 5242 ni_pi->enable_power_containment = false; 5243 5244 ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state); 5245 if (ret) 5246 ni_pi->enable_sq_ramping = false; 5247 5248 return si_populate_smc_t(rdev, radeon_state, smc_state); 5249} 5250 5251static int si_upload_sw_state(struct radeon_device *rdev, 5252 struct radeon_ps *radeon_new_state) 5253{ 5254 struct si_power_info *si_pi = si_get_pi(rdev); 5255 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5256 int ret; 5257 u32 address = si_pi->state_table_start + 5258 offsetof(SISLANDS_SMC_STATETABLE, driverState); 5259 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) + 5260 ((new_state->performance_level_count - 1) * 5261 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL)); 5262 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState; 5263 5264 memset(smc_state, 0, state_size); 5265 5266 ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state); 5267 if (ret) 5268 return ret; 5269 5270 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5271 state_size, si_pi->sram_end); 5272 5273 return ret; 5274} 5275 5276static int si_upload_ulv_state(struct radeon_device *rdev) 5277{ 5278 struct si_power_info *si_pi = si_get_pi(rdev); 5279 struct si_ulv_param *ulv = &si_pi->ulv; 5280 int ret = 0; 5281 5282 if (ulv->supported && ulv->pl.vddc) { 5283 u32 address = si_pi->state_table_start + 5284 offsetof(SISLANDS_SMC_STATETABLE, ULVState); 5285 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState; 5286 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE); 5287 5288 memset(smc_state, 0, state_size); 5289 5290 ret = si_populate_ulv_state(rdev, smc_state); 5291 if (!ret) 5292 ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state, 5293 state_size, si_pi->sram_end); 5294 } 5295 5296 return ret; 5297} 5298 5299static int si_upload_smc_data(struct radeon_device *rdev) 5300{ 5301 struct radeon_crtc *radeon_crtc = NULL; 5302 int i; 5303 5304 if (rdev->pm.dpm.new_active_crtc_count == 0) 5305 return 0; 5306 5307 for (i = 0; i < rdev->num_crtc; i++) { 5308 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) { 5309 radeon_crtc = rdev->mode_info.crtcs[i]; 5310 break; 5311 } 5312 } 5313 5314 if (radeon_crtc == NULL) 5315 return 0; 5316 5317 if (radeon_crtc->line_time <= 0) 5318 return 0; 5319 5320 if (si_write_smc_soft_register(rdev, 5321 SI_SMC_SOFT_REGISTER_crtc_index, 5322 radeon_crtc->crtc_id) != PPSMC_Result_OK) 5323 return 0; 5324 5325 if (si_write_smc_soft_register(rdev, 5326 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min, 5327 radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK) 5328 return 0; 5329 5330 if (si_write_smc_soft_register(rdev, 5331 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max, 5332 radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK) 5333 return 0; 5334 5335 return 0; 5336} 5337 5338static int si_set_mc_special_registers(struct radeon_device *rdev, 5339 struct si_mc_reg_table *table) 5340{ 5341 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 5342 u8 i, j, k; 5343 u32 temp_reg; 5344 5345 for (i = 0, j = table->last; i < table->last; i++) { 5346 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5347 return -EINVAL; 5348 switch (table->mc_reg_address[i].s1 << 2) { 5349 case MC_SEQ_MISC1: 5350 temp_reg = RREG32(MC_PMG_CMD_EMRS); 5351 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2; 5352 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5353 for (k = 0; k < table->num_entries; k++) 5354 table->mc_reg_table_entry[k].mc_data[j] = 5355 ((temp_reg & 0xffff0000)) | 5356 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16); 5357 j++; 5358 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5359 return -EINVAL; 5360 5361 temp_reg = RREG32(MC_PMG_CMD_MRS); 5362 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2; 5363 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5364 for (k = 0; k < table->num_entries; k++) { 5365 table->mc_reg_table_entry[k].mc_data[j] = 5366 (temp_reg & 0xffff0000) | 5367 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5368 if (!pi->mem_gddr5) 5369 table->mc_reg_table_entry[k].mc_data[j] |= 0x100; 5370 } 5371 j++; 5372 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5373 return -EINVAL; 5374 5375 if (!pi->mem_gddr5) { 5376 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2; 5377 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2; 5378 for (k = 0; k < table->num_entries; k++) 5379 table->mc_reg_table_entry[k].mc_data[j] = 5380 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16; 5381 j++; 5382 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5383 return -EINVAL; 5384 } 5385 break; 5386 case MC_SEQ_RESERVE_M: 5387 temp_reg = RREG32(MC_PMG_CMD_MRS1); 5388 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2; 5389 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5390 for(k = 0; k < table->num_entries; k++) 5391 table->mc_reg_table_entry[k].mc_data[j] = 5392 (temp_reg & 0xffff0000) | 5393 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff); 5394 j++; 5395 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5396 return -EINVAL; 5397 break; 5398 default: 5399 break; 5400 } 5401 } 5402 5403 table->last = j; 5404 5405 return 0; 5406} 5407 5408static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) 5409{ 5410 bool result = true; 5411 5412 switch (in_reg) { 5413 case MC_SEQ_RAS_TIMING >> 2: 5414 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; 5415 break; 5416 case MC_SEQ_CAS_TIMING >> 2: 5417 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; 5418 break; 5419 case MC_SEQ_MISC_TIMING >> 2: 5420 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; 5421 break; 5422 case MC_SEQ_MISC_TIMING2 >> 2: 5423 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; 5424 break; 5425 case MC_SEQ_RD_CTL_D0 >> 2: 5426 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; 5427 break; 5428 case MC_SEQ_RD_CTL_D1 >> 2: 5429 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; 5430 break; 5431 case MC_SEQ_WR_CTL_D0 >> 2: 5432 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; 5433 break; 5434 case MC_SEQ_WR_CTL_D1 >> 2: 5435 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; 5436 break; 5437 case MC_PMG_CMD_EMRS >> 2: 5438 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; 5439 break; 5440 case MC_PMG_CMD_MRS >> 2: 5441 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2; 5442 break; 5443 case MC_PMG_CMD_MRS1 >> 2: 5444 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2; 5445 break; 5446 case MC_SEQ_PMG_TIMING >> 2: 5447 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2; 5448 break; 5449 case MC_PMG_CMD_MRS2 >> 2: 5450 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2; 5451 break; 5452 case MC_SEQ_WR_CTL_2 >> 2: 5453 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2; 5454 break; 5455 default: 5456 result = false; 5457 break; 5458 } 5459 5460 return result; 5461} 5462 5463static void si_set_valid_flag(struct si_mc_reg_table *table) 5464{ 5465 u8 i, j; 5466 5467 for (i = 0; i < table->last; i++) { 5468 for (j = 1; j < table->num_entries; j++) { 5469 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) { 5470 table->valid_flag |= 1 << i; 5471 break; 5472 } 5473 } 5474 } 5475} 5476 5477static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table) 5478{ 5479 u32 i; 5480 u16 address; 5481 5482 for (i = 0; i < table->last; i++) 5483 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ? 5484 address : table->mc_reg_address[i].s1; 5485 5486} 5487 5488static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table, 5489 struct si_mc_reg_table *si_table) 5490{ 5491 u8 i, j; 5492 5493 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5494 return -EINVAL; 5495 if (table->num_entries > MAX_AC_TIMING_ENTRIES) 5496 return -EINVAL; 5497 5498 for (i = 0; i < table->last; i++) 5499 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1; 5500 si_table->last = table->last; 5501 5502 for (i = 0; i < table->num_entries; i++) { 5503 si_table->mc_reg_table_entry[i].mclk_max = 5504 table->mc_reg_table_entry[i].mclk_max; 5505 for (j = 0; j < table->last; j++) { 5506 si_table->mc_reg_table_entry[i].mc_data[j] = 5507 table->mc_reg_table_entry[i].mc_data[j]; 5508 } 5509 } 5510 si_table->num_entries = table->num_entries; 5511 5512 return 0; 5513} 5514 5515static int si_initialize_mc_reg_table(struct radeon_device *rdev) 5516{ 5517 struct si_power_info *si_pi = si_get_pi(rdev); 5518 struct atom_mc_reg_table *table; 5519 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table; 5520 u8 module_index = rv770_get_memory_module_index(rdev); 5521 int ret; 5522 5523 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL); 5524 if (!table) 5525 return -ENOMEM; 5526 5527 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING)); 5528 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING)); 5529 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); 5530 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2)); 5531 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS)); 5532 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS)); 5533 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1)); 5534 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0)); 5535 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1)); 5536 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0)); 5537 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1)); 5538 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING)); 5539 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2)); 5540 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2)); 5541 5542 ret = radeon_atom_init_mc_reg_table(rdev, module_index, table); 5543 if (ret) 5544 goto init_mc_done; 5545 5546 ret = si_copy_vbios_mc_reg_table(table, si_table); 5547 if (ret) 5548 goto init_mc_done; 5549 5550 si_set_s0_mc_reg_index(si_table); 5551 5552 ret = si_set_mc_special_registers(rdev, si_table); 5553 if (ret) 5554 goto init_mc_done; 5555 5556 si_set_valid_flag(si_table); 5557 5558init_mc_done: 5559 kfree(table); 5560 5561 return ret; 5562 5563} 5564 5565static void si_populate_mc_reg_addresses(struct radeon_device *rdev, 5566 SMC_SIslands_MCRegisters *mc_reg_table) 5567{ 5568 struct si_power_info *si_pi = si_get_pi(rdev); 5569 u32 i, j; 5570 5571 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) { 5572 if (si_pi->mc_reg_table.valid_flag & (1 << j)) { 5573 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE) 5574 break; 5575 mc_reg_table->address[i].s0 = 5576 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0); 5577 mc_reg_table->address[i].s1 = 5578 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1); 5579 i++; 5580 } 5581 } 5582 mc_reg_table->last = (u8)i; 5583} 5584 5585static void si_convert_mc_registers(const struct si_mc_reg_entry *entry, 5586 SMC_SIslands_MCRegisterSet *data, 5587 u32 num_entries, u32 valid_flag) 5588{ 5589 u32 i, j; 5590 5591 for(i = 0, j = 0; j < num_entries; j++) { 5592 if (valid_flag & (1 << j)) { 5593 data->value[i] = cpu_to_be32(entry->mc_data[j]); 5594 i++; 5595 } 5596 } 5597} 5598 5599static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev, 5600 struct rv7xx_pl *pl, 5601 SMC_SIslands_MCRegisterSet *mc_reg_table_data) 5602{ 5603 struct si_power_info *si_pi = si_get_pi(rdev); 5604 u32 i = 0; 5605 5606 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) { 5607 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) 5608 break; 5609 } 5610 5611 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0)) 5612 --i; 5613 5614 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i], 5615 mc_reg_table_data, si_pi->mc_reg_table.last, 5616 si_pi->mc_reg_table.valid_flag); 5617} 5618 5619static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev, 5620 struct radeon_ps *radeon_state, 5621 SMC_SIslands_MCRegisters *mc_reg_table) 5622{ 5623 struct ni_ps *state = ni_get_ps(radeon_state); 5624 int i; 5625 5626 for (i = 0; i < state->performance_level_count; i++) { 5627 si_convert_mc_reg_table_entry_to_smc(rdev, 5628 &state->performance_levels[i], 5629 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]); 5630 } 5631} 5632 5633static int si_populate_mc_reg_table(struct radeon_device *rdev, 5634 struct radeon_ps *radeon_boot_state) 5635{ 5636 struct ni_ps *boot_state = ni_get_ps(radeon_boot_state); 5637 struct si_power_info *si_pi = si_get_pi(rdev); 5638 struct si_ulv_param *ulv = &si_pi->ulv; 5639 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5640 5641 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5642 5643 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1); 5644 5645 si_populate_mc_reg_addresses(rdev, smc_mc_reg_table); 5646 5647 si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0], 5648 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]); 5649 5650 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5651 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT], 5652 si_pi->mc_reg_table.last, 5653 si_pi->mc_reg_table.valid_flag); 5654 5655 if (ulv->supported && ulv->pl.vddc != 0) 5656 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl, 5657 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]); 5658 else 5659 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0], 5660 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT], 5661 si_pi->mc_reg_table.last, 5662 si_pi->mc_reg_table.valid_flag); 5663 5664 si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table); 5665 5666 return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start, 5667 (u8 *)smc_mc_reg_table, 5668 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end); 5669} 5670 5671static int si_upload_mc_reg_table(struct radeon_device *rdev, 5672 struct radeon_ps *radeon_new_state) 5673{ 5674 struct ni_ps *new_state = ni_get_ps(radeon_new_state); 5675 struct si_power_info *si_pi = si_get_pi(rdev); 5676 u32 address = si_pi->mc_reg_table_start + 5677 offsetof(SMC_SIslands_MCRegisters, 5678 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]); 5679 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table; 5680 5681 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters)); 5682 5683 si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table); 5684 5685 5686 return si_copy_bytes_to_smc(rdev, address, 5687 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT], 5688 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count, 5689 si_pi->sram_end); 5690 5691} 5692 5693static void si_enable_voltage_control(struct radeon_device *rdev, bool enable) 5694{ 5695 if (enable) 5696 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN); 5697 else 5698 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN); 5699} 5700 5701static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev, 5702 struct radeon_ps *radeon_state) 5703{ 5704 struct ni_ps *state = ni_get_ps(radeon_state); 5705 int i; 5706 u16 pcie_speed, max_speed = 0; 5707 5708 for (i = 0; i < state->performance_level_count; i++) { 5709 pcie_speed = state->performance_levels[i].pcie_gen; 5710 if (max_speed < pcie_speed) 5711 max_speed = pcie_speed; 5712 } 5713 return max_speed; 5714} 5715 5716static u16 si_get_current_pcie_speed(struct radeon_device *rdev) 5717{ 5718 u32 speed_cntl; 5719 5720 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK; 5721 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT; 5722 5723 return (u16)speed_cntl; 5724} 5725 5726static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev, 5727 struct radeon_ps *radeon_new_state, 5728 struct radeon_ps *radeon_current_state) 5729{ 5730 struct si_power_info *si_pi = si_get_pi(rdev); 5731 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5732 enum radeon_pcie_gen current_link_speed; 5733 5734 if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) 5735 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state); 5736 else 5737 current_link_speed = si_pi->force_pcie_gen; 5738 5739 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 5740 si_pi->pspp_notify_required = false; 5741 if (target_link_speed > current_link_speed) { 5742 switch (target_link_speed) { 5743#if defined(CONFIG_ACPI) 5744 case RADEON_PCIE_GEN3: 5745 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0) 5746 break; 5747 si_pi->force_pcie_gen = RADEON_PCIE_GEN2; 5748 if (current_link_speed == RADEON_PCIE_GEN2) 5749 break; 5750 fallthrough; 5751 case RADEON_PCIE_GEN2: 5752 if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0) 5753 break; 5754#endif 5755 /* fall through */ 5756 default: 5757 si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev); 5758 break; 5759 } 5760 } else { 5761 if (target_link_speed < current_link_speed) 5762 si_pi->pspp_notify_required = true; 5763 } 5764} 5765 5766static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev, 5767 struct radeon_ps *radeon_new_state, 5768 struct radeon_ps *radeon_current_state) 5769{ 5770 struct si_power_info *si_pi = si_get_pi(rdev); 5771 enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state); 5772 u8 request; 5773 5774 if (si_pi->pspp_notify_required) { 5775 if (target_link_speed == RADEON_PCIE_GEN3) 5776 request = PCIE_PERF_REQ_PECI_GEN3; 5777 else if (target_link_speed == RADEON_PCIE_GEN2) 5778 request = PCIE_PERF_REQ_PECI_GEN2; 5779 else 5780 request = PCIE_PERF_REQ_PECI_GEN1; 5781 5782 if ((request == PCIE_PERF_REQ_PECI_GEN1) && 5783 (si_get_current_pcie_speed(rdev) > 0)) 5784 return; 5785 5786#if defined(CONFIG_ACPI) 5787 radeon_acpi_pcie_performance_request(rdev, request, false); 5788#endif 5789 } 5790} 5791 5792#if 0 5793static int si_ds_request(struct radeon_device *rdev, 5794 bool ds_status_on, u32 count_write) 5795{ 5796 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 5797 5798 if (eg_pi->sclk_deep_sleep) { 5799 if (ds_status_on) 5800 return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) == 5801 PPSMC_Result_OK) ? 5802 0 : -EINVAL; 5803 else 5804 return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) == 5805 PPSMC_Result_OK) ? 0 : -EINVAL; 5806 } 5807 return 0; 5808} 5809#endif 5810 5811static void si_set_max_cu_value(struct radeon_device *rdev) 5812{ 5813 struct si_power_info *si_pi = si_get_pi(rdev); 5814 5815 if (rdev->family == CHIP_VERDE) { 5816 switch (rdev->pdev->device) { 5817 case 0x6820: 5818 case 0x6825: 5819 case 0x6821: 5820 case 0x6823: 5821 case 0x6827: 5822 si_pi->max_cu = 10; 5823 break; 5824 case 0x682D: 5825 case 0x6824: 5826 case 0x682F: 5827 case 0x6826: 5828 si_pi->max_cu = 8; 5829 break; 5830 case 0x6828: 5831 case 0x6830: 5832 case 0x6831: 5833 case 0x6838: 5834 case 0x6839: 5835 case 0x683D: 5836 si_pi->max_cu = 10; 5837 break; 5838 case 0x683B: 5839 case 0x683F: 5840 case 0x6829: 5841 si_pi->max_cu = 8; 5842 break; 5843 default: 5844 si_pi->max_cu = 0; 5845 break; 5846 } 5847 } else { 5848 si_pi->max_cu = 0; 5849 } 5850} 5851 5852static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev, 5853 struct radeon_clock_voltage_dependency_table *table) 5854{ 5855 u32 i; 5856 int j; 5857 u16 leakage_voltage; 5858 5859 if (table) { 5860 for (i = 0; i < table->count; i++) { 5861 switch (si_get_leakage_voltage_from_leakage_index(rdev, 5862 table->entries[i].v, 5863 &leakage_voltage)) { 5864 case 0: 5865 table->entries[i].v = leakage_voltage; 5866 break; 5867 case -EAGAIN: 5868 return -EINVAL; 5869 case -EINVAL: 5870 default: 5871 break; 5872 } 5873 } 5874 5875 for (j = (table->count - 2); j >= 0; j--) { 5876 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ? 5877 table->entries[j].v : table->entries[j + 1].v; 5878 } 5879 } 5880 return 0; 5881} 5882 5883static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev) 5884{ 5885 int ret; 5886 5887 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5888 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk); 5889 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5890 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk); 5891 ret = si_patch_single_dependency_table_based_on_leakage(rdev, 5892 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk); 5893 return ret; 5894} 5895 5896static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev, 5897 struct radeon_ps *radeon_new_state, 5898 struct radeon_ps *radeon_current_state) 5899{ 5900 u32 lane_width; 5901 u32 new_lane_width = 5902 ((radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5903 u32 current_lane_width = 5904 ((radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1; 5905 5906 if (new_lane_width != current_lane_width) { 5907 radeon_set_pcie_lanes(rdev, new_lane_width); 5908 lane_width = radeon_get_pcie_lanes(rdev); 5909 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width); 5910 } 5911} 5912 5913static void si_set_vce_clock(struct radeon_device *rdev, 5914 struct radeon_ps *new_rps, 5915 struct radeon_ps *old_rps) 5916{ 5917 if ((old_rps->evclk != new_rps->evclk) || 5918 (old_rps->ecclk != new_rps->ecclk)) { 5919 /* turn the clocks on when encoding, off otherwise */ 5920 if (new_rps->evclk || new_rps->ecclk) 5921 vce_v1_0_enable_mgcg(rdev, false); 5922 else 5923 vce_v1_0_enable_mgcg(rdev, true); 5924 radeon_set_vce_clocks(rdev, new_rps->evclk, new_rps->ecclk); 5925 } 5926} 5927 5928void si_dpm_setup_asic(struct radeon_device *rdev) 5929{ 5930 int r; 5931 5932 r = si_mc_load_microcode(rdev); 5933 if (r) 5934 DRM_ERROR("Failed to load MC firmware!\n"); 5935 rv770_get_memory_type(rdev); 5936 si_read_clock_registers(rdev); 5937 si_enable_acpi_power_management(rdev); 5938} 5939 5940static int si_thermal_enable_alert(struct radeon_device *rdev, 5941 bool enable) 5942{ 5943 u32 thermal_int = RREG32(CG_THERMAL_INT); 5944 5945 if (enable) { 5946 PPSMC_Result result; 5947 5948 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW); 5949 WREG32(CG_THERMAL_INT, thermal_int); 5950 rdev->irq.dpm_thermal = false; 5951 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt); 5952 if (result != PPSMC_Result_OK) { 5953 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n"); 5954 return -EINVAL; 5955 } 5956 } else { 5957 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW; 5958 WREG32(CG_THERMAL_INT, thermal_int); 5959 rdev->irq.dpm_thermal = true; 5960 } 5961 5962 return 0; 5963} 5964 5965static int si_thermal_set_temperature_range(struct radeon_device *rdev, 5966 int min_temp, int max_temp) 5967{ 5968 int low_temp = 0 * 1000; 5969 int high_temp = 255 * 1000; 5970 5971 if (low_temp < min_temp) 5972 low_temp = min_temp; 5973 if (high_temp > max_temp) 5974 high_temp = max_temp; 5975 if (high_temp < low_temp) { 5976 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp); 5977 return -EINVAL; 5978 } 5979 5980 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK); 5981 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK); 5982 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK); 5983 5984 rdev->pm.dpm.thermal.min_temp = low_temp; 5985 rdev->pm.dpm.thermal.max_temp = high_temp; 5986 5987 return 0; 5988} 5989 5990static void si_fan_ctrl_set_static_mode(struct radeon_device *rdev, u32 mode) 5991{ 5992 struct si_power_info *si_pi = si_get_pi(rdev); 5993 u32 tmp; 5994 5995 if (si_pi->fan_ctrl_is_in_default_mode) { 5996 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT; 5997 si_pi->fan_ctrl_default_mode = tmp; 5998 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT; 5999 si_pi->t_min = tmp; 6000 si_pi->fan_ctrl_is_in_default_mode = false; 6001 } 6002 6003 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6004 tmp |= TMIN(0); 6005 WREG32(CG_FDO_CTRL2, tmp); 6006 6007 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6008 tmp |= FDO_PWM_MODE(mode); 6009 WREG32(CG_FDO_CTRL2, tmp); 6010} 6011 6012static int si_thermal_setup_fan_table(struct radeon_device *rdev) 6013{ 6014 struct si_power_info *si_pi = si_get_pi(rdev); 6015 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE }; 6016 u32 duty100; 6017 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2; 6018 u16 fdo_min, slope1, slope2; 6019 u32 reference_clock, tmp; 6020 int ret; 6021 u64 tmp64; 6022 6023 if (!si_pi->fan_table_start) { 6024 rdev->pm.dpm.fan.ucode_fan_control = false; 6025 return 0; 6026 } 6027 6028 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6029 6030 if (duty100 == 0) { 6031 rdev->pm.dpm.fan.ucode_fan_control = false; 6032 return 0; 6033 } 6034 6035 tmp64 = (u64)rdev->pm.dpm.fan.pwm_min * duty100; 6036 do_div(tmp64, 10000); 6037 fdo_min = (u16)tmp64; 6038 6039 t_diff1 = rdev->pm.dpm.fan.t_med - rdev->pm.dpm.fan.t_min; 6040 t_diff2 = rdev->pm.dpm.fan.t_high - rdev->pm.dpm.fan.t_med; 6041 6042 pwm_diff1 = rdev->pm.dpm.fan.pwm_med - rdev->pm.dpm.fan.pwm_min; 6043 pwm_diff2 = rdev->pm.dpm.fan.pwm_high - rdev->pm.dpm.fan.pwm_med; 6044 6045 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100); 6046 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100); 6047 6048 fan_table.temp_min = cpu_to_be16((50 + rdev->pm.dpm.fan.t_min) / 100); 6049 fan_table.temp_med = cpu_to_be16((50 + rdev->pm.dpm.fan.t_med) / 100); 6050 fan_table.temp_max = cpu_to_be16((50 + rdev->pm.dpm.fan.t_max) / 100); 6051 6052 fan_table.slope1 = cpu_to_be16(slope1); 6053 fan_table.slope2 = cpu_to_be16(slope2); 6054 6055 fan_table.fdo_min = cpu_to_be16(fdo_min); 6056 6057 fan_table.hys_down = cpu_to_be16(rdev->pm.dpm.fan.t_hyst); 6058 6059 fan_table.hys_up = cpu_to_be16(1); 6060 6061 fan_table.hys_slope = cpu_to_be16(1); 6062 6063 fan_table.temp_resp_lim = cpu_to_be16(5); 6064 6065 reference_clock = radeon_get_xclk(rdev); 6066 6067 fan_table.refresh_period = cpu_to_be32((rdev->pm.dpm.fan.cycle_delay * 6068 reference_clock) / 1600); 6069 6070 fan_table.fdo_max = cpu_to_be16((u16)duty100); 6071 6072 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT; 6073 fan_table.temp_src = (uint8_t)tmp; 6074 6075 ret = si_copy_bytes_to_smc(rdev, 6076 si_pi->fan_table_start, 6077 (u8 *)(&fan_table), 6078 sizeof(fan_table), 6079 si_pi->sram_end); 6080 6081 if (ret) { 6082 DRM_ERROR("Failed to load fan table to the SMC."); 6083 rdev->pm.dpm.fan.ucode_fan_control = false; 6084 } 6085 6086 return 0; 6087} 6088 6089static int si_fan_ctrl_start_smc_fan_control(struct radeon_device *rdev) 6090{ 6091 struct si_power_info *si_pi = si_get_pi(rdev); 6092 PPSMC_Result ret; 6093 6094 ret = si_send_msg_to_smc(rdev, PPSMC_StartFanControl); 6095 if (ret == PPSMC_Result_OK) { 6096 si_pi->fan_is_controlled_by_smc = true; 6097 return 0; 6098 } else { 6099 return -EINVAL; 6100 } 6101} 6102 6103static int si_fan_ctrl_stop_smc_fan_control(struct radeon_device *rdev) 6104{ 6105 struct si_power_info *si_pi = si_get_pi(rdev); 6106 PPSMC_Result ret; 6107 6108 ret = si_send_msg_to_smc(rdev, PPSMC_StopFanControl); 6109 6110 if (ret == PPSMC_Result_OK) { 6111 si_pi->fan_is_controlled_by_smc = false; 6112 return 0; 6113 } else { 6114 return -EINVAL; 6115 } 6116} 6117 6118int si_fan_ctrl_get_fan_speed_percent(struct radeon_device *rdev, 6119 u32 *speed) 6120{ 6121 u32 duty, duty100; 6122 u64 tmp64; 6123 6124 if (rdev->pm.no_fan) 6125 return -ENOENT; 6126 6127 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6128 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT; 6129 6130 if (duty100 == 0) 6131 return -EINVAL; 6132 6133 tmp64 = (u64)duty * 100; 6134 do_div(tmp64, duty100); 6135 *speed = (u32)tmp64; 6136 6137 if (*speed > 100) 6138 *speed = 100; 6139 6140 return 0; 6141} 6142 6143int si_fan_ctrl_set_fan_speed_percent(struct radeon_device *rdev, 6144 u32 speed) 6145{ 6146 struct si_power_info *si_pi = si_get_pi(rdev); 6147 u32 tmp; 6148 u32 duty, duty100; 6149 u64 tmp64; 6150 6151 if (rdev->pm.no_fan) 6152 return -ENOENT; 6153 6154 if (si_pi->fan_is_controlled_by_smc) 6155 return -EINVAL; 6156 6157 if (speed > 100) 6158 return -EINVAL; 6159 6160 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT; 6161 6162 if (duty100 == 0) 6163 return -EINVAL; 6164 6165 tmp64 = (u64)speed * duty100; 6166 do_div(tmp64, 100); 6167 duty = (u32)tmp64; 6168 6169 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK; 6170 tmp |= FDO_STATIC_DUTY(duty); 6171 WREG32(CG_FDO_CTRL0, tmp); 6172 6173 return 0; 6174} 6175 6176void si_fan_ctrl_set_mode(struct radeon_device *rdev, u32 mode) 6177{ 6178 if (mode) { 6179 /* stop auto-manage */ 6180 if (rdev->pm.dpm.fan.ucode_fan_control) 6181 si_fan_ctrl_stop_smc_fan_control(rdev); 6182 si_fan_ctrl_set_static_mode(rdev, mode); 6183 } else { 6184 /* restart auto-manage */ 6185 if (rdev->pm.dpm.fan.ucode_fan_control) 6186 si_thermal_start_smc_fan_control(rdev); 6187 else 6188 si_fan_ctrl_set_default_mode(rdev); 6189 } 6190} 6191 6192u32 si_fan_ctrl_get_mode(struct radeon_device *rdev) 6193{ 6194 struct si_power_info *si_pi = si_get_pi(rdev); 6195 u32 tmp; 6196 6197 if (si_pi->fan_is_controlled_by_smc) 6198 return 0; 6199 6200 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK; 6201 return (tmp >> FDO_PWM_MODE_SHIFT); 6202} 6203 6204#if 0 6205static int si_fan_ctrl_get_fan_speed_rpm(struct radeon_device *rdev, 6206 u32 *speed) 6207{ 6208 u32 tach_period; 6209 u32 xclk = radeon_get_xclk(rdev); 6210 6211 if (rdev->pm.no_fan) 6212 return -ENOENT; 6213 6214 if (rdev->pm.fan_pulses_per_revolution == 0) 6215 return -ENOENT; 6216 6217 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT; 6218 if (tach_period == 0) 6219 return -ENOENT; 6220 6221 *speed = 60 * xclk * 10000 / tach_period; 6222 6223 return 0; 6224} 6225 6226static int si_fan_ctrl_set_fan_speed_rpm(struct radeon_device *rdev, 6227 u32 speed) 6228{ 6229 u32 tach_period, tmp; 6230 u32 xclk = radeon_get_xclk(rdev); 6231 6232 if (rdev->pm.no_fan) 6233 return -ENOENT; 6234 6235 if (rdev->pm.fan_pulses_per_revolution == 0) 6236 return -ENOENT; 6237 6238 if ((speed < rdev->pm.fan_min_rpm) || 6239 (speed > rdev->pm.fan_max_rpm)) 6240 return -EINVAL; 6241 6242 if (rdev->pm.dpm.fan.ucode_fan_control) 6243 si_fan_ctrl_stop_smc_fan_control(rdev); 6244 6245 tach_period = 60 * xclk * 10000 / (8 * speed); 6246 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK; 6247 tmp |= TARGET_PERIOD(tach_period); 6248 WREG32(CG_TACH_CTRL, tmp); 6249 6250 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC_RPM); 6251 6252 return 0; 6253} 6254#endif 6255 6256static void si_fan_ctrl_set_default_mode(struct radeon_device *rdev) 6257{ 6258 struct si_power_info *si_pi = si_get_pi(rdev); 6259 u32 tmp; 6260 6261 if (!si_pi->fan_ctrl_is_in_default_mode) { 6262 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK; 6263 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode); 6264 WREG32(CG_FDO_CTRL2, tmp); 6265 6266 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK; 6267 tmp |= TMIN(si_pi->t_min); 6268 WREG32(CG_FDO_CTRL2, tmp); 6269 si_pi->fan_ctrl_is_in_default_mode = true; 6270 } 6271} 6272 6273static void si_thermal_start_smc_fan_control(struct radeon_device *rdev) 6274{ 6275 if (rdev->pm.dpm.fan.ucode_fan_control) { 6276 si_fan_ctrl_start_smc_fan_control(rdev); 6277 si_fan_ctrl_set_static_mode(rdev, FDO_PWM_MODE_STATIC); 6278 } 6279} 6280 6281static void si_thermal_initialize(struct radeon_device *rdev) 6282{ 6283 u32 tmp; 6284 6285 if (rdev->pm.fan_pulses_per_revolution) { 6286 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK; 6287 tmp |= EDGE_PER_REV(rdev->pm.fan_pulses_per_revolution -1); 6288 WREG32(CG_TACH_CTRL, tmp); 6289 } 6290 6291 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK; 6292 tmp |= TACH_PWM_RESP_RATE(0x28); 6293 WREG32(CG_FDO_CTRL2, tmp); 6294} 6295 6296static int si_thermal_start_thermal_controller(struct radeon_device *rdev) 6297{ 6298 int ret; 6299 6300 si_thermal_initialize(rdev); 6301 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6302 if (ret) 6303 return ret; 6304 ret = si_thermal_enable_alert(rdev, true); 6305 if (ret) 6306 return ret; 6307 if (rdev->pm.dpm.fan.ucode_fan_control) { 6308 ret = si_halt_smc(rdev); 6309 if (ret) 6310 return ret; 6311 ret = si_thermal_setup_fan_table(rdev); 6312 if (ret) 6313 return ret; 6314 ret = si_resume_smc(rdev); 6315 if (ret) 6316 return ret; 6317 si_thermal_start_smc_fan_control(rdev); 6318 } 6319 6320 return 0; 6321} 6322 6323static void si_thermal_stop_thermal_controller(struct radeon_device *rdev) 6324{ 6325 if (!rdev->pm.no_fan) { 6326 si_fan_ctrl_set_default_mode(rdev); 6327 si_fan_ctrl_stop_smc_fan_control(rdev); 6328 } 6329} 6330 6331int si_dpm_enable(struct radeon_device *rdev) 6332{ 6333 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6334 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6335 struct si_power_info *si_pi = si_get_pi(rdev); 6336 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6337 int ret; 6338 6339 if (si_is_smc_running(rdev)) 6340 return -EINVAL; 6341 if (pi->voltage_control || si_pi->voltage_control_svi2) 6342 si_enable_voltage_control(rdev, true); 6343 if (pi->mvdd_control) 6344 si_get_mvdd_configuration(rdev); 6345 if (pi->voltage_control || si_pi->voltage_control_svi2) { 6346 ret = si_construct_voltage_tables(rdev); 6347 if (ret) { 6348 DRM_ERROR("si_construct_voltage_tables failed\n"); 6349 return ret; 6350 } 6351 } 6352 if (eg_pi->dynamic_ac_timing) { 6353 ret = si_initialize_mc_reg_table(rdev); 6354 if (ret) 6355 eg_pi->dynamic_ac_timing = false; 6356 } 6357 if (pi->dynamic_ss) 6358 si_enable_spread_spectrum(rdev, true); 6359 if (pi->thermal_protection) 6360 si_enable_thermal_protection(rdev, true); 6361 si_setup_bsp(rdev); 6362 si_program_git(rdev); 6363 si_program_tp(rdev); 6364 si_program_tpp(rdev); 6365 si_program_sstp(rdev); 6366 si_enable_display_gap(rdev); 6367 si_program_vc(rdev); 6368 ret = si_upload_firmware(rdev); 6369 if (ret) { 6370 DRM_ERROR("si_upload_firmware failed\n"); 6371 return ret; 6372 } 6373 ret = si_process_firmware_header(rdev); 6374 if (ret) { 6375 DRM_ERROR("si_process_firmware_header failed\n"); 6376 return ret; 6377 } 6378 ret = si_initial_switch_from_arb_f0_to_f1(rdev); 6379 if (ret) { 6380 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n"); 6381 return ret; 6382 } 6383 ret = si_init_smc_table(rdev); 6384 if (ret) { 6385 DRM_ERROR("si_init_smc_table failed\n"); 6386 return ret; 6387 } 6388 ret = si_init_smc_spll_table(rdev); 6389 if (ret) { 6390 DRM_ERROR("si_init_smc_spll_table failed\n"); 6391 return ret; 6392 } 6393 ret = si_init_arb_table_index(rdev); 6394 if (ret) { 6395 DRM_ERROR("si_init_arb_table_index failed\n"); 6396 return ret; 6397 } 6398 if (eg_pi->dynamic_ac_timing) { 6399 ret = si_populate_mc_reg_table(rdev, boot_ps); 6400 if (ret) { 6401 DRM_ERROR("si_populate_mc_reg_table failed\n"); 6402 return ret; 6403 } 6404 } 6405 ret = si_initialize_smc_cac_tables(rdev); 6406 if (ret) { 6407 DRM_ERROR("si_initialize_smc_cac_tables failed\n"); 6408 return ret; 6409 } 6410 ret = si_initialize_hardware_cac_manager(rdev); 6411 if (ret) { 6412 DRM_ERROR("si_initialize_hardware_cac_manager failed\n"); 6413 return ret; 6414 } 6415 ret = si_initialize_smc_dte_tables(rdev); 6416 if (ret) { 6417 DRM_ERROR("si_initialize_smc_dte_tables failed\n"); 6418 return ret; 6419 } 6420 ret = si_populate_smc_tdp_limits(rdev, boot_ps); 6421 if (ret) { 6422 DRM_ERROR("si_populate_smc_tdp_limits failed\n"); 6423 return ret; 6424 } 6425 ret = si_populate_smc_tdp_limits_2(rdev, boot_ps); 6426 if (ret) { 6427 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n"); 6428 return ret; 6429 } 6430 si_program_response_times(rdev); 6431 si_program_ds_registers(rdev); 6432 si_dpm_start_smc(rdev); 6433 ret = si_notify_smc_display_change(rdev, false); 6434 if (ret) { 6435 DRM_ERROR("si_notify_smc_display_change failed\n"); 6436 return ret; 6437 } 6438 si_enable_sclk_control(rdev, true); 6439 si_start_dpm(rdev); 6440 6441 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true); 6442 6443 si_thermal_start_thermal_controller(rdev); 6444 6445 ni_update_current_ps(rdev, boot_ps); 6446 6447 return 0; 6448} 6449 6450static int si_set_temperature_range(struct radeon_device *rdev) 6451{ 6452 int ret; 6453 6454 ret = si_thermal_enable_alert(rdev, false); 6455 if (ret) 6456 return ret; 6457 ret = si_thermal_set_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX); 6458 if (ret) 6459 return ret; 6460 ret = si_thermal_enable_alert(rdev, true); 6461 if (ret) 6462 return ret; 6463 6464 return ret; 6465} 6466 6467int si_dpm_late_enable(struct radeon_device *rdev) 6468{ 6469 int ret; 6470 6471 ret = si_set_temperature_range(rdev); 6472 if (ret) 6473 return ret; 6474 6475 return ret; 6476} 6477 6478void si_dpm_disable(struct radeon_device *rdev) 6479{ 6480 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6481 struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps; 6482 6483 if (!si_is_smc_running(rdev)) 6484 return; 6485 si_thermal_stop_thermal_controller(rdev); 6486 si_disable_ulv(rdev); 6487 si_clear_vc(rdev); 6488 if (pi->thermal_protection) 6489 si_enable_thermal_protection(rdev, false); 6490 si_enable_power_containment(rdev, boot_ps, false); 6491 si_enable_smc_cac(rdev, boot_ps, false); 6492 si_enable_spread_spectrum(rdev, false); 6493 si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false); 6494 si_stop_dpm(rdev); 6495 si_reset_to_default(rdev); 6496 si_dpm_stop_smc(rdev); 6497 si_force_switch_to_arb_f0(rdev); 6498 6499 ni_update_current_ps(rdev, boot_ps); 6500} 6501 6502int si_dpm_pre_set_power_state(struct radeon_device *rdev) 6503{ 6504 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6505 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps; 6506 struct radeon_ps *new_ps = &requested_ps; 6507 6508 ni_update_requested_ps(rdev, new_ps); 6509 6510 si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps); 6511 6512 return 0; 6513} 6514 6515static int si_power_control_set_level(struct radeon_device *rdev) 6516{ 6517 struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps; 6518 int ret; 6519 6520 ret = si_restrict_performance_levels_before_switch(rdev); 6521 if (ret) 6522 return ret; 6523 ret = si_halt_smc(rdev); 6524 if (ret) 6525 return ret; 6526 ret = si_populate_smc_tdp_limits(rdev, new_ps); 6527 if (ret) 6528 return ret; 6529 ret = si_populate_smc_tdp_limits_2(rdev, new_ps); 6530 if (ret) 6531 return ret; 6532 ret = si_resume_smc(rdev); 6533 if (ret) 6534 return ret; 6535 ret = si_set_sw_state(rdev); 6536 if (ret) 6537 return ret; 6538 return 0; 6539} 6540 6541int si_dpm_set_power_state(struct radeon_device *rdev) 6542{ 6543 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6544 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6545 struct radeon_ps *old_ps = &eg_pi->current_rps; 6546 int ret; 6547 6548 ret = si_disable_ulv(rdev); 6549 if (ret) { 6550 DRM_ERROR("si_disable_ulv failed\n"); 6551 return ret; 6552 } 6553 ret = si_restrict_performance_levels_before_switch(rdev); 6554 if (ret) { 6555 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n"); 6556 return ret; 6557 } 6558 if (eg_pi->pcie_performance_request) 6559 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps); 6560 ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); 6561 ret = si_enable_power_containment(rdev, new_ps, false); 6562 if (ret) { 6563 DRM_ERROR("si_enable_power_containment failed\n"); 6564 return ret; 6565 } 6566 ret = si_enable_smc_cac(rdev, new_ps, false); 6567 if (ret) { 6568 DRM_ERROR("si_enable_smc_cac failed\n"); 6569 return ret; 6570 } 6571 ret = si_halt_smc(rdev); 6572 if (ret) { 6573 DRM_ERROR("si_halt_smc failed\n"); 6574 return ret; 6575 } 6576 ret = si_upload_sw_state(rdev, new_ps); 6577 if (ret) { 6578 DRM_ERROR("si_upload_sw_state failed\n"); 6579 return ret; 6580 } 6581 ret = si_upload_smc_data(rdev); 6582 if (ret) { 6583 DRM_ERROR("si_upload_smc_data failed\n"); 6584 return ret; 6585 } 6586 ret = si_upload_ulv_state(rdev); 6587 if (ret) { 6588 DRM_ERROR("si_upload_ulv_state failed\n"); 6589 return ret; 6590 } 6591 if (eg_pi->dynamic_ac_timing) { 6592 ret = si_upload_mc_reg_table(rdev, new_ps); 6593 if (ret) { 6594 DRM_ERROR("si_upload_mc_reg_table failed\n"); 6595 return ret; 6596 } 6597 } 6598 ret = si_program_memory_timing_parameters(rdev, new_ps); 6599 if (ret) { 6600 DRM_ERROR("si_program_memory_timing_parameters failed\n"); 6601 return ret; 6602 } 6603 si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps); 6604 6605 ret = si_resume_smc(rdev); 6606 if (ret) { 6607 DRM_ERROR("si_resume_smc failed\n"); 6608 return ret; 6609 } 6610 ret = si_set_sw_state(rdev); 6611 if (ret) { 6612 DRM_ERROR("si_set_sw_state failed\n"); 6613 return ret; 6614 } 6615 ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); 6616 si_set_vce_clock(rdev, new_ps, old_ps); 6617 if (eg_pi->pcie_performance_request) 6618 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps); 6619 ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps); 6620 if (ret) { 6621 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n"); 6622 return ret; 6623 } 6624 ret = si_enable_smc_cac(rdev, new_ps, true); 6625 if (ret) { 6626 DRM_ERROR("si_enable_smc_cac failed\n"); 6627 return ret; 6628 } 6629 ret = si_enable_power_containment(rdev, new_ps, true); 6630 if (ret) { 6631 DRM_ERROR("si_enable_power_containment failed\n"); 6632 return ret; 6633 } 6634 6635 ret = si_power_control_set_level(rdev); 6636 if (ret) { 6637 DRM_ERROR("si_power_control_set_level failed\n"); 6638 return ret; 6639 } 6640 6641 return 0; 6642} 6643 6644void si_dpm_post_set_power_state(struct radeon_device *rdev) 6645{ 6646 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6647 struct radeon_ps *new_ps = &eg_pi->requested_rps; 6648 6649 ni_update_current_ps(rdev, new_ps); 6650} 6651 6652#if 0 6653void si_dpm_reset_asic(struct radeon_device *rdev) 6654{ 6655 si_restrict_performance_levels_before_switch(rdev); 6656 si_disable_ulv(rdev); 6657 si_set_boot_state(rdev); 6658} 6659#endif 6660 6661void si_dpm_display_configuration_changed(struct radeon_device *rdev) 6662{ 6663 si_program_display_gap(rdev); 6664} 6665 6666union power_info { 6667 struct _ATOM_POWERPLAY_INFO info; 6668 struct _ATOM_POWERPLAY_INFO_V2 info_2; 6669 struct _ATOM_POWERPLAY_INFO_V3 info_3; 6670 struct _ATOM_PPLIB_POWERPLAYTABLE pplib; 6671 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2; 6672 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3; 6673}; 6674 6675union pplib_clock_info { 6676 struct _ATOM_PPLIB_R600_CLOCK_INFO r600; 6677 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780; 6678 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen; 6679 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo; 6680 struct _ATOM_PPLIB_SI_CLOCK_INFO si; 6681}; 6682 6683union pplib_power_state { 6684 struct _ATOM_PPLIB_STATE v1; 6685 struct _ATOM_PPLIB_STATE_V2 v2; 6686}; 6687 6688static void si_parse_pplib_non_clock_info(struct radeon_device *rdev, 6689 struct radeon_ps *rps, 6690 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info, 6691 u8 table_rev) 6692{ 6693 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings); 6694 rps->class = le16_to_cpu(non_clock_info->usClassification); 6695 rps->class2 = le16_to_cpu(non_clock_info->usClassification2); 6696 6697 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) { 6698 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK); 6699 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK); 6700 } else if (r600_is_uvd_state(rps->class, rps->class2)) { 6701 rps->vclk = RV770_DEFAULT_VCLK_FREQ; 6702 rps->dclk = RV770_DEFAULT_DCLK_FREQ; 6703 } else { 6704 rps->vclk = 0; 6705 rps->dclk = 0; 6706 } 6707 6708 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) 6709 rdev->pm.dpm.boot_ps = rps; 6710 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) 6711 rdev->pm.dpm.uvd_ps = rps; 6712} 6713 6714static void si_parse_pplib_clock_info(struct radeon_device *rdev, 6715 struct radeon_ps *rps, int index, 6716 union pplib_clock_info *clock_info) 6717{ 6718 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 6719 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 6720 struct si_power_info *si_pi = si_get_pi(rdev); 6721 struct ni_ps *ps = ni_get_ps(rps); 6722 u16 leakage_voltage; 6723 struct rv7xx_pl *pl = &ps->performance_levels[index]; 6724 int ret; 6725 6726 ps->performance_level_count = index + 1; 6727 6728 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6729 pl->sclk |= clock_info->si.ucEngineClockHigh << 16; 6730 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6731 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16; 6732 6733 pl->vddc = le16_to_cpu(clock_info->si.usVDDC); 6734 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI); 6735 pl->flags = le32_to_cpu(clock_info->si.ulFlags); 6736 pl->pcie_gen = r600_get_pcie_gen_support(rdev, 6737 si_pi->sys_pcie_mask, 6738 si_pi->boot_pcie_gen, 6739 clock_info->si.ucPCIEGen); 6740 6741 /* patch up vddc if necessary */ 6742 ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc, 6743 &leakage_voltage); 6744 if (ret == 0) 6745 pl->vddc = leakage_voltage; 6746 6747 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) { 6748 pi->acpi_vddc = pl->vddc; 6749 eg_pi->acpi_vddci = pl->vddci; 6750 si_pi->acpi_pcie_gen = pl->pcie_gen; 6751 } 6752 6753 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) && 6754 index == 0) { 6755 /* XXX disable for A0 tahiti */ 6756 si_pi->ulv.supported = false; 6757 si_pi->ulv.pl = *pl; 6758 si_pi->ulv.one_pcie_lane_in_ulv = false; 6759 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT; 6760 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT; 6761 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT; 6762 } 6763 6764 if (pi->min_vddc_in_table > pl->vddc) 6765 pi->min_vddc_in_table = pl->vddc; 6766 6767 if (pi->max_vddc_in_table < pl->vddc) 6768 pi->max_vddc_in_table = pl->vddc; 6769 6770 /* patch up boot state */ 6771 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) { 6772 u16 vddc, vddci, mvdd; 6773 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd); 6774 pl->mclk = rdev->clock.default_mclk; 6775 pl->sclk = rdev->clock.default_sclk; 6776 pl->vddc = vddc; 6777 pl->vddci = vddci; 6778 si_pi->mvdd_bootup_value = mvdd; 6779 } 6780 6781 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) == 6782 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 6783 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk; 6784 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; 6785 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc; 6786 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci; 6787 } 6788} 6789 6790static int si_parse_power_table(struct radeon_device *rdev) 6791{ 6792 struct radeon_mode_info *mode_info = &rdev->mode_info; 6793 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info; 6794 union pplib_power_state *power_state; 6795 int i, j, k, non_clock_array_index, clock_array_index; 6796 union pplib_clock_info *clock_info; 6797 struct _StateArray *state_array; 6798 struct _ClockInfoArray *clock_info_array; 6799 struct _NonClockInfoArray *non_clock_info_array; 6800 union power_info *power_info; 6801 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo); 6802 u16 data_offset; 6803 u8 frev, crev; 6804 u8 *power_state_offset; 6805 struct ni_ps *ps; 6806 6807 if (!atom_parse_data_header(mode_info->atom_context, index, NULL, 6808 &frev, &crev, &data_offset)) 6809 return -EINVAL; 6810 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset); 6811 6812 state_array = (struct _StateArray *) 6813 (mode_info->atom_context->bios + data_offset + 6814 le16_to_cpu(power_info->pplib.usStateArrayOffset)); 6815 clock_info_array = (struct _ClockInfoArray *) 6816 (mode_info->atom_context->bios + data_offset + 6817 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset)); 6818 non_clock_info_array = (struct _NonClockInfoArray *) 6819 (mode_info->atom_context->bios + data_offset + 6820 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset)); 6821 6822 rdev->pm.dpm.ps = kcalloc(state_array->ucNumEntries, 6823 sizeof(struct radeon_ps), 6824 GFP_KERNEL); 6825 if (!rdev->pm.dpm.ps) 6826 return -ENOMEM; 6827 power_state_offset = (u8 *)state_array->states; 6828 for (i = 0; i < state_array->ucNumEntries; i++) { 6829 u8 *idx; 6830 power_state = (union pplib_power_state *)power_state_offset; 6831 non_clock_array_index = power_state->v2.nonClockInfoIndex; 6832 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *) 6833 &non_clock_info_array->nonClockInfo[non_clock_array_index]; 6834 if (!rdev->pm.power_state[i].clock_info) 6835 return -EINVAL; 6836 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL); 6837 if (ps == NULL) { 6838 kfree(rdev->pm.dpm.ps); 6839 return -ENOMEM; 6840 } 6841 rdev->pm.dpm.ps[i].ps_priv = ps; 6842 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i], 6843 non_clock_info, 6844 non_clock_info_array->ucEntrySize); 6845 k = 0; 6846 idx = (u8 *)&power_state->v2.clockInfoIndex[0]; 6847 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) { 6848 clock_array_index = idx[j]; 6849 if (clock_array_index >= clock_info_array->ucNumEntries) 6850 continue; 6851 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS) 6852 break; 6853 clock_info = (union pplib_clock_info *) 6854 ((u8 *)&clock_info_array->clockInfo[0] + 6855 (clock_array_index * clock_info_array->ucEntrySize)); 6856 si_parse_pplib_clock_info(rdev, 6857 &rdev->pm.dpm.ps[i], k, 6858 clock_info); 6859 k++; 6860 } 6861 power_state_offset += 2 + power_state->v2.ucNumDPMLevels; 6862 } 6863 rdev->pm.dpm.num_ps = state_array->ucNumEntries; 6864 6865 /* fill in the vce power states */ 6866 for (i = 0; i < RADEON_MAX_VCE_LEVELS; i++) { 6867 u32 sclk, mclk; 6868 clock_array_index = rdev->pm.dpm.vce_states[i].clk_idx; 6869 clock_info = (union pplib_clock_info *) 6870 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize]; 6871 sclk = le16_to_cpu(clock_info->si.usEngineClockLow); 6872 sclk |= clock_info->si.ucEngineClockHigh << 16; 6873 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow); 6874 mclk |= clock_info->si.ucMemoryClockHigh << 16; 6875 rdev->pm.dpm.vce_states[i].sclk = sclk; 6876 rdev->pm.dpm.vce_states[i].mclk = mclk; 6877 } 6878 6879 return 0; 6880} 6881 6882int si_dpm_init(struct radeon_device *rdev) 6883{ 6884 struct rv7xx_power_info *pi; 6885 struct evergreen_power_info *eg_pi; 6886 struct ni_power_info *ni_pi; 6887 struct si_power_info *si_pi; 6888 struct atom_clock_dividers dividers; 6889 enum pci_bus_speed speed_cap = PCI_SPEED_UNKNOWN; 6890 struct pci_dev *root = rdev->pdev->bus->self; 6891 int ret; 6892 6893 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); 6894 if (si_pi == NULL) 6895 return -ENOMEM; 6896 rdev->pm.dpm.priv = si_pi; 6897 ni_pi = &si_pi->ni; 6898 eg_pi = &ni_pi->eg; 6899 pi = &eg_pi->rv7xx; 6900 6901 if (!pci_is_root_bus(rdev->pdev->bus)) 6902 speed_cap = pcie_get_speed_cap(root); 6903 if (speed_cap == PCI_SPEED_UNKNOWN) { 6904 si_pi->sys_pcie_mask = 0; 6905 } else { 6906 if (speed_cap == PCIE_SPEED_8_0GT) 6907 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6908 RADEON_PCIE_SPEED_50 | 6909 RADEON_PCIE_SPEED_80; 6910 else if (speed_cap == PCIE_SPEED_5_0GT) 6911 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | 6912 RADEON_PCIE_SPEED_50; 6913 else 6914 si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; 6915 } 6916 si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; 6917 si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev); 6918 6919 si_set_max_cu_value(rdev); 6920 6921 rv770_get_max_vddc(rdev); 6922 si_get_leakage_vddc(rdev); 6923 si_patch_dependency_tables_based_on_leakage(rdev); 6924 6925 pi->acpi_vddc = 0; 6926 eg_pi->acpi_vddci = 0; 6927 pi->min_vddc_in_table = 0; 6928 pi->max_vddc_in_table = 0; 6929 6930 ret = r600_get_platform_caps(rdev); 6931 if (ret) 6932 return ret; 6933 6934 ret = r600_parse_extended_power_table(rdev); 6935 if (ret) 6936 return ret; 6937 6938 ret = si_parse_power_table(rdev); 6939 if (ret) 6940 return ret; 6941 6942 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries = 6943 kcalloc(4, 6944 sizeof(struct radeon_clock_voltage_dependency_entry), 6945 GFP_KERNEL); 6946 if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) { 6947 r600_free_extended_power_table(rdev); 6948 return -ENOMEM; 6949 } 6950 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4; 6951 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0; 6952 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0; 6953 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000; 6954 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720; 6955 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000; 6956 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810; 6957 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000; 6958 rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900; 6959 6960 if (rdev->pm.dpm.voltage_response_time == 0) 6961 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT; 6962 if (rdev->pm.dpm.backbias_response_time == 0) 6963 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT; 6964 6965 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 6966 0, false, ÷rs); 6967 if (ret) 6968 pi->ref_div = dividers.ref_div + 1; 6969 else 6970 pi->ref_div = R600_REFERENCEDIVIDER_DFLT; 6971 6972 eg_pi->smu_uvd_hs = false; 6973 6974 pi->mclk_strobe_mode_threshold = 40000; 6975 if (si_is_special_1gb_platform(rdev)) 6976 pi->mclk_stutter_mode_threshold = 0; 6977 else 6978 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold; 6979 pi->mclk_edc_enable_threshold = 40000; 6980 eg_pi->mclk_edc_wr_enable_threshold = 40000; 6981 6982 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold; 6983 6984 pi->voltage_control = 6985 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6986 VOLTAGE_OBJ_GPIO_LUT); 6987 if (!pi->voltage_control) { 6988 si_pi->voltage_control_svi2 = 6989 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6990 VOLTAGE_OBJ_SVID2); 6991 if (si_pi->voltage_control_svi2) 6992 radeon_atom_get_svi2_info(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 6993 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id); 6994 } 6995 6996 pi->mvdd_control = 6997 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, 6998 VOLTAGE_OBJ_GPIO_LUT); 6999 7000 eg_pi->vddci_control = 7001 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7002 VOLTAGE_OBJ_GPIO_LUT); 7003 if (!eg_pi->vddci_control) 7004 si_pi->vddci_control_svi2 = 7005 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, 7006 VOLTAGE_OBJ_SVID2); 7007 7008 si_pi->vddc_phase_shed_control = 7009 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, 7010 VOLTAGE_OBJ_PHASE_LUT); 7011 7012 rv770_get_engine_memory_ss(rdev); 7013 7014 pi->asi = RV770_ASI_DFLT; 7015 pi->pasi = CYPRESS_HASI_DFLT; 7016 pi->vrc = SISLANDS_VRC_DFLT; 7017 7018 pi->gfx_clock_gating = true; 7019 7020 eg_pi->sclk_deep_sleep = true; 7021 si_pi->sclk_deep_sleep_above_low = false; 7022 7023 if (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE) 7024 pi->thermal_protection = true; 7025 else 7026 pi->thermal_protection = false; 7027 7028 eg_pi->dynamic_ac_timing = true; 7029 7030 eg_pi->light_sleep = true; 7031#if defined(CONFIG_ACPI) 7032 eg_pi->pcie_performance_request = 7033 radeon_acpi_is_pcie_performance_request_supported(rdev); 7034#else 7035 eg_pi->pcie_performance_request = false; 7036#endif 7037 7038 si_pi->sram_end = SMC_RAM_END; 7039 7040 rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4; 7041 rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000; 7042 rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200; 7043 rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0; 7044 rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL; 7045 rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0; 7046 rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL; 7047 7048 si_initialize_powertune_defaults(rdev); 7049 7050 /* make sure dc limits are valid */ 7051 if ((rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) || 7052 (rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0)) 7053 rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc = 7054 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac; 7055 7056 si_pi->fan_ctrl_is_in_default_mode = true; 7057 7058 return 0; 7059} 7060 7061void si_dpm_fini(struct radeon_device *rdev) 7062{ 7063 int i; 7064 7065 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 7066 kfree(rdev->pm.dpm.ps[i].ps_priv); 7067 } 7068 kfree(rdev->pm.dpm.ps); 7069 kfree(rdev->pm.dpm.priv); 7070 kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries); 7071 r600_free_extended_power_table(rdev); 7072} 7073 7074void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev, 7075 struct seq_file *m) 7076{ 7077 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7078 struct radeon_ps *rps = &eg_pi->current_rps; 7079 struct ni_ps *ps = ni_get_ps(rps); 7080 struct rv7xx_pl *pl; 7081 u32 current_index = 7082 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7083 CURRENT_STATE_INDEX_SHIFT; 7084 7085 if (current_index >= ps->performance_level_count) { 7086 seq_printf(m, "invalid dpm profile %d\n", current_index); 7087 } else { 7088 pl = &ps->performance_levels[current_index]; 7089 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk); 7090 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n", 7091 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1); 7092 } 7093} 7094 7095u32 si_dpm_get_current_sclk(struct radeon_device *rdev) 7096{ 7097 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7098 struct radeon_ps *rps = &eg_pi->current_rps; 7099 struct ni_ps *ps = ni_get_ps(rps); 7100 struct rv7xx_pl *pl; 7101 u32 current_index = 7102 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7103 CURRENT_STATE_INDEX_SHIFT; 7104 7105 if (current_index >= ps->performance_level_count) { 7106 return 0; 7107 } else { 7108 pl = &ps->performance_levels[current_index]; 7109 return pl->sclk; 7110 } 7111} 7112 7113u32 si_dpm_get_current_mclk(struct radeon_device *rdev) 7114{ 7115 struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev); 7116 struct radeon_ps *rps = &eg_pi->current_rps; 7117 struct ni_ps *ps = ni_get_ps(rps); 7118 struct rv7xx_pl *pl; 7119 u32 current_index = 7120 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >> 7121 CURRENT_STATE_INDEX_SHIFT; 7122 7123 if (current_index >= ps->performance_level_count) { 7124 return 0; 7125 } else { 7126 pl = &ps->performance_levels[current_index]; 7127 return pl->mclk; 7128 } 7129} 7130