1/* 2 * Copyright 2011 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 25#include "radeon.h" 26#include "rv740d.h" 27#include "r600_dpm.h" 28#include "rv770_dpm.h" 29#include "atom.h" 30 31struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); 32 33u32 rv740_get_decoded_reference_divider(u32 encoded_ref) 34{ 35 u32 ref = 0; 36 37 switch (encoded_ref) { 38 case 0: 39 ref = 1; 40 break; 41 case 16: 42 ref = 2; 43 break; 44 case 17: 45 ref = 3; 46 break; 47 case 18: 48 ref = 2; 49 break; 50 case 19: 51 ref = 3; 52 break; 53 case 20: 54 ref = 4; 55 break; 56 case 21: 57 ref = 5; 58 break; 59 default: 60 DRM_ERROR("Invalid encoded Reference Divider\n"); 61 ref = 0; 62 break; 63 } 64 65 return ref; 66} 67 68struct dll_speed_setting { 69 u16 min; 70 u16 max; 71 u32 dll_speed; 72}; 73 74static struct dll_speed_setting dll_speed_table[16] = 75{ 76 { 270, 320, 0x0f }, 77 { 240, 270, 0x0e }, 78 { 200, 240, 0x0d }, 79 { 180, 200, 0x0c }, 80 { 160, 180, 0x0b }, 81 { 140, 160, 0x0a }, 82 { 120, 140, 0x09 }, 83 { 110, 120, 0x08 }, 84 { 95, 110, 0x07 }, 85 { 85, 95, 0x06 }, 86 { 78, 85, 0x05 }, 87 { 70, 78, 0x04 }, 88 { 65, 70, 0x03 }, 89 { 60, 65, 0x02 }, 90 { 42, 60, 0x01 }, 91 { 00, 42, 0x00 } 92}; 93 94u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) 95{ 96 int i; 97 u32 factor; 98 u16 data_rate; 99 100 if (is_gddr5) 101 factor = 4; 102 else 103 factor = 2; 104 105 data_rate = (u16)(memory_clock * factor / 1000); 106 107 if (data_rate < dll_speed_table[0].max) { 108 for (i = 0; i < 16; i++) { 109 if (data_rate > dll_speed_table[i].min && 110 data_rate <= dll_speed_table[i].max) 111 return dll_speed_table[i].dll_speed; 112 } 113 } 114 115 DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n"); 116 117 return 0x0f; 118} 119 120int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, 121 RV770_SMC_SCLK_VALUE *sclk) 122{ 123 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 124 struct atom_clock_dividers dividers; 125 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; 126 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; 127 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; 128 u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; 129 u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; 130 u64 tmp; 131 u32 reference_clock = rdev->clock.spll.reference_freq; 132 u32 reference_divider; 133 u32 fbdiv; 134 int ret; 135 136 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, 137 engine_clock, false, ÷rs); 138 if (ret) 139 return ret; 140 141 reference_divider = 1 + dividers.ref_div; 142 143 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; 144 do_div(tmp, reference_clock); 145 fbdiv = (u32) tmp; 146 147 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); 148 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); 149 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); 150 151 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 152 spll_func_cntl_2 |= SCLK_MUX_SEL(2); 153 154 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; 155 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); 156 spll_func_cntl_3 |= SPLL_DITHEN; 157 158 if (pi->sclk_ss) { 159 struct radeon_atom_ss ss; 160 u32 vco_freq = engine_clock * dividers.post_div; 161 162 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 163 ASIC_INTERNAL_ENGINE_SS, vco_freq)) { 164 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); 165 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); 166 167 cg_spll_spread_spectrum &= ~CLK_S_MASK; 168 cg_spll_spread_spectrum |= CLK_S(clk_s); 169 cg_spll_spread_spectrum |= SSEN; 170 171 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; 172 cg_spll_spread_spectrum_2 |= CLK_V(clk_v); 173 } 174 } 175 176 sclk->sclk_value = cpu_to_be32(engine_clock); 177 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 178 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); 179 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); 180 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); 181 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); 182 183 return 0; 184} 185 186int rv740_populate_mclk_value(struct radeon_device *rdev, 187 u32 engine_clock, u32 memory_clock, 188 RV7XX_SMC_MCLK_VALUE *mclk) 189{ 190 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 191 u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; 192 u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; 193 u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; 194 u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; 195 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; 196 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; 197 u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; 198 u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; 199 struct atom_clock_dividers dividers; 200 u32 ibias; 201 u32 dll_speed; 202 int ret; 203 204 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, 205 memory_clock, false, ÷rs); 206 if (ret) 207 return ret; 208 209 ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); 210 211 mpll_ad_func_cntl &= ~(CLKR_MASK | 212 YCLK_POST_DIV_MASK | 213 CLKF_MASK | 214 CLKFRAC_MASK | 215 IBIAS_MASK); 216 mpll_ad_func_cntl |= CLKR(dividers.ref_div); 217 mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); 218 mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); 219 mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); 220 mpll_ad_func_cntl |= IBIAS(ibias); 221 222 if (dividers.vco_mode) 223 mpll_ad_func_cntl_2 |= VCO_MODE; 224 else 225 mpll_ad_func_cntl_2 &= ~VCO_MODE; 226 227 if (pi->mem_gddr5) { 228 mpll_dq_func_cntl &= ~(CLKR_MASK | 229 YCLK_POST_DIV_MASK | 230 CLKF_MASK | 231 CLKFRAC_MASK | 232 IBIAS_MASK); 233 mpll_dq_func_cntl |= CLKR(dividers.ref_div); 234 mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); 235 mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div); 236 mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div); 237 mpll_dq_func_cntl |= IBIAS(ibias); 238 239 if (dividers.vco_mode) 240 mpll_dq_func_cntl_2 |= VCO_MODE; 241 else 242 mpll_dq_func_cntl_2 &= ~VCO_MODE; 243 } 244 245 if (pi->mclk_ss) { 246 struct radeon_atom_ss ss; 247 u32 vco_freq = memory_clock * dividers.post_div; 248 249 if (radeon_atombios_get_asic_ss_info(rdev, &ss, 250 ASIC_INTERNAL_MEMORY_SS, vco_freq)) { 251 u32 reference_clock = rdev->clock.mpll.reference_freq; 252 u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); 253 u32 clk_s, clk_v; 254 255 if (!decoded_ref) 256 return -EINVAL; 257 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); 258 clk_v = 0x40000 * ss.percentage * 259 (dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000); 260 261 mpll_ss1 &= ~CLKV_MASK; 262 mpll_ss1 |= CLKV(clk_v); 263 264 mpll_ss2 &= ~CLKS_MASK; 265 mpll_ss2 |= CLKS(clk_s); 266 } 267 } 268 269 dll_speed = rv740_get_dll_speed(pi->mem_gddr5, 270 memory_clock); 271 272 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; 273 mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed); 274 275 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); 276 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 277 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); 278 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 279 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); 280 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 281 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); 282 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); 283 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); 284 285 return 0; 286} 287 288void rv740_read_clock_registers(struct radeon_device *rdev) 289{ 290 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 291 292 pi->clk_regs.rv770.cg_spll_func_cntl = 293 RREG32(CG_SPLL_FUNC_CNTL); 294 pi->clk_regs.rv770.cg_spll_func_cntl_2 = 295 RREG32(CG_SPLL_FUNC_CNTL_2); 296 pi->clk_regs.rv770.cg_spll_func_cntl_3 = 297 RREG32(CG_SPLL_FUNC_CNTL_3); 298 pi->clk_regs.rv770.cg_spll_spread_spectrum = 299 RREG32(CG_SPLL_SPREAD_SPECTRUM); 300 pi->clk_regs.rv770.cg_spll_spread_spectrum_2 = 301 RREG32(CG_SPLL_SPREAD_SPECTRUM_2); 302 303 pi->clk_regs.rv770.mpll_ad_func_cntl = 304 RREG32(MPLL_AD_FUNC_CNTL); 305 pi->clk_regs.rv770.mpll_ad_func_cntl_2 = 306 RREG32(MPLL_AD_FUNC_CNTL_2); 307 pi->clk_regs.rv770.mpll_dq_func_cntl = 308 RREG32(MPLL_DQ_FUNC_CNTL); 309 pi->clk_regs.rv770.mpll_dq_func_cntl_2 = 310 RREG32(MPLL_DQ_FUNC_CNTL_2); 311 pi->clk_regs.rv770.mclk_pwrmgt_cntl = 312 RREG32(MCLK_PWRMGT_CNTL); 313 pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL); 314 pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1); 315 pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2); 316} 317 318int rv740_populate_smc_acpi_state(struct radeon_device *rdev, 319 RV770_SMC_STATETABLE *table) 320{ 321 struct rv7xx_power_info *pi = rv770_get_pi(rdev); 322 u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; 323 u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; 324 u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; 325 u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; 326 u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; 327 u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; 328 u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; 329 u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; 330 u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; 331 332 table->ACPIState = table->initialState; 333 334 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; 335 336 if (pi->acpi_vddc) { 337 rv770_populate_vddc_value(rdev, pi->acpi_vddc, 338 &table->ACPIState.levels[0].vddc); 339 table->ACPIState.levels[0].gen2PCIE = 340 pi->pcie_gen2 ? 341 pi->acpi_pcie_gen2 : 0; 342 table->ACPIState.levels[0].gen2XSP = 343 pi->acpi_pcie_gen2; 344 } else { 345 rv770_populate_vddc_value(rdev, pi->min_vddc_in_table, 346 &table->ACPIState.levels[0].vddc); 347 table->ACPIState.levels[0].gen2PCIE = 0; 348 } 349 350 mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; 351 352 mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN; 353 354 mclk_pwrmgt_cntl |= (MRDCKA0_RESET | 355 MRDCKA1_RESET | 356 MRDCKB0_RESET | 357 MRDCKB1_RESET | 358 MRDCKC0_RESET | 359 MRDCKC1_RESET | 360 MRDCKD0_RESET | 361 MRDCKD1_RESET); 362 363 dll_cntl |= (MRDCKA0_BYPASS | 364 MRDCKA1_BYPASS | 365 MRDCKB0_BYPASS | 366 MRDCKB1_BYPASS | 367 MRDCKC0_BYPASS | 368 MRDCKC1_BYPASS | 369 MRDCKD0_BYPASS | 370 MRDCKD1_BYPASS); 371 372 spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; 373 374 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; 375 spll_func_cntl_2 |= SCLK_MUX_SEL(4); 376 377 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); 378 table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); 379 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); 380 table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); 381 table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); 382 table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); 383 384 table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0; 385 386 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); 387 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); 388 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); 389 390 table->ACPIState.levels[0].sclk.sclk_value = 0; 391 392 table->ACPIState.levels[1] = table->ACPIState.levels[0]; 393 table->ACPIState.levels[2] = table->ACPIState.levels[0]; 394 395 rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); 396 397 return 0; 398} 399 400void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev, 401 bool enable) 402{ 403 if (enable) 404 WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); 405 else 406 WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); 407} 408 409u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) 410{ 411 u8 mc_para_index; 412 413 if ((memory_clock < 10000) || (memory_clock > 47500)) 414 mc_para_index = 0x00; 415 else 416 mc_para_index = (u8)((memory_clock - 10000) / 2500); 417 418 return mc_para_index; 419} 420