1/* 2 * Permission is hereby granted, free of charge, to any person obtaining a 3 * copy of this software and associated documentation files (the "Software"), 4 * to deal in the Software without restriction, including without limitation 5 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 6 * and/or sell copies of the Software, and to permit persons to whom the 7 * Software is furnished to do so, subject to the following conditions: 8 * 9 * The above copyright notice and this permission notice shall be included in 10 * all copies or substantial portions of the Software. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 13 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 14 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 15 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 16 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 17 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 18 * OTHER DEALINGS IN THE SOFTWARE. 19 * 20 * Authors: Rafał Miłecki <zajec5@gmail.com> 21 * Alex Deucher <alexdeucher@gmail.com> 22 */ 23 24#include <linux/hwmon-sysfs.h> 25#include <linux/hwmon.h> 26#include <linux/pci.h> 27#include <linux/power_supply.h> 28 29#include <drm/drm_debugfs.h> 30#include <drm/drm_vblank.h> 31 32#include "atom.h" 33#include "avivod.h" 34#include "r600_dpm.h" 35#include "radeon.h" 36 37#define RADEON_IDLE_LOOP_MS 100 38#define RADEON_RECLOCK_DELAY_MS 200 39#define RADEON_WAIT_VBLANK_TIMEOUT 200 40 41static const char *radeon_pm_state_type_name[5] = { 42 "", 43 "Powersave", 44 "Battery", 45 "Balanced", 46 "Performance", 47}; 48 49static void radeon_dynpm_idle_work_handler(struct work_struct *work); 50static int radeon_debugfs_pm_init(struct radeon_device *rdev); 51static bool radeon_pm_in_vbl(struct radeon_device *rdev); 52static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish); 53static void radeon_pm_update_profile(struct radeon_device *rdev); 54static void radeon_pm_set_clocks(struct radeon_device *rdev); 55 56int radeon_pm_get_type_index(struct radeon_device *rdev, 57 enum radeon_pm_state_type ps_type, 58 int instance) 59{ 60 int i; 61 int found_instance = -1; 62 63 for (i = 0; i < rdev->pm.num_power_states; i++) { 64 if (rdev->pm.power_state[i].type == ps_type) { 65 found_instance++; 66 if (found_instance == instance) 67 return i; 68 } 69 } 70 /* return default if no match */ 71 return rdev->pm.default_power_state_index; 72} 73 74void radeon_pm_acpi_event_handler(struct radeon_device *rdev) 75{ 76 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { 77 mutex_lock(&rdev->pm.mutex); 78 if (power_supply_is_system_supplied() > 0) 79 rdev->pm.dpm.ac_power = true; 80 else 81 rdev->pm.dpm.ac_power = false; 82 if (rdev->family == CHIP_ARUBA) { 83 if (rdev->asic->dpm.enable_bapm) 84 radeon_dpm_enable_bapm(rdev, rdev->pm.dpm.ac_power); 85 } 86 mutex_unlock(&rdev->pm.mutex); 87 } else if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 88 if (rdev->pm.profile == PM_PROFILE_AUTO) { 89 mutex_lock(&rdev->pm.mutex); 90 radeon_pm_update_profile(rdev); 91 radeon_pm_set_clocks(rdev); 92 mutex_unlock(&rdev->pm.mutex); 93 } 94 } 95} 96 97static void radeon_pm_update_profile(struct radeon_device *rdev) 98{ 99 switch (rdev->pm.profile) { 100 case PM_PROFILE_DEFAULT: 101 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX; 102 break; 103 case PM_PROFILE_AUTO: 104 if (power_supply_is_system_supplied() > 0) { 105 if (rdev->pm.active_crtc_count > 1) 106 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 107 else 108 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 109 } else { 110 if (rdev->pm.active_crtc_count > 1) 111 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 112 else 113 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 114 } 115 break; 116 case PM_PROFILE_LOW: 117 if (rdev->pm.active_crtc_count > 1) 118 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX; 119 else 120 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX; 121 break; 122 case PM_PROFILE_MID: 123 if (rdev->pm.active_crtc_count > 1) 124 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX; 125 else 126 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX; 127 break; 128 case PM_PROFILE_HIGH: 129 if (rdev->pm.active_crtc_count > 1) 130 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX; 131 else 132 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX; 133 break; 134 } 135 136 if (rdev->pm.active_crtc_count == 0) { 137 rdev->pm.requested_power_state_index = 138 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx; 139 rdev->pm.requested_clock_mode_index = 140 rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx; 141 } else { 142 rdev->pm.requested_power_state_index = 143 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx; 144 rdev->pm.requested_clock_mode_index = 145 rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx; 146 } 147} 148 149static void radeon_unmap_vram_bos(struct radeon_device *rdev) 150{ 151 struct radeon_bo *bo, *n; 152 153 if (list_empty(&rdev->gem.objects)) 154 return; 155 156 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 157 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) 158 ttm_bo_unmap_virtual(&bo->tbo); 159 } 160} 161 162static void radeon_sync_with_vblank(struct radeon_device *rdev) 163{ 164 if (rdev->pm.active_crtcs) { 165 rdev->pm.vblank_sync = false; 166 wait_event_timeout( 167 rdev->irq.vblank_queue, rdev->pm.vblank_sync, 168 msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT)); 169 } 170} 171 172static void radeon_set_power_state(struct radeon_device *rdev) 173{ 174 u32 sclk, mclk; 175 bool misc_after = false; 176 177 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 178 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 179 return; 180 181 if (radeon_gui_idle(rdev)) { 182 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 183 clock_info[rdev->pm.requested_clock_mode_index].sclk; 184 if (sclk > rdev->pm.default_sclk) 185 sclk = rdev->pm.default_sclk; 186 187 /* starting with BTC, there is one state that is used for both 188 * MH and SH. Difference is that we always use the high clock index for 189 * mclk and vddci. 190 */ 191 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) && 192 (rdev->family >= CHIP_BARTS) && 193 rdev->pm.active_crtc_count && 194 ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) || 195 (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX))) 196 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 197 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk; 198 else 199 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index]. 200 clock_info[rdev->pm.requested_clock_mode_index].mclk; 201 202 if (mclk > rdev->pm.default_mclk) 203 mclk = rdev->pm.default_mclk; 204 205 /* upvolt before raising clocks, downvolt after lowering clocks */ 206 if (sclk < rdev->pm.current_sclk) 207 misc_after = true; 208 209 radeon_sync_with_vblank(rdev); 210 211 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 212 if (!radeon_pm_in_vbl(rdev)) 213 return; 214 } 215 216 radeon_pm_prepare(rdev); 217 218 if (!misc_after) 219 /* voltage, pcie lanes, etc.*/ 220 radeon_pm_misc(rdev); 221 222 /* set engine clock */ 223 if (sclk != rdev->pm.current_sclk) { 224 radeon_pm_debug_check_in_vbl(rdev, false); 225 radeon_set_engine_clock(rdev, sclk); 226 radeon_pm_debug_check_in_vbl(rdev, true); 227 rdev->pm.current_sclk = sclk; 228 DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk); 229 } 230 231 /* set memory clock */ 232 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) { 233 radeon_pm_debug_check_in_vbl(rdev, false); 234 radeon_set_memory_clock(rdev, mclk); 235 radeon_pm_debug_check_in_vbl(rdev, true); 236 rdev->pm.current_mclk = mclk; 237 DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk); 238 } 239 240 if (misc_after) 241 /* voltage, pcie lanes, etc.*/ 242 radeon_pm_misc(rdev); 243 244 radeon_pm_finish(rdev); 245 246 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index; 247 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index; 248 } else 249 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n"); 250} 251 252static void radeon_pm_set_clocks(struct radeon_device *rdev) 253{ 254 struct drm_crtc *crtc; 255 int i, r; 256 257 /* no need to take locks, etc. if nothing's going to change */ 258 if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) && 259 (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index)) 260 return; 261 262 down_write(&rdev->pm.mclk_lock); 263 mutex_lock(&rdev->ring_lock); 264 265 /* wait for the rings to drain */ 266 for (i = 0; i < RADEON_NUM_RINGS; i++) { 267 struct radeon_ring *ring = &rdev->ring[i]; 268 if (!ring->ready) { 269 continue; 270 } 271 r = radeon_fence_wait_empty(rdev, i); 272 if (r) { 273 /* needs a GPU reset dont reset here */ 274 mutex_unlock(&rdev->ring_lock); 275 up_write(&rdev->pm.mclk_lock); 276 return; 277 } 278 } 279 280 radeon_unmap_vram_bos(rdev); 281 282 if (rdev->irq.installed) { 283 i = 0; 284 drm_for_each_crtc(crtc, rdev->ddev) { 285 if (rdev->pm.active_crtcs & (1 << i)) { 286 /* This can fail if a modeset is in progress */ 287 if (drm_crtc_vblank_get(crtc) == 0) 288 rdev->pm.req_vblank |= (1 << i); 289 else 290 DRM_DEBUG_DRIVER("crtc %d no vblank, can glitch\n", 291 i); 292 } 293 i++; 294 } 295 } 296 297 radeon_set_power_state(rdev); 298 299 if (rdev->irq.installed) { 300 i = 0; 301 drm_for_each_crtc(crtc, rdev->ddev) { 302 if (rdev->pm.req_vblank & (1 << i)) { 303 rdev->pm.req_vblank &= ~(1 << i); 304 drm_crtc_vblank_put(crtc); 305 } 306 i++; 307 } 308 } 309 310 /* update display watermarks based on new power state */ 311 radeon_update_bandwidth_info(rdev); 312 if (rdev->pm.active_crtc_count) 313 radeon_bandwidth_update(rdev); 314 315 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 316 317 mutex_unlock(&rdev->ring_lock); 318 up_write(&rdev->pm.mclk_lock); 319} 320 321static void radeon_pm_print_states(struct radeon_device *rdev) 322{ 323 int i, j; 324 struct radeon_power_state *power_state; 325 struct radeon_pm_clock_info *clock_info; 326 327 DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states); 328 for (i = 0; i < rdev->pm.num_power_states; i++) { 329 power_state = &rdev->pm.power_state[i]; 330 DRM_DEBUG_DRIVER("State %d: %s\n", i, 331 radeon_pm_state_type_name[power_state->type]); 332 if (i == rdev->pm.default_power_state_index) 333 DRM_DEBUG_DRIVER("\tDefault"); 334 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP)) 335 DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes); 336 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY) 337 DRM_DEBUG_DRIVER("\tSingle display only\n"); 338 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes); 339 for (j = 0; j < power_state->num_clock_modes; j++) { 340 clock_info = &(power_state->clock_info[j]); 341 if (rdev->flags & RADEON_IS_IGP) 342 DRM_DEBUG_DRIVER("\t\t%d e: %d\n", 343 j, 344 clock_info->sclk * 10); 345 else 346 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n", 347 j, 348 clock_info->sclk * 10, 349 clock_info->mclk * 10, 350 clock_info->voltage.voltage); 351 } 352 } 353} 354 355static ssize_t radeon_get_pm_profile(struct device *dev, 356 struct device_attribute *attr, 357 char *buf) 358{ 359 struct drm_device *ddev = dev_get_drvdata(dev); 360 struct radeon_device *rdev = ddev->dev_private; 361 int cp = rdev->pm.profile; 362 363 return snprintf(buf, PAGE_SIZE, "%s\n", 364 (cp == PM_PROFILE_AUTO) ? "auto" : 365 (cp == PM_PROFILE_LOW) ? "low" : 366 (cp == PM_PROFILE_MID) ? "mid" : 367 (cp == PM_PROFILE_HIGH) ? "high" : "default"); 368} 369 370static ssize_t radeon_set_pm_profile(struct device *dev, 371 struct device_attribute *attr, 372 const char *buf, 373 size_t count) 374{ 375 struct drm_device *ddev = dev_get_drvdata(dev); 376 struct radeon_device *rdev = ddev->dev_private; 377 378 /* Can't set profile when the card is off */ 379 if ((rdev->flags & RADEON_IS_PX) && 380 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 381 return -EINVAL; 382 383 mutex_lock(&rdev->pm.mutex); 384 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 385 if (strncmp("default", buf, strlen("default")) == 0) 386 rdev->pm.profile = PM_PROFILE_DEFAULT; 387 else if (strncmp("auto", buf, strlen("auto")) == 0) 388 rdev->pm.profile = PM_PROFILE_AUTO; 389 else if (strncmp("low", buf, strlen("low")) == 0) 390 rdev->pm.profile = PM_PROFILE_LOW; 391 else if (strncmp("mid", buf, strlen("mid")) == 0) 392 rdev->pm.profile = PM_PROFILE_MID; 393 else if (strncmp("high", buf, strlen("high")) == 0) 394 rdev->pm.profile = PM_PROFILE_HIGH; 395 else { 396 count = -EINVAL; 397 goto fail; 398 } 399 radeon_pm_update_profile(rdev); 400 radeon_pm_set_clocks(rdev); 401 } else 402 count = -EINVAL; 403 404fail: 405 mutex_unlock(&rdev->pm.mutex); 406 407 return count; 408} 409 410static ssize_t radeon_get_pm_method(struct device *dev, 411 struct device_attribute *attr, 412 char *buf) 413{ 414 struct drm_device *ddev = dev_get_drvdata(dev); 415 struct radeon_device *rdev = ddev->dev_private; 416 int pm = rdev->pm.pm_method; 417 418 return snprintf(buf, PAGE_SIZE, "%s\n", 419 (pm == PM_METHOD_DYNPM) ? "dynpm" : 420 (pm == PM_METHOD_PROFILE) ? "profile" : "dpm"); 421} 422 423static ssize_t radeon_set_pm_method(struct device *dev, 424 struct device_attribute *attr, 425 const char *buf, 426 size_t count) 427{ 428 struct drm_device *ddev = dev_get_drvdata(dev); 429 struct radeon_device *rdev = ddev->dev_private; 430 431 /* Can't set method when the card is off */ 432 if ((rdev->flags & RADEON_IS_PX) && 433 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 434 count = -EINVAL; 435 goto fail; 436 } 437 438 /* we don't support the legacy modes with dpm */ 439 if (rdev->pm.pm_method == PM_METHOD_DPM) { 440 count = -EINVAL; 441 goto fail; 442 } 443 444 if (strncmp("dynpm", buf, strlen("dynpm")) == 0) { 445 mutex_lock(&rdev->pm.mutex); 446 rdev->pm.pm_method = PM_METHOD_DYNPM; 447 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 448 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 449 mutex_unlock(&rdev->pm.mutex); 450 } else if (strncmp("profile", buf, strlen("profile")) == 0) { 451 mutex_lock(&rdev->pm.mutex); 452 /* disable dynpm */ 453 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 454 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 455 rdev->pm.pm_method = PM_METHOD_PROFILE; 456 mutex_unlock(&rdev->pm.mutex); 457 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 458 } else { 459 count = -EINVAL; 460 goto fail; 461 } 462 radeon_pm_compute_clocks(rdev); 463fail: 464 return count; 465} 466 467static ssize_t radeon_get_dpm_state(struct device *dev, 468 struct device_attribute *attr, 469 char *buf) 470{ 471 struct drm_device *ddev = dev_get_drvdata(dev); 472 struct radeon_device *rdev = ddev->dev_private; 473 enum radeon_pm_state_type pm = rdev->pm.dpm.user_state; 474 475 return snprintf(buf, PAGE_SIZE, "%s\n", 476 (pm == POWER_STATE_TYPE_BATTERY) ? "battery" : 477 (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance"); 478} 479 480static ssize_t radeon_set_dpm_state(struct device *dev, 481 struct device_attribute *attr, 482 const char *buf, 483 size_t count) 484{ 485 struct drm_device *ddev = dev_get_drvdata(dev); 486 struct radeon_device *rdev = ddev->dev_private; 487 488 mutex_lock(&rdev->pm.mutex); 489 if (strncmp("battery", buf, strlen("battery")) == 0) 490 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY; 491 else if (strncmp("balanced", buf, strlen("balanced")) == 0) 492 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 493 else if (strncmp("performance", buf, strlen("performance")) == 0) 494 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE; 495 else { 496 mutex_unlock(&rdev->pm.mutex); 497 count = -EINVAL; 498 goto fail; 499 } 500 mutex_unlock(&rdev->pm.mutex); 501 502 /* Can't set dpm state when the card is off */ 503 if (!(rdev->flags & RADEON_IS_PX) || 504 (ddev->switch_power_state == DRM_SWITCH_POWER_ON)) 505 radeon_pm_compute_clocks(rdev); 506 507fail: 508 return count; 509} 510 511static ssize_t radeon_get_dpm_forced_performance_level(struct device *dev, 512 struct device_attribute *attr, 513 char *buf) 514{ 515 struct drm_device *ddev = dev_get_drvdata(dev); 516 struct radeon_device *rdev = ddev->dev_private; 517 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 518 519 if ((rdev->flags & RADEON_IS_PX) && 520 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 521 return snprintf(buf, PAGE_SIZE, "off\n"); 522 523 return snprintf(buf, PAGE_SIZE, "%s\n", 524 (level == RADEON_DPM_FORCED_LEVEL_AUTO) ? "auto" : 525 (level == RADEON_DPM_FORCED_LEVEL_LOW) ? "low" : "high"); 526} 527 528static ssize_t radeon_set_dpm_forced_performance_level(struct device *dev, 529 struct device_attribute *attr, 530 const char *buf, 531 size_t count) 532{ 533 struct drm_device *ddev = dev_get_drvdata(dev); 534 struct radeon_device *rdev = ddev->dev_private; 535 enum radeon_dpm_forced_level level; 536 int ret = 0; 537 538 /* Can't force performance level when the card is off */ 539 if ((rdev->flags & RADEON_IS_PX) && 540 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 541 return -EINVAL; 542 543 mutex_lock(&rdev->pm.mutex); 544 if (strncmp("low", buf, strlen("low")) == 0) { 545 level = RADEON_DPM_FORCED_LEVEL_LOW; 546 } else if (strncmp("high", buf, strlen("high")) == 0) { 547 level = RADEON_DPM_FORCED_LEVEL_HIGH; 548 } else if (strncmp("auto", buf, strlen("auto")) == 0) { 549 level = RADEON_DPM_FORCED_LEVEL_AUTO; 550 } else { 551 count = -EINVAL; 552 goto fail; 553 } 554 if (rdev->asic->dpm.force_performance_level) { 555 if (rdev->pm.dpm.thermal_active) { 556 count = -EINVAL; 557 goto fail; 558 } 559 ret = radeon_dpm_force_performance_level(rdev, level); 560 if (ret) 561 count = -EINVAL; 562 } 563fail: 564 mutex_unlock(&rdev->pm.mutex); 565 566 return count; 567} 568 569static ssize_t radeon_hwmon_get_pwm1_enable(struct device *dev, 570 struct device_attribute *attr, 571 char *buf) 572{ 573 struct radeon_device *rdev = dev_get_drvdata(dev); 574 u32 pwm_mode = 0; 575 576 if (rdev->asic->dpm.fan_ctrl_get_mode) 577 pwm_mode = rdev->asic->dpm.fan_ctrl_get_mode(rdev); 578 579 /* never 0 (full-speed), fuse or smc-controlled always */ 580 return sprintf(buf, "%i\n", pwm_mode == FDO_PWM_MODE_STATIC ? 1 : 2); 581} 582 583static ssize_t radeon_hwmon_set_pwm1_enable(struct device *dev, 584 struct device_attribute *attr, 585 const char *buf, 586 size_t count) 587{ 588 struct radeon_device *rdev = dev_get_drvdata(dev); 589 int err; 590 int value; 591 592 if(!rdev->asic->dpm.fan_ctrl_set_mode) 593 return -EINVAL; 594 595 err = kstrtoint(buf, 10, &value); 596 if (err) 597 return err; 598 599 switch (value) { 600 case 1: /* manual, percent-based */ 601 rdev->asic->dpm.fan_ctrl_set_mode(rdev, FDO_PWM_MODE_STATIC); 602 break; 603 default: /* disable */ 604 rdev->asic->dpm.fan_ctrl_set_mode(rdev, 0); 605 break; 606 } 607 608 return count; 609} 610 611static ssize_t radeon_hwmon_get_pwm1_min(struct device *dev, 612 struct device_attribute *attr, 613 char *buf) 614{ 615 return sprintf(buf, "%i\n", 0); 616} 617 618static ssize_t radeon_hwmon_get_pwm1_max(struct device *dev, 619 struct device_attribute *attr, 620 char *buf) 621{ 622 return sprintf(buf, "%i\n", 255); 623} 624 625static ssize_t radeon_hwmon_set_pwm1(struct device *dev, 626 struct device_attribute *attr, 627 const char *buf, size_t count) 628{ 629 struct radeon_device *rdev = dev_get_drvdata(dev); 630 int err; 631 u32 value; 632 633 err = kstrtou32(buf, 10, &value); 634 if (err) 635 return err; 636 637 value = (value * 100) / 255; 638 639 err = rdev->asic->dpm.set_fan_speed_percent(rdev, value); 640 if (err) 641 return err; 642 643 return count; 644} 645 646static ssize_t radeon_hwmon_get_pwm1(struct device *dev, 647 struct device_attribute *attr, 648 char *buf) 649{ 650 struct radeon_device *rdev = dev_get_drvdata(dev); 651 int err; 652 u32 speed; 653 654 err = rdev->asic->dpm.get_fan_speed_percent(rdev, &speed); 655 if (err) 656 return err; 657 658 speed = (speed * 255) / 100; 659 660 return sprintf(buf, "%i\n", speed); 661} 662 663static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile); 664static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method); 665static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state); 666static DEVICE_ATTR(power_dpm_force_performance_level, S_IRUGO | S_IWUSR, 667 radeon_get_dpm_forced_performance_level, 668 radeon_set_dpm_forced_performance_level); 669 670static ssize_t radeon_hwmon_show_temp(struct device *dev, 671 struct device_attribute *attr, 672 char *buf) 673{ 674 struct radeon_device *rdev = dev_get_drvdata(dev); 675 struct drm_device *ddev = rdev->ddev; 676 int temp; 677 678 /* Can't get temperature when the card is off */ 679 if ((rdev->flags & RADEON_IS_PX) && 680 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 681 return -EINVAL; 682 683 if (rdev->asic->pm.get_temperature) 684 temp = radeon_get_temperature(rdev); 685 else 686 temp = 0; 687 688 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 689} 690 691static ssize_t radeon_hwmon_show_temp_thresh(struct device *dev, 692 struct device_attribute *attr, 693 char *buf) 694{ 695 struct radeon_device *rdev = dev_get_drvdata(dev); 696 int hyst = to_sensor_dev_attr(attr)->index; 697 int temp; 698 699 if (hyst) 700 temp = rdev->pm.dpm.thermal.min_temp; 701 else 702 temp = rdev->pm.dpm.thermal.max_temp; 703 704 return snprintf(buf, PAGE_SIZE, "%d\n", temp); 705} 706 707static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0); 708static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 0); 709static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, radeon_hwmon_show_temp_thresh, NULL, 1); 710static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1, radeon_hwmon_set_pwm1, 0); 711static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, radeon_hwmon_get_pwm1_enable, radeon_hwmon_set_pwm1_enable, 0); 712static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, radeon_hwmon_get_pwm1_min, NULL, 0); 713static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, radeon_hwmon_get_pwm1_max, NULL, 0); 714 715static ssize_t radeon_hwmon_show_sclk(struct device *dev, 716 struct device_attribute *attr, char *buf) 717{ 718 struct radeon_device *rdev = dev_get_drvdata(dev); 719 struct drm_device *ddev = rdev->ddev; 720 u32 sclk = 0; 721 722 /* Can't get clock frequency when the card is off */ 723 if ((rdev->flags & RADEON_IS_PX) && 724 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) 725 return -EINVAL; 726 727 if (rdev->asic->dpm.get_current_sclk) 728 sclk = radeon_dpm_get_current_sclk(rdev); 729 730 /* Value returned by dpm is in 10 KHz units, need to convert it into Hz 731 for hwmon */ 732 sclk *= 10000; 733 734 return snprintf(buf, PAGE_SIZE, "%u\n", sclk); 735} 736 737static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, radeon_hwmon_show_sclk, NULL, 738 0); 739 740 741static struct attribute *hwmon_attributes[] = { 742 &sensor_dev_attr_temp1_input.dev_attr.attr, 743 &sensor_dev_attr_temp1_crit.dev_attr.attr, 744 &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr, 745 &sensor_dev_attr_pwm1.dev_attr.attr, 746 &sensor_dev_attr_pwm1_enable.dev_attr.attr, 747 &sensor_dev_attr_pwm1_min.dev_attr.attr, 748 &sensor_dev_attr_pwm1_max.dev_attr.attr, 749 &sensor_dev_attr_freq1_input.dev_attr.attr, 750 NULL 751}; 752 753static umode_t hwmon_attributes_visible(struct kobject *kobj, 754 struct attribute *attr, int index) 755{ 756 struct device *dev = kobj_to_dev(kobj); 757 struct radeon_device *rdev = dev_get_drvdata(dev); 758 umode_t effective_mode = attr->mode; 759 760 /* Skip attributes if DPM is not enabled */ 761 if (rdev->pm.pm_method != PM_METHOD_DPM && 762 (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr || 763 attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr || 764 attr == &sensor_dev_attr_pwm1.dev_attr.attr || 765 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 766 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 767 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr || 768 attr == &sensor_dev_attr_freq1_input.dev_attr.attr)) 769 return 0; 770 771 /* Skip fan attributes if fan is not present */ 772 if (rdev->pm.no_fan && 773 (attr == &sensor_dev_attr_pwm1.dev_attr.attr || 774 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr || 775 attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 776 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 777 return 0; 778 779 /* mask fan attributes if we have no bindings for this asic to expose */ 780 if ((!rdev->asic->dpm.get_fan_speed_percent && 781 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */ 782 (!rdev->asic->dpm.fan_ctrl_get_mode && 783 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */ 784 effective_mode &= ~S_IRUGO; 785 786 if ((!rdev->asic->dpm.set_fan_speed_percent && 787 attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */ 788 (!rdev->asic->dpm.fan_ctrl_set_mode && 789 attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */ 790 effective_mode &= ~S_IWUSR; 791 792 /* hide max/min values if we can't both query and manage the fan */ 793 if ((!rdev->asic->dpm.set_fan_speed_percent && 794 !rdev->asic->dpm.get_fan_speed_percent) && 795 (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr || 796 attr == &sensor_dev_attr_pwm1_min.dev_attr.attr)) 797 return 0; 798 799 return effective_mode; 800} 801 802static const struct attribute_group hwmon_attrgroup = { 803 .attrs = hwmon_attributes, 804 .is_visible = hwmon_attributes_visible, 805}; 806 807static const struct attribute_group *hwmon_groups[] = { 808 &hwmon_attrgroup, 809 NULL 810}; 811 812static int radeon_hwmon_init(struct radeon_device *rdev) 813{ 814 int err = 0; 815 816 switch (rdev->pm.int_thermal_type) { 817 case THERMAL_TYPE_RV6XX: 818 case THERMAL_TYPE_RV770: 819 case THERMAL_TYPE_EVERGREEN: 820 case THERMAL_TYPE_NI: 821 case THERMAL_TYPE_SUMO: 822 case THERMAL_TYPE_SI: 823 case THERMAL_TYPE_CI: 824 case THERMAL_TYPE_KV: 825 if (rdev->asic->pm.get_temperature == NULL) 826 return err; 827 rdev->pm.int_hwmon_dev = hwmon_device_register_with_groups(rdev->dev, 828 "radeon", rdev, 829 hwmon_groups); 830 if (IS_ERR(rdev->pm.int_hwmon_dev)) { 831 err = PTR_ERR(rdev->pm.int_hwmon_dev); 832 dev_err(rdev->dev, 833 "Unable to register hwmon device: %d\n", err); 834 } 835 break; 836 default: 837 break; 838 } 839 840 return err; 841} 842 843static void radeon_hwmon_fini(struct radeon_device *rdev) 844{ 845 if (rdev->pm.int_hwmon_dev) 846 hwmon_device_unregister(rdev->pm.int_hwmon_dev); 847} 848 849static void radeon_dpm_thermal_work_handler(struct work_struct *work) 850{ 851 struct radeon_device *rdev = 852 container_of(work, struct radeon_device, 853 pm.dpm.thermal.work); 854 /* switch to the thermal state */ 855 enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL; 856 857 if (!rdev->pm.dpm_enabled) 858 return; 859 860 if (rdev->asic->pm.get_temperature) { 861 int temp = radeon_get_temperature(rdev); 862 863 if (temp < rdev->pm.dpm.thermal.min_temp) 864 /* switch back the user state */ 865 dpm_state = rdev->pm.dpm.user_state; 866 } else { 867 if (rdev->pm.dpm.thermal.high_to_low) 868 /* switch back the user state */ 869 dpm_state = rdev->pm.dpm.user_state; 870 } 871 mutex_lock(&rdev->pm.mutex); 872 if (dpm_state == POWER_STATE_TYPE_INTERNAL_THERMAL) 873 rdev->pm.dpm.thermal_active = true; 874 else 875 rdev->pm.dpm.thermal_active = false; 876 rdev->pm.dpm.state = dpm_state; 877 mutex_unlock(&rdev->pm.mutex); 878 879 radeon_pm_compute_clocks(rdev); 880} 881 882static bool radeon_dpm_single_display(struct radeon_device *rdev) 883{ 884 bool single_display = (rdev->pm.dpm.new_active_crtc_count < 2) ? 885 true : false; 886 887 /* check if the vblank period is too short to adjust the mclk */ 888 if (single_display && rdev->asic->dpm.vblank_too_short) { 889 if (radeon_dpm_vblank_too_short(rdev)) 890 single_display = false; 891 } 892 893 /* 120hz tends to be problematic even if they are under the 894 * vblank limit. 895 */ 896 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120)) 897 single_display = false; 898 899 return single_display; 900} 901 902static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev, 903 enum radeon_pm_state_type dpm_state) 904{ 905 int i; 906 struct radeon_ps *ps; 907 u32 ui_class; 908 bool single_display = radeon_dpm_single_display(rdev); 909 910 /* certain older asics have a separare 3D performance state, 911 * so try that first if the user selected performance 912 */ 913 if (dpm_state == POWER_STATE_TYPE_PERFORMANCE) 914 dpm_state = POWER_STATE_TYPE_INTERNAL_3DPERF; 915 /* balanced states don't exist at the moment */ 916 if (dpm_state == POWER_STATE_TYPE_BALANCED) 917 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 918 919restart_search: 920 /* Pick the best power state based on current conditions */ 921 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 922 ps = &rdev->pm.dpm.ps[i]; 923 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK; 924 switch (dpm_state) { 925 /* user states */ 926 case POWER_STATE_TYPE_BATTERY: 927 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) { 928 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 929 if (single_display) 930 return ps; 931 } else 932 return ps; 933 } 934 break; 935 case POWER_STATE_TYPE_BALANCED: 936 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) { 937 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 938 if (single_display) 939 return ps; 940 } else 941 return ps; 942 } 943 break; 944 case POWER_STATE_TYPE_PERFORMANCE: 945 if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) { 946 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) { 947 if (single_display) 948 return ps; 949 } else 950 return ps; 951 } 952 break; 953 /* internal states */ 954 case POWER_STATE_TYPE_INTERNAL_UVD: 955 if (rdev->pm.dpm.uvd_ps) 956 return rdev->pm.dpm.uvd_ps; 957 else 958 break; 959 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 960 if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) 961 return ps; 962 break; 963 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 964 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE) 965 return ps; 966 break; 967 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 968 if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE) 969 return ps; 970 break; 971 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 972 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC) 973 return ps; 974 break; 975 case POWER_STATE_TYPE_INTERNAL_BOOT: 976 return rdev->pm.dpm.boot_ps; 977 case POWER_STATE_TYPE_INTERNAL_THERMAL: 978 if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL) 979 return ps; 980 break; 981 case POWER_STATE_TYPE_INTERNAL_ACPI: 982 if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) 983 return ps; 984 break; 985 case POWER_STATE_TYPE_INTERNAL_ULV: 986 if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) 987 return ps; 988 break; 989 case POWER_STATE_TYPE_INTERNAL_3DPERF: 990 if (ps->class & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE) 991 return ps; 992 break; 993 default: 994 break; 995 } 996 } 997 /* use a fallback state if we didn't match */ 998 switch (dpm_state) { 999 case POWER_STATE_TYPE_INTERNAL_UVD_SD: 1000 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1001 goto restart_search; 1002 case POWER_STATE_TYPE_INTERNAL_UVD_HD: 1003 case POWER_STATE_TYPE_INTERNAL_UVD_HD2: 1004 case POWER_STATE_TYPE_INTERNAL_UVD_MVC: 1005 if (rdev->pm.dpm.uvd_ps) { 1006 return rdev->pm.dpm.uvd_ps; 1007 } else { 1008 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1009 goto restart_search; 1010 } 1011 case POWER_STATE_TYPE_INTERNAL_THERMAL: 1012 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI; 1013 goto restart_search; 1014 case POWER_STATE_TYPE_INTERNAL_ACPI: 1015 dpm_state = POWER_STATE_TYPE_BATTERY; 1016 goto restart_search; 1017 case POWER_STATE_TYPE_BATTERY: 1018 case POWER_STATE_TYPE_BALANCED: 1019 case POWER_STATE_TYPE_INTERNAL_3DPERF: 1020 dpm_state = POWER_STATE_TYPE_PERFORMANCE; 1021 goto restart_search; 1022 default: 1023 break; 1024 } 1025 1026 return NULL; 1027} 1028 1029static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev) 1030{ 1031 int i; 1032 struct radeon_ps *ps; 1033 enum radeon_pm_state_type dpm_state; 1034 int ret; 1035 bool single_display = radeon_dpm_single_display(rdev); 1036 1037 /* if dpm init failed */ 1038 if (!rdev->pm.dpm_enabled) 1039 return; 1040 1041 if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) { 1042 /* add other state override checks here */ 1043 if ((!rdev->pm.dpm.thermal_active) && 1044 (!rdev->pm.dpm.uvd_active)) 1045 rdev->pm.dpm.state = rdev->pm.dpm.user_state; 1046 } 1047 dpm_state = rdev->pm.dpm.state; 1048 1049 ps = radeon_dpm_pick_power_state(rdev, dpm_state); 1050 if (ps) 1051 rdev->pm.dpm.requested_ps = ps; 1052 else 1053 return; 1054 1055 /* no need to reprogram if nothing changed unless we are on BTC+ */ 1056 if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) { 1057 /* vce just modifies an existing state so force a change */ 1058 if (ps->vce_active != rdev->pm.dpm.vce_active) 1059 goto force; 1060 /* user has made a display change (such as timing) */ 1061 if (rdev->pm.dpm.single_display != single_display) 1062 goto force; 1063 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) { 1064 /* for pre-BTC and APUs if the num crtcs changed but state is the same, 1065 * all we need to do is update the display configuration. 1066 */ 1067 if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) { 1068 /* update display watermarks based on new power state */ 1069 radeon_bandwidth_update(rdev); 1070 /* update displays */ 1071 radeon_dpm_display_configuration_changed(rdev); 1072 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1073 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1074 } 1075 return; 1076 } else { 1077 /* for BTC+ if the num crtcs hasn't changed and state is the same, 1078 * nothing to do, if the num crtcs is > 1 and state is the same, 1079 * update display configuration. 1080 */ 1081 if (rdev->pm.dpm.new_active_crtcs == 1082 rdev->pm.dpm.current_active_crtcs) { 1083 return; 1084 } else { 1085 if ((rdev->pm.dpm.current_active_crtc_count > 1) && 1086 (rdev->pm.dpm.new_active_crtc_count > 1)) { 1087 /* update display watermarks based on new power state */ 1088 radeon_bandwidth_update(rdev); 1089 /* update displays */ 1090 radeon_dpm_display_configuration_changed(rdev); 1091 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1092 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1093 return; 1094 } 1095 } 1096 } 1097 } 1098 1099force: 1100 if (radeon_dpm == 1) { 1101 printk("switching from power state:\n"); 1102 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps); 1103 printk("switching to power state:\n"); 1104 radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps); 1105 } 1106 1107 down_write(&rdev->pm.mclk_lock); 1108 mutex_lock(&rdev->ring_lock); 1109 1110 /* update whether vce is active */ 1111 ps->vce_active = rdev->pm.dpm.vce_active; 1112 1113 ret = radeon_dpm_pre_set_power_state(rdev); 1114 if (ret) 1115 goto done; 1116 1117 /* update display watermarks based on new power state */ 1118 radeon_bandwidth_update(rdev); 1119 /* update displays */ 1120 radeon_dpm_display_configuration_changed(rdev); 1121 1122 /* wait for the rings to drain */ 1123 for (i = 0; i < RADEON_NUM_RINGS; i++) { 1124 struct radeon_ring *ring = &rdev->ring[i]; 1125 if (ring->ready) 1126 radeon_fence_wait_empty(rdev, i); 1127 } 1128 1129 /* program the new power state */ 1130 radeon_dpm_set_power_state(rdev); 1131 1132 /* update current power state */ 1133 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps; 1134 1135 radeon_dpm_post_set_power_state(rdev); 1136 1137 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs; 1138 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count; 1139 rdev->pm.dpm.single_display = single_display; 1140 1141 if (rdev->asic->dpm.force_performance_level) { 1142 if (rdev->pm.dpm.thermal_active) { 1143 enum radeon_dpm_forced_level level = rdev->pm.dpm.forced_level; 1144 /* force low perf level for thermal */ 1145 radeon_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_LOW); 1146 /* save the user's level */ 1147 rdev->pm.dpm.forced_level = level; 1148 } else { 1149 /* otherwise, user selected level */ 1150 radeon_dpm_force_performance_level(rdev, rdev->pm.dpm.forced_level); 1151 } 1152 } 1153 1154done: 1155 mutex_unlock(&rdev->ring_lock); 1156 up_write(&rdev->pm.mclk_lock); 1157} 1158 1159void radeon_dpm_enable_uvd(struct radeon_device *rdev, bool enable) 1160{ 1161 enum radeon_pm_state_type dpm_state; 1162 1163 if (rdev->asic->dpm.powergate_uvd) { 1164 mutex_lock(&rdev->pm.mutex); 1165 /* don't powergate anything if we 1166 have active but pause streams */ 1167 enable |= rdev->pm.dpm.sd > 0; 1168 enable |= rdev->pm.dpm.hd > 0; 1169 /* enable/disable UVD */ 1170 radeon_dpm_powergate_uvd(rdev, !enable); 1171 mutex_unlock(&rdev->pm.mutex); 1172 } else { 1173 if (enable) { 1174 mutex_lock(&rdev->pm.mutex); 1175 rdev->pm.dpm.uvd_active = true; 1176 /* disable this for now */ 1177#if 0 1178 if ((rdev->pm.dpm.sd == 1) && (rdev->pm.dpm.hd == 0)) 1179 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_SD; 1180 else if ((rdev->pm.dpm.sd == 2) && (rdev->pm.dpm.hd == 0)) 1181 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1182 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 1)) 1183 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD; 1184 else if ((rdev->pm.dpm.sd == 0) && (rdev->pm.dpm.hd == 2)) 1185 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD_HD2; 1186 else 1187#endif 1188 dpm_state = POWER_STATE_TYPE_INTERNAL_UVD; 1189 rdev->pm.dpm.state = dpm_state; 1190 mutex_unlock(&rdev->pm.mutex); 1191 } else { 1192 mutex_lock(&rdev->pm.mutex); 1193 rdev->pm.dpm.uvd_active = false; 1194 mutex_unlock(&rdev->pm.mutex); 1195 } 1196 1197 radeon_pm_compute_clocks(rdev); 1198 } 1199} 1200 1201void radeon_dpm_enable_vce(struct radeon_device *rdev, bool enable) 1202{ 1203 if (enable) { 1204 mutex_lock(&rdev->pm.mutex); 1205 rdev->pm.dpm.vce_active = true; 1206 /* XXX select vce level based on ring/task */ 1207 rdev->pm.dpm.vce_level = RADEON_VCE_LEVEL_AC_ALL; 1208 mutex_unlock(&rdev->pm.mutex); 1209 } else { 1210 mutex_lock(&rdev->pm.mutex); 1211 rdev->pm.dpm.vce_active = false; 1212 mutex_unlock(&rdev->pm.mutex); 1213 } 1214 1215 radeon_pm_compute_clocks(rdev); 1216} 1217 1218static void radeon_pm_suspend_old(struct radeon_device *rdev) 1219{ 1220 mutex_lock(&rdev->pm.mutex); 1221 if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1222 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) 1223 rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED; 1224 } 1225 mutex_unlock(&rdev->pm.mutex); 1226 1227 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1228} 1229 1230static void radeon_pm_suspend_dpm(struct radeon_device *rdev) 1231{ 1232 mutex_lock(&rdev->pm.mutex); 1233 /* disable dpm */ 1234 radeon_dpm_disable(rdev); 1235 /* reset the power state */ 1236 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1237 rdev->pm.dpm_enabled = false; 1238 mutex_unlock(&rdev->pm.mutex); 1239} 1240 1241void radeon_pm_suspend(struct radeon_device *rdev) 1242{ 1243 if (rdev->pm.pm_method == PM_METHOD_DPM) 1244 radeon_pm_suspend_dpm(rdev); 1245 else 1246 radeon_pm_suspend_old(rdev); 1247} 1248 1249static void radeon_pm_resume_old(struct radeon_device *rdev) 1250{ 1251 /* set up the default clocks if the MC ucode is loaded */ 1252 if ((rdev->family >= CHIP_BARTS) && 1253 (rdev->family <= CHIP_CAYMAN) && 1254 rdev->mc_fw) { 1255 if (rdev->pm.default_vddc) 1256 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1257 SET_VOLTAGE_TYPE_ASIC_VDDC); 1258 if (rdev->pm.default_vddci) 1259 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1260 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1261 if (rdev->pm.default_sclk) 1262 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1263 if (rdev->pm.default_mclk) 1264 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1265 } 1266 /* asic init will reset the default power state */ 1267 mutex_lock(&rdev->pm.mutex); 1268 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 1269 rdev->pm.current_clock_mode_index = 0; 1270 rdev->pm.current_sclk = rdev->pm.default_sclk; 1271 rdev->pm.current_mclk = rdev->pm.default_mclk; 1272 if (rdev->pm.power_state) { 1273 rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage; 1274 rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci; 1275 } 1276 if (rdev->pm.pm_method == PM_METHOD_DYNPM 1277 && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) { 1278 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1279 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1280 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1281 } 1282 mutex_unlock(&rdev->pm.mutex); 1283 radeon_pm_compute_clocks(rdev); 1284} 1285 1286static void radeon_pm_resume_dpm(struct radeon_device *rdev) 1287{ 1288 int ret; 1289 1290 /* asic init will reset to the boot state */ 1291 mutex_lock(&rdev->pm.mutex); 1292 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1293 radeon_dpm_setup_asic(rdev); 1294 ret = radeon_dpm_enable(rdev); 1295 mutex_unlock(&rdev->pm.mutex); 1296 if (ret) 1297 goto dpm_resume_fail; 1298 rdev->pm.dpm_enabled = true; 1299 return; 1300 1301dpm_resume_fail: 1302 DRM_ERROR("radeon: dpm resume failed\n"); 1303 if ((rdev->family >= CHIP_BARTS) && 1304 (rdev->family <= CHIP_CAYMAN) && 1305 rdev->mc_fw) { 1306 if (rdev->pm.default_vddc) 1307 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1308 SET_VOLTAGE_TYPE_ASIC_VDDC); 1309 if (rdev->pm.default_vddci) 1310 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1311 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1312 if (rdev->pm.default_sclk) 1313 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1314 if (rdev->pm.default_mclk) 1315 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1316 } 1317} 1318 1319void radeon_pm_resume(struct radeon_device *rdev) 1320{ 1321 if (rdev->pm.pm_method == PM_METHOD_DPM) 1322 radeon_pm_resume_dpm(rdev); 1323 else 1324 radeon_pm_resume_old(rdev); 1325} 1326 1327static int radeon_pm_init_old(struct radeon_device *rdev) 1328{ 1329 int ret; 1330 1331 rdev->pm.profile = PM_PROFILE_DEFAULT; 1332 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1333 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1334 rdev->pm.dynpm_can_upclock = true; 1335 rdev->pm.dynpm_can_downclock = true; 1336 rdev->pm.default_sclk = rdev->clock.default_sclk; 1337 rdev->pm.default_mclk = rdev->clock.default_mclk; 1338 rdev->pm.current_sclk = rdev->clock.default_sclk; 1339 rdev->pm.current_mclk = rdev->clock.default_mclk; 1340 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1341 1342 if (rdev->bios) { 1343 if (rdev->is_atom_bios) 1344 radeon_atombios_get_power_modes(rdev); 1345 else 1346 radeon_combios_get_power_modes(rdev); 1347 radeon_pm_print_states(rdev); 1348 radeon_pm_init_profile(rdev); 1349 /* set up the default clocks if the MC ucode is loaded */ 1350 if ((rdev->family >= CHIP_BARTS) && 1351 (rdev->family <= CHIP_CAYMAN) && 1352 rdev->mc_fw) { 1353 if (rdev->pm.default_vddc) 1354 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1355 SET_VOLTAGE_TYPE_ASIC_VDDC); 1356 if (rdev->pm.default_vddci) 1357 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1358 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1359 if (rdev->pm.default_sclk) 1360 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1361 if (rdev->pm.default_mclk) 1362 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1363 } 1364 } 1365 1366 /* set up the internal thermal sensor if applicable */ 1367 ret = radeon_hwmon_init(rdev); 1368 if (ret) 1369 return ret; 1370 1371 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler); 1372 1373 if (rdev->pm.num_power_states > 1) { 1374 if (radeon_debugfs_pm_init(rdev)) { 1375 DRM_ERROR("Failed to register debugfs file for PM!\n"); 1376 } 1377 1378 DRM_INFO("radeon: power management initialized\n"); 1379 } 1380 1381 return 0; 1382} 1383 1384static void radeon_dpm_print_power_states(struct radeon_device *rdev) 1385{ 1386 int i; 1387 1388 for (i = 0; i < rdev->pm.dpm.num_ps; i++) { 1389 printk("== power state %d ==\n", i); 1390 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]); 1391 } 1392} 1393 1394static int radeon_pm_init_dpm(struct radeon_device *rdev) 1395{ 1396 int ret; 1397 1398 /* default to balanced state */ 1399 rdev->pm.dpm.state = POWER_STATE_TYPE_BALANCED; 1400 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED; 1401 rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO; 1402 rdev->pm.default_sclk = rdev->clock.default_sclk; 1403 rdev->pm.default_mclk = rdev->clock.default_mclk; 1404 rdev->pm.current_sclk = rdev->clock.default_sclk; 1405 rdev->pm.current_mclk = rdev->clock.default_mclk; 1406 rdev->pm.int_thermal_type = THERMAL_TYPE_NONE; 1407 1408 if (rdev->bios && rdev->is_atom_bios) 1409 radeon_atombios_get_power_modes(rdev); 1410 else 1411 return -EINVAL; 1412 1413 /* set up the internal thermal sensor if applicable */ 1414 ret = radeon_hwmon_init(rdev); 1415 if (ret) 1416 return ret; 1417 1418 INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler); 1419 mutex_lock(&rdev->pm.mutex); 1420 radeon_dpm_init(rdev); 1421 rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps; 1422 if (radeon_dpm == 1) 1423 radeon_dpm_print_power_states(rdev); 1424 radeon_dpm_setup_asic(rdev); 1425 ret = radeon_dpm_enable(rdev); 1426 mutex_unlock(&rdev->pm.mutex); 1427 if (ret) 1428 goto dpm_failed; 1429 rdev->pm.dpm_enabled = true; 1430 1431 if (radeon_debugfs_pm_init(rdev)) { 1432 DRM_ERROR("Failed to register debugfs file for dpm!\n"); 1433 } 1434 1435 DRM_INFO("radeon: dpm initialized\n"); 1436 1437 return 0; 1438 1439dpm_failed: 1440 rdev->pm.dpm_enabled = false; 1441 if ((rdev->family >= CHIP_BARTS) && 1442 (rdev->family <= CHIP_CAYMAN) && 1443 rdev->mc_fw) { 1444 if (rdev->pm.default_vddc) 1445 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc, 1446 SET_VOLTAGE_TYPE_ASIC_VDDC); 1447 if (rdev->pm.default_vddci) 1448 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci, 1449 SET_VOLTAGE_TYPE_ASIC_VDDCI); 1450 if (rdev->pm.default_sclk) 1451 radeon_set_engine_clock(rdev, rdev->pm.default_sclk); 1452 if (rdev->pm.default_mclk) 1453 radeon_set_memory_clock(rdev, rdev->pm.default_mclk); 1454 } 1455 DRM_ERROR("radeon: dpm initialization failed\n"); 1456 return ret; 1457} 1458 1459struct radeon_dpm_quirk { 1460 u32 chip_vendor; 1461 u32 chip_device; 1462 u32 subsys_vendor; 1463 u32 subsys_device; 1464}; 1465 1466/* cards with dpm stability problems */ 1467static struct radeon_dpm_quirk radeon_dpm_quirk_list[] = { 1468 /* TURKS - https://bugs.launchpad.net/ubuntu/+source/linux/+bug/1386534 */ 1469 { PCI_VENDOR_ID_ATI, 0x6759, 0x1682, 0x3195 }, 1470 /* TURKS - https://bugzilla.kernel.org/show_bug.cgi?id=83731 */ 1471 { PCI_VENDOR_ID_ATI, 0x6840, 0x1179, 0xfb81 }, 1472 { 0, 0, 0, 0 }, 1473}; 1474 1475int radeon_pm_init(struct radeon_device *rdev) 1476{ 1477 struct radeon_dpm_quirk *p = radeon_dpm_quirk_list; 1478 bool disable_dpm = false; 1479 1480 /* Apply dpm quirks */ 1481 while (p && p->chip_device != 0) { 1482 if (rdev->pdev->vendor == p->chip_vendor && 1483 rdev->pdev->device == p->chip_device && 1484 rdev->pdev->subsystem_vendor == p->subsys_vendor && 1485 rdev->pdev->subsystem_device == p->subsys_device) { 1486 disable_dpm = true; 1487 break; 1488 } 1489 ++p; 1490 } 1491 1492 /* enable dpm on rv6xx+ */ 1493 switch (rdev->family) { 1494 case CHIP_RV610: 1495 case CHIP_RV630: 1496 case CHIP_RV620: 1497 case CHIP_RV635: 1498 case CHIP_RV670: 1499 case CHIP_RS780: 1500 case CHIP_RS880: 1501 case CHIP_RV770: 1502 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1503 if (!rdev->rlc_fw) 1504 rdev->pm.pm_method = PM_METHOD_PROFILE; 1505 else if ((rdev->family >= CHIP_RV770) && 1506 (!(rdev->flags & RADEON_IS_IGP)) && 1507 (!rdev->smc_fw)) 1508 rdev->pm.pm_method = PM_METHOD_PROFILE; 1509 else if (radeon_dpm == 1) 1510 rdev->pm.pm_method = PM_METHOD_DPM; 1511 else 1512 rdev->pm.pm_method = PM_METHOD_PROFILE; 1513 break; 1514 case CHIP_RV730: 1515 case CHIP_RV710: 1516 case CHIP_RV740: 1517 case CHIP_CEDAR: 1518 case CHIP_REDWOOD: 1519 case CHIP_JUNIPER: 1520 case CHIP_CYPRESS: 1521 case CHIP_HEMLOCK: 1522 case CHIP_PALM: 1523 case CHIP_SUMO: 1524 case CHIP_SUMO2: 1525 case CHIP_BARTS: 1526 case CHIP_TURKS: 1527 case CHIP_CAICOS: 1528 case CHIP_CAYMAN: 1529 case CHIP_ARUBA: 1530 case CHIP_TAHITI: 1531 case CHIP_PITCAIRN: 1532 case CHIP_VERDE: 1533 case CHIP_OLAND: 1534 case CHIP_HAINAN: 1535 case CHIP_BONAIRE: 1536 case CHIP_KABINI: 1537 case CHIP_KAVERI: 1538 case CHIP_HAWAII: 1539 case CHIP_MULLINS: 1540 /* DPM requires the RLC, RV770+ dGPU requires SMC */ 1541 if (!rdev->rlc_fw) 1542 rdev->pm.pm_method = PM_METHOD_PROFILE; 1543 else if ((rdev->family >= CHIP_RV770) && 1544 (!(rdev->flags & RADEON_IS_IGP)) && 1545 (!rdev->smc_fw)) 1546 rdev->pm.pm_method = PM_METHOD_PROFILE; 1547 else if (disable_dpm && (radeon_dpm == -1)) 1548 rdev->pm.pm_method = PM_METHOD_PROFILE; 1549 else if (radeon_dpm == 0) 1550 rdev->pm.pm_method = PM_METHOD_PROFILE; 1551 else 1552 rdev->pm.pm_method = PM_METHOD_DPM; 1553 break; 1554 default: 1555 /* default to profile method */ 1556 rdev->pm.pm_method = PM_METHOD_PROFILE; 1557 break; 1558 } 1559 1560 if (rdev->pm.pm_method == PM_METHOD_DPM) 1561 return radeon_pm_init_dpm(rdev); 1562 else 1563 return radeon_pm_init_old(rdev); 1564} 1565 1566int radeon_pm_late_init(struct radeon_device *rdev) 1567{ 1568 int ret = 0; 1569 1570 if (rdev->pm.pm_method == PM_METHOD_DPM) { 1571 if (rdev->pm.dpm_enabled) { 1572 if (!rdev->pm.sysfs_initialized) { 1573 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state); 1574 if (ret) 1575 DRM_ERROR("failed to create device file for dpm state\n"); 1576 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1577 if (ret) 1578 DRM_ERROR("failed to create device file for dpm state\n"); 1579 /* XXX: these are noops for dpm but are here for backwards compat */ 1580 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1581 if (ret) 1582 DRM_ERROR("failed to create device file for power profile\n"); 1583 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1584 if (ret) 1585 DRM_ERROR("failed to create device file for power method\n"); 1586 rdev->pm.sysfs_initialized = true; 1587 } 1588 1589 mutex_lock(&rdev->pm.mutex); 1590 ret = radeon_dpm_late_enable(rdev); 1591 mutex_unlock(&rdev->pm.mutex); 1592 if (ret) { 1593 rdev->pm.dpm_enabled = false; 1594 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n"); 1595 } else { 1596 /* set the dpm state for PX since there won't be 1597 * a modeset to call this. 1598 */ 1599 radeon_pm_compute_clocks(rdev); 1600 } 1601 } 1602 } else { 1603 if ((rdev->pm.num_power_states > 1) && 1604 (!rdev->pm.sysfs_initialized)) { 1605 /* where's the best place to put these? */ 1606 ret = device_create_file(rdev->dev, &dev_attr_power_profile); 1607 if (ret) 1608 DRM_ERROR("failed to create device file for power profile\n"); 1609 ret = device_create_file(rdev->dev, &dev_attr_power_method); 1610 if (ret) 1611 DRM_ERROR("failed to create device file for power method\n"); 1612 if (!ret) 1613 rdev->pm.sysfs_initialized = true; 1614 } 1615 } 1616 return ret; 1617} 1618 1619static void radeon_pm_fini_old(struct radeon_device *rdev) 1620{ 1621 if (rdev->pm.num_power_states > 1) { 1622 mutex_lock(&rdev->pm.mutex); 1623 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1624 rdev->pm.profile = PM_PROFILE_DEFAULT; 1625 radeon_pm_update_profile(rdev); 1626 radeon_pm_set_clocks(rdev); 1627 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1628 /* reset default clocks */ 1629 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED; 1630 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1631 radeon_pm_set_clocks(rdev); 1632 } 1633 mutex_unlock(&rdev->pm.mutex); 1634 1635 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work); 1636 1637 device_remove_file(rdev->dev, &dev_attr_power_profile); 1638 device_remove_file(rdev->dev, &dev_attr_power_method); 1639 } 1640 1641 radeon_hwmon_fini(rdev); 1642 kfree(rdev->pm.power_state); 1643} 1644 1645static void radeon_pm_fini_dpm(struct radeon_device *rdev) 1646{ 1647 if (rdev->pm.num_power_states > 1) { 1648 mutex_lock(&rdev->pm.mutex); 1649 radeon_dpm_disable(rdev); 1650 mutex_unlock(&rdev->pm.mutex); 1651 1652 device_remove_file(rdev->dev, &dev_attr_power_dpm_state); 1653 device_remove_file(rdev->dev, &dev_attr_power_dpm_force_performance_level); 1654 /* XXX backwards compat */ 1655 device_remove_file(rdev->dev, &dev_attr_power_profile); 1656 device_remove_file(rdev->dev, &dev_attr_power_method); 1657 } 1658 radeon_dpm_fini(rdev); 1659 1660 radeon_hwmon_fini(rdev); 1661 kfree(rdev->pm.power_state); 1662} 1663 1664void radeon_pm_fini(struct radeon_device *rdev) 1665{ 1666 if (rdev->pm.pm_method == PM_METHOD_DPM) 1667 radeon_pm_fini_dpm(rdev); 1668 else 1669 radeon_pm_fini_old(rdev); 1670} 1671 1672static void radeon_pm_compute_clocks_old(struct radeon_device *rdev) 1673{ 1674 struct drm_device *ddev = rdev->ddev; 1675 struct drm_crtc *crtc; 1676 struct radeon_crtc *radeon_crtc; 1677 1678 if (rdev->pm.num_power_states < 2) 1679 return; 1680 1681 mutex_lock(&rdev->pm.mutex); 1682 1683 rdev->pm.active_crtcs = 0; 1684 rdev->pm.active_crtc_count = 0; 1685 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1686 list_for_each_entry(crtc, 1687 &ddev->mode_config.crtc_list, head) { 1688 radeon_crtc = to_radeon_crtc(crtc); 1689 if (radeon_crtc->enabled) { 1690 rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id); 1691 rdev->pm.active_crtc_count++; 1692 } 1693 } 1694 } 1695 1696 if (rdev->pm.pm_method == PM_METHOD_PROFILE) { 1697 radeon_pm_update_profile(rdev); 1698 radeon_pm_set_clocks(rdev); 1699 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) { 1700 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) { 1701 if (rdev->pm.active_crtc_count > 1) { 1702 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1703 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1704 1705 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED; 1706 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT; 1707 radeon_pm_get_dynpm_state(rdev); 1708 radeon_pm_set_clocks(rdev); 1709 1710 DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n"); 1711 } 1712 } else if (rdev->pm.active_crtc_count == 1) { 1713 /* TODO: Increase clocks if needed for current mode */ 1714 1715 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) { 1716 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1717 rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK; 1718 radeon_pm_get_dynpm_state(rdev); 1719 radeon_pm_set_clocks(rdev); 1720 1721 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1722 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1723 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) { 1724 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE; 1725 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1726 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1727 DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n"); 1728 } 1729 } else { /* count == 0 */ 1730 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) { 1731 cancel_delayed_work(&rdev->pm.dynpm_idle_work); 1732 1733 rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM; 1734 rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM; 1735 radeon_pm_get_dynpm_state(rdev); 1736 radeon_pm_set_clocks(rdev); 1737 } 1738 } 1739 } 1740 } 1741 1742 mutex_unlock(&rdev->pm.mutex); 1743} 1744 1745static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev) 1746{ 1747 struct drm_device *ddev = rdev->ddev; 1748 struct drm_crtc *crtc; 1749 struct radeon_crtc *radeon_crtc; 1750 struct radeon_connector *radeon_connector; 1751 1752 if (!rdev->pm.dpm_enabled) 1753 return; 1754 1755 mutex_lock(&rdev->pm.mutex); 1756 1757 /* update active crtc counts */ 1758 rdev->pm.dpm.new_active_crtcs = 0; 1759 rdev->pm.dpm.new_active_crtc_count = 0; 1760 rdev->pm.dpm.high_pixelclock_count = 0; 1761 if (rdev->num_crtc && rdev->mode_info.mode_config_initialized) { 1762 list_for_each_entry(crtc, 1763 &ddev->mode_config.crtc_list, head) { 1764 radeon_crtc = to_radeon_crtc(crtc); 1765 if (crtc->enabled) { 1766 rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id); 1767 rdev->pm.dpm.new_active_crtc_count++; 1768 if (!radeon_crtc->connector) 1769 continue; 1770 1771 radeon_connector = to_radeon_connector(radeon_crtc->connector); 1772 if (radeon_connector->pixelclock_for_modeset > 297000) 1773 rdev->pm.dpm.high_pixelclock_count++; 1774 } 1775 } 1776 } 1777 1778 /* update battery/ac status */ 1779 if (power_supply_is_system_supplied() > 0) 1780 rdev->pm.dpm.ac_power = true; 1781 else 1782 rdev->pm.dpm.ac_power = false; 1783 1784 radeon_dpm_change_power_state_locked(rdev); 1785 1786 mutex_unlock(&rdev->pm.mutex); 1787 1788} 1789 1790void radeon_pm_compute_clocks(struct radeon_device *rdev) 1791{ 1792 if (rdev->pm.pm_method == PM_METHOD_DPM) 1793 radeon_pm_compute_clocks_dpm(rdev); 1794 else 1795 radeon_pm_compute_clocks_old(rdev); 1796} 1797 1798static bool radeon_pm_in_vbl(struct radeon_device *rdev) 1799{ 1800 int crtc, vpos, hpos, vbl_status; 1801 bool in_vbl = true; 1802 1803 /* Iterate over all active crtc's. All crtc's must be in vblank, 1804 * otherwise return in_vbl == false. 1805 */ 1806 for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) { 1807 if (rdev->pm.active_crtcs & (1 << crtc)) { 1808 vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, 1809 crtc, 1810 USE_REAL_VBLANKSTART, 1811 &vpos, &hpos, NULL, NULL, 1812 &rdev->mode_info.crtcs[crtc]->base.hwmode); 1813 if ((vbl_status & DRM_SCANOUTPOS_VALID) && 1814 !(vbl_status & DRM_SCANOUTPOS_IN_VBLANK)) 1815 in_vbl = false; 1816 } 1817 } 1818 1819 return in_vbl; 1820} 1821 1822static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish) 1823{ 1824 u32 stat_crtc = 0; 1825 bool in_vbl = radeon_pm_in_vbl(rdev); 1826 1827 if (!in_vbl) 1828 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc, 1829 finish ? "exit" : "entry"); 1830 return in_vbl; 1831} 1832 1833static void radeon_dynpm_idle_work_handler(struct work_struct *work) 1834{ 1835 struct radeon_device *rdev; 1836 int resched; 1837 rdev = container_of(work, struct radeon_device, 1838 pm.dynpm_idle_work.work); 1839 1840 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); 1841 mutex_lock(&rdev->pm.mutex); 1842 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) { 1843 int not_processed = 0; 1844 int i; 1845 1846 for (i = 0; i < RADEON_NUM_RINGS; ++i) { 1847 struct radeon_ring *ring = &rdev->ring[i]; 1848 1849 if (ring->ready) { 1850 not_processed += radeon_fence_count_emitted(rdev, i); 1851 if (not_processed >= 3) 1852 break; 1853 } 1854 } 1855 1856 if (not_processed >= 3) { /* should upclock */ 1857 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) { 1858 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1859 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1860 rdev->pm.dynpm_can_upclock) { 1861 rdev->pm.dynpm_planned_action = 1862 DYNPM_ACTION_UPCLOCK; 1863 rdev->pm.dynpm_action_timeout = jiffies + 1864 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1865 } 1866 } else if (not_processed == 0) { /* should downclock */ 1867 if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) { 1868 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 1869 } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE && 1870 rdev->pm.dynpm_can_downclock) { 1871 rdev->pm.dynpm_planned_action = 1872 DYNPM_ACTION_DOWNCLOCK; 1873 rdev->pm.dynpm_action_timeout = jiffies + 1874 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS); 1875 } 1876 } 1877 1878 /* Note, radeon_pm_set_clocks is called with static_switch set 1879 * to false since we want to wait for vbl to avoid flicker. 1880 */ 1881 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE && 1882 jiffies > rdev->pm.dynpm_action_timeout) { 1883 radeon_pm_get_dynpm_state(rdev); 1884 radeon_pm_set_clocks(rdev); 1885 } 1886 1887 schedule_delayed_work(&rdev->pm.dynpm_idle_work, 1888 msecs_to_jiffies(RADEON_IDLE_LOOP_MS)); 1889 } 1890 mutex_unlock(&rdev->pm.mutex); 1891 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); 1892} 1893 1894/* 1895 * Debugfs info 1896 */ 1897#if defined(CONFIG_DEBUG_FS) 1898 1899static int radeon_debugfs_pm_info(struct seq_file *m, void *data) 1900{ 1901 struct drm_info_node *node = (struct drm_info_node *) m->private; 1902 struct drm_device *dev = node->minor->dev; 1903 struct radeon_device *rdev = dev->dev_private; 1904 struct drm_device *ddev = rdev->ddev; 1905 1906 if ((rdev->flags & RADEON_IS_PX) && 1907 (ddev->switch_power_state != DRM_SWITCH_POWER_ON)) { 1908 seq_printf(m, "PX asic powered off\n"); 1909 } else if (rdev->pm.dpm_enabled) { 1910 mutex_lock(&rdev->pm.mutex); 1911 if (rdev->asic->dpm.debugfs_print_current_performance_level) 1912 radeon_dpm_debugfs_print_current_performance_level(rdev, m); 1913 else 1914 seq_printf(m, "Debugfs support not implemented for this asic\n"); 1915 mutex_unlock(&rdev->pm.mutex); 1916 } else { 1917 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk); 1918 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */ 1919 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP)) 1920 seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk); 1921 else 1922 seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev)); 1923 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk); 1924 if (rdev->asic->pm.get_memory_clock) 1925 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev)); 1926 if (rdev->pm.current_vddc) 1927 seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc); 1928 if (rdev->asic->pm.get_pcie_lanes) 1929 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev)); 1930 } 1931 1932 return 0; 1933} 1934 1935static struct drm_info_list radeon_pm_info_list[] = { 1936 {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL}, 1937}; 1938#endif 1939 1940static int radeon_debugfs_pm_init(struct radeon_device *rdev) 1941{ 1942#if defined(CONFIG_DEBUG_FS) 1943 return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list)); 1944#else 1945 return 0; 1946#endif 1947} 1948