18c2ecf20Sopenharmony_ci/* 28c2ecf20Sopenharmony_ci * Copyright 2008 Advanced Micro Devices, Inc. 38c2ecf20Sopenharmony_ci * Copyright 2008 Red Hat Inc. 48c2ecf20Sopenharmony_ci * Copyright 2009 Jerome Glisse. 58c2ecf20Sopenharmony_ci * 68c2ecf20Sopenharmony_ci * Permission is hereby granted, free of charge, to any person obtaining a 78c2ecf20Sopenharmony_ci * copy of this software and associated documentation files (the "Software"), 88c2ecf20Sopenharmony_ci * to deal in the Software without restriction, including without limitation 98c2ecf20Sopenharmony_ci * the rights to use, copy, modify, merge, publish, distribute, sublicense, 108c2ecf20Sopenharmony_ci * and/or sell copies of the Software, and to permit persons to whom the 118c2ecf20Sopenharmony_ci * Software is furnished to do so, subject to the following conditions: 128c2ecf20Sopenharmony_ci * 138c2ecf20Sopenharmony_ci * The above copyright notice and this permission notice shall be included in 148c2ecf20Sopenharmony_ci * all copies or substantial portions of the Software. 158c2ecf20Sopenharmony_ci * 168c2ecf20Sopenharmony_ci * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 178c2ecf20Sopenharmony_ci * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 188c2ecf20Sopenharmony_ci * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 198c2ecf20Sopenharmony_ci * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 208c2ecf20Sopenharmony_ci * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 218c2ecf20Sopenharmony_ci * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 228c2ecf20Sopenharmony_ci * OTHER DEALINGS IN THE SOFTWARE. 238c2ecf20Sopenharmony_ci * 248c2ecf20Sopenharmony_ci * Authors: Dave Airlie 258c2ecf20Sopenharmony_ci * Alex Deucher 268c2ecf20Sopenharmony_ci * Jerome Glisse 278c2ecf20Sopenharmony_ci */ 288c2ecf20Sopenharmony_ci#ifndef __RADEON_OBJECT_H__ 298c2ecf20Sopenharmony_ci#define __RADEON_OBJECT_H__ 308c2ecf20Sopenharmony_ci 318c2ecf20Sopenharmony_ci#include <drm/radeon_drm.h> 328c2ecf20Sopenharmony_ci#include "radeon.h" 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci/** 358c2ecf20Sopenharmony_ci * radeon_mem_type_to_domain - return domain corresponding to mem_type 368c2ecf20Sopenharmony_ci * @mem_type: ttm memory type 378c2ecf20Sopenharmony_ci * 388c2ecf20Sopenharmony_ci * Returns corresponding domain of the ttm mem_type 398c2ecf20Sopenharmony_ci */ 408c2ecf20Sopenharmony_cistatic inline unsigned radeon_mem_type_to_domain(u32 mem_type) 418c2ecf20Sopenharmony_ci{ 428c2ecf20Sopenharmony_ci switch (mem_type) { 438c2ecf20Sopenharmony_ci case TTM_PL_VRAM: 448c2ecf20Sopenharmony_ci return RADEON_GEM_DOMAIN_VRAM; 458c2ecf20Sopenharmony_ci case TTM_PL_TT: 468c2ecf20Sopenharmony_ci return RADEON_GEM_DOMAIN_GTT; 478c2ecf20Sopenharmony_ci case TTM_PL_SYSTEM: 488c2ecf20Sopenharmony_ci return RADEON_GEM_DOMAIN_CPU; 498c2ecf20Sopenharmony_ci default: 508c2ecf20Sopenharmony_ci break; 518c2ecf20Sopenharmony_ci } 528c2ecf20Sopenharmony_ci return 0; 538c2ecf20Sopenharmony_ci} 548c2ecf20Sopenharmony_ci 558c2ecf20Sopenharmony_ci/** 568c2ecf20Sopenharmony_ci * radeon_bo_reserve - reserve bo 578c2ecf20Sopenharmony_ci * @bo: bo structure 588c2ecf20Sopenharmony_ci * @no_intr: don't return -ERESTARTSYS on pending signal 598c2ecf20Sopenharmony_ci * 608c2ecf20Sopenharmony_ci * Returns: 618c2ecf20Sopenharmony_ci * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 628c2ecf20Sopenharmony_ci * a signal. Release all buffer reservations and return to user-space. 638c2ecf20Sopenharmony_ci */ 648c2ecf20Sopenharmony_cistatic inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr) 658c2ecf20Sopenharmony_ci{ 668c2ecf20Sopenharmony_ci int r; 678c2ecf20Sopenharmony_ci 688c2ecf20Sopenharmony_ci r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 698c2ecf20Sopenharmony_ci if (unlikely(r != 0)) { 708c2ecf20Sopenharmony_ci if (r != -ERESTARTSYS) 718c2ecf20Sopenharmony_ci dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 728c2ecf20Sopenharmony_ci return r; 738c2ecf20Sopenharmony_ci } 748c2ecf20Sopenharmony_ci return 0; 758c2ecf20Sopenharmony_ci} 768c2ecf20Sopenharmony_ci 778c2ecf20Sopenharmony_cistatic inline void radeon_bo_unreserve(struct radeon_bo *bo) 788c2ecf20Sopenharmony_ci{ 798c2ecf20Sopenharmony_ci ttm_bo_unreserve(&bo->tbo); 808c2ecf20Sopenharmony_ci} 818c2ecf20Sopenharmony_ci 828c2ecf20Sopenharmony_ci/** 838c2ecf20Sopenharmony_ci * radeon_bo_gpu_offset - return GPU offset of bo 848c2ecf20Sopenharmony_ci * @bo: radeon object for which we query the offset 858c2ecf20Sopenharmony_ci * 868c2ecf20Sopenharmony_ci * Returns current GPU offset of the object. 878c2ecf20Sopenharmony_ci * 888c2ecf20Sopenharmony_ci * Note: object should either be pinned or reserved when calling this 898c2ecf20Sopenharmony_ci * function, it might be useful to add check for this for debugging. 908c2ecf20Sopenharmony_ci */ 918c2ecf20Sopenharmony_cistatic inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo) 928c2ecf20Sopenharmony_ci{ 938c2ecf20Sopenharmony_ci struct radeon_device *rdev; 948c2ecf20Sopenharmony_ci u64 start = 0; 958c2ecf20Sopenharmony_ci 968c2ecf20Sopenharmony_ci rdev = radeon_get_rdev(bo->tbo.bdev); 978c2ecf20Sopenharmony_ci 988c2ecf20Sopenharmony_ci switch (bo->tbo.mem.mem_type) { 998c2ecf20Sopenharmony_ci case TTM_PL_TT: 1008c2ecf20Sopenharmony_ci start = rdev->mc.gtt_start; 1018c2ecf20Sopenharmony_ci break; 1028c2ecf20Sopenharmony_ci case TTM_PL_VRAM: 1038c2ecf20Sopenharmony_ci start = rdev->mc.vram_start; 1048c2ecf20Sopenharmony_ci break; 1058c2ecf20Sopenharmony_ci } 1068c2ecf20Sopenharmony_ci 1078c2ecf20Sopenharmony_ci return (bo->tbo.mem.start << PAGE_SHIFT) + start; 1088c2ecf20Sopenharmony_ci} 1098c2ecf20Sopenharmony_ci 1108c2ecf20Sopenharmony_cistatic inline unsigned long radeon_bo_size(struct radeon_bo *bo) 1118c2ecf20Sopenharmony_ci{ 1128c2ecf20Sopenharmony_ci return bo->tbo.num_pages << PAGE_SHIFT; 1138c2ecf20Sopenharmony_ci} 1148c2ecf20Sopenharmony_ci 1158c2ecf20Sopenharmony_cistatic inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo) 1168c2ecf20Sopenharmony_ci{ 1178c2ecf20Sopenharmony_ci return (bo->tbo.num_pages << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE; 1188c2ecf20Sopenharmony_ci} 1198c2ecf20Sopenharmony_ci 1208c2ecf20Sopenharmony_cistatic inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo) 1218c2ecf20Sopenharmony_ci{ 1228c2ecf20Sopenharmony_ci return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE; 1238c2ecf20Sopenharmony_ci} 1248c2ecf20Sopenharmony_ci 1258c2ecf20Sopenharmony_ci/** 1268c2ecf20Sopenharmony_ci * radeon_bo_mmap_offset - return mmap offset of bo 1278c2ecf20Sopenharmony_ci * @bo: radeon object for which we query the offset 1288c2ecf20Sopenharmony_ci * 1298c2ecf20Sopenharmony_ci * Returns mmap offset of the object. 1308c2ecf20Sopenharmony_ci */ 1318c2ecf20Sopenharmony_cistatic inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo) 1328c2ecf20Sopenharmony_ci{ 1338c2ecf20Sopenharmony_ci return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); 1348c2ecf20Sopenharmony_ci} 1358c2ecf20Sopenharmony_ci 1368c2ecf20Sopenharmony_ciextern int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, 1378c2ecf20Sopenharmony_ci bool no_wait); 1388c2ecf20Sopenharmony_ci 1398c2ecf20Sopenharmony_ciextern int radeon_bo_create(struct radeon_device *rdev, 1408c2ecf20Sopenharmony_ci unsigned long size, int byte_align, 1418c2ecf20Sopenharmony_ci bool kernel, u32 domain, u32 flags, 1428c2ecf20Sopenharmony_ci struct sg_table *sg, 1438c2ecf20Sopenharmony_ci struct dma_resv *resv, 1448c2ecf20Sopenharmony_ci struct radeon_bo **bo_ptr); 1458c2ecf20Sopenharmony_ciextern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr); 1468c2ecf20Sopenharmony_ciextern void radeon_bo_kunmap(struct radeon_bo *bo); 1478c2ecf20Sopenharmony_ciextern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo); 1488c2ecf20Sopenharmony_ciextern void radeon_bo_unref(struct radeon_bo **bo); 1498c2ecf20Sopenharmony_ciextern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr); 1508c2ecf20Sopenharmony_ciextern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, 1518c2ecf20Sopenharmony_ci u64 max_offset, u64 *gpu_addr); 1528c2ecf20Sopenharmony_ciextern int radeon_bo_unpin(struct radeon_bo *bo); 1538c2ecf20Sopenharmony_ciextern int radeon_bo_evict_vram(struct radeon_device *rdev); 1548c2ecf20Sopenharmony_ciextern void radeon_bo_force_delete(struct radeon_device *rdev); 1558c2ecf20Sopenharmony_ciextern int radeon_bo_init(struct radeon_device *rdev); 1568c2ecf20Sopenharmony_ciextern void radeon_bo_fini(struct radeon_device *rdev); 1578c2ecf20Sopenharmony_ciextern int radeon_bo_list_validate(struct radeon_device *rdev, 1588c2ecf20Sopenharmony_ci struct ww_acquire_ctx *ticket, 1598c2ecf20Sopenharmony_ci struct list_head *head, int ring); 1608c2ecf20Sopenharmony_ciextern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 1618c2ecf20Sopenharmony_ci u32 tiling_flags, u32 pitch); 1628c2ecf20Sopenharmony_ciextern void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 1638c2ecf20Sopenharmony_ci u32 *tiling_flags, u32 *pitch); 1648c2ecf20Sopenharmony_ciextern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 1658c2ecf20Sopenharmony_ci bool force_drop); 1668c2ecf20Sopenharmony_ciextern void radeon_bo_move_notify(struct ttm_buffer_object *bo, 1678c2ecf20Sopenharmony_ci bool evict, 1688c2ecf20Sopenharmony_ci struct ttm_resource *new_mem); 1698c2ecf20Sopenharmony_ciextern int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 1708c2ecf20Sopenharmony_ciextern int radeon_bo_get_surface_reg(struct radeon_bo *bo); 1718c2ecf20Sopenharmony_ciextern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 1728c2ecf20Sopenharmony_ci bool shared); 1738c2ecf20Sopenharmony_ci 1748c2ecf20Sopenharmony_ci/* 1758c2ecf20Sopenharmony_ci * sub allocation 1768c2ecf20Sopenharmony_ci */ 1778c2ecf20Sopenharmony_ci 1788c2ecf20Sopenharmony_cistatic inline uint64_t radeon_sa_bo_gpu_addr(struct radeon_sa_bo *sa_bo) 1798c2ecf20Sopenharmony_ci{ 1808c2ecf20Sopenharmony_ci return sa_bo->manager->gpu_addr + sa_bo->soffset; 1818c2ecf20Sopenharmony_ci} 1828c2ecf20Sopenharmony_ci 1838c2ecf20Sopenharmony_cistatic inline void * radeon_sa_bo_cpu_addr(struct radeon_sa_bo *sa_bo) 1848c2ecf20Sopenharmony_ci{ 1858c2ecf20Sopenharmony_ci return sa_bo->manager->cpu_ptr + sa_bo->soffset; 1868c2ecf20Sopenharmony_ci} 1878c2ecf20Sopenharmony_ci 1888c2ecf20Sopenharmony_ciextern int radeon_sa_bo_manager_init(struct radeon_device *rdev, 1898c2ecf20Sopenharmony_ci struct radeon_sa_manager *sa_manager, 1908c2ecf20Sopenharmony_ci unsigned size, u32 align, u32 domain, 1918c2ecf20Sopenharmony_ci u32 flags); 1928c2ecf20Sopenharmony_ciextern void radeon_sa_bo_manager_fini(struct radeon_device *rdev, 1938c2ecf20Sopenharmony_ci struct radeon_sa_manager *sa_manager); 1948c2ecf20Sopenharmony_ciextern int radeon_sa_bo_manager_start(struct radeon_device *rdev, 1958c2ecf20Sopenharmony_ci struct radeon_sa_manager *sa_manager); 1968c2ecf20Sopenharmony_ciextern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev, 1978c2ecf20Sopenharmony_ci struct radeon_sa_manager *sa_manager); 1988c2ecf20Sopenharmony_ciextern int radeon_sa_bo_new(struct radeon_device *rdev, 1998c2ecf20Sopenharmony_ci struct radeon_sa_manager *sa_manager, 2008c2ecf20Sopenharmony_ci struct radeon_sa_bo **sa_bo, 2018c2ecf20Sopenharmony_ci unsigned size, unsigned align); 2028c2ecf20Sopenharmony_ciextern void radeon_sa_bo_free(struct radeon_device *rdev, 2038c2ecf20Sopenharmony_ci struct radeon_sa_bo **sa_bo, 2048c2ecf20Sopenharmony_ci struct radeon_fence *fence); 2058c2ecf20Sopenharmony_ci#if defined(CONFIG_DEBUG_FS) 2068c2ecf20Sopenharmony_ciextern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager, 2078c2ecf20Sopenharmony_ci struct seq_file *m); 2088c2ecf20Sopenharmony_ci#endif 2098c2ecf20Sopenharmony_ci 2108c2ecf20Sopenharmony_ci 2118c2ecf20Sopenharmony_ci#endif 212