1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27#include <linux/backlight.h> 28#include <linux/pci.h> 29 30#include <drm/drm_crtc_helper.h> 31#include <drm/drm_device.h> 32#include <drm/drm_file.h> 33#include <drm/drm_util.h> 34#include <drm/radeon_drm.h> 35 36#include "radeon.h" 37#include "radeon_asic.h" 38#include "atom.h" 39#ifdef CONFIG_PMAC_BACKLIGHT 40#include <asm/backlight.h> 41#endif 42 43static void radeon_legacy_encoder_disable(struct drm_encoder *encoder) 44{ 45 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 46 const struct drm_encoder_helper_funcs *encoder_funcs; 47 48 encoder_funcs = encoder->helper_private; 49 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF); 50 radeon_encoder->active_device = 0; 51} 52 53static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode) 54{ 55 struct drm_device *dev = encoder->dev; 56 struct radeon_device *rdev = dev->dev_private; 57 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 58 uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man; 59 int panel_pwr_delay = 2000; 60 bool is_mac = false; 61 uint8_t backlight_level; 62 DRM_DEBUG_KMS("\n"); 63 64 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 65 backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 66 67 if (radeon_encoder->enc_priv) { 68 if (rdev->is_atom_bios) { 69 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 70 panel_pwr_delay = lvds->panel_pwr_delay; 71 if (lvds->bl_dev) 72 backlight_level = lvds->backlight_level; 73 } else { 74 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 75 panel_pwr_delay = lvds->panel_pwr_delay; 76 if (lvds->bl_dev) 77 backlight_level = lvds->backlight_level; 78 } 79 } 80 81 /* macs (and possibly some x86 oem systems?) wire up LVDS strangely 82 * Taken from radeonfb. 83 */ 84 if ((rdev->mode_info.connector_table == CT_IBOOK) || 85 (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) || 86 (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) || 87 (rdev->mode_info.connector_table == CT_POWERBOOK_VGA)) 88 is_mac = true; 89 90 switch (mode) { 91 case DRM_MODE_DPMS_ON: 92 disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN); 93 disp_pwr_man |= RADEON_AUTO_PWRUP_EN; 94 WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man); 95 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 96 lvds_pll_cntl |= RADEON_LVDS_PLL_EN; 97 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 98 mdelay(1); 99 100 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 101 lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET; 102 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 103 104 lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS | 105 RADEON_LVDS_BL_MOD_LEVEL_MASK); 106 lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN | 107 RADEON_LVDS_DIGON | RADEON_LVDS_BLON | 108 (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT)); 109 if (is_mac) 110 lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN; 111 mdelay(panel_pwr_delay); 112 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 113 break; 114 case DRM_MODE_DPMS_STANDBY: 115 case DRM_MODE_DPMS_SUSPEND: 116 case DRM_MODE_DPMS_OFF: 117 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 118 WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb); 119 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 120 if (is_mac) { 121 lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN; 122 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 123 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN); 124 } else { 125 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 126 lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON); 127 } 128 mdelay(panel_pwr_delay); 129 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 130 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 131 mdelay(panel_pwr_delay); 132 break; 133 } 134 135 if (rdev->is_atom_bios) 136 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 137 else 138 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 139 140} 141 142static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode) 143{ 144 struct radeon_device *rdev = encoder->dev->dev_private; 145 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 146 DRM_DEBUG("\n"); 147 148 if (radeon_encoder->enc_priv) { 149 if (rdev->is_atom_bios) { 150 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 151 lvds->dpms_mode = mode; 152 } else { 153 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 154 lvds->dpms_mode = mode; 155 } 156 } 157 158 radeon_legacy_lvds_update(encoder, mode); 159} 160 161static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder) 162{ 163 struct radeon_device *rdev = encoder->dev->dev_private; 164 165 if (rdev->is_atom_bios) 166 radeon_atom_output_lock(encoder, true); 167 else 168 radeon_combios_output_lock(encoder, true); 169 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF); 170} 171 172static void radeon_legacy_lvds_commit(struct drm_encoder *encoder) 173{ 174 struct radeon_device *rdev = encoder->dev->dev_private; 175 176 radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON); 177 if (rdev->is_atom_bios) 178 radeon_atom_output_lock(encoder, false); 179 else 180 radeon_combios_output_lock(encoder, false); 181} 182 183static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder, 184 struct drm_display_mode *mode, 185 struct drm_display_mode *adjusted_mode) 186{ 187 struct drm_device *dev = encoder->dev; 188 struct radeon_device *rdev = dev->dev_private; 189 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 190 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 191 uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl; 192 193 DRM_DEBUG_KMS("\n"); 194 195 lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL); 196 lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN; 197 198 lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 199 if (rdev->is_atom_bios) { 200 /* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl 201 * need to call that on resume to set up the reg properly. 202 */ 203 radeon_encoder->pixel_clock = adjusted_mode->clock; 204 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE); 205 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 206 } else { 207 struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv; 208 if (lvds) { 209 DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl); 210 lvds_gen_cntl = lvds->lvds_gen_cntl; 211 lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 212 (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 213 lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) | 214 (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT)); 215 } else 216 lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 217 } 218 lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS; 219 lvds_gen_cntl &= ~(RADEON_LVDS_ON | 220 RADEON_LVDS_BLON | 221 RADEON_LVDS_EN | 222 RADEON_LVDS_RST_FM); 223 224 if (ASIC_IS_R300(rdev)) 225 lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK); 226 227 if (radeon_crtc->crtc_id == 0) { 228 if (ASIC_IS_R300(rdev)) { 229 if (radeon_encoder->rmx_type != RMX_OFF) 230 lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX; 231 } else 232 lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2; 233 } else { 234 if (ASIC_IS_R300(rdev)) 235 lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2; 236 else 237 lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2; 238 } 239 240 WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl); 241 WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl); 242 WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl); 243 244 if (rdev->family == CHIP_RV410) 245 WREG32(RADEON_CLOCK_CNTL_INDEX, 0); 246 247 if (rdev->is_atom_bios) 248 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 249 else 250 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 251} 252 253static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder, 254 const struct drm_display_mode *mode, 255 struct drm_display_mode *adjusted_mode) 256{ 257 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 258 259 /* set the active encoder to connector routing */ 260 radeon_encoder_set_active_device(encoder); 261 drm_mode_set_crtcinfo(adjusted_mode, 0); 262 263 /* get the native mode for LVDS */ 264 if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) 265 radeon_panel_mode_fixup(encoder, adjusted_mode); 266 267 return true; 268} 269 270static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = { 271 .dpms = radeon_legacy_lvds_dpms, 272 .mode_fixup = radeon_legacy_mode_fixup, 273 .prepare = radeon_legacy_lvds_prepare, 274 .mode_set = radeon_legacy_lvds_mode_set, 275 .commit = radeon_legacy_lvds_commit, 276 .disable = radeon_legacy_encoder_disable, 277}; 278 279u8 280radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder) 281{ 282 struct drm_device *dev = radeon_encoder->base.dev; 283 struct radeon_device *rdev = dev->dev_private; 284 u8 backlight_level; 285 286 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 287 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 288 289 return backlight_level; 290} 291 292void 293radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level) 294{ 295 struct drm_device *dev = radeon_encoder->base.dev; 296 struct radeon_device *rdev = dev->dev_private; 297 int dpms_mode = DRM_MODE_DPMS_ON; 298 299 if (radeon_encoder->enc_priv) { 300 if (rdev->is_atom_bios) { 301 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 302 if (lvds->backlight_level > 0) 303 dpms_mode = lvds->dpms_mode; 304 else 305 dpms_mode = DRM_MODE_DPMS_OFF; 306 lvds->backlight_level = level; 307 } else { 308 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 309 if (lvds->backlight_level > 0) 310 dpms_mode = lvds->dpms_mode; 311 else 312 dpms_mode = DRM_MODE_DPMS_OFF; 313 lvds->backlight_level = level; 314 } 315 } 316 317 radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode); 318} 319 320#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE) 321 322static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd) 323{ 324 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 325 uint8_t level; 326 327 /* Convert brightness to hardware level */ 328 if (bd->props.brightness < 0) 329 level = 0; 330 else if (bd->props.brightness > RADEON_MAX_BL_LEVEL) 331 level = RADEON_MAX_BL_LEVEL; 332 else 333 level = bd->props.brightness; 334 335 if (pdata->negative) 336 level = RADEON_MAX_BL_LEVEL - level; 337 338 return level; 339} 340 341static int radeon_legacy_backlight_update_status(struct backlight_device *bd) 342{ 343 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 344 struct radeon_encoder *radeon_encoder = pdata->encoder; 345 346 radeon_legacy_set_backlight_level(radeon_encoder, 347 radeon_legacy_lvds_level(bd)); 348 349 return 0; 350} 351 352static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd) 353{ 354 struct radeon_backlight_privdata *pdata = bl_get_data(bd); 355 struct radeon_encoder *radeon_encoder = pdata->encoder; 356 struct drm_device *dev = radeon_encoder->base.dev; 357 struct radeon_device *rdev = dev->dev_private; 358 uint8_t backlight_level; 359 360 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 361 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 362 363 return pdata->negative ? RADEON_MAX_BL_LEVEL - backlight_level : backlight_level; 364} 365 366static const struct backlight_ops radeon_backlight_ops = { 367 .get_brightness = radeon_legacy_backlight_get_brightness, 368 .update_status = radeon_legacy_backlight_update_status, 369}; 370 371void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder, 372 struct drm_connector *drm_connector) 373{ 374 struct drm_device *dev = radeon_encoder->base.dev; 375 struct radeon_device *rdev = dev->dev_private; 376 struct backlight_device *bd; 377 struct backlight_properties props; 378 struct radeon_backlight_privdata *pdata; 379 uint8_t backlight_level; 380 char bl_name[16]; 381 382 if (!radeon_encoder->enc_priv) 383 return; 384 385#ifdef CONFIG_PMAC_BACKLIGHT 386 if (!pmac_has_backlight_type("ati") && 387 !pmac_has_backlight_type("mnca")) 388 return; 389#endif 390 391 pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL); 392 if (!pdata) { 393 DRM_ERROR("Memory allocation failed\n"); 394 goto error; 395 } 396 397 memset(&props, 0, sizeof(props)); 398 props.max_brightness = RADEON_MAX_BL_LEVEL; 399 props.type = BACKLIGHT_RAW; 400 snprintf(bl_name, sizeof(bl_name), 401 "radeon_bl%d", dev->primary->index); 402 bd = backlight_device_register(bl_name, drm_connector->kdev, 403 pdata, &radeon_backlight_ops, &props); 404 if (IS_ERR(bd)) { 405 DRM_ERROR("Backlight registration failed\n"); 406 goto error; 407 } 408 409 pdata->encoder = radeon_encoder; 410 411 backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >> 412 RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff; 413 414 /* First, try to detect backlight level sense based on the assumption 415 * that firmware set it up at full brightness 416 */ 417 if (backlight_level == 0) 418 pdata->negative = true; 419 else if (backlight_level == 0xff) 420 pdata->negative = false; 421 else { 422 /* XXX hack... maybe some day we can figure out in what direction 423 * backlight should work on a given panel? 424 */ 425 pdata->negative = (rdev->family != CHIP_RV200 && 426 rdev->family != CHIP_RV250 && 427 rdev->family != CHIP_RV280 && 428 rdev->family != CHIP_RV350); 429 430#ifdef CONFIG_PMAC_BACKLIGHT 431 pdata->negative = (pdata->negative || 432 of_machine_is_compatible("PowerBook4,3") || 433 of_machine_is_compatible("PowerBook6,3") || 434 of_machine_is_compatible("PowerBook6,5")); 435#endif 436 } 437 438 if (rdev->is_atom_bios) { 439 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 440 lvds->bl_dev = bd; 441 } else { 442 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 443 lvds->bl_dev = bd; 444 } 445 446 bd->props.brightness = radeon_legacy_backlight_get_brightness(bd); 447 bd->props.power = FB_BLANK_UNBLANK; 448 backlight_update_status(bd); 449 450 DRM_INFO("radeon legacy LVDS backlight initialized\n"); 451 rdev->mode_info.bl_encoder = radeon_encoder; 452 453 return; 454 455error: 456 kfree(pdata); 457 return; 458} 459 460static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder) 461{ 462 struct drm_device *dev = radeon_encoder->base.dev; 463 struct radeon_device *rdev = dev->dev_private; 464 struct backlight_device *bd = NULL; 465 466 if (!radeon_encoder->enc_priv) 467 return; 468 469 if (rdev->is_atom_bios) { 470 struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv; 471 bd = lvds->bl_dev; 472 lvds->bl_dev = NULL; 473 } else { 474 struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv; 475 bd = lvds->bl_dev; 476 lvds->bl_dev = NULL; 477 } 478 479 if (bd) { 480 struct radeon_backlight_privdata *pdata; 481 482 pdata = bl_get_data(bd); 483 backlight_device_unregister(bd); 484 kfree(pdata); 485 486 DRM_INFO("radeon legacy LVDS backlight unloaded\n"); 487 } 488} 489 490#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */ 491 492void radeon_legacy_backlight_init(struct radeon_encoder *encoder) 493{ 494} 495 496static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder) 497{ 498} 499 500#endif 501 502 503static void radeon_lvds_enc_destroy(struct drm_encoder *encoder) 504{ 505 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 506 507 if (radeon_encoder->enc_priv) { 508 radeon_legacy_backlight_exit(radeon_encoder); 509 kfree(radeon_encoder->enc_priv); 510 } 511 drm_encoder_cleanup(encoder); 512 kfree(radeon_encoder); 513} 514 515static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = { 516 .destroy = radeon_lvds_enc_destroy, 517}; 518 519static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode) 520{ 521 struct drm_device *dev = encoder->dev; 522 struct radeon_device *rdev = dev->dev_private; 523 uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 524 uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL); 525 uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 526 527 DRM_DEBUG_KMS("\n"); 528 529 switch (mode) { 530 case DRM_MODE_DPMS_ON: 531 crtc_ext_cntl |= RADEON_CRTC_CRT_ON; 532 dac_cntl &= ~RADEON_DAC_PDWN; 533 dac_macro_cntl &= ~(RADEON_DAC_PDWN_R | 534 RADEON_DAC_PDWN_G | 535 RADEON_DAC_PDWN_B); 536 break; 537 case DRM_MODE_DPMS_STANDBY: 538 case DRM_MODE_DPMS_SUSPEND: 539 case DRM_MODE_DPMS_OFF: 540 crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON; 541 dac_cntl |= RADEON_DAC_PDWN; 542 dac_macro_cntl |= (RADEON_DAC_PDWN_R | 543 RADEON_DAC_PDWN_G | 544 RADEON_DAC_PDWN_B); 545 break; 546 } 547 548 /* handled in radeon_crtc_dpms() */ 549 if (!(rdev->flags & RADEON_SINGLE_CRTC)) 550 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 551 WREG32(RADEON_DAC_CNTL, dac_cntl); 552 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 553 554 if (rdev->is_atom_bios) 555 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 556 else 557 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 558 559} 560 561static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder) 562{ 563 struct radeon_device *rdev = encoder->dev->dev_private; 564 565 if (rdev->is_atom_bios) 566 radeon_atom_output_lock(encoder, true); 567 else 568 radeon_combios_output_lock(encoder, true); 569 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 570} 571 572static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder) 573{ 574 struct radeon_device *rdev = encoder->dev->dev_private; 575 576 radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON); 577 578 if (rdev->is_atom_bios) 579 radeon_atom_output_lock(encoder, false); 580 else 581 radeon_combios_output_lock(encoder, false); 582} 583 584static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder, 585 struct drm_display_mode *mode, 586 struct drm_display_mode *adjusted_mode) 587{ 588 struct drm_device *dev = encoder->dev; 589 struct radeon_device *rdev = dev->dev_private; 590 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 591 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 592 uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl; 593 594 DRM_DEBUG_KMS("\n"); 595 596 if (radeon_crtc->crtc_id == 0) { 597 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 598 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 599 ~(RADEON_DISP_DAC_SOURCE_MASK); 600 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 601 } else { 602 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~(RADEON_DAC2_DAC_CLK_SEL); 603 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 604 } 605 } else { 606 if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) { 607 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) & 608 ~(RADEON_DISP_DAC_SOURCE_MASK); 609 disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2; 610 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 611 } else { 612 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL; 613 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 614 } 615 } 616 617 dac_cntl = (RADEON_DAC_MASK_ALL | 618 RADEON_DAC_VGA_ADR_EN | 619 /* TODO 6-bits */ 620 RADEON_DAC_8BIT_EN); 621 622 WREG32_P(RADEON_DAC_CNTL, 623 dac_cntl, 624 RADEON_DAC_RANGE_CNTL | 625 RADEON_DAC_BLANKING); 626 627 if (radeon_encoder->enc_priv) { 628 struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv; 629 dac_macro_cntl = p_dac->ps2_pdac_adj; 630 } else 631 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 632 dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B; 633 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 634 635 if (rdev->is_atom_bios) 636 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 637 else 638 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 639} 640 641static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder, 642 struct drm_connector *connector) 643{ 644 struct drm_device *dev = encoder->dev; 645 struct radeon_device *rdev = dev->dev_private; 646 uint32_t vclk_ecp_cntl, crtc_ext_cntl; 647 uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp; 648 enum drm_connector_status found = connector_status_disconnected; 649 bool color = true; 650 651 /* just don't bother on RN50 those chip are often connected to remoting 652 * console hw and often we get failure to load detect those. So to make 653 * everyone happy report the encoder as always connected. 654 */ 655 if (ASIC_IS_RN50(rdev)) { 656 return connector_status_connected; 657 } 658 659 /* save the regs we need */ 660 vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL); 661 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 662 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 663 dac_cntl = RREG32(RADEON_DAC_CNTL); 664 dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL); 665 666 tmp = vclk_ecp_cntl & 667 ~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb); 668 WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp); 669 670 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 671 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 672 673 tmp = RADEON_DAC_FORCE_BLANK_OFF_EN | 674 RADEON_DAC_FORCE_DATA_EN; 675 676 if (color) 677 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 678 else 679 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 680 681 if (ASIC_IS_R300(rdev)) 682 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 683 else if (ASIC_IS_RV100(rdev)) 684 tmp |= (0x1ac << RADEON_DAC_FORCE_DATA_SHIFT); 685 else 686 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 687 688 WREG32(RADEON_DAC_EXT_CNTL, tmp); 689 690 tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN); 691 tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN; 692 WREG32(RADEON_DAC_CNTL, tmp); 693 694 tmp = dac_macro_cntl; 695 tmp &= ~(RADEON_DAC_PDWN_R | 696 RADEON_DAC_PDWN_G | 697 RADEON_DAC_PDWN_B); 698 699 WREG32(RADEON_DAC_MACRO_CNTL, tmp); 700 701 mdelay(2); 702 703 if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT) 704 found = connector_status_connected; 705 706 /* restore the regs we used */ 707 WREG32(RADEON_DAC_CNTL, dac_cntl); 708 WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl); 709 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 710 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 711 WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl); 712 713 return found; 714} 715 716static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = { 717 .dpms = radeon_legacy_primary_dac_dpms, 718 .mode_fixup = radeon_legacy_mode_fixup, 719 .prepare = radeon_legacy_primary_dac_prepare, 720 .mode_set = radeon_legacy_primary_dac_mode_set, 721 .commit = radeon_legacy_primary_dac_commit, 722 .detect = radeon_legacy_primary_dac_detect, 723 .disable = radeon_legacy_encoder_disable, 724}; 725 726 727static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = { 728 .destroy = radeon_enc_destroy, 729}; 730 731static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode) 732{ 733 struct drm_device *dev = encoder->dev; 734 struct radeon_device *rdev = dev->dev_private; 735 uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL); 736 DRM_DEBUG_KMS("\n"); 737 738 switch (mode) { 739 case DRM_MODE_DPMS_ON: 740 fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN); 741 break; 742 case DRM_MODE_DPMS_STANDBY: 743 case DRM_MODE_DPMS_SUSPEND: 744 case DRM_MODE_DPMS_OFF: 745 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 746 break; 747 } 748 749 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 750 751 if (rdev->is_atom_bios) 752 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 753 else 754 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 755 756} 757 758static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder) 759{ 760 struct radeon_device *rdev = encoder->dev->dev_private; 761 762 if (rdev->is_atom_bios) 763 radeon_atom_output_lock(encoder, true); 764 else 765 radeon_combios_output_lock(encoder, true); 766 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF); 767} 768 769static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder) 770{ 771 struct radeon_device *rdev = encoder->dev->dev_private; 772 773 radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON); 774 775 if (rdev->is_atom_bios) 776 radeon_atom_output_lock(encoder, true); 777 else 778 radeon_combios_output_lock(encoder, true); 779} 780 781static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder, 782 struct drm_display_mode *mode, 783 struct drm_display_mode *adjusted_mode) 784{ 785 struct drm_device *dev = encoder->dev; 786 struct radeon_device *rdev = dev->dev_private; 787 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 788 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 789 uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl; 790 int i; 791 792 DRM_DEBUG_KMS("\n"); 793 794 tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL); 795 tmp &= 0xfffff; 796 if (rdev->family == CHIP_RV280) { 797 /* bit 22 of TMDS_PLL_CNTL is read-back inverted */ 798 tmp ^= (1 << 22); 799 tmds_pll_cntl ^= (1 << 22); 800 } 801 802 if (radeon_encoder->enc_priv) { 803 struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv; 804 805 for (i = 0; i < 4; i++) { 806 if (tmds->tmds_pll[i].freq == 0) 807 break; 808 if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) { 809 tmp = tmds->tmds_pll[i].value ; 810 break; 811 } 812 } 813 } 814 815 if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) { 816 if (tmp & 0xfff00000) 817 tmds_pll_cntl = tmp; 818 else { 819 tmds_pll_cntl &= 0xfff00000; 820 tmds_pll_cntl |= tmp; 821 } 822 } else 823 tmds_pll_cntl = tmp; 824 825 tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) & 826 ~(RADEON_TMDS_TRANSMITTER_PLLRST); 827 828 if (rdev->family == CHIP_R200 || 829 rdev->family == CHIP_R100 || 830 ASIC_IS_R300(rdev)) 831 tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN); 832 else /* RV chips got this bit reversed */ 833 tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN; 834 835 fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) | 836 (RADEON_FP_CRTC_DONT_SHADOW_VPAR | 837 RADEON_FP_CRTC_DONT_SHADOW_HEND)); 838 839 fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN); 840 841 fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN | 842 RADEON_FP_DFP_SYNC_SEL | 843 RADEON_FP_CRT_SYNC_SEL | 844 RADEON_FP_CRTC_LOCK_8DOT | 845 RADEON_FP_USE_SHADOW_EN | 846 RADEON_FP_CRTC_USE_SHADOW_VEND | 847 RADEON_FP_CRT_SYNC_ALT); 848 849 if (1) /* FIXME rgbBits == 8 */ 850 fp_gen_cntl |= RADEON_FP_PANEL_FORMAT; /* 24 bit format */ 851 else 852 fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */ 853 854 if (radeon_crtc->crtc_id == 0) { 855 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 856 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 857 if (radeon_encoder->rmx_type != RMX_OFF) 858 fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX; 859 else 860 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1; 861 } else 862 fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2; 863 } else { 864 if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) { 865 fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK; 866 fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2; 867 } else 868 fp_gen_cntl |= RADEON_FP_SEL_CRTC2; 869 } 870 871 WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl); 872 WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl); 873 WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl); 874 875 if (rdev->is_atom_bios) 876 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 877 else 878 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 879} 880 881static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = { 882 .dpms = radeon_legacy_tmds_int_dpms, 883 .mode_fixup = radeon_legacy_mode_fixup, 884 .prepare = radeon_legacy_tmds_int_prepare, 885 .mode_set = radeon_legacy_tmds_int_mode_set, 886 .commit = radeon_legacy_tmds_int_commit, 887 .disable = radeon_legacy_encoder_disable, 888}; 889 890 891static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = { 892 .destroy = radeon_enc_destroy, 893}; 894 895static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode) 896{ 897 struct drm_device *dev = encoder->dev; 898 struct radeon_device *rdev = dev->dev_private; 899 uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 900 DRM_DEBUG_KMS("\n"); 901 902 switch (mode) { 903 case DRM_MODE_DPMS_ON: 904 fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN; 905 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 906 break; 907 case DRM_MODE_DPMS_STANDBY: 908 case DRM_MODE_DPMS_SUSPEND: 909 case DRM_MODE_DPMS_OFF: 910 fp2_gen_cntl |= RADEON_FP2_BLANK_EN; 911 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 912 break; 913 } 914 915 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 916 917 if (rdev->is_atom_bios) 918 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 919 else 920 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 921 922} 923 924static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder) 925{ 926 struct radeon_device *rdev = encoder->dev->dev_private; 927 928 if (rdev->is_atom_bios) 929 radeon_atom_output_lock(encoder, true); 930 else 931 radeon_combios_output_lock(encoder, true); 932 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF); 933} 934 935static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder) 936{ 937 struct radeon_device *rdev = encoder->dev->dev_private; 938 radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON); 939 940 if (rdev->is_atom_bios) 941 radeon_atom_output_lock(encoder, false); 942 else 943 radeon_combios_output_lock(encoder, false); 944} 945 946static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder, 947 struct drm_display_mode *mode, 948 struct drm_display_mode *adjusted_mode) 949{ 950 struct drm_device *dev = encoder->dev; 951 struct radeon_device *rdev = dev->dev_private; 952 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 953 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 954 uint32_t fp2_gen_cntl; 955 956 DRM_DEBUG_KMS("\n"); 957 958 if (rdev->is_atom_bios) { 959 radeon_encoder->pixel_clock = adjusted_mode->clock; 960 atombios_dvo_setup(encoder, ATOM_ENABLE); 961 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 962 } else { 963 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 964 965 if (1) /* FIXME rgbBits == 8 */ 966 fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */ 967 else 968 fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */ 969 970 fp2_gen_cntl &= ~(RADEON_FP2_ON | 971 RADEON_FP2_DVO_EN | 972 RADEON_FP2_DVO_RATE_SEL_SDR); 973 974 /* XXX: these are oem specific */ 975 if (ASIC_IS_R300(rdev)) { 976 if ((dev->pdev->device == 0x4850) && 977 (dev->pdev->subsystem_vendor == 0x1028) && 978 (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */ 979 fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE; 980 else 981 fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE; 982 983 /*if (mode->clock > 165000) 984 fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/ 985 } 986 if (!radeon_combios_external_tmds_setup(encoder)) 987 radeon_external_tmds_setup(encoder); 988 } 989 990 if (radeon_crtc->crtc_id == 0) { 991 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 992 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 993 if (radeon_encoder->rmx_type != RMX_OFF) 994 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX; 995 else 996 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1; 997 } else 998 fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2; 999 } else { 1000 if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) { 1001 fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK; 1002 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1003 } else 1004 fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2; 1005 } 1006 1007 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1008 1009 if (rdev->is_atom_bios) 1010 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1011 else 1012 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1013} 1014 1015static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder) 1016{ 1017 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1018 /* don't destroy the i2c bus record here, this will be done in radeon_i2c_fini */ 1019 kfree(radeon_encoder->enc_priv); 1020 drm_encoder_cleanup(encoder); 1021 kfree(radeon_encoder); 1022} 1023 1024static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = { 1025 .dpms = radeon_legacy_tmds_ext_dpms, 1026 .mode_fixup = radeon_legacy_mode_fixup, 1027 .prepare = radeon_legacy_tmds_ext_prepare, 1028 .mode_set = radeon_legacy_tmds_ext_mode_set, 1029 .commit = radeon_legacy_tmds_ext_commit, 1030 .disable = radeon_legacy_encoder_disable, 1031}; 1032 1033 1034static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = { 1035 .destroy = radeon_ext_tmds_enc_destroy, 1036}; 1037 1038static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode) 1039{ 1040 struct drm_device *dev = encoder->dev; 1041 struct radeon_device *rdev = dev->dev_private; 1042 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1043 uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0; 1044 uint32_t tv_master_cntl = 0; 1045 bool is_tv; 1046 DRM_DEBUG_KMS("\n"); 1047 1048 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1049 1050 if (rdev->family == CHIP_R200) 1051 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1052 else { 1053 if (is_tv) 1054 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1055 else 1056 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1057 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1058 } 1059 1060 switch (mode) { 1061 case DRM_MODE_DPMS_ON: 1062 if (rdev->family == CHIP_R200) { 1063 fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1064 } else { 1065 if (is_tv) 1066 tv_master_cntl |= RADEON_TV_ON; 1067 else 1068 crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON; 1069 1070 if (rdev->family == CHIP_R420 || 1071 rdev->family == CHIP_R423 || 1072 rdev->family == CHIP_RV410) 1073 tv_dac_cntl &= ~(R420_TV_DAC_RDACPD | 1074 R420_TV_DAC_GDACPD | 1075 R420_TV_DAC_BDACPD | 1076 RADEON_TV_DAC_BGSLEEP); 1077 else 1078 tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD | 1079 RADEON_TV_DAC_GDACPD | 1080 RADEON_TV_DAC_BDACPD | 1081 RADEON_TV_DAC_BGSLEEP); 1082 } 1083 break; 1084 case DRM_MODE_DPMS_STANDBY: 1085 case DRM_MODE_DPMS_SUSPEND: 1086 case DRM_MODE_DPMS_OFF: 1087 if (rdev->family == CHIP_R200) 1088 fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN); 1089 else { 1090 if (is_tv) 1091 tv_master_cntl &= ~RADEON_TV_ON; 1092 else 1093 crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON; 1094 1095 if (rdev->family == CHIP_R420 || 1096 rdev->family == CHIP_R423 || 1097 rdev->family == CHIP_RV410) 1098 tv_dac_cntl |= (R420_TV_DAC_RDACPD | 1099 R420_TV_DAC_GDACPD | 1100 R420_TV_DAC_BDACPD | 1101 RADEON_TV_DAC_BGSLEEP); 1102 else 1103 tv_dac_cntl |= (RADEON_TV_DAC_RDACPD | 1104 RADEON_TV_DAC_GDACPD | 1105 RADEON_TV_DAC_BDACPD | 1106 RADEON_TV_DAC_BGSLEEP); 1107 } 1108 break; 1109 } 1110 1111 if (rdev->family == CHIP_R200) { 1112 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1113 } else { 1114 if (is_tv) 1115 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1116 /* handled in radeon_crtc_dpms() */ 1117 else if (!(rdev->flags & RADEON_SINGLE_CRTC)) 1118 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1119 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1120 } 1121 1122 if (rdev->is_atom_bios) 1123 radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1124 else 1125 radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false); 1126 1127} 1128 1129static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder) 1130{ 1131 struct radeon_device *rdev = encoder->dev->dev_private; 1132 1133 if (rdev->is_atom_bios) 1134 radeon_atom_output_lock(encoder, true); 1135 else 1136 radeon_combios_output_lock(encoder, true); 1137 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF); 1138} 1139 1140static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder) 1141{ 1142 struct radeon_device *rdev = encoder->dev->dev_private; 1143 1144 radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON); 1145 1146 if (rdev->is_atom_bios) 1147 radeon_atom_output_lock(encoder, true); 1148 else 1149 radeon_combios_output_lock(encoder, true); 1150} 1151 1152static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder, 1153 struct drm_display_mode *mode, 1154 struct drm_display_mode *adjusted_mode) 1155{ 1156 struct drm_device *dev = encoder->dev; 1157 struct radeon_device *rdev = dev->dev_private; 1158 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc); 1159 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1160 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1161 uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0; 1162 uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0; 1163 bool is_tv = false; 1164 1165 DRM_DEBUG_KMS("\n"); 1166 1167 is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false; 1168 1169 if (rdev->family != CHIP_R200) { 1170 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1171 if (rdev->family == CHIP_R420 || 1172 rdev->family == CHIP_R423 || 1173 rdev->family == CHIP_RV410) { 1174 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1175 RADEON_TV_DAC_BGADJ_MASK | 1176 R420_TV_DAC_DACADJ_MASK | 1177 R420_TV_DAC_RDACPD | 1178 R420_TV_DAC_GDACPD | 1179 R420_TV_DAC_BDACPD | 1180 R420_TV_DAC_TVENABLE); 1181 } else { 1182 tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK | 1183 RADEON_TV_DAC_BGADJ_MASK | 1184 RADEON_TV_DAC_DACADJ_MASK | 1185 RADEON_TV_DAC_RDACPD | 1186 RADEON_TV_DAC_GDACPD | 1187 RADEON_TV_DAC_BDACPD); 1188 } 1189 1190 tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD; 1191 1192 if (is_tv) { 1193 if (tv_dac->tv_std == TV_STD_NTSC || 1194 tv_dac->tv_std == TV_STD_NTSC_J || 1195 tv_dac->tv_std == TV_STD_PAL_M || 1196 tv_dac->tv_std == TV_STD_PAL_60) 1197 tv_dac_cntl |= tv_dac->ntsc_tvdac_adj; 1198 else 1199 tv_dac_cntl |= tv_dac->pal_tvdac_adj; 1200 1201 if (tv_dac->tv_std == TV_STD_NTSC || 1202 tv_dac->tv_std == TV_STD_NTSC_J) 1203 tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC; 1204 else 1205 tv_dac_cntl |= RADEON_TV_DAC_STD_PAL; 1206 } else 1207 tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 | 1208 tv_dac->ps2_tvdac_adj); 1209 1210 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1211 } 1212 1213 if (ASIC_IS_R300(rdev)) { 1214 gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1; 1215 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1216 } else if (rdev->family != CHIP_R200) 1217 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1218 else if (rdev->family == CHIP_R200) 1219 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1220 1221 if (rdev->family >= CHIP_R200) 1222 disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL); 1223 1224 if (is_tv) { 1225 uint32_t dac_cntl; 1226 1227 dac_cntl = RREG32(RADEON_DAC_CNTL); 1228 dac_cntl &= ~RADEON_DAC_TVO_EN; 1229 WREG32(RADEON_DAC_CNTL, dac_cntl); 1230 1231 if (ASIC_IS_R300(rdev)) 1232 gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1; 1233 1234 dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL; 1235 if (radeon_crtc->crtc_id == 0) { 1236 if (ASIC_IS_R300(rdev)) { 1237 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1238 disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC | 1239 RADEON_DISP_TV_SOURCE_CRTC); 1240 } 1241 if (rdev->family >= CHIP_R200) { 1242 disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2; 1243 } else { 1244 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1245 } 1246 } else { 1247 if (ASIC_IS_R300(rdev)) { 1248 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1249 disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC; 1250 } 1251 if (rdev->family >= CHIP_R200) { 1252 disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2; 1253 } else { 1254 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1255 } 1256 } 1257 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1258 } else { 1259 1260 dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL; 1261 1262 if (radeon_crtc->crtc_id == 0) { 1263 if (ASIC_IS_R300(rdev)) { 1264 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1265 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC; 1266 } else if (rdev->family == CHIP_R200) { 1267 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1268 RADEON_FP2_DVO_RATE_SEL_SDR); 1269 } else 1270 disp_hw_debug |= RADEON_CRT2_DISP1_SEL; 1271 } else { 1272 if (ASIC_IS_R300(rdev)) { 1273 disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK; 1274 disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1275 } else if (rdev->family == CHIP_R200) { 1276 fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK | 1277 RADEON_FP2_DVO_RATE_SEL_SDR); 1278 fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2; 1279 } else 1280 disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL; 1281 } 1282 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1283 } 1284 1285 if (ASIC_IS_R300(rdev)) { 1286 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1287 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1288 } else if (rdev->family != CHIP_R200) 1289 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1290 else if (rdev->family == CHIP_R200) 1291 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1292 1293 if (rdev->family >= CHIP_R200) 1294 WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl); 1295 1296 if (is_tv) 1297 radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode); 1298 1299 if (rdev->is_atom_bios) 1300 radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1301 else 1302 radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id); 1303 1304} 1305 1306static bool r300_legacy_tv_detect(struct drm_encoder *encoder, 1307 struct drm_connector *connector) 1308{ 1309 struct drm_device *dev = encoder->dev; 1310 struct radeon_device *rdev = dev->dev_private; 1311 uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1312 uint32_t disp_output_cntl, gpiopad_a, tmp; 1313 bool found = false; 1314 1315 /* save regs needed */ 1316 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1317 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1318 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1319 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1320 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1321 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1322 1323 WREG32_P(RADEON_GPIOPAD_A, 0, ~1); 1324 1325 WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL); 1326 1327 WREG32(RADEON_CRTC2_GEN_CNTL, 1328 RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT); 1329 1330 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1331 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1332 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1333 1334 WREG32(RADEON_DAC_EXT_CNTL, 1335 RADEON_DAC2_FORCE_BLANK_OFF_EN | 1336 RADEON_DAC2_FORCE_DATA_EN | 1337 RADEON_DAC_FORCE_DATA_SEL_RGB | 1338 (0xec << RADEON_DAC_FORCE_DATA_SHIFT)); 1339 1340 WREG32(RADEON_TV_DAC_CNTL, 1341 RADEON_TV_DAC_STD_NTSC | 1342 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1343 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1344 1345 RREG32(RADEON_TV_DAC_CNTL); 1346 mdelay(4); 1347 1348 WREG32(RADEON_TV_DAC_CNTL, 1349 RADEON_TV_DAC_NBLANK | 1350 RADEON_TV_DAC_NHOLD | 1351 RADEON_TV_MONITOR_DETECT_EN | 1352 RADEON_TV_DAC_STD_NTSC | 1353 (8 << RADEON_TV_DAC_BGADJ_SHIFT) | 1354 (6 << RADEON_TV_DAC_DACADJ_SHIFT)); 1355 1356 RREG32(RADEON_TV_DAC_CNTL); 1357 mdelay(6); 1358 1359 tmp = RREG32(RADEON_TV_DAC_CNTL); 1360 if ((tmp & RADEON_TV_DAC_GDACDET) != 0) { 1361 found = true; 1362 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1363 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1364 found = true; 1365 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1366 } 1367 1368 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1369 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1370 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1371 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1372 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1373 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1374 return found; 1375} 1376 1377static bool radeon_legacy_tv_detect(struct drm_encoder *encoder, 1378 struct drm_connector *connector) 1379{ 1380 struct drm_device *dev = encoder->dev; 1381 struct radeon_device *rdev = dev->dev_private; 1382 uint32_t tv_dac_cntl, dac_cntl2; 1383 uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp; 1384 bool found = false; 1385 1386 if (ASIC_IS_R300(rdev)) 1387 return r300_legacy_tv_detect(encoder, connector); 1388 1389 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1390 tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL); 1391 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1392 config_cntl = RREG32(RADEON_CONFIG_CNTL); 1393 tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL); 1394 1395 tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL; 1396 WREG32(RADEON_DAC_CNTL2, tmp); 1397 1398 tmp = tv_master_cntl | RADEON_TV_ON; 1399 tmp &= ~(RADEON_TV_ASYNC_RST | 1400 RADEON_RESTART_PHASE_FIX | 1401 RADEON_CRT_FIFO_CE_EN | 1402 RADEON_TV_FIFO_CE_EN | 1403 RADEON_RE_SYNC_NOW_SEL_MASK); 1404 tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST; 1405 WREG32(RADEON_TV_MASTER_CNTL, tmp); 1406 1407 tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD | 1408 RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC | 1409 (8 << RADEON_TV_DAC_BGADJ_SHIFT); 1410 1411 if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK) 1412 tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT); 1413 else 1414 tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT); 1415 WREG32(RADEON_TV_DAC_CNTL, tmp); 1416 1417 tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN | 1418 RADEON_RED_MX_FORCE_DAC_DATA | 1419 RADEON_GRN_MX_FORCE_DAC_DATA | 1420 RADEON_BLU_MX_FORCE_DAC_DATA | 1421 (0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT); 1422 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp); 1423 1424 mdelay(3); 1425 tmp = RREG32(RADEON_TV_DAC_CNTL); 1426 if (tmp & RADEON_TV_DAC_GDACDET) { 1427 found = true; 1428 DRM_DEBUG_KMS("S-video TV connection detected\n"); 1429 } else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) { 1430 found = true; 1431 DRM_DEBUG_KMS("Composite TV connection detected\n"); 1432 } 1433 1434 WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl); 1435 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1436 WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl); 1437 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1438 return found; 1439} 1440 1441static bool radeon_legacy_ext_dac_detect(struct drm_encoder *encoder, 1442 struct drm_connector *connector) 1443{ 1444 struct drm_device *dev = encoder->dev; 1445 struct radeon_device *rdev = dev->dev_private; 1446 uint32_t gpio_monid, fp2_gen_cntl, disp_output_cntl, crtc2_gen_cntl; 1447 uint32_t disp_lin_trans_grph_a, disp_lin_trans_grph_b, disp_lin_trans_grph_c; 1448 uint32_t disp_lin_trans_grph_d, disp_lin_trans_grph_e, disp_lin_trans_grph_f; 1449 uint32_t tmp, crtc2_h_total_disp, crtc2_v_total_disp; 1450 uint32_t crtc2_h_sync_strt_wid, crtc2_v_sync_strt_wid; 1451 bool found = false; 1452 int i; 1453 1454 /* save the regs we need */ 1455 gpio_monid = RREG32(RADEON_GPIO_MONID); 1456 fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL); 1457 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1458 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1459 disp_lin_trans_grph_a = RREG32(RADEON_DISP_LIN_TRANS_GRPH_A); 1460 disp_lin_trans_grph_b = RREG32(RADEON_DISP_LIN_TRANS_GRPH_B); 1461 disp_lin_trans_grph_c = RREG32(RADEON_DISP_LIN_TRANS_GRPH_C); 1462 disp_lin_trans_grph_d = RREG32(RADEON_DISP_LIN_TRANS_GRPH_D); 1463 disp_lin_trans_grph_e = RREG32(RADEON_DISP_LIN_TRANS_GRPH_E); 1464 disp_lin_trans_grph_f = RREG32(RADEON_DISP_LIN_TRANS_GRPH_F); 1465 crtc2_h_total_disp = RREG32(RADEON_CRTC2_H_TOTAL_DISP); 1466 crtc2_v_total_disp = RREG32(RADEON_CRTC2_V_TOTAL_DISP); 1467 crtc2_h_sync_strt_wid = RREG32(RADEON_CRTC2_H_SYNC_STRT_WID); 1468 crtc2_v_sync_strt_wid = RREG32(RADEON_CRTC2_V_SYNC_STRT_WID); 1469 1470 tmp = RREG32(RADEON_GPIO_MONID); 1471 tmp &= ~RADEON_GPIO_A_0; 1472 WREG32(RADEON_GPIO_MONID, tmp); 1473 1474 WREG32(RADEON_FP2_GEN_CNTL, (RADEON_FP2_ON | 1475 RADEON_FP2_PANEL_FORMAT | 1476 R200_FP2_SOURCE_SEL_TRANS_UNIT | 1477 RADEON_FP2_DVO_EN | 1478 R200_FP2_DVO_RATE_SEL_SDR)); 1479 1480 WREG32(RADEON_DISP_OUTPUT_CNTL, (RADEON_DISP_DAC_SOURCE_RMX | 1481 RADEON_DISP_TRANS_MATRIX_GRAPHICS)); 1482 1483 WREG32(RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_EN | 1484 RADEON_CRTC2_DISP_REQ_EN_B)); 1485 1486 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, 0x00000000); 1487 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, 0x000003f0); 1488 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, 0x00000000); 1489 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, 0x000003f0); 1490 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, 0x00000000); 1491 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, 0x000003f0); 1492 1493 WREG32(RADEON_CRTC2_H_TOTAL_DISP, 0x01000008); 1494 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, 0x00000800); 1495 WREG32(RADEON_CRTC2_V_TOTAL_DISP, 0x00080001); 1496 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, 0x00000080); 1497 1498 for (i = 0; i < 200; i++) { 1499 tmp = RREG32(RADEON_GPIO_MONID); 1500 if (tmp & RADEON_GPIO_Y_0) 1501 found = true; 1502 1503 if (found) 1504 break; 1505 1506 if (!drm_can_sleep()) 1507 mdelay(1); 1508 else 1509 msleep(1); 1510 } 1511 1512 /* restore the regs we used */ 1513 WREG32(RADEON_DISP_LIN_TRANS_GRPH_A, disp_lin_trans_grph_a); 1514 WREG32(RADEON_DISP_LIN_TRANS_GRPH_B, disp_lin_trans_grph_b); 1515 WREG32(RADEON_DISP_LIN_TRANS_GRPH_C, disp_lin_trans_grph_c); 1516 WREG32(RADEON_DISP_LIN_TRANS_GRPH_D, disp_lin_trans_grph_d); 1517 WREG32(RADEON_DISP_LIN_TRANS_GRPH_E, disp_lin_trans_grph_e); 1518 WREG32(RADEON_DISP_LIN_TRANS_GRPH_F, disp_lin_trans_grph_f); 1519 WREG32(RADEON_CRTC2_H_TOTAL_DISP, crtc2_h_total_disp); 1520 WREG32(RADEON_CRTC2_V_TOTAL_DISP, crtc2_v_total_disp); 1521 WREG32(RADEON_CRTC2_H_SYNC_STRT_WID, crtc2_h_sync_strt_wid); 1522 WREG32(RADEON_CRTC2_V_SYNC_STRT_WID, crtc2_v_sync_strt_wid); 1523 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1524 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1525 WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl); 1526 WREG32(RADEON_GPIO_MONID, gpio_monid); 1527 1528 return found; 1529} 1530 1531static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder, 1532 struct drm_connector *connector) 1533{ 1534 struct drm_device *dev = encoder->dev; 1535 struct radeon_device *rdev = dev->dev_private; 1536 uint32_t crtc2_gen_cntl = 0, tv_dac_cntl, dac_cntl2, dac_ext_cntl; 1537 uint32_t gpiopad_a = 0, pixclks_cntl, tmp; 1538 uint32_t disp_output_cntl = 0, disp_hw_debug = 0, crtc_ext_cntl = 0; 1539 enum drm_connector_status found = connector_status_disconnected; 1540 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 1541 struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv; 1542 bool color = true; 1543 struct drm_crtc *crtc; 1544 1545 /* find out if crtc2 is in use or if this encoder is using it */ 1546 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 1547 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); 1548 if ((radeon_crtc->crtc_id == 1) && crtc->enabled) { 1549 if (encoder->crtc != crtc) { 1550 return connector_status_disconnected; 1551 } 1552 } 1553 } 1554 1555 if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO || 1556 connector->connector_type == DRM_MODE_CONNECTOR_Composite || 1557 connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) { 1558 bool tv_detect; 1559 1560 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT)) 1561 return connector_status_disconnected; 1562 1563 tv_detect = radeon_legacy_tv_detect(encoder, connector); 1564 if (tv_detect && tv_dac) 1565 found = connector_status_connected; 1566 return found; 1567 } 1568 1569 /* don't probe if the encoder is being used for something else not CRT related */ 1570 if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) { 1571 DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device); 1572 return connector_status_disconnected; 1573 } 1574 1575 /* R200 uses an external DAC for secondary DAC */ 1576 if (rdev->family == CHIP_R200) { 1577 if (radeon_legacy_ext_dac_detect(encoder, connector)) 1578 found = connector_status_connected; 1579 return found; 1580 } 1581 1582 /* save the regs we need */ 1583 pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL); 1584 1585 if (rdev->flags & RADEON_SINGLE_CRTC) { 1586 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL); 1587 } else { 1588 if (ASIC_IS_R300(rdev)) { 1589 gpiopad_a = RREG32(RADEON_GPIOPAD_A); 1590 disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL); 1591 } else { 1592 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG); 1593 } 1594 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL); 1595 } 1596 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL); 1597 dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL); 1598 dac_cntl2 = RREG32(RADEON_DAC_CNTL2); 1599 1600 tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb 1601 | RADEON_PIX2CLK_DAC_ALWAYS_ONb); 1602 WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp); 1603 1604 if (rdev->flags & RADEON_SINGLE_CRTC) { 1605 tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON; 1606 WREG32(RADEON_CRTC_EXT_CNTL, tmp); 1607 } else { 1608 tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK; 1609 tmp |= RADEON_CRTC2_CRT2_ON | 1610 (2 << RADEON_CRTC2_PIX_WIDTH_SHIFT); 1611 WREG32(RADEON_CRTC2_GEN_CNTL, tmp); 1612 1613 if (ASIC_IS_R300(rdev)) { 1614 WREG32_P(RADEON_GPIOPAD_A, 1, ~1); 1615 tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK; 1616 tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2; 1617 WREG32(RADEON_DISP_OUTPUT_CNTL, tmp); 1618 } else { 1619 tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL; 1620 WREG32(RADEON_DISP_HW_DEBUG, tmp); 1621 } 1622 } 1623 1624 tmp = RADEON_TV_DAC_NBLANK | 1625 RADEON_TV_DAC_NHOLD | 1626 RADEON_TV_MONITOR_DETECT_EN | 1627 RADEON_TV_DAC_STD_PS2; 1628 1629 WREG32(RADEON_TV_DAC_CNTL, tmp); 1630 1631 tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN | 1632 RADEON_DAC2_FORCE_DATA_EN; 1633 1634 if (color) 1635 tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB; 1636 else 1637 tmp |= RADEON_DAC_FORCE_DATA_SEL_G; 1638 1639 if (ASIC_IS_R300(rdev)) 1640 tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT); 1641 else 1642 tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT); 1643 1644 WREG32(RADEON_DAC_EXT_CNTL, tmp); 1645 1646 tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN; 1647 WREG32(RADEON_DAC_CNTL2, tmp); 1648 1649 mdelay(10); 1650 1651 if (ASIC_IS_R300(rdev)) { 1652 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B) 1653 found = connector_status_connected; 1654 } else { 1655 if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT) 1656 found = connector_status_connected; 1657 } 1658 1659 /* restore regs we used */ 1660 WREG32(RADEON_DAC_CNTL2, dac_cntl2); 1661 WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl); 1662 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl); 1663 1664 if (rdev->flags & RADEON_SINGLE_CRTC) { 1665 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl); 1666 } else { 1667 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl); 1668 if (ASIC_IS_R300(rdev)) { 1669 WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl); 1670 WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1); 1671 } else { 1672 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1673 } 1674 } 1675 1676 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl); 1677 1678 return found; 1679 1680} 1681 1682static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = { 1683 .dpms = radeon_legacy_tv_dac_dpms, 1684 .mode_fixup = radeon_legacy_mode_fixup, 1685 .prepare = radeon_legacy_tv_dac_prepare, 1686 .mode_set = radeon_legacy_tv_dac_mode_set, 1687 .commit = radeon_legacy_tv_dac_commit, 1688 .detect = radeon_legacy_tv_dac_detect, 1689 .disable = radeon_legacy_encoder_disable, 1690}; 1691 1692 1693static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = { 1694 .destroy = radeon_enc_destroy, 1695}; 1696 1697 1698static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder) 1699{ 1700 struct drm_device *dev = encoder->base.dev; 1701 struct radeon_device *rdev = dev->dev_private; 1702 struct radeon_encoder_int_tmds *tmds = NULL; 1703 bool ret; 1704 1705 tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL); 1706 1707 if (!tmds) 1708 return NULL; 1709 1710 if (rdev->is_atom_bios) 1711 ret = radeon_atombios_get_tmds_info(encoder, tmds); 1712 else 1713 ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds); 1714 1715 if (!ret) 1716 radeon_legacy_get_tmds_info_from_table(encoder, tmds); 1717 1718 return tmds; 1719} 1720 1721static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder) 1722{ 1723 struct drm_device *dev = encoder->base.dev; 1724 struct radeon_device *rdev = dev->dev_private; 1725 struct radeon_encoder_ext_tmds *tmds = NULL; 1726 bool ret; 1727 1728 if (rdev->is_atom_bios) 1729 return NULL; 1730 1731 tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL); 1732 1733 if (!tmds) 1734 return NULL; 1735 1736 ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds); 1737 1738 if (!ret) 1739 radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds); 1740 1741 return tmds; 1742} 1743 1744void 1745radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device) 1746{ 1747 struct radeon_device *rdev = dev->dev_private; 1748 struct drm_encoder *encoder; 1749 struct radeon_encoder *radeon_encoder; 1750 1751 /* see if we already added it */ 1752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { 1753 radeon_encoder = to_radeon_encoder(encoder); 1754 if (radeon_encoder->encoder_enum == encoder_enum) { 1755 radeon_encoder->devices |= supported_device; 1756 return; 1757 } 1758 1759 } 1760 1761 /* add a new one */ 1762 radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL); 1763 if (!radeon_encoder) 1764 return; 1765 1766 encoder = &radeon_encoder->base; 1767 if (rdev->flags & RADEON_SINGLE_CRTC) 1768 encoder->possible_crtcs = 0x1; 1769 else 1770 encoder->possible_crtcs = 0x3; 1771 1772 radeon_encoder->enc_priv = NULL; 1773 1774 radeon_encoder->encoder_enum = encoder_enum; 1775 radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT; 1776 radeon_encoder->devices = supported_device; 1777 radeon_encoder->rmx_type = RMX_OFF; 1778 1779 switch (radeon_encoder->encoder_id) { 1780 case ENCODER_OBJECT_ID_INTERNAL_LVDS: 1781 encoder->possible_crtcs = 0x1; 1782 drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, 1783 DRM_MODE_ENCODER_LVDS, NULL); 1784 drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs); 1785 if (rdev->is_atom_bios) 1786 radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder); 1787 else 1788 radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder); 1789 radeon_encoder->rmx_type = RMX_FULL; 1790 break; 1791 case ENCODER_OBJECT_ID_INTERNAL_TMDS1: 1792 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, 1793 DRM_MODE_ENCODER_TMDS, NULL); 1794 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs); 1795 radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder); 1796 break; 1797 case ENCODER_OBJECT_ID_INTERNAL_DAC1: 1798 drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, 1799 DRM_MODE_ENCODER_DAC, NULL); 1800 drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs); 1801 if (rdev->is_atom_bios) 1802 radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder); 1803 else 1804 radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder); 1805 break; 1806 case ENCODER_OBJECT_ID_INTERNAL_DAC2: 1807 drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, 1808 DRM_MODE_ENCODER_TVDAC, NULL); 1809 drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs); 1810 if (rdev->is_atom_bios) 1811 radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder); 1812 else 1813 radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder); 1814 break; 1815 case ENCODER_OBJECT_ID_INTERNAL_DVO1: 1816 drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, 1817 DRM_MODE_ENCODER_TMDS, NULL); 1818 drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs); 1819 if (!rdev->is_atom_bios) 1820 radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder); 1821 break; 1822 } 1823} 1824