1/* 2 * Copyright 2007-8 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 */ 26 27#include <linux/export.h> 28#include <linux/pci.h> 29 30#include <drm/drm_device.h> 31#include <drm/drm_edid.h> 32#include <drm/radeon_drm.h> 33 34#include "radeon.h" 35#include "atom.h" 36 37extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 38 struct i2c_msg *msgs, int num); 39extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); 40 41/** 42 * radeon_ddc_probe 43 * 44 */ 45bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) 46{ 47 u8 out = 0x0; 48 u8 buf[8]; 49 int ret; 50 struct i2c_msg msgs[] = { 51 { 52 .addr = DDC_ADDR, 53 .flags = 0, 54 .len = 1, 55 .buf = &out, 56 }, 57 { 58 .addr = DDC_ADDR, 59 .flags = I2C_M_RD, 60 .len = 8, 61 .buf = buf, 62 } 63 }; 64 65 /* on hw with routers, select right port */ 66 if (radeon_connector->router.ddc_valid) 67 radeon_router_select_ddc_port(radeon_connector); 68 69 if (use_aux) { 70 ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); 71 } else { 72 ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); 73 } 74 75 if (ret != 2) 76 /* Couldn't find an accessible DDC on this connector */ 77 return false; 78 /* Probe also for valid EDID header 79 * EDID header starts with: 80 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. 81 * Only the first 6 bytes must be valid as 82 * drm_edid_block_valid() can fix the last 2 bytes */ 83 if (drm_edid_header_is_valid(buf) < 6) { 84 /* Couldn't find an accessible EDID on this 85 * connector */ 86 return false; 87 } 88 return true; 89} 90 91/* bit banging i2c */ 92 93static int pre_xfer(struct i2c_adapter *i2c_adap) 94{ 95 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 96 struct radeon_device *rdev = i2c->dev->dev_private; 97 struct radeon_i2c_bus_rec *rec = &i2c->rec; 98 uint32_t temp; 99 100 mutex_lock(&i2c->mutex); 101 102 /* RV410 appears to have a bug where the hw i2c in reset 103 * holds the i2c port in a bad state - switch hw i2c away before 104 * doing DDC - do this for all r200s/r300s/r400s for safety sake 105 */ 106 if (rec->hw_capable) { 107 if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { 108 u32 reg; 109 110 if (rdev->family >= CHIP_RV350) 111 reg = RADEON_GPIO_MONID; 112 else if ((rdev->family == CHIP_R300) || 113 (rdev->family == CHIP_R350)) 114 reg = RADEON_GPIO_DVI_DDC; 115 else 116 reg = RADEON_GPIO_CRT2_DDC; 117 118 mutex_lock(&rdev->dc_hw_i2c_mutex); 119 if (rec->a_clk_reg == reg) { 120 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 121 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); 122 } else { 123 WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | 124 R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); 125 } 126 mutex_unlock(&rdev->dc_hw_i2c_mutex); 127 } 128 } 129 130 /* switch the pads to ddc mode */ 131 if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { 132 temp = RREG32(rec->mask_clk_reg); 133 temp &= ~(1 << 16); 134 WREG32(rec->mask_clk_reg, temp); 135 } 136 137 /* clear the output pin values */ 138 temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; 139 WREG32(rec->a_clk_reg, temp); 140 141 temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; 142 WREG32(rec->a_data_reg, temp); 143 144 /* set the pins to input */ 145 temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 146 WREG32(rec->en_clk_reg, temp); 147 148 temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 149 WREG32(rec->en_data_reg, temp); 150 151 /* mask the gpio pins for software use */ 152 temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; 153 WREG32(rec->mask_clk_reg, temp); 154 temp = RREG32(rec->mask_clk_reg); 155 156 temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; 157 WREG32(rec->mask_data_reg, temp); 158 temp = RREG32(rec->mask_data_reg); 159 160 return 0; 161} 162 163static void post_xfer(struct i2c_adapter *i2c_adap) 164{ 165 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 166 struct radeon_device *rdev = i2c->dev->dev_private; 167 struct radeon_i2c_bus_rec *rec = &i2c->rec; 168 uint32_t temp; 169 170 /* unmask the gpio pins for software use */ 171 temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; 172 WREG32(rec->mask_clk_reg, temp); 173 temp = RREG32(rec->mask_clk_reg); 174 175 temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; 176 WREG32(rec->mask_data_reg, temp); 177 temp = RREG32(rec->mask_data_reg); 178 179 mutex_unlock(&i2c->mutex); 180} 181 182static int get_clock(void *i2c_priv) 183{ 184 struct radeon_i2c_chan *i2c = i2c_priv; 185 struct radeon_device *rdev = i2c->dev->dev_private; 186 struct radeon_i2c_bus_rec *rec = &i2c->rec; 187 uint32_t val; 188 189 /* read the value off the pin */ 190 val = RREG32(rec->y_clk_reg); 191 val &= rec->y_clk_mask; 192 193 return (val != 0); 194} 195 196 197static int get_data(void *i2c_priv) 198{ 199 struct radeon_i2c_chan *i2c = i2c_priv; 200 struct radeon_device *rdev = i2c->dev->dev_private; 201 struct radeon_i2c_bus_rec *rec = &i2c->rec; 202 uint32_t val; 203 204 /* read the value off the pin */ 205 val = RREG32(rec->y_data_reg); 206 val &= rec->y_data_mask; 207 208 return (val != 0); 209} 210 211static void set_clock(void *i2c_priv, int clock) 212{ 213 struct radeon_i2c_chan *i2c = i2c_priv; 214 struct radeon_device *rdev = i2c->dev->dev_private; 215 struct radeon_i2c_bus_rec *rec = &i2c->rec; 216 uint32_t val; 217 218 /* set pin direction */ 219 val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; 220 val |= clock ? 0 : rec->en_clk_mask; 221 WREG32(rec->en_clk_reg, val); 222} 223 224static void set_data(void *i2c_priv, int data) 225{ 226 struct radeon_i2c_chan *i2c = i2c_priv; 227 struct radeon_device *rdev = i2c->dev->dev_private; 228 struct radeon_i2c_bus_rec *rec = &i2c->rec; 229 uint32_t val; 230 231 /* set pin direction */ 232 val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; 233 val |= data ? 0 : rec->en_data_mask; 234 WREG32(rec->en_data_reg, val); 235} 236 237/* hw i2c */ 238 239static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) 240{ 241 u32 sclk = rdev->pm.current_sclk; 242 u32 prescale = 0; 243 u32 nm; 244 u8 n, m, loop; 245 int i2c_clock; 246 247 switch (rdev->family) { 248 case CHIP_R100: 249 case CHIP_RV100: 250 case CHIP_RS100: 251 case CHIP_RV200: 252 case CHIP_RS200: 253 case CHIP_R200: 254 case CHIP_RV250: 255 case CHIP_RS300: 256 case CHIP_RV280: 257 case CHIP_R300: 258 case CHIP_R350: 259 case CHIP_RV350: 260 i2c_clock = 60; 261 nm = (sclk * 10) / (i2c_clock * 4); 262 for (loop = 1; loop < 255; loop++) { 263 if ((nm / loop) < loop) 264 break; 265 } 266 n = loop - 1; 267 m = loop - 2; 268 prescale = m | (n << 8); 269 break; 270 case CHIP_RV380: 271 case CHIP_RS400: 272 case CHIP_RS480: 273 case CHIP_R420: 274 case CHIP_R423: 275 case CHIP_RV410: 276 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 277 break; 278 case CHIP_RS600: 279 case CHIP_RS690: 280 case CHIP_RS740: 281 /* todo */ 282 break; 283 case CHIP_RV515: 284 case CHIP_R520: 285 case CHIP_RV530: 286 case CHIP_RV560: 287 case CHIP_RV570: 288 case CHIP_R580: 289 i2c_clock = 50; 290 if (rdev->family == CHIP_R520) 291 prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); 292 else 293 prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; 294 break; 295 case CHIP_R600: 296 case CHIP_RV610: 297 case CHIP_RV630: 298 case CHIP_RV670: 299 /* todo */ 300 break; 301 case CHIP_RV620: 302 case CHIP_RV635: 303 case CHIP_RS780: 304 case CHIP_RS880: 305 case CHIP_RV770: 306 case CHIP_RV730: 307 case CHIP_RV710: 308 case CHIP_RV740: 309 /* todo */ 310 break; 311 case CHIP_CEDAR: 312 case CHIP_REDWOOD: 313 case CHIP_JUNIPER: 314 case CHIP_CYPRESS: 315 case CHIP_HEMLOCK: 316 /* todo */ 317 break; 318 default: 319 DRM_ERROR("i2c: unhandled radeon chip\n"); 320 break; 321 } 322 return prescale; 323} 324 325 326/* hw i2c engine for r1xx-4xx hardware 327 * hw can buffer up to 15 bytes 328 */ 329static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 330 struct i2c_msg *msgs, int num) 331{ 332 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 333 struct radeon_device *rdev = i2c->dev->dev_private; 334 struct radeon_i2c_bus_rec *rec = &i2c->rec; 335 struct i2c_msg *p; 336 int i, j, k, ret = num; 337 u32 prescale; 338 u32 i2c_cntl_0, i2c_cntl_1, i2c_data; 339 u32 tmp, reg; 340 341 mutex_lock(&rdev->dc_hw_i2c_mutex); 342 /* take the pm lock since we need a constant sclk */ 343 mutex_lock(&rdev->pm.mutex); 344 345 prescale = radeon_get_i2c_prescale(rdev); 346 347 reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | 348 RADEON_I2C_DRIVE_EN | 349 RADEON_I2C_START | 350 RADEON_I2C_STOP | 351 RADEON_I2C_GO); 352 353 if (rdev->is_atom_bios) { 354 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 355 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 356 } 357 358 if (rec->mm_i2c) { 359 i2c_cntl_0 = RADEON_I2C_CNTL_0; 360 i2c_cntl_1 = RADEON_I2C_CNTL_1; 361 i2c_data = RADEON_I2C_DATA; 362 } else { 363 i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; 364 i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; 365 i2c_data = RADEON_DVI_I2C_DATA; 366 367 switch (rdev->family) { 368 case CHIP_R100: 369 case CHIP_RV100: 370 case CHIP_RS100: 371 case CHIP_RV200: 372 case CHIP_RS200: 373 case CHIP_RS300: 374 switch (rec->mask_clk_reg) { 375 case RADEON_GPIO_DVI_DDC: 376 /* no gpio select bit */ 377 break; 378 default: 379 DRM_ERROR("gpio not supported with hw i2c\n"); 380 ret = -EINVAL; 381 goto done; 382 } 383 break; 384 case CHIP_R200: 385 /* only bit 4 on r200 */ 386 switch (rec->mask_clk_reg) { 387 case RADEON_GPIO_DVI_DDC: 388 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 389 break; 390 case RADEON_GPIO_MONID: 391 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 392 break; 393 default: 394 DRM_ERROR("gpio not supported with hw i2c\n"); 395 ret = -EINVAL; 396 goto done; 397 } 398 break; 399 case CHIP_RV250: 400 case CHIP_RV280: 401 /* bits 3 and 4 */ 402 switch (rec->mask_clk_reg) { 403 case RADEON_GPIO_DVI_DDC: 404 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 405 break; 406 case RADEON_GPIO_VGA_DDC: 407 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 408 break; 409 case RADEON_GPIO_CRT2_DDC: 410 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 411 break; 412 default: 413 DRM_ERROR("gpio not supported with hw i2c\n"); 414 ret = -EINVAL; 415 goto done; 416 } 417 break; 418 case CHIP_R300: 419 case CHIP_R350: 420 /* only bit 4 on r300/r350 */ 421 switch (rec->mask_clk_reg) { 422 case RADEON_GPIO_VGA_DDC: 423 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 424 break; 425 case RADEON_GPIO_DVI_DDC: 426 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 427 break; 428 default: 429 DRM_ERROR("gpio not supported with hw i2c\n"); 430 ret = -EINVAL; 431 goto done; 432 } 433 break; 434 case CHIP_RV350: 435 case CHIP_RV380: 436 case CHIP_R420: 437 case CHIP_R423: 438 case CHIP_RV410: 439 case CHIP_RS400: 440 case CHIP_RS480: 441 /* bits 3 and 4 */ 442 switch (rec->mask_clk_reg) { 443 case RADEON_GPIO_VGA_DDC: 444 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); 445 break; 446 case RADEON_GPIO_DVI_DDC: 447 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); 448 break; 449 case RADEON_GPIO_MONID: 450 reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); 451 break; 452 default: 453 DRM_ERROR("gpio not supported with hw i2c\n"); 454 ret = -EINVAL; 455 goto done; 456 } 457 break; 458 default: 459 DRM_ERROR("unsupported asic\n"); 460 ret = -EINVAL; 461 goto done; 462 break; 463 } 464 } 465 466 /* check for bus probe */ 467 p = &msgs[0]; 468 if ((num == 1) && (p->len == 0)) { 469 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 470 RADEON_I2C_NACK | 471 RADEON_I2C_HALT | 472 RADEON_I2C_SOFT_RST)); 473 WREG32(i2c_data, (p->addr << 1) & 0xff); 474 WREG32(i2c_data, 0); 475 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 476 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 477 RADEON_I2C_EN | 478 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 479 WREG32(i2c_cntl_0, reg); 480 for (k = 0; k < 32; k++) { 481 udelay(10); 482 tmp = RREG32(i2c_cntl_0); 483 if (tmp & RADEON_I2C_GO) 484 continue; 485 tmp = RREG32(i2c_cntl_0); 486 if (tmp & RADEON_I2C_DONE) 487 break; 488 else { 489 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 490 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 491 ret = -EIO; 492 goto done; 493 } 494 } 495 goto done; 496 } 497 498 for (i = 0; i < num; i++) { 499 p = &msgs[i]; 500 for (j = 0; j < p->len; j++) { 501 if (p->flags & I2C_M_RD) { 502 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 503 RADEON_I2C_NACK | 504 RADEON_I2C_HALT | 505 RADEON_I2C_SOFT_RST)); 506 WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); 507 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 508 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 509 RADEON_I2C_EN | 510 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 511 WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); 512 for (k = 0; k < 32; k++) { 513 udelay(10); 514 tmp = RREG32(i2c_cntl_0); 515 if (tmp & RADEON_I2C_GO) 516 continue; 517 tmp = RREG32(i2c_cntl_0); 518 if (tmp & RADEON_I2C_DONE) 519 break; 520 else { 521 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 522 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 523 ret = -EIO; 524 goto done; 525 } 526 } 527 p->buf[j] = RREG32(i2c_data) & 0xff; 528 } else { 529 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 530 RADEON_I2C_NACK | 531 RADEON_I2C_HALT | 532 RADEON_I2C_SOFT_RST)); 533 WREG32(i2c_data, (p->addr << 1) & 0xff); 534 WREG32(i2c_data, p->buf[j]); 535 WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | 536 (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | 537 RADEON_I2C_EN | 538 (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); 539 WREG32(i2c_cntl_0, reg); 540 for (k = 0; k < 32; k++) { 541 udelay(10); 542 tmp = RREG32(i2c_cntl_0); 543 if (tmp & RADEON_I2C_GO) 544 continue; 545 tmp = RREG32(i2c_cntl_0); 546 if (tmp & RADEON_I2C_DONE) 547 break; 548 else { 549 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 550 WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); 551 ret = -EIO; 552 goto done; 553 } 554 } 555 } 556 } 557 } 558 559done: 560 WREG32(i2c_cntl_0, 0); 561 WREG32(i2c_cntl_1, 0); 562 WREG32(i2c_cntl_0, (RADEON_I2C_DONE | 563 RADEON_I2C_NACK | 564 RADEON_I2C_HALT | 565 RADEON_I2C_SOFT_RST)); 566 567 if (rdev->is_atom_bios) { 568 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 569 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 570 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 571 } 572 573 mutex_unlock(&rdev->pm.mutex); 574 mutex_unlock(&rdev->dc_hw_i2c_mutex); 575 576 return ret; 577} 578 579/* hw i2c engine for r5xx hardware 580 * hw can buffer up to 15 bytes 581 */ 582static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 583 struct i2c_msg *msgs, int num) 584{ 585 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 586 struct radeon_device *rdev = i2c->dev->dev_private; 587 struct radeon_i2c_bus_rec *rec = &i2c->rec; 588 struct i2c_msg *p; 589 int i, j, remaining, current_count, buffer_offset, ret = num; 590 u32 prescale; 591 u32 tmp, reg; 592 u32 saved1, saved2; 593 594 mutex_lock(&rdev->dc_hw_i2c_mutex); 595 /* take the pm lock since we need a constant sclk */ 596 mutex_lock(&rdev->pm.mutex); 597 598 prescale = radeon_get_i2c_prescale(rdev); 599 600 /* clear gpio mask bits */ 601 tmp = RREG32(rec->mask_clk_reg); 602 tmp &= ~rec->mask_clk_mask; 603 WREG32(rec->mask_clk_reg, tmp); 604 tmp = RREG32(rec->mask_clk_reg); 605 606 tmp = RREG32(rec->mask_data_reg); 607 tmp &= ~rec->mask_data_mask; 608 WREG32(rec->mask_data_reg, tmp); 609 tmp = RREG32(rec->mask_data_reg); 610 611 /* clear pin values */ 612 tmp = RREG32(rec->a_clk_reg); 613 tmp &= ~rec->a_clk_mask; 614 WREG32(rec->a_clk_reg, tmp); 615 tmp = RREG32(rec->a_clk_reg); 616 617 tmp = RREG32(rec->a_data_reg); 618 tmp &= ~rec->a_data_mask; 619 WREG32(rec->a_data_reg, tmp); 620 tmp = RREG32(rec->a_data_reg); 621 622 /* set the pins to input */ 623 tmp = RREG32(rec->en_clk_reg); 624 tmp &= ~rec->en_clk_mask; 625 WREG32(rec->en_clk_reg, tmp); 626 tmp = RREG32(rec->en_clk_reg); 627 628 tmp = RREG32(rec->en_data_reg); 629 tmp &= ~rec->en_data_mask; 630 WREG32(rec->en_data_reg, tmp); 631 tmp = RREG32(rec->en_data_reg); 632 633 /* */ 634 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 635 WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); 636 saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); 637 saved2 = RREG32(0x494); 638 WREG32(0x494, saved2 | 0x1); 639 640 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); 641 for (i = 0; i < 50; i++) { 642 udelay(1); 643 if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) 644 break; 645 } 646 if (i == 50) { 647 DRM_ERROR("failed to get i2c bus\n"); 648 ret = -EBUSY; 649 goto done; 650 } 651 652 reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; 653 switch (rec->mask_clk_reg) { 654 case AVIVO_DC_GPIO_DDC1_MASK: 655 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); 656 break; 657 case AVIVO_DC_GPIO_DDC2_MASK: 658 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); 659 break; 660 case AVIVO_DC_GPIO_DDC3_MASK: 661 reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); 662 break; 663 default: 664 DRM_ERROR("gpio not supported with hw i2c\n"); 665 ret = -EINVAL; 666 goto done; 667 } 668 669 /* check for bus probe */ 670 p = &msgs[0]; 671 if ((num == 1) && (p->len == 0)) { 672 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 673 AVIVO_DC_I2C_NACK | 674 AVIVO_DC_I2C_HALT)); 675 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 676 udelay(1); 677 WREG32(AVIVO_DC_I2C_RESET, 0); 678 679 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 680 WREG32(AVIVO_DC_I2C_DATA, 0); 681 682 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 683 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 684 AVIVO_DC_I2C_DATA_COUNT(1) | 685 (prescale << 16))); 686 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 687 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 688 for (j = 0; j < 200; j++) { 689 udelay(50); 690 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 691 if (tmp & AVIVO_DC_I2C_GO) 692 continue; 693 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 694 if (tmp & AVIVO_DC_I2C_DONE) 695 break; 696 else { 697 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 698 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 699 ret = -EIO; 700 goto done; 701 } 702 } 703 goto done; 704 } 705 706 for (i = 0; i < num; i++) { 707 p = &msgs[i]; 708 remaining = p->len; 709 buffer_offset = 0; 710 if (p->flags & I2C_M_RD) { 711 while (remaining) { 712 if (remaining > 15) 713 current_count = 15; 714 else 715 current_count = remaining; 716 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 717 AVIVO_DC_I2C_NACK | 718 AVIVO_DC_I2C_HALT)); 719 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 720 udelay(1); 721 WREG32(AVIVO_DC_I2C_RESET, 0); 722 723 WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); 724 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 725 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 726 AVIVO_DC_I2C_DATA_COUNT(current_count) | 727 (prescale << 16))); 728 WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); 729 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 730 for (j = 0; j < 200; j++) { 731 udelay(50); 732 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 733 if (tmp & AVIVO_DC_I2C_GO) 734 continue; 735 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 736 if (tmp & AVIVO_DC_I2C_DONE) 737 break; 738 else { 739 DRM_DEBUG("i2c read error 0x%08x\n", tmp); 740 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 741 ret = -EIO; 742 goto done; 743 } 744 } 745 for (j = 0; j < current_count; j++) 746 p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; 747 remaining -= current_count; 748 buffer_offset += current_count; 749 } 750 } else { 751 while (remaining) { 752 if (remaining > 15) 753 current_count = 15; 754 else 755 current_count = remaining; 756 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 757 AVIVO_DC_I2C_NACK | 758 AVIVO_DC_I2C_HALT)); 759 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 760 udelay(1); 761 WREG32(AVIVO_DC_I2C_RESET, 0); 762 763 WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); 764 for (j = 0; j < current_count; j++) 765 WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); 766 767 WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); 768 WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | 769 AVIVO_DC_I2C_DATA_COUNT(current_count) | 770 (prescale << 16))); 771 WREG32(AVIVO_DC_I2C_CONTROL1, reg); 772 WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); 773 for (j = 0; j < 200; j++) { 774 udelay(50); 775 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 776 if (tmp & AVIVO_DC_I2C_GO) 777 continue; 778 tmp = RREG32(AVIVO_DC_I2C_STATUS1); 779 if (tmp & AVIVO_DC_I2C_DONE) 780 break; 781 else { 782 DRM_DEBUG("i2c write error 0x%08x\n", tmp); 783 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); 784 ret = -EIO; 785 goto done; 786 } 787 } 788 remaining -= current_count; 789 buffer_offset += current_count; 790 } 791 } 792 } 793 794done: 795 WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | 796 AVIVO_DC_I2C_NACK | 797 AVIVO_DC_I2C_HALT)); 798 WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); 799 udelay(1); 800 WREG32(AVIVO_DC_I2C_RESET, 0); 801 802 WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); 803 WREG32(AVIVO_DC_I2C_CONTROL1, saved1); 804 WREG32(0x494, saved2); 805 tmp = RREG32(RADEON_BIOS_6_SCRATCH); 806 tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; 807 WREG32(RADEON_BIOS_6_SCRATCH, tmp); 808 809 mutex_unlock(&rdev->pm.mutex); 810 mutex_unlock(&rdev->dc_hw_i2c_mutex); 811 812 return ret; 813} 814 815static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, 816 struct i2c_msg *msgs, int num) 817{ 818 struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); 819 struct radeon_device *rdev = i2c->dev->dev_private; 820 struct radeon_i2c_bus_rec *rec = &i2c->rec; 821 int ret = 0; 822 823 mutex_lock(&i2c->mutex); 824 825 switch (rdev->family) { 826 case CHIP_R100: 827 case CHIP_RV100: 828 case CHIP_RS100: 829 case CHIP_RV200: 830 case CHIP_RS200: 831 case CHIP_R200: 832 case CHIP_RV250: 833 case CHIP_RS300: 834 case CHIP_RV280: 835 case CHIP_R300: 836 case CHIP_R350: 837 case CHIP_RV350: 838 case CHIP_RV380: 839 case CHIP_R420: 840 case CHIP_R423: 841 case CHIP_RV410: 842 case CHIP_RS400: 843 case CHIP_RS480: 844 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 845 break; 846 case CHIP_RS600: 847 case CHIP_RS690: 848 case CHIP_RS740: 849 /* XXX fill in hw i2c implementation */ 850 break; 851 case CHIP_RV515: 852 case CHIP_R520: 853 case CHIP_RV530: 854 case CHIP_RV560: 855 case CHIP_RV570: 856 case CHIP_R580: 857 if (rec->mm_i2c) 858 ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); 859 else 860 ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); 861 break; 862 case CHIP_R600: 863 case CHIP_RV610: 864 case CHIP_RV630: 865 case CHIP_RV670: 866 /* XXX fill in hw i2c implementation */ 867 break; 868 case CHIP_RV620: 869 case CHIP_RV635: 870 case CHIP_RS780: 871 case CHIP_RS880: 872 case CHIP_RV770: 873 case CHIP_RV730: 874 case CHIP_RV710: 875 case CHIP_RV740: 876 /* XXX fill in hw i2c implementation */ 877 break; 878 case CHIP_CEDAR: 879 case CHIP_REDWOOD: 880 case CHIP_JUNIPER: 881 case CHIP_CYPRESS: 882 case CHIP_HEMLOCK: 883 /* XXX fill in hw i2c implementation */ 884 break; 885 default: 886 DRM_ERROR("i2c: unhandled radeon chip\n"); 887 ret = -EIO; 888 break; 889 } 890 891 mutex_unlock(&i2c->mutex); 892 893 return ret; 894} 895 896static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) 897{ 898 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 899} 900 901static const struct i2c_algorithm radeon_i2c_algo = { 902 .master_xfer = radeon_hw_i2c_xfer, 903 .functionality = radeon_hw_i2c_func, 904}; 905 906static const struct i2c_algorithm radeon_atom_i2c_algo = { 907 .master_xfer = radeon_atom_hw_i2c_xfer, 908 .functionality = radeon_atom_hw_i2c_func, 909}; 910 911struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, 912 struct radeon_i2c_bus_rec *rec, 913 const char *name) 914{ 915 struct radeon_device *rdev = dev->dev_private; 916 struct radeon_i2c_chan *i2c; 917 int ret; 918 919 /* don't add the mm_i2c bus unless hw_i2c is enabled */ 920 if (rec->mm_i2c && (radeon_hw_i2c == 0)) 921 return NULL; 922 923 i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); 924 if (i2c == NULL) 925 return NULL; 926 927 i2c->rec = *rec; 928 i2c->adapter.owner = THIS_MODULE; 929 i2c->adapter.class = I2C_CLASS_DDC; 930 i2c->adapter.dev.parent = &dev->pdev->dev; 931 i2c->dev = dev; 932 i2c_set_adapdata(&i2c->adapter, i2c); 933 mutex_init(&i2c->mutex); 934 if (rec->mm_i2c || 935 (rec->hw_capable && 936 radeon_hw_i2c && 937 ((rdev->family <= CHIP_RS480) || 938 ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { 939 /* set the radeon hw i2c adapter */ 940 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 941 "Radeon i2c hw bus %s", name); 942 i2c->adapter.algo = &radeon_i2c_algo; 943 ret = i2c_add_adapter(&i2c->adapter); 944 if (ret) 945 goto out_free; 946 } else if (rec->hw_capable && 947 radeon_hw_i2c && 948 ASIC_IS_DCE3(rdev)) { 949 /* hw i2c using atom */ 950 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 951 "Radeon i2c hw bus %s", name); 952 i2c->adapter.algo = &radeon_atom_i2c_algo; 953 ret = i2c_add_adapter(&i2c->adapter); 954 if (ret) 955 goto out_free; 956 } else { 957 /* set the radeon bit adapter */ 958 snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), 959 "Radeon i2c bit bus %s", name); 960 i2c->adapter.algo_data = &i2c->bit; 961 i2c->bit.pre_xfer = pre_xfer; 962 i2c->bit.post_xfer = post_xfer; 963 i2c->bit.setsda = set_data; 964 i2c->bit.setscl = set_clock; 965 i2c->bit.getsda = get_data; 966 i2c->bit.getscl = get_clock; 967 i2c->bit.udelay = 10; 968 i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ 969 i2c->bit.data = i2c; 970 ret = i2c_bit_add_bus(&i2c->adapter); 971 if (ret) { 972 DRM_ERROR("Failed to register bit i2c %s\n", name); 973 goto out_free; 974 } 975 } 976 977 return i2c; 978out_free: 979 kfree(i2c); 980 return NULL; 981 982} 983 984void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) 985{ 986 if (!i2c) 987 return; 988 WARN_ON(i2c->has_aux); 989 i2c_del_adapter(&i2c->adapter); 990 kfree(i2c); 991} 992 993/* Add the default buses */ 994void radeon_i2c_init(struct radeon_device *rdev) 995{ 996 if (radeon_hw_i2c) 997 DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); 998 999 if (rdev->is_atom_bios) 1000 radeon_atombios_i2c_init(rdev); 1001 else 1002 radeon_combios_i2c_init(rdev); 1003} 1004 1005/* remove all the buses */ 1006void radeon_i2c_fini(struct radeon_device *rdev) 1007{ 1008 int i; 1009 1010 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1011 if (rdev->i2c_bus[i]) { 1012 radeon_i2c_destroy(rdev->i2c_bus[i]); 1013 rdev->i2c_bus[i] = NULL; 1014 } 1015 } 1016} 1017 1018/* Add additional buses */ 1019void radeon_i2c_add(struct radeon_device *rdev, 1020 struct radeon_i2c_bus_rec *rec, 1021 const char *name) 1022{ 1023 struct drm_device *dev = rdev->ddev; 1024 int i; 1025 1026 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1027 if (!rdev->i2c_bus[i]) { 1028 rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); 1029 return; 1030 } 1031 } 1032} 1033 1034/* looks up bus based on id */ 1035struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, 1036 struct radeon_i2c_bus_rec *i2c_bus) 1037{ 1038 int i; 1039 1040 for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { 1041 if (rdev->i2c_bus[i] && 1042 (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { 1043 return rdev->i2c_bus[i]; 1044 } 1045 } 1046 return NULL; 1047} 1048 1049void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, 1050 u8 slave_addr, 1051 u8 addr, 1052 u8 *val) 1053{ 1054 u8 out_buf[2]; 1055 u8 in_buf[2]; 1056 struct i2c_msg msgs[] = { 1057 { 1058 .addr = slave_addr, 1059 .flags = 0, 1060 .len = 1, 1061 .buf = out_buf, 1062 }, 1063 { 1064 .addr = slave_addr, 1065 .flags = I2C_M_RD, 1066 .len = 1, 1067 .buf = in_buf, 1068 } 1069 }; 1070 1071 out_buf[0] = addr; 1072 out_buf[1] = 0; 1073 1074 if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { 1075 *val = in_buf[0]; 1076 DRM_DEBUG("val = 0x%02x\n", *val); 1077 } else { 1078 DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", 1079 addr, *val); 1080 } 1081} 1082 1083void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, 1084 u8 slave_addr, 1085 u8 addr, 1086 u8 val) 1087{ 1088 uint8_t out_buf[2]; 1089 struct i2c_msg msg = { 1090 .addr = slave_addr, 1091 .flags = 0, 1092 .len = 2, 1093 .buf = out_buf, 1094 }; 1095 1096 out_buf[0] = addr; 1097 out_buf[1] = val; 1098 1099 if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) 1100 DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", 1101 addr, val); 1102} 1103 1104/* ddc router switching */ 1105void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) 1106{ 1107 u8 val; 1108 1109 if (!radeon_connector->router.ddc_valid) 1110 return; 1111 1112 if (!radeon_connector->router_bus) 1113 return; 1114 1115 radeon_i2c_get_byte(radeon_connector->router_bus, 1116 radeon_connector->router.i2c_addr, 1117 0x3, &val); 1118 val &= ~radeon_connector->router.ddc_mux_control_pin; 1119 radeon_i2c_put_byte(radeon_connector->router_bus, 1120 radeon_connector->router.i2c_addr, 1121 0x3, val); 1122 radeon_i2c_get_byte(radeon_connector->router_bus, 1123 radeon_connector->router.i2c_addr, 1124 0x1, &val); 1125 val &= ~radeon_connector->router.ddc_mux_control_pin; 1126 val |= radeon_connector->router.ddc_mux_state; 1127 radeon_i2c_put_byte(radeon_connector->router_bus, 1128 radeon_connector->router.i2c_addr, 1129 0x1, val); 1130} 1131 1132/* clock/data router switching */ 1133void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) 1134{ 1135 u8 val; 1136 1137 if (!radeon_connector->router.cd_valid) 1138 return; 1139 1140 if (!radeon_connector->router_bus) 1141 return; 1142 1143 radeon_i2c_get_byte(radeon_connector->router_bus, 1144 radeon_connector->router.i2c_addr, 1145 0x3, &val); 1146 val &= ~radeon_connector->router.cd_mux_control_pin; 1147 radeon_i2c_put_byte(radeon_connector->router_bus, 1148 radeon_connector->router.i2c_addr, 1149 0x3, val); 1150 radeon_i2c_get_byte(radeon_connector->router_bus, 1151 radeon_connector->router.i2c_addr, 1152 0x1, &val); 1153 val &= ~radeon_connector->router.cd_mux_control_pin; 1154 val |= radeon_connector->router.cd_mux_state; 1155 radeon_i2c_put_byte(radeon_connector->router_bus, 1156 radeon_connector->router.i2c_addr, 1157 0x1, val); 1158} 1159 1160