1/* 2 * Copyright 2004 ATI Technologies Inc., Markham, Ontario 3 * Copyright 2007-8 Advanced Micro Devices, Inc. 4 * Copyright 2008 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 */ 27 28#include <linux/pci.h> 29 30#include <drm/drm_device.h> 31#include <drm/radeon_drm.h> 32 33#include "radeon.h" 34#include "atom.h" 35 36#ifdef CONFIG_PPC_PMAC 37/* not sure which of these are needed */ 38#include <asm/machdep.h> 39#include <asm/pmac_feature.h> 40#include <asm/prom.h> 41#endif /* CONFIG_PPC_PMAC */ 42 43/* from radeon_legacy_encoder.c */ 44extern void 45radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, 46 uint32_t supported_device); 47 48/* old legacy ATI BIOS routines */ 49 50/* COMBIOS table offsets */ 51enum radeon_combios_table_offset { 52 /* absolute offset tables */ 53 COMBIOS_ASIC_INIT_1_TABLE, 54 COMBIOS_BIOS_SUPPORT_TABLE, 55 COMBIOS_DAC_PROGRAMMING_TABLE, 56 COMBIOS_MAX_COLOR_DEPTH_TABLE, 57 COMBIOS_CRTC_INFO_TABLE, 58 COMBIOS_PLL_INFO_TABLE, 59 COMBIOS_TV_INFO_TABLE, 60 COMBIOS_DFP_INFO_TABLE, 61 COMBIOS_HW_CONFIG_INFO_TABLE, 62 COMBIOS_MULTIMEDIA_INFO_TABLE, 63 COMBIOS_TV_STD_PATCH_TABLE, 64 COMBIOS_LCD_INFO_TABLE, 65 COMBIOS_MOBILE_INFO_TABLE, 66 COMBIOS_PLL_INIT_TABLE, 67 COMBIOS_MEM_CONFIG_TABLE, 68 COMBIOS_SAVE_MASK_TABLE, 69 COMBIOS_HARDCODED_EDID_TABLE, 70 COMBIOS_ASIC_INIT_2_TABLE, 71 COMBIOS_CONNECTOR_INFO_TABLE, 72 COMBIOS_DYN_CLK_1_TABLE, 73 COMBIOS_RESERVED_MEM_TABLE, 74 COMBIOS_EXT_TMDS_INFO_TABLE, 75 COMBIOS_MEM_CLK_INFO_TABLE, 76 COMBIOS_EXT_DAC_INFO_TABLE, 77 COMBIOS_MISC_INFO_TABLE, 78 COMBIOS_CRT_INFO_TABLE, 79 COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE, 80 COMBIOS_COMPONENT_VIDEO_INFO_TABLE, 81 COMBIOS_FAN_SPEED_INFO_TABLE, 82 COMBIOS_OVERDRIVE_INFO_TABLE, 83 COMBIOS_OEM_INFO_TABLE, 84 COMBIOS_DYN_CLK_2_TABLE, 85 COMBIOS_POWER_CONNECTOR_INFO_TABLE, 86 COMBIOS_I2C_INFO_TABLE, 87 /* relative offset tables */ 88 COMBIOS_ASIC_INIT_3_TABLE, /* offset from misc info */ 89 COMBIOS_ASIC_INIT_4_TABLE, /* offset from misc info */ 90 COMBIOS_DETECTED_MEM_TABLE, /* offset from misc info */ 91 COMBIOS_ASIC_INIT_5_TABLE, /* offset from misc info */ 92 COMBIOS_RAM_RESET_TABLE, /* offset from mem config */ 93 COMBIOS_POWERPLAY_INFO_TABLE, /* offset from mobile info */ 94 COMBIOS_GPIO_INFO_TABLE, /* offset from mobile info */ 95 COMBIOS_LCD_DDC_INFO_TABLE, /* offset from mobile info */ 96 COMBIOS_TMDS_POWER_TABLE, /* offset from mobile info */ 97 COMBIOS_TMDS_POWER_ON_TABLE, /* offset from tmds power */ 98 COMBIOS_TMDS_POWER_OFF_TABLE, /* offset from tmds power */ 99}; 100 101enum radeon_combios_ddc { 102 DDC_NONE_DETECTED, 103 DDC_MONID, 104 DDC_DVI, 105 DDC_VGA, 106 DDC_CRT2, 107 DDC_LCD, 108 DDC_GPIO, 109}; 110 111enum radeon_combios_connector { 112 CONNECTOR_NONE_LEGACY, 113 CONNECTOR_PROPRIETARY_LEGACY, 114 CONNECTOR_CRT_LEGACY, 115 CONNECTOR_DVI_I_LEGACY, 116 CONNECTOR_DVI_D_LEGACY, 117 CONNECTOR_CTV_LEGACY, 118 CONNECTOR_STV_LEGACY, 119 CONNECTOR_UNSUPPORTED_LEGACY 120}; 121 122static const int legacy_connector_convert[] = { 123 DRM_MODE_CONNECTOR_Unknown, 124 DRM_MODE_CONNECTOR_DVID, 125 DRM_MODE_CONNECTOR_VGA, 126 DRM_MODE_CONNECTOR_DVII, 127 DRM_MODE_CONNECTOR_DVID, 128 DRM_MODE_CONNECTOR_Composite, 129 DRM_MODE_CONNECTOR_SVIDEO, 130 DRM_MODE_CONNECTOR_Unknown, 131}; 132 133static uint16_t combios_get_table_offset(struct drm_device *dev, 134 enum radeon_combios_table_offset table) 135{ 136 struct radeon_device *rdev = dev->dev_private; 137 int rev, size; 138 uint16_t offset = 0, check_offset; 139 140 if (!rdev->bios) 141 return 0; 142 143 switch (table) { 144 /* absolute offset tables */ 145 case COMBIOS_ASIC_INIT_1_TABLE: 146 check_offset = 0xc; 147 break; 148 case COMBIOS_BIOS_SUPPORT_TABLE: 149 check_offset = 0x14; 150 break; 151 case COMBIOS_DAC_PROGRAMMING_TABLE: 152 check_offset = 0x2a; 153 break; 154 case COMBIOS_MAX_COLOR_DEPTH_TABLE: 155 check_offset = 0x2c; 156 break; 157 case COMBIOS_CRTC_INFO_TABLE: 158 check_offset = 0x2e; 159 break; 160 case COMBIOS_PLL_INFO_TABLE: 161 check_offset = 0x30; 162 break; 163 case COMBIOS_TV_INFO_TABLE: 164 check_offset = 0x32; 165 break; 166 case COMBIOS_DFP_INFO_TABLE: 167 check_offset = 0x34; 168 break; 169 case COMBIOS_HW_CONFIG_INFO_TABLE: 170 check_offset = 0x36; 171 break; 172 case COMBIOS_MULTIMEDIA_INFO_TABLE: 173 check_offset = 0x38; 174 break; 175 case COMBIOS_TV_STD_PATCH_TABLE: 176 check_offset = 0x3e; 177 break; 178 case COMBIOS_LCD_INFO_TABLE: 179 check_offset = 0x40; 180 break; 181 case COMBIOS_MOBILE_INFO_TABLE: 182 check_offset = 0x42; 183 break; 184 case COMBIOS_PLL_INIT_TABLE: 185 check_offset = 0x46; 186 break; 187 case COMBIOS_MEM_CONFIG_TABLE: 188 check_offset = 0x48; 189 break; 190 case COMBIOS_SAVE_MASK_TABLE: 191 check_offset = 0x4a; 192 break; 193 case COMBIOS_HARDCODED_EDID_TABLE: 194 check_offset = 0x4c; 195 break; 196 case COMBIOS_ASIC_INIT_2_TABLE: 197 check_offset = 0x4e; 198 break; 199 case COMBIOS_CONNECTOR_INFO_TABLE: 200 check_offset = 0x50; 201 break; 202 case COMBIOS_DYN_CLK_1_TABLE: 203 check_offset = 0x52; 204 break; 205 case COMBIOS_RESERVED_MEM_TABLE: 206 check_offset = 0x54; 207 break; 208 case COMBIOS_EXT_TMDS_INFO_TABLE: 209 check_offset = 0x58; 210 break; 211 case COMBIOS_MEM_CLK_INFO_TABLE: 212 check_offset = 0x5a; 213 break; 214 case COMBIOS_EXT_DAC_INFO_TABLE: 215 check_offset = 0x5c; 216 break; 217 case COMBIOS_MISC_INFO_TABLE: 218 check_offset = 0x5e; 219 break; 220 case COMBIOS_CRT_INFO_TABLE: 221 check_offset = 0x60; 222 break; 223 case COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE: 224 check_offset = 0x62; 225 break; 226 case COMBIOS_COMPONENT_VIDEO_INFO_TABLE: 227 check_offset = 0x64; 228 break; 229 case COMBIOS_FAN_SPEED_INFO_TABLE: 230 check_offset = 0x66; 231 break; 232 case COMBIOS_OVERDRIVE_INFO_TABLE: 233 check_offset = 0x68; 234 break; 235 case COMBIOS_OEM_INFO_TABLE: 236 check_offset = 0x6a; 237 break; 238 case COMBIOS_DYN_CLK_2_TABLE: 239 check_offset = 0x6c; 240 break; 241 case COMBIOS_POWER_CONNECTOR_INFO_TABLE: 242 check_offset = 0x6e; 243 break; 244 case COMBIOS_I2C_INFO_TABLE: 245 check_offset = 0x70; 246 break; 247 /* relative offset tables */ 248 case COMBIOS_ASIC_INIT_3_TABLE: /* offset from misc info */ 249 check_offset = 250 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 251 if (check_offset) { 252 rev = RBIOS8(check_offset); 253 if (rev > 0) { 254 check_offset = RBIOS16(check_offset + 0x3); 255 if (check_offset) 256 offset = check_offset; 257 } 258 } 259 break; 260 case COMBIOS_ASIC_INIT_4_TABLE: /* offset from misc info */ 261 check_offset = 262 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 263 if (check_offset) { 264 rev = RBIOS8(check_offset); 265 if (rev > 0) { 266 check_offset = RBIOS16(check_offset + 0x5); 267 if (check_offset) 268 offset = check_offset; 269 } 270 } 271 break; 272 case COMBIOS_DETECTED_MEM_TABLE: /* offset from misc info */ 273 check_offset = 274 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 275 if (check_offset) { 276 rev = RBIOS8(check_offset); 277 if (rev > 0) { 278 check_offset = RBIOS16(check_offset + 0x7); 279 if (check_offset) 280 offset = check_offset; 281 } 282 } 283 break; 284 case COMBIOS_ASIC_INIT_5_TABLE: /* offset from misc info */ 285 check_offset = 286 combios_get_table_offset(dev, COMBIOS_MISC_INFO_TABLE); 287 if (check_offset) { 288 rev = RBIOS8(check_offset); 289 if (rev == 2) { 290 check_offset = RBIOS16(check_offset + 0x9); 291 if (check_offset) 292 offset = check_offset; 293 } 294 } 295 break; 296 case COMBIOS_RAM_RESET_TABLE: /* offset from mem config */ 297 check_offset = 298 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 299 if (check_offset) { 300 while (RBIOS8(check_offset++)); 301 check_offset += 2; 302 if (check_offset) 303 offset = check_offset; 304 } 305 break; 306 case COMBIOS_POWERPLAY_INFO_TABLE: /* offset from mobile info */ 307 check_offset = 308 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 309 if (check_offset) { 310 check_offset = RBIOS16(check_offset + 0x11); 311 if (check_offset) 312 offset = check_offset; 313 } 314 break; 315 case COMBIOS_GPIO_INFO_TABLE: /* offset from mobile info */ 316 check_offset = 317 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 318 if (check_offset) { 319 check_offset = RBIOS16(check_offset + 0x13); 320 if (check_offset) 321 offset = check_offset; 322 } 323 break; 324 case COMBIOS_LCD_DDC_INFO_TABLE: /* offset from mobile info */ 325 check_offset = 326 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 327 if (check_offset) { 328 check_offset = RBIOS16(check_offset + 0x15); 329 if (check_offset) 330 offset = check_offset; 331 } 332 break; 333 case COMBIOS_TMDS_POWER_TABLE: /* offset from mobile info */ 334 check_offset = 335 combios_get_table_offset(dev, COMBIOS_MOBILE_INFO_TABLE); 336 if (check_offset) { 337 check_offset = RBIOS16(check_offset + 0x17); 338 if (check_offset) 339 offset = check_offset; 340 } 341 break; 342 case COMBIOS_TMDS_POWER_ON_TABLE: /* offset from tmds power */ 343 check_offset = 344 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 345 if (check_offset) { 346 check_offset = RBIOS16(check_offset + 0x2); 347 if (check_offset) 348 offset = check_offset; 349 } 350 break; 351 case COMBIOS_TMDS_POWER_OFF_TABLE: /* offset from tmds power */ 352 check_offset = 353 combios_get_table_offset(dev, COMBIOS_TMDS_POWER_TABLE); 354 if (check_offset) { 355 check_offset = RBIOS16(check_offset + 0x4); 356 if (check_offset) 357 offset = check_offset; 358 } 359 break; 360 default: 361 check_offset = 0; 362 break; 363 } 364 365 size = RBIOS8(rdev->bios_header_start + 0x6); 366 /* check absolute offset tables */ 367 if (table < COMBIOS_ASIC_INIT_3_TABLE && check_offset && check_offset < size) 368 offset = RBIOS16(rdev->bios_header_start + check_offset); 369 370 return offset; 371} 372 373bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev) 374{ 375 int edid_info, size; 376 struct edid *edid; 377 unsigned char *raw; 378 edid_info = combios_get_table_offset(rdev->ddev, COMBIOS_HARDCODED_EDID_TABLE); 379 if (!edid_info) 380 return false; 381 382 raw = rdev->bios + edid_info; 383 size = EDID_LENGTH * (raw[0x7e] + 1); 384 edid = kmalloc(size, GFP_KERNEL); 385 if (edid == NULL) 386 return false; 387 388 memcpy((unsigned char *)edid, raw, size); 389 390 if (!drm_edid_is_valid(edid)) { 391 kfree(edid); 392 return false; 393 } 394 395 rdev->mode_info.bios_hardcoded_edid = edid; 396 rdev->mode_info.bios_hardcoded_edid_size = size; 397 return true; 398} 399 400/* this is used for atom LCDs as well */ 401struct edid * 402radeon_bios_get_hardcoded_edid(struct radeon_device *rdev) 403{ 404 struct edid *edid; 405 406 if (rdev->mode_info.bios_hardcoded_edid) { 407 edid = kmalloc(rdev->mode_info.bios_hardcoded_edid_size, GFP_KERNEL); 408 if (edid) { 409 memcpy((unsigned char *)edid, 410 (unsigned char *)rdev->mode_info.bios_hardcoded_edid, 411 rdev->mode_info.bios_hardcoded_edid_size); 412 return edid; 413 } 414 } 415 return NULL; 416} 417 418static struct radeon_i2c_bus_rec combios_setup_i2c_bus(struct radeon_device *rdev, 419 enum radeon_combios_ddc ddc, 420 u32 clk_mask, 421 u32 data_mask) 422{ 423 struct radeon_i2c_bus_rec i2c; 424 int ddc_line = 0; 425 426 /* ddc id = mask reg 427 * DDC_NONE_DETECTED = none 428 * DDC_DVI = RADEON_GPIO_DVI_DDC 429 * DDC_VGA = RADEON_GPIO_VGA_DDC 430 * DDC_LCD = RADEON_GPIOPAD_MASK 431 * DDC_GPIO = RADEON_MDGPIO_MASK 432 * r1xx 433 * DDC_MONID = RADEON_GPIO_MONID 434 * DDC_CRT2 = RADEON_GPIO_CRT2_DDC 435 * r200 436 * DDC_MONID = RADEON_GPIO_MONID 437 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 438 * r300/r350 439 * DDC_MONID = RADEON_GPIO_DVI_DDC 440 * DDC_CRT2 = RADEON_GPIO_DVI_DDC 441 * rv2xx/rv3xx 442 * DDC_MONID = RADEON_GPIO_MONID 443 * DDC_CRT2 = RADEON_GPIO_MONID 444 * rs3xx/rs4xx 445 * DDC_MONID = RADEON_GPIOPAD_MASK 446 * DDC_CRT2 = RADEON_GPIO_MONID 447 */ 448 switch (ddc) { 449 case DDC_NONE_DETECTED: 450 default: 451 ddc_line = 0; 452 break; 453 case DDC_DVI: 454 ddc_line = RADEON_GPIO_DVI_DDC; 455 break; 456 case DDC_VGA: 457 ddc_line = RADEON_GPIO_VGA_DDC; 458 break; 459 case DDC_LCD: 460 ddc_line = RADEON_GPIOPAD_MASK; 461 break; 462 case DDC_GPIO: 463 ddc_line = RADEON_MDGPIO_MASK; 464 break; 465 case DDC_MONID: 466 if (rdev->family == CHIP_RS300 || 467 rdev->family == CHIP_RS400 || 468 rdev->family == CHIP_RS480) 469 ddc_line = RADEON_GPIOPAD_MASK; 470 else if (rdev->family == CHIP_R300 || 471 rdev->family == CHIP_R350) { 472 ddc_line = RADEON_GPIO_DVI_DDC; 473 ddc = DDC_DVI; 474 } else 475 ddc_line = RADEON_GPIO_MONID; 476 break; 477 case DDC_CRT2: 478 if (rdev->family == CHIP_R200 || 479 rdev->family == CHIP_R300 || 480 rdev->family == CHIP_R350) { 481 ddc_line = RADEON_GPIO_DVI_DDC; 482 ddc = DDC_DVI; 483 } else if (rdev->family == CHIP_RS300 || 484 rdev->family == CHIP_RS400 || 485 rdev->family == CHIP_RS480) 486 ddc_line = RADEON_GPIO_MONID; 487 else if (rdev->family >= CHIP_RV350) { 488 ddc_line = RADEON_GPIO_MONID; 489 ddc = DDC_MONID; 490 } else 491 ddc_line = RADEON_GPIO_CRT2_DDC; 492 break; 493 } 494 495 if (ddc_line == RADEON_GPIOPAD_MASK) { 496 i2c.mask_clk_reg = RADEON_GPIOPAD_MASK; 497 i2c.mask_data_reg = RADEON_GPIOPAD_MASK; 498 i2c.a_clk_reg = RADEON_GPIOPAD_A; 499 i2c.a_data_reg = RADEON_GPIOPAD_A; 500 i2c.en_clk_reg = RADEON_GPIOPAD_EN; 501 i2c.en_data_reg = RADEON_GPIOPAD_EN; 502 i2c.y_clk_reg = RADEON_GPIOPAD_Y; 503 i2c.y_data_reg = RADEON_GPIOPAD_Y; 504 } else if (ddc_line == RADEON_MDGPIO_MASK) { 505 i2c.mask_clk_reg = RADEON_MDGPIO_MASK; 506 i2c.mask_data_reg = RADEON_MDGPIO_MASK; 507 i2c.a_clk_reg = RADEON_MDGPIO_A; 508 i2c.a_data_reg = RADEON_MDGPIO_A; 509 i2c.en_clk_reg = RADEON_MDGPIO_EN; 510 i2c.en_data_reg = RADEON_MDGPIO_EN; 511 i2c.y_clk_reg = RADEON_MDGPIO_Y; 512 i2c.y_data_reg = RADEON_MDGPIO_Y; 513 } else { 514 i2c.mask_clk_reg = ddc_line; 515 i2c.mask_data_reg = ddc_line; 516 i2c.a_clk_reg = ddc_line; 517 i2c.a_data_reg = ddc_line; 518 i2c.en_clk_reg = ddc_line; 519 i2c.en_data_reg = ddc_line; 520 i2c.y_clk_reg = ddc_line; 521 i2c.y_data_reg = ddc_line; 522 } 523 524 if (clk_mask && data_mask) { 525 /* system specific masks */ 526 i2c.mask_clk_mask = clk_mask; 527 i2c.mask_data_mask = data_mask; 528 i2c.a_clk_mask = clk_mask; 529 i2c.a_data_mask = data_mask; 530 i2c.en_clk_mask = clk_mask; 531 i2c.en_data_mask = data_mask; 532 i2c.y_clk_mask = clk_mask; 533 i2c.y_data_mask = data_mask; 534 } else if ((ddc_line == RADEON_GPIOPAD_MASK) || 535 (ddc_line == RADEON_MDGPIO_MASK)) { 536 /* default gpiopad masks */ 537 i2c.mask_clk_mask = (0x20 << 8); 538 i2c.mask_data_mask = 0x80; 539 i2c.a_clk_mask = (0x20 << 8); 540 i2c.a_data_mask = 0x80; 541 i2c.en_clk_mask = (0x20 << 8); 542 i2c.en_data_mask = 0x80; 543 i2c.y_clk_mask = (0x20 << 8); 544 i2c.y_data_mask = 0x80; 545 } else { 546 /* default masks for ddc pads */ 547 i2c.mask_clk_mask = RADEON_GPIO_MASK_1; 548 i2c.mask_data_mask = RADEON_GPIO_MASK_0; 549 i2c.a_clk_mask = RADEON_GPIO_A_1; 550 i2c.a_data_mask = RADEON_GPIO_A_0; 551 i2c.en_clk_mask = RADEON_GPIO_EN_1; 552 i2c.en_data_mask = RADEON_GPIO_EN_0; 553 i2c.y_clk_mask = RADEON_GPIO_Y_1; 554 i2c.y_data_mask = RADEON_GPIO_Y_0; 555 } 556 557 switch (rdev->family) { 558 case CHIP_R100: 559 case CHIP_RV100: 560 case CHIP_RS100: 561 case CHIP_RV200: 562 case CHIP_RS200: 563 case CHIP_RS300: 564 switch (ddc_line) { 565 case RADEON_GPIO_DVI_DDC: 566 i2c.hw_capable = true; 567 break; 568 default: 569 i2c.hw_capable = false; 570 break; 571 } 572 break; 573 case CHIP_R200: 574 switch (ddc_line) { 575 case RADEON_GPIO_DVI_DDC: 576 case RADEON_GPIO_MONID: 577 i2c.hw_capable = true; 578 break; 579 default: 580 i2c.hw_capable = false; 581 break; 582 } 583 break; 584 case CHIP_RV250: 585 case CHIP_RV280: 586 switch (ddc_line) { 587 case RADEON_GPIO_VGA_DDC: 588 case RADEON_GPIO_DVI_DDC: 589 case RADEON_GPIO_CRT2_DDC: 590 i2c.hw_capable = true; 591 break; 592 default: 593 i2c.hw_capable = false; 594 break; 595 } 596 break; 597 case CHIP_R300: 598 case CHIP_R350: 599 switch (ddc_line) { 600 case RADEON_GPIO_VGA_DDC: 601 case RADEON_GPIO_DVI_DDC: 602 i2c.hw_capable = true; 603 break; 604 default: 605 i2c.hw_capable = false; 606 break; 607 } 608 break; 609 case CHIP_RV350: 610 case CHIP_RV380: 611 case CHIP_RS400: 612 case CHIP_RS480: 613 switch (ddc_line) { 614 case RADEON_GPIO_VGA_DDC: 615 case RADEON_GPIO_DVI_DDC: 616 i2c.hw_capable = true; 617 break; 618 case RADEON_GPIO_MONID: 619 /* hw i2c on RADEON_GPIO_MONID doesn't seem to work 620 * reliably on some pre-r4xx hardware; not sure why. 621 */ 622 i2c.hw_capable = false; 623 break; 624 default: 625 i2c.hw_capable = false; 626 break; 627 } 628 break; 629 default: 630 i2c.hw_capable = false; 631 break; 632 } 633 i2c.mm_i2c = false; 634 635 i2c.i2c_id = ddc; 636 i2c.hpd = RADEON_HPD_NONE; 637 638 if (ddc_line) 639 i2c.valid = true; 640 else 641 i2c.valid = false; 642 643 return i2c; 644} 645 646static struct radeon_i2c_bus_rec radeon_combios_get_i2c_info_from_table(struct radeon_device *rdev) 647{ 648 struct drm_device *dev = rdev->ddev; 649 struct radeon_i2c_bus_rec i2c; 650 u16 offset; 651 u8 id, blocks, clk, data; 652 int i; 653 654 i2c.valid = false; 655 656 offset = combios_get_table_offset(dev, COMBIOS_I2C_INFO_TABLE); 657 if (offset) { 658 blocks = RBIOS8(offset + 2); 659 for (i = 0; i < blocks; i++) { 660 id = RBIOS8(offset + 3 + (i * 5) + 0); 661 if (id == 136) { 662 clk = RBIOS8(offset + 3 + (i * 5) + 3); 663 data = RBIOS8(offset + 3 + (i * 5) + 4); 664 /* gpiopad */ 665 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 666 (1 << clk), (1 << data)); 667 break; 668 } 669 } 670 } 671 return i2c; 672} 673 674void radeon_combios_i2c_init(struct radeon_device *rdev) 675{ 676 struct drm_device *dev = rdev->ddev; 677 struct radeon_i2c_bus_rec i2c; 678 679 /* actual hw pads 680 * r1xx/rs2xx/rs3xx 681 * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm 682 * r200 683 * 0x60, 0x64, 0x68, mm 684 * r300/r350 685 * 0x60, 0x64, mm 686 * rv2xx/rv3xx/rs4xx 687 * 0x60, 0x64, 0x68, gpiopads, mm 688 */ 689 690 /* 0x60 */ 691 i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 692 rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC"); 693 /* 0x64 */ 694 i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 695 rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC"); 696 697 /* mm i2c */ 698 i2c.valid = true; 699 i2c.hw_capable = true; 700 i2c.mm_i2c = true; 701 i2c.i2c_id = 0xa0; 702 rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C"); 703 704 if (rdev->family == CHIP_R300 || 705 rdev->family == CHIP_R350) { 706 /* only 2 sw i2c pads */ 707 } else if (rdev->family == CHIP_RS300 || 708 rdev->family == CHIP_RS400 || 709 rdev->family == CHIP_RS480) { 710 /* 0x68 */ 711 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 712 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 713 714 /* gpiopad */ 715 i2c = radeon_combios_get_i2c_info_from_table(rdev); 716 if (i2c.valid) 717 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK"); 718 } else if ((rdev->family == CHIP_R200) || 719 (rdev->family >= CHIP_R300)) { 720 /* 0x68 */ 721 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 722 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 723 } else { 724 /* 0x68 */ 725 i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 726 rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID"); 727 /* 0x6c */ 728 i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 729 rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC"); 730 } 731} 732 733bool radeon_combios_get_clock_info(struct drm_device *dev) 734{ 735 struct radeon_device *rdev = dev->dev_private; 736 uint16_t pll_info; 737 struct radeon_pll *p1pll = &rdev->clock.p1pll; 738 struct radeon_pll *p2pll = &rdev->clock.p2pll; 739 struct radeon_pll *spll = &rdev->clock.spll; 740 struct radeon_pll *mpll = &rdev->clock.mpll; 741 int8_t rev; 742 uint16_t sclk, mclk; 743 744 pll_info = combios_get_table_offset(dev, COMBIOS_PLL_INFO_TABLE); 745 if (pll_info) { 746 rev = RBIOS8(pll_info); 747 748 /* pixel clocks */ 749 p1pll->reference_freq = RBIOS16(pll_info + 0xe); 750 p1pll->reference_div = RBIOS16(pll_info + 0x10); 751 p1pll->pll_out_min = RBIOS32(pll_info + 0x12); 752 p1pll->pll_out_max = RBIOS32(pll_info + 0x16); 753 p1pll->lcd_pll_out_min = p1pll->pll_out_min; 754 p1pll->lcd_pll_out_max = p1pll->pll_out_max; 755 756 if (rev > 9) { 757 p1pll->pll_in_min = RBIOS32(pll_info + 0x36); 758 p1pll->pll_in_max = RBIOS32(pll_info + 0x3a); 759 } else { 760 p1pll->pll_in_min = 40; 761 p1pll->pll_in_max = 500; 762 } 763 *p2pll = *p1pll; 764 765 /* system clock */ 766 spll->reference_freq = RBIOS16(pll_info + 0x1a); 767 spll->reference_div = RBIOS16(pll_info + 0x1c); 768 spll->pll_out_min = RBIOS32(pll_info + 0x1e); 769 spll->pll_out_max = RBIOS32(pll_info + 0x22); 770 771 if (rev > 10) { 772 spll->pll_in_min = RBIOS32(pll_info + 0x48); 773 spll->pll_in_max = RBIOS32(pll_info + 0x4c); 774 } else { 775 /* ??? */ 776 spll->pll_in_min = 40; 777 spll->pll_in_max = 500; 778 } 779 780 /* memory clock */ 781 mpll->reference_freq = RBIOS16(pll_info + 0x26); 782 mpll->reference_div = RBIOS16(pll_info + 0x28); 783 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); 784 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); 785 786 if (rev > 10) { 787 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); 788 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); 789 } else { 790 /* ??? */ 791 mpll->pll_in_min = 40; 792 mpll->pll_in_max = 500; 793 } 794 795 /* default sclk/mclk */ 796 sclk = RBIOS16(pll_info + 0xa); 797 mclk = RBIOS16(pll_info + 0x8); 798 if (sclk == 0) 799 sclk = 200 * 100; 800 if (mclk == 0) 801 mclk = 200 * 100; 802 803 rdev->clock.default_sclk = sclk; 804 rdev->clock.default_mclk = mclk; 805 806 if (RBIOS32(pll_info + 0x16)) 807 rdev->clock.max_pixel_clock = RBIOS32(pll_info + 0x16); 808 else 809 rdev->clock.max_pixel_clock = 35000; /* might need something asic specific */ 810 811 return true; 812 } 813 return false; 814} 815 816bool radeon_combios_sideport_present(struct radeon_device *rdev) 817{ 818 struct drm_device *dev = rdev->ddev; 819 u16 igp_info; 820 821 /* sideport is AMD only */ 822 if (rdev->family == CHIP_RS400) 823 return false; 824 825 igp_info = combios_get_table_offset(dev, COMBIOS_INTEGRATED_SYSTEM_INFO_TABLE); 826 827 if (igp_info) { 828 if (RBIOS16(igp_info + 0x4)) 829 return true; 830 } 831 return false; 832} 833 834static const uint32_t default_primarydac_adj[CHIP_LAST] = { 835 0x00000808, /* r100 */ 836 0x00000808, /* rv100 */ 837 0x00000808, /* rs100 */ 838 0x00000808, /* rv200 */ 839 0x00000808, /* rs200 */ 840 0x00000808, /* r200 */ 841 0x00000808, /* rv250 */ 842 0x00000000, /* rs300 */ 843 0x00000808, /* rv280 */ 844 0x00000808, /* r300 */ 845 0x00000808, /* r350 */ 846 0x00000808, /* rv350 */ 847 0x00000808, /* rv380 */ 848 0x00000808, /* r420 */ 849 0x00000808, /* r423 */ 850 0x00000808, /* rv410 */ 851 0x00000000, /* rs400 */ 852 0x00000000, /* rs480 */ 853}; 854 855static void radeon_legacy_get_primary_dac_info_from_table(struct radeon_device *rdev, 856 struct radeon_encoder_primary_dac *p_dac) 857{ 858 p_dac->ps2_pdac_adj = default_primarydac_adj[rdev->family]; 859 return; 860} 861 862struct radeon_encoder_primary_dac *radeon_combios_get_primary_dac_info(struct 863 radeon_encoder 864 *encoder) 865{ 866 struct drm_device *dev = encoder->base.dev; 867 struct radeon_device *rdev = dev->dev_private; 868 uint16_t dac_info; 869 uint8_t rev, bg, dac; 870 struct radeon_encoder_primary_dac *p_dac = NULL; 871 int found = 0; 872 873 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), 874 GFP_KERNEL); 875 876 if (!p_dac) 877 return NULL; 878 879 /* check CRT table */ 880 dac_info = combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 881 if (dac_info) { 882 rev = RBIOS8(dac_info) & 0x3; 883 if (rev < 2) { 884 bg = RBIOS8(dac_info + 0x2) & 0xf; 885 dac = (RBIOS8(dac_info + 0x2) >> 4) & 0xf; 886 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 887 } else { 888 bg = RBIOS8(dac_info + 0x2) & 0xf; 889 dac = RBIOS8(dac_info + 0x3) & 0xf; 890 p_dac->ps2_pdac_adj = (bg << 8) | (dac); 891 } 892 /* if the values are zeros, use the table */ 893 if ((dac == 0) || (bg == 0)) 894 found = 0; 895 else 896 found = 1; 897 } 898 899 /* quirks */ 900 /* Radeon 7000 (RV100) */ 901 if (((dev->pdev->device == 0x5159) && 902 (dev->pdev->subsystem_vendor == 0x174B) && 903 (dev->pdev->subsystem_device == 0x7c28)) || 904 /* Radeon 9100 (R200) */ 905 ((dev->pdev->device == 0x514D) && 906 (dev->pdev->subsystem_vendor == 0x174B) && 907 (dev->pdev->subsystem_device == 0x7149))) { 908 /* vbios value is bad, use the default */ 909 found = 0; 910 } 911 912 if (!found) /* fallback to defaults */ 913 radeon_legacy_get_primary_dac_info_from_table(rdev, p_dac); 914 915 return p_dac; 916} 917 918enum radeon_tv_std 919radeon_combios_get_tv_info(struct radeon_device *rdev) 920{ 921 struct drm_device *dev = rdev->ddev; 922 uint16_t tv_info; 923 enum radeon_tv_std tv_std = TV_STD_NTSC; 924 925 tv_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 926 if (tv_info) { 927 if (RBIOS8(tv_info + 6) == 'T') { 928 switch (RBIOS8(tv_info + 7) & 0xf) { 929 case 1: 930 tv_std = TV_STD_NTSC; 931 DRM_DEBUG_KMS("Default TV standard: NTSC\n"); 932 break; 933 case 2: 934 tv_std = TV_STD_PAL; 935 DRM_DEBUG_KMS("Default TV standard: PAL\n"); 936 break; 937 case 3: 938 tv_std = TV_STD_PAL_M; 939 DRM_DEBUG_KMS("Default TV standard: PAL-M\n"); 940 break; 941 case 4: 942 tv_std = TV_STD_PAL_60; 943 DRM_DEBUG_KMS("Default TV standard: PAL-60\n"); 944 break; 945 case 5: 946 tv_std = TV_STD_NTSC_J; 947 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n"); 948 break; 949 case 6: 950 tv_std = TV_STD_SCART_PAL; 951 DRM_DEBUG_KMS("Default TV standard: SCART-PAL\n"); 952 break; 953 default: 954 tv_std = TV_STD_NTSC; 955 DRM_DEBUG_KMS 956 ("Unknown TV standard; defaulting to NTSC\n"); 957 break; 958 } 959 960 switch ((RBIOS8(tv_info + 9) >> 2) & 0x3) { 961 case 0: 962 DRM_DEBUG_KMS("29.498928713 MHz TV ref clk\n"); 963 break; 964 case 1: 965 DRM_DEBUG_KMS("28.636360000 MHz TV ref clk\n"); 966 break; 967 case 2: 968 DRM_DEBUG_KMS("14.318180000 MHz TV ref clk\n"); 969 break; 970 case 3: 971 DRM_DEBUG_KMS("27.000000000 MHz TV ref clk\n"); 972 break; 973 default: 974 break; 975 } 976 } 977 } 978 return tv_std; 979} 980 981static const uint32_t default_tvdac_adj[CHIP_LAST] = { 982 0x00000000, /* r100 */ 983 0x00280000, /* rv100 */ 984 0x00000000, /* rs100 */ 985 0x00880000, /* rv200 */ 986 0x00000000, /* rs200 */ 987 0x00000000, /* r200 */ 988 0x00770000, /* rv250 */ 989 0x00290000, /* rs300 */ 990 0x00560000, /* rv280 */ 991 0x00780000, /* r300 */ 992 0x00770000, /* r350 */ 993 0x00780000, /* rv350 */ 994 0x00780000, /* rv380 */ 995 0x01080000, /* r420 */ 996 0x01080000, /* r423 */ 997 0x01080000, /* rv410 */ 998 0x00780000, /* rs400 */ 999 0x00780000, /* rs480 */ 1000}; 1001 1002static void radeon_legacy_get_tv_dac_info_from_table(struct radeon_device *rdev, 1003 struct radeon_encoder_tv_dac *tv_dac) 1004{ 1005 tv_dac->ps2_tvdac_adj = default_tvdac_adj[rdev->family]; 1006 if ((rdev->flags & RADEON_IS_MOBILITY) && (rdev->family == CHIP_RV250)) 1007 tv_dac->ps2_tvdac_adj = 0x00880000; 1008 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1009 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1010 return; 1011} 1012 1013struct radeon_encoder_tv_dac *radeon_combios_get_tv_dac_info(struct 1014 radeon_encoder 1015 *encoder) 1016{ 1017 struct drm_device *dev = encoder->base.dev; 1018 struct radeon_device *rdev = dev->dev_private; 1019 uint16_t dac_info; 1020 uint8_t rev, bg, dac; 1021 struct radeon_encoder_tv_dac *tv_dac = NULL; 1022 int found = 0; 1023 1024 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL); 1025 if (!tv_dac) 1026 return NULL; 1027 1028 /* first check TV table */ 1029 dac_info = combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 1030 if (dac_info) { 1031 rev = RBIOS8(dac_info + 0x3); 1032 if (rev > 4) { 1033 bg = RBIOS8(dac_info + 0xc) & 0xf; 1034 dac = RBIOS8(dac_info + 0xd) & 0xf; 1035 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1036 1037 bg = RBIOS8(dac_info + 0xe) & 0xf; 1038 dac = RBIOS8(dac_info + 0xf) & 0xf; 1039 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1040 1041 bg = RBIOS8(dac_info + 0x10) & 0xf; 1042 dac = RBIOS8(dac_info + 0x11) & 0xf; 1043 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1044 /* if the values are all zeros, use the table */ 1045 if (tv_dac->ps2_tvdac_adj) 1046 found = 1; 1047 } else if (rev > 1) { 1048 bg = RBIOS8(dac_info + 0xc) & 0xf; 1049 dac = (RBIOS8(dac_info + 0xc) >> 4) & 0xf; 1050 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20); 1051 1052 bg = RBIOS8(dac_info + 0xd) & 0xf; 1053 dac = (RBIOS8(dac_info + 0xd) >> 4) & 0xf; 1054 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20); 1055 1056 bg = RBIOS8(dac_info + 0xe) & 0xf; 1057 dac = (RBIOS8(dac_info + 0xe) >> 4) & 0xf; 1058 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20); 1059 /* if the values are all zeros, use the table */ 1060 if (tv_dac->ps2_tvdac_adj) 1061 found = 1; 1062 } 1063 tv_dac->tv_std = radeon_combios_get_tv_info(rdev); 1064 } 1065 if (!found) { 1066 /* then check CRT table */ 1067 dac_info = 1068 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 1069 if (dac_info) { 1070 rev = RBIOS8(dac_info) & 0x3; 1071 if (rev < 2) { 1072 bg = RBIOS8(dac_info + 0x3) & 0xf; 1073 dac = (RBIOS8(dac_info + 0x3) >> 4) & 0xf; 1074 tv_dac->ps2_tvdac_adj = 1075 (bg << 16) | (dac << 20); 1076 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1077 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1078 /* if the values are all zeros, use the table */ 1079 if (tv_dac->ps2_tvdac_adj) 1080 found = 1; 1081 } else { 1082 bg = RBIOS8(dac_info + 0x4) & 0xf; 1083 dac = RBIOS8(dac_info + 0x5) & 0xf; 1084 tv_dac->ps2_tvdac_adj = 1085 (bg << 16) | (dac << 20); 1086 tv_dac->pal_tvdac_adj = tv_dac->ps2_tvdac_adj; 1087 tv_dac->ntsc_tvdac_adj = tv_dac->ps2_tvdac_adj; 1088 /* if the values are all zeros, use the table */ 1089 if (tv_dac->ps2_tvdac_adj) 1090 found = 1; 1091 } 1092 } else { 1093 DRM_INFO("No TV DAC info found in BIOS\n"); 1094 } 1095 } 1096 1097 if (!found) /* fallback to defaults */ 1098 radeon_legacy_get_tv_dac_info_from_table(rdev, tv_dac); 1099 1100 return tv_dac; 1101} 1102 1103static struct radeon_encoder_lvds *radeon_legacy_get_lvds_info_from_regs(struct 1104 radeon_device 1105 *rdev) 1106{ 1107 struct radeon_encoder_lvds *lvds = NULL; 1108 uint32_t fp_vert_stretch, fp_horz_stretch; 1109 uint32_t ppll_div_sel, ppll_val; 1110 uint32_t lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL); 1111 1112 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1113 1114 if (!lvds) 1115 return NULL; 1116 1117 fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH); 1118 fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH); 1119 1120 /* These should be fail-safe defaults, fingers crossed */ 1121 lvds->panel_pwr_delay = 200; 1122 lvds->panel_vcc_delay = 2000; 1123 1124 lvds->lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL); 1125 lvds->panel_digon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) & 0xf; 1126 lvds->panel_blon_delay = (lvds_ss_gen_cntl >> RADEON_LVDS_PWRSEQ_DELAY2_SHIFT) & 0xf; 1127 1128 if (fp_vert_stretch & RADEON_VERT_STRETCH_ENABLE) 1129 lvds->native_mode.vdisplay = 1130 ((fp_vert_stretch & RADEON_VERT_PANEL_SIZE) >> 1131 RADEON_VERT_PANEL_SHIFT) + 1; 1132 else 1133 lvds->native_mode.vdisplay = 1134 (RREG32(RADEON_CRTC_V_TOTAL_DISP) >> 16) + 1; 1135 1136 if (fp_horz_stretch & RADEON_HORZ_STRETCH_ENABLE) 1137 lvds->native_mode.hdisplay = 1138 (((fp_horz_stretch & RADEON_HORZ_PANEL_SIZE) >> 1139 RADEON_HORZ_PANEL_SHIFT) + 1) * 8; 1140 else 1141 lvds->native_mode.hdisplay = 1142 ((RREG32(RADEON_CRTC_H_TOTAL_DISP) >> 16) + 1) * 8; 1143 1144 if ((lvds->native_mode.hdisplay < 640) || 1145 (lvds->native_mode.vdisplay < 480)) { 1146 lvds->native_mode.hdisplay = 640; 1147 lvds->native_mode.vdisplay = 480; 1148 } 1149 1150 ppll_div_sel = RREG8(RADEON_CLOCK_CNTL_INDEX + 1) & 0x3; 1151 ppll_val = RREG32_PLL(RADEON_PPLL_DIV_0 + ppll_div_sel); 1152 if ((ppll_val & 0x000707ff) == 0x1bb) 1153 lvds->use_bios_dividers = false; 1154 else { 1155 lvds->panel_ref_divider = 1156 RREG32_PLL(RADEON_PPLL_REF_DIV) & 0x3ff; 1157 lvds->panel_post_divider = (ppll_val >> 16) & 0x7; 1158 lvds->panel_fb_divider = ppll_val & 0x7ff; 1159 1160 if ((lvds->panel_ref_divider != 0) && 1161 (lvds->panel_fb_divider > 3)) 1162 lvds->use_bios_dividers = true; 1163 } 1164 lvds->panel_vcc_delay = 200; 1165 1166 DRM_INFO("Panel info derived from registers\n"); 1167 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1168 lvds->native_mode.vdisplay); 1169 1170 return lvds; 1171} 1172 1173struct radeon_encoder_lvds *radeon_combios_get_lvds_info(struct radeon_encoder 1174 *encoder) 1175{ 1176 struct drm_device *dev = encoder->base.dev; 1177 struct radeon_device *rdev = dev->dev_private; 1178 uint16_t lcd_info; 1179 uint32_t panel_setup; 1180 char stmp[30]; 1181 int tmp, i; 1182 struct radeon_encoder_lvds *lvds = NULL; 1183 1184 lcd_info = combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 1185 1186 if (lcd_info) { 1187 lvds = kzalloc(sizeof(struct radeon_encoder_lvds), GFP_KERNEL); 1188 1189 if (!lvds) 1190 return NULL; 1191 1192 for (i = 0; i < 24; i++) 1193 stmp[i] = RBIOS8(lcd_info + i + 1); 1194 stmp[24] = 0; 1195 1196 DRM_INFO("Panel ID String: %s\n", stmp); 1197 1198 lvds->native_mode.hdisplay = RBIOS16(lcd_info + 0x19); 1199 lvds->native_mode.vdisplay = RBIOS16(lcd_info + 0x1b); 1200 1201 DRM_INFO("Panel Size %dx%d\n", lvds->native_mode.hdisplay, 1202 lvds->native_mode.vdisplay); 1203 1204 lvds->panel_vcc_delay = RBIOS16(lcd_info + 0x2c); 1205 lvds->panel_vcc_delay = min_t(u16, lvds->panel_vcc_delay, 2000); 1206 1207 lvds->panel_pwr_delay = RBIOS8(lcd_info + 0x24); 1208 lvds->panel_digon_delay = RBIOS16(lcd_info + 0x38) & 0xf; 1209 lvds->panel_blon_delay = (RBIOS16(lcd_info + 0x38) >> 4) & 0xf; 1210 1211 lvds->panel_ref_divider = RBIOS16(lcd_info + 0x2e); 1212 lvds->panel_post_divider = RBIOS8(lcd_info + 0x30); 1213 lvds->panel_fb_divider = RBIOS16(lcd_info + 0x31); 1214 if ((lvds->panel_ref_divider != 0) && 1215 (lvds->panel_fb_divider > 3)) 1216 lvds->use_bios_dividers = true; 1217 1218 panel_setup = RBIOS32(lcd_info + 0x39); 1219 lvds->lvds_gen_cntl = 0xff00; 1220 if (panel_setup & 0x1) 1221 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_FORMAT; 1222 1223 if ((panel_setup >> 4) & 0x1) 1224 lvds->lvds_gen_cntl |= RADEON_LVDS_PANEL_TYPE; 1225 1226 switch ((panel_setup >> 8) & 0x7) { 1227 case 0: 1228 lvds->lvds_gen_cntl |= RADEON_LVDS_NO_FM; 1229 break; 1230 case 1: 1231 lvds->lvds_gen_cntl |= RADEON_LVDS_2_GREY; 1232 break; 1233 case 2: 1234 lvds->lvds_gen_cntl |= RADEON_LVDS_4_GREY; 1235 break; 1236 default: 1237 break; 1238 } 1239 1240 if ((panel_setup >> 16) & 0x1) 1241 lvds->lvds_gen_cntl |= RADEON_LVDS_FP_POL_LOW; 1242 1243 if ((panel_setup >> 17) & 0x1) 1244 lvds->lvds_gen_cntl |= RADEON_LVDS_LP_POL_LOW; 1245 1246 if ((panel_setup >> 18) & 0x1) 1247 lvds->lvds_gen_cntl |= RADEON_LVDS_DTM_POL_LOW; 1248 1249 if ((panel_setup >> 23) & 0x1) 1250 lvds->lvds_gen_cntl |= RADEON_LVDS_BL_CLK_SEL; 1251 1252 lvds->lvds_gen_cntl |= (panel_setup & 0xf0000000); 1253 1254 for (i = 0; i < 32; i++) { 1255 tmp = RBIOS16(lcd_info + 64 + i * 2); 1256 if (tmp == 0) 1257 break; 1258 1259 if ((RBIOS16(tmp) == lvds->native_mode.hdisplay) && 1260 (RBIOS16(tmp + 2) == lvds->native_mode.vdisplay)) { 1261 u32 hss = (RBIOS16(tmp + 21) - RBIOS16(tmp + 19) - 1) * 8; 1262 1263 if (hss > lvds->native_mode.hdisplay) 1264 hss = (10 - 1) * 8; 1265 1266 lvds->native_mode.htotal = lvds->native_mode.hdisplay + 1267 (RBIOS16(tmp + 17) - RBIOS16(tmp + 19)) * 8; 1268 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay + 1269 hss; 1270 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start + 1271 (RBIOS8(tmp + 23) * 8); 1272 1273 lvds->native_mode.vtotal = lvds->native_mode.vdisplay + 1274 (RBIOS16(tmp + 24) - RBIOS16(tmp + 26)); 1275 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay + 1276 ((RBIOS16(tmp + 28) & 0x7ff) - RBIOS16(tmp + 26)); 1277 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start + 1278 ((RBIOS16(tmp + 28) & 0xf800) >> 11); 1279 1280 lvds->native_mode.clock = RBIOS16(tmp + 9) * 10; 1281 lvds->native_mode.flags = 0; 1282 /* set crtc values */ 1283 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V); 1284 1285 } 1286 } 1287 } else { 1288 DRM_INFO("No panel info found in BIOS\n"); 1289 lvds = radeon_legacy_get_lvds_info_from_regs(rdev); 1290 } 1291 1292 if (lvds) 1293 encoder->native_mode = lvds->native_mode; 1294 return lvds; 1295} 1296 1297static const struct radeon_tmds_pll default_tmds_pll[CHIP_LAST][4] = { 1298 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R100 */ 1299 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV100 */ 1300 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS100 */ 1301 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RV200 */ 1302 {{12000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_RS200 */ 1303 {{15000, 0xa1b}, {0xffffffff, 0xa3f}, {0, 0}, {0, 0}}, /* CHIP_R200 */ 1304 {{15500, 0x81b}, {0xffffffff, 0x83f}, {0, 0}, {0, 0}}, /* CHIP_RV250 */ 1305 {{0, 0}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RS300 */ 1306 {{13000, 0x400f4}, {15000, 0x400f7}, {0xffffffff, 0x40111}, {0, 0}}, /* CHIP_RV280 */ 1307 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R300 */ 1308 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R350 */ 1309 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV350 */ 1310 {{15000, 0xb0155}, {0xffffffff, 0xb01cb}, {0, 0}, {0, 0}}, /* CHIP_RV380 */ 1311 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R420 */ 1312 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_R423 */ 1313 {{0xffffffff, 0xb01cb}, {0, 0}, {0, 0}, {0, 0}}, /* CHIP_RV410 */ 1314 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS400 */ 1315 { {0, 0}, {0, 0}, {0, 0}, {0, 0} }, /* CHIP_RS480 */ 1316}; 1317 1318bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder, 1319 struct radeon_encoder_int_tmds *tmds) 1320{ 1321 struct drm_device *dev = encoder->base.dev; 1322 struct radeon_device *rdev = dev->dev_private; 1323 int i; 1324 1325 for (i = 0; i < 4; i++) { 1326 tmds->tmds_pll[i].value = 1327 default_tmds_pll[rdev->family][i].value; 1328 tmds->tmds_pll[i].freq = default_tmds_pll[rdev->family][i].freq; 1329 } 1330 1331 return true; 1332} 1333 1334bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder, 1335 struct radeon_encoder_int_tmds *tmds) 1336{ 1337 struct drm_device *dev = encoder->base.dev; 1338 struct radeon_device *rdev = dev->dev_private; 1339 uint16_t tmds_info; 1340 int i, n; 1341 uint8_t ver; 1342 1343 tmds_info = combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 1344 1345 if (tmds_info) { 1346 ver = RBIOS8(tmds_info); 1347 DRM_DEBUG_KMS("DFP table revision: %d\n", ver); 1348 if (ver == 3) { 1349 n = RBIOS8(tmds_info + 5) + 1; 1350 if (n > 4) 1351 n = 4; 1352 for (i = 0; i < n; i++) { 1353 tmds->tmds_pll[i].value = 1354 RBIOS32(tmds_info + i * 10 + 0x08); 1355 tmds->tmds_pll[i].freq = 1356 RBIOS16(tmds_info + i * 10 + 0x10); 1357 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1358 tmds->tmds_pll[i].freq, 1359 tmds->tmds_pll[i].value); 1360 } 1361 } else if (ver == 4) { 1362 int stride = 0; 1363 n = RBIOS8(tmds_info + 5) + 1; 1364 if (n > 4) 1365 n = 4; 1366 for (i = 0; i < n; i++) { 1367 tmds->tmds_pll[i].value = 1368 RBIOS32(tmds_info + stride + 0x08); 1369 tmds->tmds_pll[i].freq = 1370 RBIOS16(tmds_info + stride + 0x10); 1371 if (i == 0) 1372 stride += 10; 1373 else 1374 stride += 6; 1375 DRM_DEBUG_KMS("TMDS PLL From COMBIOS %u %x\n", 1376 tmds->tmds_pll[i].freq, 1377 tmds->tmds_pll[i].value); 1378 } 1379 } 1380 } else { 1381 DRM_INFO("No TMDS info found in BIOS\n"); 1382 return false; 1383 } 1384 return true; 1385} 1386 1387bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder, 1388 struct radeon_encoder_ext_tmds *tmds) 1389{ 1390 struct drm_device *dev = encoder->base.dev; 1391 struct radeon_device *rdev = dev->dev_private; 1392 struct radeon_i2c_bus_rec i2c_bus; 1393 1394 /* default for macs */ 1395 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1396 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1397 1398 /* XXX some macs have duallink chips */ 1399 switch (rdev->mode_info.connector_table) { 1400 case CT_POWERBOOK_EXTERNAL: 1401 case CT_MINI_EXTERNAL: 1402 default: 1403 tmds->dvo_chip = DVO_SIL164; 1404 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1405 break; 1406 } 1407 1408 return true; 1409} 1410 1411bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder, 1412 struct radeon_encoder_ext_tmds *tmds) 1413{ 1414 struct drm_device *dev = encoder->base.dev; 1415 struct radeon_device *rdev = dev->dev_private; 1416 uint16_t offset; 1417 uint8_t ver; 1418 enum radeon_combios_ddc gpio; 1419 struct radeon_i2c_bus_rec i2c_bus; 1420 1421 tmds->i2c_bus = NULL; 1422 if (rdev->flags & RADEON_IS_IGP) { 1423 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1424 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1425 tmds->dvo_chip = DVO_SIL164; 1426 tmds->slave_addr = 0x70 >> 1; /* 7 bit addressing */ 1427 } else { 1428 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 1429 if (offset) { 1430 ver = RBIOS8(offset); 1431 DRM_DEBUG_KMS("External TMDS Table revision: %d\n", ver); 1432 tmds->slave_addr = RBIOS8(offset + 4 + 2); 1433 tmds->slave_addr >>= 1; /* 7 bit addressing */ 1434 gpio = RBIOS8(offset + 4 + 3); 1435 if (gpio == DDC_LCD) { 1436 /* MM i2c */ 1437 i2c_bus.valid = true; 1438 i2c_bus.hw_capable = true; 1439 i2c_bus.mm_i2c = true; 1440 i2c_bus.i2c_id = 0xa0; 1441 } else 1442 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 1443 tmds->i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 1444 } 1445 } 1446 1447 if (!tmds->i2c_bus) { 1448 DRM_INFO("No valid Ext TMDS info found in BIOS\n"); 1449 return false; 1450 } 1451 1452 return true; 1453} 1454 1455bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev) 1456{ 1457 struct radeon_device *rdev = dev->dev_private; 1458 struct radeon_i2c_bus_rec ddc_i2c; 1459 struct radeon_hpd hpd; 1460 1461 rdev->mode_info.connector_table = radeon_connector_table; 1462 if (rdev->mode_info.connector_table == CT_NONE) { 1463#ifdef CONFIG_PPC_PMAC 1464 if (of_machine_is_compatible("PowerBook3,3")) { 1465 /* powerbook with VGA */ 1466 rdev->mode_info.connector_table = CT_POWERBOOK_VGA; 1467 } else if (of_machine_is_compatible("PowerBook3,4") || 1468 of_machine_is_compatible("PowerBook3,5")) { 1469 /* powerbook with internal tmds */ 1470 rdev->mode_info.connector_table = CT_POWERBOOK_INTERNAL; 1471 } else if (of_machine_is_compatible("PowerBook5,1") || 1472 of_machine_is_compatible("PowerBook5,2") || 1473 of_machine_is_compatible("PowerBook5,3") || 1474 of_machine_is_compatible("PowerBook5,4") || 1475 of_machine_is_compatible("PowerBook5,5")) { 1476 /* powerbook with external single link tmds (sil164) */ 1477 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1478 } else if (of_machine_is_compatible("PowerBook5,6")) { 1479 /* powerbook with external dual or single link tmds */ 1480 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1481 } else if (of_machine_is_compatible("PowerBook5,7") || 1482 of_machine_is_compatible("PowerBook5,8") || 1483 of_machine_is_compatible("PowerBook5,9")) { 1484 /* PowerBook6,2 ? */ 1485 /* powerbook with external dual link tmds (sil1178?) */ 1486 rdev->mode_info.connector_table = CT_POWERBOOK_EXTERNAL; 1487 } else if (of_machine_is_compatible("PowerBook4,1") || 1488 of_machine_is_compatible("PowerBook4,2") || 1489 of_machine_is_compatible("PowerBook4,3") || 1490 of_machine_is_compatible("PowerBook6,3") || 1491 of_machine_is_compatible("PowerBook6,5") || 1492 of_machine_is_compatible("PowerBook6,7")) { 1493 /* ibook */ 1494 rdev->mode_info.connector_table = CT_IBOOK; 1495 } else if (of_machine_is_compatible("PowerMac3,5")) { 1496 /* PowerMac G4 Silver radeon 7500 */ 1497 rdev->mode_info.connector_table = CT_MAC_G4_SILVER; 1498 } else if (of_machine_is_compatible("PowerMac4,4")) { 1499 /* emac */ 1500 rdev->mode_info.connector_table = CT_EMAC; 1501 } else if (of_machine_is_compatible("PowerMac10,1")) { 1502 /* mini with internal tmds */ 1503 rdev->mode_info.connector_table = CT_MINI_INTERNAL; 1504 } else if (of_machine_is_compatible("PowerMac10,2")) { 1505 /* mini with external tmds */ 1506 rdev->mode_info.connector_table = CT_MINI_EXTERNAL; 1507 } else if (of_machine_is_compatible("PowerMac12,1")) { 1508 /* PowerMac8,1 ? */ 1509 /* imac g5 isight */ 1510 rdev->mode_info.connector_table = CT_IMAC_G5_ISIGHT; 1511 } else if ((rdev->pdev->device == 0x4a48) && 1512 (rdev->pdev->subsystem_vendor == 0x1002) && 1513 (rdev->pdev->subsystem_device == 0x4a48)) { 1514 /* Mac X800 */ 1515 rdev->mode_info.connector_table = CT_MAC_X800; 1516 } else if ((of_machine_is_compatible("PowerMac7,2") || 1517 of_machine_is_compatible("PowerMac7,3")) && 1518 (rdev->pdev->device == 0x4150) && 1519 (rdev->pdev->subsystem_vendor == 0x1002) && 1520 (rdev->pdev->subsystem_device == 0x4150)) { 1521 /* Mac G5 tower 9600 */ 1522 rdev->mode_info.connector_table = CT_MAC_G5_9600; 1523 } else if ((rdev->pdev->device == 0x4c66) && 1524 (rdev->pdev->subsystem_vendor == 0x1002) && 1525 (rdev->pdev->subsystem_device == 0x4c66)) { 1526 /* SAM440ep RV250 embedded board */ 1527 rdev->mode_info.connector_table = CT_SAM440EP; 1528 } else 1529#endif /* CONFIG_PPC_PMAC */ 1530#ifdef CONFIG_PPC64 1531 if (ASIC_IS_RN50(rdev)) 1532 rdev->mode_info.connector_table = CT_RN50_POWER; 1533 else 1534#endif 1535 rdev->mode_info.connector_table = CT_GENERIC; 1536 } 1537 1538 switch (rdev->mode_info.connector_table) { 1539 case CT_GENERIC: 1540 DRM_INFO("Connector Table: %d (generic)\n", 1541 rdev->mode_info.connector_table); 1542 /* these are the most common settings */ 1543 if (rdev->flags & RADEON_SINGLE_CRTC) { 1544 /* VGA - primary dac */ 1545 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1546 hpd.hpd = RADEON_HPD_NONE; 1547 radeon_add_legacy_encoder(dev, 1548 radeon_get_encoder_enum(dev, 1549 ATOM_DEVICE_CRT1_SUPPORT, 1550 1), 1551 ATOM_DEVICE_CRT1_SUPPORT); 1552 radeon_add_legacy_connector(dev, 0, 1553 ATOM_DEVICE_CRT1_SUPPORT, 1554 DRM_MODE_CONNECTOR_VGA, 1555 &ddc_i2c, 1556 CONNECTOR_OBJECT_ID_VGA, 1557 &hpd); 1558 } else if (rdev->flags & RADEON_IS_MOBILITY) { 1559 /* LVDS */ 1560 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 1561 hpd.hpd = RADEON_HPD_NONE; 1562 radeon_add_legacy_encoder(dev, 1563 radeon_get_encoder_enum(dev, 1564 ATOM_DEVICE_LCD1_SUPPORT, 1565 0), 1566 ATOM_DEVICE_LCD1_SUPPORT); 1567 radeon_add_legacy_connector(dev, 0, 1568 ATOM_DEVICE_LCD1_SUPPORT, 1569 DRM_MODE_CONNECTOR_LVDS, 1570 &ddc_i2c, 1571 CONNECTOR_OBJECT_ID_LVDS, 1572 &hpd); 1573 1574 /* VGA - primary dac */ 1575 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1576 hpd.hpd = RADEON_HPD_NONE; 1577 radeon_add_legacy_encoder(dev, 1578 radeon_get_encoder_enum(dev, 1579 ATOM_DEVICE_CRT1_SUPPORT, 1580 1), 1581 ATOM_DEVICE_CRT1_SUPPORT); 1582 radeon_add_legacy_connector(dev, 1, 1583 ATOM_DEVICE_CRT1_SUPPORT, 1584 DRM_MODE_CONNECTOR_VGA, 1585 &ddc_i2c, 1586 CONNECTOR_OBJECT_ID_VGA, 1587 &hpd); 1588 } else { 1589 /* DVI-I - tv dac, int tmds */ 1590 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1591 hpd.hpd = RADEON_HPD_1; 1592 radeon_add_legacy_encoder(dev, 1593 radeon_get_encoder_enum(dev, 1594 ATOM_DEVICE_DFP1_SUPPORT, 1595 0), 1596 ATOM_DEVICE_DFP1_SUPPORT); 1597 radeon_add_legacy_encoder(dev, 1598 radeon_get_encoder_enum(dev, 1599 ATOM_DEVICE_CRT2_SUPPORT, 1600 2), 1601 ATOM_DEVICE_CRT2_SUPPORT); 1602 radeon_add_legacy_connector(dev, 0, 1603 ATOM_DEVICE_DFP1_SUPPORT | 1604 ATOM_DEVICE_CRT2_SUPPORT, 1605 DRM_MODE_CONNECTOR_DVII, 1606 &ddc_i2c, 1607 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1608 &hpd); 1609 1610 /* VGA - primary dac */ 1611 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1612 hpd.hpd = RADEON_HPD_NONE; 1613 radeon_add_legacy_encoder(dev, 1614 radeon_get_encoder_enum(dev, 1615 ATOM_DEVICE_CRT1_SUPPORT, 1616 1), 1617 ATOM_DEVICE_CRT1_SUPPORT); 1618 radeon_add_legacy_connector(dev, 1, 1619 ATOM_DEVICE_CRT1_SUPPORT, 1620 DRM_MODE_CONNECTOR_VGA, 1621 &ddc_i2c, 1622 CONNECTOR_OBJECT_ID_VGA, 1623 &hpd); 1624 } 1625 1626 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 1627 /* TV - tv dac */ 1628 ddc_i2c.valid = false; 1629 hpd.hpd = RADEON_HPD_NONE; 1630 radeon_add_legacy_encoder(dev, 1631 radeon_get_encoder_enum(dev, 1632 ATOM_DEVICE_TV1_SUPPORT, 1633 2), 1634 ATOM_DEVICE_TV1_SUPPORT); 1635 radeon_add_legacy_connector(dev, 2, 1636 ATOM_DEVICE_TV1_SUPPORT, 1637 DRM_MODE_CONNECTOR_SVIDEO, 1638 &ddc_i2c, 1639 CONNECTOR_OBJECT_ID_SVIDEO, 1640 &hpd); 1641 } 1642 break; 1643 case CT_IBOOK: 1644 DRM_INFO("Connector Table: %d (ibook)\n", 1645 rdev->mode_info.connector_table); 1646 /* LVDS */ 1647 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1648 hpd.hpd = RADEON_HPD_NONE; 1649 radeon_add_legacy_encoder(dev, 1650 radeon_get_encoder_enum(dev, 1651 ATOM_DEVICE_LCD1_SUPPORT, 1652 0), 1653 ATOM_DEVICE_LCD1_SUPPORT); 1654 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1655 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1656 CONNECTOR_OBJECT_ID_LVDS, 1657 &hpd); 1658 /* VGA - TV DAC */ 1659 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1660 hpd.hpd = RADEON_HPD_NONE; 1661 radeon_add_legacy_encoder(dev, 1662 radeon_get_encoder_enum(dev, 1663 ATOM_DEVICE_CRT2_SUPPORT, 1664 2), 1665 ATOM_DEVICE_CRT2_SUPPORT); 1666 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1667 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1668 CONNECTOR_OBJECT_ID_VGA, 1669 &hpd); 1670 /* TV - TV DAC */ 1671 ddc_i2c.valid = false; 1672 hpd.hpd = RADEON_HPD_NONE; 1673 radeon_add_legacy_encoder(dev, 1674 radeon_get_encoder_enum(dev, 1675 ATOM_DEVICE_TV1_SUPPORT, 1676 2), 1677 ATOM_DEVICE_TV1_SUPPORT); 1678 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1679 DRM_MODE_CONNECTOR_SVIDEO, 1680 &ddc_i2c, 1681 CONNECTOR_OBJECT_ID_SVIDEO, 1682 &hpd); 1683 break; 1684 case CT_POWERBOOK_EXTERNAL: 1685 DRM_INFO("Connector Table: %d (powerbook external tmds)\n", 1686 rdev->mode_info.connector_table); 1687 /* LVDS */ 1688 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1689 hpd.hpd = RADEON_HPD_NONE; 1690 radeon_add_legacy_encoder(dev, 1691 radeon_get_encoder_enum(dev, 1692 ATOM_DEVICE_LCD1_SUPPORT, 1693 0), 1694 ATOM_DEVICE_LCD1_SUPPORT); 1695 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1696 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1697 CONNECTOR_OBJECT_ID_LVDS, 1698 &hpd); 1699 /* DVI-I - primary dac, ext tmds */ 1700 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1701 hpd.hpd = RADEON_HPD_2; /* ??? */ 1702 radeon_add_legacy_encoder(dev, 1703 radeon_get_encoder_enum(dev, 1704 ATOM_DEVICE_DFP2_SUPPORT, 1705 0), 1706 ATOM_DEVICE_DFP2_SUPPORT); 1707 radeon_add_legacy_encoder(dev, 1708 radeon_get_encoder_enum(dev, 1709 ATOM_DEVICE_CRT1_SUPPORT, 1710 1), 1711 ATOM_DEVICE_CRT1_SUPPORT); 1712 /* XXX some are SL */ 1713 radeon_add_legacy_connector(dev, 1, 1714 ATOM_DEVICE_DFP2_SUPPORT | 1715 ATOM_DEVICE_CRT1_SUPPORT, 1716 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1717 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 1718 &hpd); 1719 /* TV - TV DAC */ 1720 ddc_i2c.valid = false; 1721 hpd.hpd = RADEON_HPD_NONE; 1722 radeon_add_legacy_encoder(dev, 1723 radeon_get_encoder_enum(dev, 1724 ATOM_DEVICE_TV1_SUPPORT, 1725 2), 1726 ATOM_DEVICE_TV1_SUPPORT); 1727 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1728 DRM_MODE_CONNECTOR_SVIDEO, 1729 &ddc_i2c, 1730 CONNECTOR_OBJECT_ID_SVIDEO, 1731 &hpd); 1732 break; 1733 case CT_POWERBOOK_INTERNAL: 1734 DRM_INFO("Connector Table: %d (powerbook internal tmds)\n", 1735 rdev->mode_info.connector_table); 1736 /* LVDS */ 1737 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1738 hpd.hpd = RADEON_HPD_NONE; 1739 radeon_add_legacy_encoder(dev, 1740 radeon_get_encoder_enum(dev, 1741 ATOM_DEVICE_LCD1_SUPPORT, 1742 0), 1743 ATOM_DEVICE_LCD1_SUPPORT); 1744 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1745 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1746 CONNECTOR_OBJECT_ID_LVDS, 1747 &hpd); 1748 /* DVI-I - primary dac, int tmds */ 1749 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1750 hpd.hpd = RADEON_HPD_1; /* ??? */ 1751 radeon_add_legacy_encoder(dev, 1752 radeon_get_encoder_enum(dev, 1753 ATOM_DEVICE_DFP1_SUPPORT, 1754 0), 1755 ATOM_DEVICE_DFP1_SUPPORT); 1756 radeon_add_legacy_encoder(dev, 1757 radeon_get_encoder_enum(dev, 1758 ATOM_DEVICE_CRT1_SUPPORT, 1759 1), 1760 ATOM_DEVICE_CRT1_SUPPORT); 1761 radeon_add_legacy_connector(dev, 1, 1762 ATOM_DEVICE_DFP1_SUPPORT | 1763 ATOM_DEVICE_CRT1_SUPPORT, 1764 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1765 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1766 &hpd); 1767 /* TV - TV DAC */ 1768 ddc_i2c.valid = false; 1769 hpd.hpd = RADEON_HPD_NONE; 1770 radeon_add_legacy_encoder(dev, 1771 radeon_get_encoder_enum(dev, 1772 ATOM_DEVICE_TV1_SUPPORT, 1773 2), 1774 ATOM_DEVICE_TV1_SUPPORT); 1775 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1776 DRM_MODE_CONNECTOR_SVIDEO, 1777 &ddc_i2c, 1778 CONNECTOR_OBJECT_ID_SVIDEO, 1779 &hpd); 1780 break; 1781 case CT_POWERBOOK_VGA: 1782 DRM_INFO("Connector Table: %d (powerbook vga)\n", 1783 rdev->mode_info.connector_table); 1784 /* LVDS */ 1785 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1786 hpd.hpd = RADEON_HPD_NONE; 1787 radeon_add_legacy_encoder(dev, 1788 radeon_get_encoder_enum(dev, 1789 ATOM_DEVICE_LCD1_SUPPORT, 1790 0), 1791 ATOM_DEVICE_LCD1_SUPPORT); 1792 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 1793 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 1794 CONNECTOR_OBJECT_ID_LVDS, 1795 &hpd); 1796 /* VGA - primary dac */ 1797 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1798 hpd.hpd = RADEON_HPD_NONE; 1799 radeon_add_legacy_encoder(dev, 1800 radeon_get_encoder_enum(dev, 1801 ATOM_DEVICE_CRT1_SUPPORT, 1802 1), 1803 ATOM_DEVICE_CRT1_SUPPORT); 1804 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 1805 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1806 CONNECTOR_OBJECT_ID_VGA, 1807 &hpd); 1808 /* TV - TV DAC */ 1809 ddc_i2c.valid = false; 1810 hpd.hpd = RADEON_HPD_NONE; 1811 radeon_add_legacy_encoder(dev, 1812 radeon_get_encoder_enum(dev, 1813 ATOM_DEVICE_TV1_SUPPORT, 1814 2), 1815 ATOM_DEVICE_TV1_SUPPORT); 1816 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1817 DRM_MODE_CONNECTOR_SVIDEO, 1818 &ddc_i2c, 1819 CONNECTOR_OBJECT_ID_SVIDEO, 1820 &hpd); 1821 break; 1822 case CT_MINI_EXTERNAL: 1823 DRM_INFO("Connector Table: %d (mini external tmds)\n", 1824 rdev->mode_info.connector_table); 1825 /* DVI-I - tv dac, ext tmds */ 1826 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1827 hpd.hpd = RADEON_HPD_2; /* ??? */ 1828 radeon_add_legacy_encoder(dev, 1829 radeon_get_encoder_enum(dev, 1830 ATOM_DEVICE_DFP2_SUPPORT, 1831 0), 1832 ATOM_DEVICE_DFP2_SUPPORT); 1833 radeon_add_legacy_encoder(dev, 1834 radeon_get_encoder_enum(dev, 1835 ATOM_DEVICE_CRT2_SUPPORT, 1836 2), 1837 ATOM_DEVICE_CRT2_SUPPORT); 1838 /* XXX are any DL? */ 1839 radeon_add_legacy_connector(dev, 0, 1840 ATOM_DEVICE_DFP2_SUPPORT | 1841 ATOM_DEVICE_CRT2_SUPPORT, 1842 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1843 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1844 &hpd); 1845 /* TV - TV DAC */ 1846 ddc_i2c.valid = false; 1847 hpd.hpd = RADEON_HPD_NONE; 1848 radeon_add_legacy_encoder(dev, 1849 radeon_get_encoder_enum(dev, 1850 ATOM_DEVICE_TV1_SUPPORT, 1851 2), 1852 ATOM_DEVICE_TV1_SUPPORT); 1853 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1854 DRM_MODE_CONNECTOR_SVIDEO, 1855 &ddc_i2c, 1856 CONNECTOR_OBJECT_ID_SVIDEO, 1857 &hpd); 1858 break; 1859 case CT_MINI_INTERNAL: 1860 DRM_INFO("Connector Table: %d (mini internal tmds)\n", 1861 rdev->mode_info.connector_table); 1862 /* DVI-I - tv dac, int tmds */ 1863 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1864 hpd.hpd = RADEON_HPD_1; /* ??? */ 1865 radeon_add_legacy_encoder(dev, 1866 radeon_get_encoder_enum(dev, 1867 ATOM_DEVICE_DFP1_SUPPORT, 1868 0), 1869 ATOM_DEVICE_DFP1_SUPPORT); 1870 radeon_add_legacy_encoder(dev, 1871 radeon_get_encoder_enum(dev, 1872 ATOM_DEVICE_CRT2_SUPPORT, 1873 2), 1874 ATOM_DEVICE_CRT2_SUPPORT); 1875 radeon_add_legacy_connector(dev, 0, 1876 ATOM_DEVICE_DFP1_SUPPORT | 1877 ATOM_DEVICE_CRT2_SUPPORT, 1878 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 1879 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 1880 &hpd); 1881 /* TV - TV DAC */ 1882 ddc_i2c.valid = false; 1883 hpd.hpd = RADEON_HPD_NONE; 1884 radeon_add_legacy_encoder(dev, 1885 radeon_get_encoder_enum(dev, 1886 ATOM_DEVICE_TV1_SUPPORT, 1887 2), 1888 ATOM_DEVICE_TV1_SUPPORT); 1889 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_TV1_SUPPORT, 1890 DRM_MODE_CONNECTOR_SVIDEO, 1891 &ddc_i2c, 1892 CONNECTOR_OBJECT_ID_SVIDEO, 1893 &hpd); 1894 break; 1895 case CT_IMAC_G5_ISIGHT: 1896 DRM_INFO("Connector Table: %d (imac g5 isight)\n", 1897 rdev->mode_info.connector_table); 1898 /* DVI-D - int tmds */ 1899 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 1900 hpd.hpd = RADEON_HPD_1; /* ??? */ 1901 radeon_add_legacy_encoder(dev, 1902 radeon_get_encoder_enum(dev, 1903 ATOM_DEVICE_DFP1_SUPPORT, 1904 0), 1905 ATOM_DEVICE_DFP1_SUPPORT); 1906 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_DFP1_SUPPORT, 1907 DRM_MODE_CONNECTOR_DVID, &ddc_i2c, 1908 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 1909 &hpd); 1910 /* VGA - tv dac */ 1911 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 1912 hpd.hpd = RADEON_HPD_NONE; 1913 radeon_add_legacy_encoder(dev, 1914 radeon_get_encoder_enum(dev, 1915 ATOM_DEVICE_CRT2_SUPPORT, 1916 2), 1917 ATOM_DEVICE_CRT2_SUPPORT); 1918 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1919 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1920 CONNECTOR_OBJECT_ID_VGA, 1921 &hpd); 1922 /* TV - TV DAC */ 1923 ddc_i2c.valid = false; 1924 hpd.hpd = RADEON_HPD_NONE; 1925 radeon_add_legacy_encoder(dev, 1926 radeon_get_encoder_enum(dev, 1927 ATOM_DEVICE_TV1_SUPPORT, 1928 2), 1929 ATOM_DEVICE_TV1_SUPPORT); 1930 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1931 DRM_MODE_CONNECTOR_SVIDEO, 1932 &ddc_i2c, 1933 CONNECTOR_OBJECT_ID_SVIDEO, 1934 &hpd); 1935 break; 1936 case CT_EMAC: 1937 DRM_INFO("Connector Table: %d (emac)\n", 1938 rdev->mode_info.connector_table); 1939 /* VGA - primary dac */ 1940 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1941 hpd.hpd = RADEON_HPD_NONE; 1942 radeon_add_legacy_encoder(dev, 1943 radeon_get_encoder_enum(dev, 1944 ATOM_DEVICE_CRT1_SUPPORT, 1945 1), 1946 ATOM_DEVICE_CRT1_SUPPORT); 1947 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1948 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1949 CONNECTOR_OBJECT_ID_VGA, 1950 &hpd); 1951 /* VGA - tv dac */ 1952 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1953 hpd.hpd = RADEON_HPD_NONE; 1954 radeon_add_legacy_encoder(dev, 1955 radeon_get_encoder_enum(dev, 1956 ATOM_DEVICE_CRT2_SUPPORT, 1957 2), 1958 ATOM_DEVICE_CRT2_SUPPORT); 1959 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 1960 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1961 CONNECTOR_OBJECT_ID_VGA, 1962 &hpd); 1963 /* TV - TV DAC */ 1964 ddc_i2c.valid = false; 1965 hpd.hpd = RADEON_HPD_NONE; 1966 radeon_add_legacy_encoder(dev, 1967 radeon_get_encoder_enum(dev, 1968 ATOM_DEVICE_TV1_SUPPORT, 1969 2), 1970 ATOM_DEVICE_TV1_SUPPORT); 1971 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 1972 DRM_MODE_CONNECTOR_SVIDEO, 1973 &ddc_i2c, 1974 CONNECTOR_OBJECT_ID_SVIDEO, 1975 &hpd); 1976 break; 1977 case CT_RN50_POWER: 1978 DRM_INFO("Connector Table: %d (rn50-power)\n", 1979 rdev->mode_info.connector_table); 1980 /* VGA - primary dac */ 1981 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 1982 hpd.hpd = RADEON_HPD_NONE; 1983 radeon_add_legacy_encoder(dev, 1984 radeon_get_encoder_enum(dev, 1985 ATOM_DEVICE_CRT1_SUPPORT, 1986 1), 1987 ATOM_DEVICE_CRT1_SUPPORT); 1988 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_CRT1_SUPPORT, 1989 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 1990 CONNECTOR_OBJECT_ID_VGA, 1991 &hpd); 1992 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0); 1993 hpd.hpd = RADEON_HPD_NONE; 1994 radeon_add_legacy_encoder(dev, 1995 radeon_get_encoder_enum(dev, 1996 ATOM_DEVICE_CRT2_SUPPORT, 1997 2), 1998 ATOM_DEVICE_CRT2_SUPPORT); 1999 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT2_SUPPORT, 2000 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2001 CONNECTOR_OBJECT_ID_VGA, 2002 &hpd); 2003 break; 2004 case CT_MAC_X800: 2005 DRM_INFO("Connector Table: %d (mac x800)\n", 2006 rdev->mode_info.connector_table); 2007 /* DVI - primary dac, internal tmds */ 2008 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2009 hpd.hpd = RADEON_HPD_1; /* ??? */ 2010 radeon_add_legacy_encoder(dev, 2011 radeon_get_encoder_enum(dev, 2012 ATOM_DEVICE_DFP1_SUPPORT, 2013 0), 2014 ATOM_DEVICE_DFP1_SUPPORT); 2015 radeon_add_legacy_encoder(dev, 2016 radeon_get_encoder_enum(dev, 2017 ATOM_DEVICE_CRT1_SUPPORT, 2018 1), 2019 ATOM_DEVICE_CRT1_SUPPORT); 2020 radeon_add_legacy_connector(dev, 0, 2021 ATOM_DEVICE_DFP1_SUPPORT | 2022 ATOM_DEVICE_CRT1_SUPPORT, 2023 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2024 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2025 &hpd); 2026 /* DVI - tv dac, dvo */ 2027 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2028 hpd.hpd = RADEON_HPD_2; /* ??? */ 2029 radeon_add_legacy_encoder(dev, 2030 radeon_get_encoder_enum(dev, 2031 ATOM_DEVICE_DFP2_SUPPORT, 2032 0), 2033 ATOM_DEVICE_DFP2_SUPPORT); 2034 radeon_add_legacy_encoder(dev, 2035 radeon_get_encoder_enum(dev, 2036 ATOM_DEVICE_CRT2_SUPPORT, 2037 2), 2038 ATOM_DEVICE_CRT2_SUPPORT); 2039 radeon_add_legacy_connector(dev, 1, 2040 ATOM_DEVICE_DFP2_SUPPORT | 2041 ATOM_DEVICE_CRT2_SUPPORT, 2042 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2043 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, 2044 &hpd); 2045 break; 2046 case CT_MAC_G5_9600: 2047 DRM_INFO("Connector Table: %d (mac g5 9600)\n", 2048 rdev->mode_info.connector_table); 2049 /* DVI - tv dac, dvo */ 2050 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2051 hpd.hpd = RADEON_HPD_1; /* ??? */ 2052 radeon_add_legacy_encoder(dev, 2053 radeon_get_encoder_enum(dev, 2054 ATOM_DEVICE_DFP2_SUPPORT, 2055 0), 2056 ATOM_DEVICE_DFP2_SUPPORT); 2057 radeon_add_legacy_encoder(dev, 2058 radeon_get_encoder_enum(dev, 2059 ATOM_DEVICE_CRT2_SUPPORT, 2060 2), 2061 ATOM_DEVICE_CRT2_SUPPORT); 2062 radeon_add_legacy_connector(dev, 0, 2063 ATOM_DEVICE_DFP2_SUPPORT | 2064 ATOM_DEVICE_CRT2_SUPPORT, 2065 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2066 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2067 &hpd); 2068 /* ADC - primary dac, internal tmds */ 2069 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2070 hpd.hpd = RADEON_HPD_2; /* ??? */ 2071 radeon_add_legacy_encoder(dev, 2072 radeon_get_encoder_enum(dev, 2073 ATOM_DEVICE_DFP1_SUPPORT, 2074 0), 2075 ATOM_DEVICE_DFP1_SUPPORT); 2076 radeon_add_legacy_encoder(dev, 2077 radeon_get_encoder_enum(dev, 2078 ATOM_DEVICE_CRT1_SUPPORT, 2079 1), 2080 ATOM_DEVICE_CRT1_SUPPORT); 2081 radeon_add_legacy_connector(dev, 1, 2082 ATOM_DEVICE_DFP1_SUPPORT | 2083 ATOM_DEVICE_CRT1_SUPPORT, 2084 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2085 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2086 &hpd); 2087 /* TV - TV DAC */ 2088 ddc_i2c.valid = false; 2089 hpd.hpd = RADEON_HPD_NONE; 2090 radeon_add_legacy_encoder(dev, 2091 radeon_get_encoder_enum(dev, 2092 ATOM_DEVICE_TV1_SUPPORT, 2093 2), 2094 ATOM_DEVICE_TV1_SUPPORT); 2095 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2096 DRM_MODE_CONNECTOR_SVIDEO, 2097 &ddc_i2c, 2098 CONNECTOR_OBJECT_ID_SVIDEO, 2099 &hpd); 2100 break; 2101 case CT_SAM440EP: 2102 DRM_INFO("Connector Table: %d (SAM440ep embedded board)\n", 2103 rdev->mode_info.connector_table); 2104 /* LVDS */ 2105 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_NONE_DETECTED, 0, 0); 2106 hpd.hpd = RADEON_HPD_NONE; 2107 radeon_add_legacy_encoder(dev, 2108 radeon_get_encoder_enum(dev, 2109 ATOM_DEVICE_LCD1_SUPPORT, 2110 0), 2111 ATOM_DEVICE_LCD1_SUPPORT); 2112 radeon_add_legacy_connector(dev, 0, ATOM_DEVICE_LCD1_SUPPORT, 2113 DRM_MODE_CONNECTOR_LVDS, &ddc_i2c, 2114 CONNECTOR_OBJECT_ID_LVDS, 2115 &hpd); 2116 /* DVI-I - secondary dac, int tmds */ 2117 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2118 hpd.hpd = RADEON_HPD_1; /* ??? */ 2119 radeon_add_legacy_encoder(dev, 2120 radeon_get_encoder_enum(dev, 2121 ATOM_DEVICE_DFP1_SUPPORT, 2122 0), 2123 ATOM_DEVICE_DFP1_SUPPORT); 2124 radeon_add_legacy_encoder(dev, 2125 radeon_get_encoder_enum(dev, 2126 ATOM_DEVICE_CRT2_SUPPORT, 2127 2), 2128 ATOM_DEVICE_CRT2_SUPPORT); 2129 radeon_add_legacy_connector(dev, 1, 2130 ATOM_DEVICE_DFP1_SUPPORT | 2131 ATOM_DEVICE_CRT2_SUPPORT, 2132 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2133 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2134 &hpd); 2135 /* VGA - primary dac */ 2136 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2137 hpd.hpd = RADEON_HPD_NONE; 2138 radeon_add_legacy_encoder(dev, 2139 radeon_get_encoder_enum(dev, 2140 ATOM_DEVICE_CRT1_SUPPORT, 2141 1), 2142 ATOM_DEVICE_CRT1_SUPPORT); 2143 radeon_add_legacy_connector(dev, 2, 2144 ATOM_DEVICE_CRT1_SUPPORT, 2145 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2146 CONNECTOR_OBJECT_ID_VGA, 2147 &hpd); 2148 /* TV - TV DAC */ 2149 ddc_i2c.valid = false; 2150 hpd.hpd = RADEON_HPD_NONE; 2151 radeon_add_legacy_encoder(dev, 2152 radeon_get_encoder_enum(dev, 2153 ATOM_DEVICE_TV1_SUPPORT, 2154 2), 2155 ATOM_DEVICE_TV1_SUPPORT); 2156 radeon_add_legacy_connector(dev, 3, ATOM_DEVICE_TV1_SUPPORT, 2157 DRM_MODE_CONNECTOR_SVIDEO, 2158 &ddc_i2c, 2159 CONNECTOR_OBJECT_ID_SVIDEO, 2160 &hpd); 2161 break; 2162 case CT_MAC_G4_SILVER: 2163 DRM_INFO("Connector Table: %d (mac g4 silver)\n", 2164 rdev->mode_info.connector_table); 2165 /* DVI-I - tv dac, int tmds */ 2166 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2167 hpd.hpd = RADEON_HPD_1; /* ??? */ 2168 radeon_add_legacy_encoder(dev, 2169 radeon_get_encoder_enum(dev, 2170 ATOM_DEVICE_DFP1_SUPPORT, 2171 0), 2172 ATOM_DEVICE_DFP1_SUPPORT); 2173 radeon_add_legacy_encoder(dev, 2174 radeon_get_encoder_enum(dev, 2175 ATOM_DEVICE_CRT2_SUPPORT, 2176 2), 2177 ATOM_DEVICE_CRT2_SUPPORT); 2178 radeon_add_legacy_connector(dev, 0, 2179 ATOM_DEVICE_DFP1_SUPPORT | 2180 ATOM_DEVICE_CRT2_SUPPORT, 2181 DRM_MODE_CONNECTOR_DVII, &ddc_i2c, 2182 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2183 &hpd); 2184 /* VGA - primary dac */ 2185 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2186 hpd.hpd = RADEON_HPD_NONE; 2187 radeon_add_legacy_encoder(dev, 2188 radeon_get_encoder_enum(dev, 2189 ATOM_DEVICE_CRT1_SUPPORT, 2190 1), 2191 ATOM_DEVICE_CRT1_SUPPORT); 2192 radeon_add_legacy_connector(dev, 1, ATOM_DEVICE_CRT1_SUPPORT, 2193 DRM_MODE_CONNECTOR_VGA, &ddc_i2c, 2194 CONNECTOR_OBJECT_ID_VGA, 2195 &hpd); 2196 /* TV - TV DAC */ 2197 ddc_i2c.valid = false; 2198 hpd.hpd = RADEON_HPD_NONE; 2199 radeon_add_legacy_encoder(dev, 2200 radeon_get_encoder_enum(dev, 2201 ATOM_DEVICE_TV1_SUPPORT, 2202 2), 2203 ATOM_DEVICE_TV1_SUPPORT); 2204 radeon_add_legacy_connector(dev, 2, ATOM_DEVICE_TV1_SUPPORT, 2205 DRM_MODE_CONNECTOR_SVIDEO, 2206 &ddc_i2c, 2207 CONNECTOR_OBJECT_ID_SVIDEO, 2208 &hpd); 2209 break; 2210 default: 2211 DRM_INFO("Connector table: %d (invalid)\n", 2212 rdev->mode_info.connector_table); 2213 return false; 2214 } 2215 2216 radeon_link_encoder_connector(dev); 2217 2218 return true; 2219} 2220 2221static bool radeon_apply_legacy_quirks(struct drm_device *dev, 2222 int bios_index, 2223 enum radeon_combios_connector 2224 *legacy_connector, 2225 struct radeon_i2c_bus_rec *ddc_i2c, 2226 struct radeon_hpd *hpd) 2227{ 2228 2229 /* Certain IBM chipset RN50s have a BIOS reporting two VGAs, 2230 one with VGA DDC and one with CRT2 DDC. - kill the CRT2 DDC one */ 2231 if (dev->pdev->device == 0x515e && 2232 dev->pdev->subsystem_vendor == 0x1014) { 2233 if (*legacy_connector == CONNECTOR_CRT_LEGACY && 2234 ddc_i2c->mask_clk_reg == RADEON_GPIO_CRT2_DDC) 2235 return false; 2236 } 2237 2238 /* X300 card with extra non-existent DVI port */ 2239 if (dev->pdev->device == 0x5B60 && 2240 dev->pdev->subsystem_vendor == 0x17af && 2241 dev->pdev->subsystem_device == 0x201e && bios_index == 2) { 2242 if (*legacy_connector == CONNECTOR_DVI_I_LEGACY) 2243 return false; 2244 } 2245 2246 return true; 2247} 2248 2249static bool radeon_apply_legacy_tv_quirks(struct drm_device *dev) 2250{ 2251 /* Acer 5102 has non-existent TV port */ 2252 if (dev->pdev->device == 0x5975 && 2253 dev->pdev->subsystem_vendor == 0x1025 && 2254 dev->pdev->subsystem_device == 0x009f) 2255 return false; 2256 2257 /* HP dc5750 has non-existent TV port */ 2258 if (dev->pdev->device == 0x5974 && 2259 dev->pdev->subsystem_vendor == 0x103c && 2260 dev->pdev->subsystem_device == 0x280a) 2261 return false; 2262 2263 /* MSI S270 has non-existent TV port */ 2264 if (dev->pdev->device == 0x5955 && 2265 dev->pdev->subsystem_vendor == 0x1462 && 2266 dev->pdev->subsystem_device == 0x0131) 2267 return false; 2268 2269 return true; 2270} 2271 2272static uint16_t combios_check_dl_dvi(struct drm_device *dev, int is_dvi_d) 2273{ 2274 struct radeon_device *rdev = dev->dev_private; 2275 uint32_t ext_tmds_info; 2276 2277 if (rdev->flags & RADEON_IS_IGP) { 2278 if (is_dvi_d) 2279 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2280 else 2281 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2282 } 2283 ext_tmds_info = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2284 if (ext_tmds_info) { 2285 uint8_t rev = RBIOS8(ext_tmds_info); 2286 uint8_t flags = RBIOS8(ext_tmds_info + 4 + 5); 2287 if (rev >= 3) { 2288 if (is_dvi_d) 2289 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2290 else 2291 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2292 } else { 2293 if (flags & 1) { 2294 if (is_dvi_d) 2295 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D; 2296 else 2297 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I; 2298 } 2299 } 2300 } 2301 if (is_dvi_d) 2302 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D; 2303 else 2304 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2305} 2306 2307bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev) 2308{ 2309 struct radeon_device *rdev = dev->dev_private; 2310 uint32_t conn_info, entry, devices; 2311 uint16_t tmp, connector_object_id; 2312 enum radeon_combios_ddc ddc_type; 2313 enum radeon_combios_connector connector; 2314 int i = 0; 2315 struct radeon_i2c_bus_rec ddc_i2c; 2316 struct radeon_hpd hpd; 2317 2318 conn_info = combios_get_table_offset(dev, COMBIOS_CONNECTOR_INFO_TABLE); 2319 if (conn_info) { 2320 for (i = 0; i < 4; i++) { 2321 entry = conn_info + 2 + i * 2; 2322 2323 if (!RBIOS16(entry)) 2324 break; 2325 2326 tmp = RBIOS16(entry); 2327 2328 connector = (tmp >> 12) & 0xf; 2329 2330 ddc_type = (tmp >> 8) & 0xf; 2331 if (ddc_type == 5) 2332 ddc_i2c = radeon_combios_get_i2c_info_from_table(rdev); 2333 else 2334 ddc_i2c = combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2335 2336 switch (connector) { 2337 case CONNECTOR_PROPRIETARY_LEGACY: 2338 case CONNECTOR_DVI_I_LEGACY: 2339 case CONNECTOR_DVI_D_LEGACY: 2340 if ((tmp >> 4) & 0x1) 2341 hpd.hpd = RADEON_HPD_2; 2342 else 2343 hpd.hpd = RADEON_HPD_1; 2344 break; 2345 default: 2346 hpd.hpd = RADEON_HPD_NONE; 2347 break; 2348 } 2349 2350 if (!radeon_apply_legacy_quirks(dev, i, &connector, 2351 &ddc_i2c, &hpd)) 2352 continue; 2353 2354 switch (connector) { 2355 case CONNECTOR_PROPRIETARY_LEGACY: 2356 if ((tmp >> 4) & 0x1) 2357 devices = ATOM_DEVICE_DFP2_SUPPORT; 2358 else 2359 devices = ATOM_DEVICE_DFP1_SUPPORT; 2360 radeon_add_legacy_encoder(dev, 2361 radeon_get_encoder_enum 2362 (dev, devices, 0), 2363 devices); 2364 radeon_add_legacy_connector(dev, i, devices, 2365 legacy_connector_convert 2366 [connector], 2367 &ddc_i2c, 2368 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D, 2369 &hpd); 2370 break; 2371 case CONNECTOR_CRT_LEGACY: 2372 if (tmp & 0x1) { 2373 devices = ATOM_DEVICE_CRT2_SUPPORT; 2374 radeon_add_legacy_encoder(dev, 2375 radeon_get_encoder_enum 2376 (dev, 2377 ATOM_DEVICE_CRT2_SUPPORT, 2378 2), 2379 ATOM_DEVICE_CRT2_SUPPORT); 2380 } else { 2381 devices = ATOM_DEVICE_CRT1_SUPPORT; 2382 radeon_add_legacy_encoder(dev, 2383 radeon_get_encoder_enum 2384 (dev, 2385 ATOM_DEVICE_CRT1_SUPPORT, 2386 1), 2387 ATOM_DEVICE_CRT1_SUPPORT); 2388 } 2389 radeon_add_legacy_connector(dev, 2390 i, 2391 devices, 2392 legacy_connector_convert 2393 [connector], 2394 &ddc_i2c, 2395 CONNECTOR_OBJECT_ID_VGA, 2396 &hpd); 2397 break; 2398 case CONNECTOR_DVI_I_LEGACY: 2399 devices = 0; 2400 if (tmp & 0x1) { 2401 devices |= ATOM_DEVICE_CRT2_SUPPORT; 2402 radeon_add_legacy_encoder(dev, 2403 radeon_get_encoder_enum 2404 (dev, 2405 ATOM_DEVICE_CRT2_SUPPORT, 2406 2), 2407 ATOM_DEVICE_CRT2_SUPPORT); 2408 } else { 2409 devices |= ATOM_DEVICE_CRT1_SUPPORT; 2410 radeon_add_legacy_encoder(dev, 2411 radeon_get_encoder_enum 2412 (dev, 2413 ATOM_DEVICE_CRT1_SUPPORT, 2414 1), 2415 ATOM_DEVICE_CRT1_SUPPORT); 2416 } 2417 /* RV100 board with external TDMS bit mis-set. 2418 * Actually uses internal TMDS, clear the bit. 2419 */ 2420 if (dev->pdev->device == 0x5159 && 2421 dev->pdev->subsystem_vendor == 0x1014 && 2422 dev->pdev->subsystem_device == 0x029A) { 2423 tmp &= ~(1 << 4); 2424 } 2425 if ((tmp >> 4) & 0x1) { 2426 devices |= ATOM_DEVICE_DFP2_SUPPORT; 2427 radeon_add_legacy_encoder(dev, 2428 radeon_get_encoder_enum 2429 (dev, 2430 ATOM_DEVICE_DFP2_SUPPORT, 2431 0), 2432 ATOM_DEVICE_DFP2_SUPPORT); 2433 connector_object_id = combios_check_dl_dvi(dev, 0); 2434 } else { 2435 devices |= ATOM_DEVICE_DFP1_SUPPORT; 2436 radeon_add_legacy_encoder(dev, 2437 radeon_get_encoder_enum 2438 (dev, 2439 ATOM_DEVICE_DFP1_SUPPORT, 2440 0), 2441 ATOM_DEVICE_DFP1_SUPPORT); 2442 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2443 } 2444 radeon_add_legacy_connector(dev, 2445 i, 2446 devices, 2447 legacy_connector_convert 2448 [connector], 2449 &ddc_i2c, 2450 connector_object_id, 2451 &hpd); 2452 break; 2453 case CONNECTOR_DVI_D_LEGACY: 2454 if ((tmp >> 4) & 0x1) { 2455 devices = ATOM_DEVICE_DFP2_SUPPORT; 2456 connector_object_id = combios_check_dl_dvi(dev, 1); 2457 } else { 2458 devices = ATOM_DEVICE_DFP1_SUPPORT; 2459 connector_object_id = CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I; 2460 } 2461 radeon_add_legacy_encoder(dev, 2462 radeon_get_encoder_enum 2463 (dev, devices, 0), 2464 devices); 2465 radeon_add_legacy_connector(dev, i, devices, 2466 legacy_connector_convert 2467 [connector], 2468 &ddc_i2c, 2469 connector_object_id, 2470 &hpd); 2471 break; 2472 case CONNECTOR_CTV_LEGACY: 2473 case CONNECTOR_STV_LEGACY: 2474 radeon_add_legacy_encoder(dev, 2475 radeon_get_encoder_enum 2476 (dev, 2477 ATOM_DEVICE_TV1_SUPPORT, 2478 2), 2479 ATOM_DEVICE_TV1_SUPPORT); 2480 radeon_add_legacy_connector(dev, i, 2481 ATOM_DEVICE_TV1_SUPPORT, 2482 legacy_connector_convert 2483 [connector], 2484 &ddc_i2c, 2485 CONNECTOR_OBJECT_ID_SVIDEO, 2486 &hpd); 2487 break; 2488 default: 2489 DRM_ERROR("Unknown connector type: %d\n", 2490 connector); 2491 continue; 2492 } 2493 2494 } 2495 } else { 2496 uint16_t tmds_info = 2497 combios_get_table_offset(dev, COMBIOS_DFP_INFO_TABLE); 2498 if (tmds_info) { 2499 DRM_DEBUG_KMS("Found DFP table, assuming DVI connector\n"); 2500 2501 radeon_add_legacy_encoder(dev, 2502 radeon_get_encoder_enum(dev, 2503 ATOM_DEVICE_CRT1_SUPPORT, 2504 1), 2505 ATOM_DEVICE_CRT1_SUPPORT); 2506 radeon_add_legacy_encoder(dev, 2507 radeon_get_encoder_enum(dev, 2508 ATOM_DEVICE_DFP1_SUPPORT, 2509 0), 2510 ATOM_DEVICE_DFP1_SUPPORT); 2511 2512 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0); 2513 hpd.hpd = RADEON_HPD_1; 2514 radeon_add_legacy_connector(dev, 2515 0, 2516 ATOM_DEVICE_CRT1_SUPPORT | 2517 ATOM_DEVICE_DFP1_SUPPORT, 2518 DRM_MODE_CONNECTOR_DVII, 2519 &ddc_i2c, 2520 CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I, 2521 &hpd); 2522 } else { 2523 uint16_t crt_info = 2524 combios_get_table_offset(dev, COMBIOS_CRT_INFO_TABLE); 2525 DRM_DEBUG_KMS("Found CRT table, assuming VGA connector\n"); 2526 if (crt_info) { 2527 radeon_add_legacy_encoder(dev, 2528 radeon_get_encoder_enum(dev, 2529 ATOM_DEVICE_CRT1_SUPPORT, 2530 1), 2531 ATOM_DEVICE_CRT1_SUPPORT); 2532 ddc_i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0); 2533 hpd.hpd = RADEON_HPD_NONE; 2534 radeon_add_legacy_connector(dev, 2535 0, 2536 ATOM_DEVICE_CRT1_SUPPORT, 2537 DRM_MODE_CONNECTOR_VGA, 2538 &ddc_i2c, 2539 CONNECTOR_OBJECT_ID_VGA, 2540 &hpd); 2541 } else { 2542 DRM_DEBUG_KMS("No connector info found\n"); 2543 return false; 2544 } 2545 } 2546 } 2547 2548 if (rdev->flags & RADEON_IS_MOBILITY || rdev->flags & RADEON_IS_IGP) { 2549 uint16_t lcd_info = 2550 combios_get_table_offset(dev, COMBIOS_LCD_INFO_TABLE); 2551 if (lcd_info) { 2552 uint16_t lcd_ddc_info = 2553 combios_get_table_offset(dev, 2554 COMBIOS_LCD_DDC_INFO_TABLE); 2555 2556 radeon_add_legacy_encoder(dev, 2557 radeon_get_encoder_enum(dev, 2558 ATOM_DEVICE_LCD1_SUPPORT, 2559 0), 2560 ATOM_DEVICE_LCD1_SUPPORT); 2561 2562 if (lcd_ddc_info) { 2563 ddc_type = RBIOS8(lcd_ddc_info + 2); 2564 switch (ddc_type) { 2565 case DDC_LCD: 2566 ddc_i2c = 2567 combios_setup_i2c_bus(rdev, 2568 DDC_LCD, 2569 RBIOS32(lcd_ddc_info + 3), 2570 RBIOS32(lcd_ddc_info + 7)); 2571 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2572 break; 2573 case DDC_GPIO: 2574 ddc_i2c = 2575 combios_setup_i2c_bus(rdev, 2576 DDC_GPIO, 2577 RBIOS32(lcd_ddc_info + 3), 2578 RBIOS32(lcd_ddc_info + 7)); 2579 radeon_i2c_add(rdev, &ddc_i2c, "LCD"); 2580 break; 2581 default: 2582 ddc_i2c = 2583 combios_setup_i2c_bus(rdev, ddc_type, 0, 0); 2584 break; 2585 } 2586 DRM_DEBUG_KMS("LCD DDC Info Table found!\n"); 2587 } else 2588 ddc_i2c.valid = false; 2589 2590 hpd.hpd = RADEON_HPD_NONE; 2591 radeon_add_legacy_connector(dev, 2592 5, 2593 ATOM_DEVICE_LCD1_SUPPORT, 2594 DRM_MODE_CONNECTOR_LVDS, 2595 &ddc_i2c, 2596 CONNECTOR_OBJECT_ID_LVDS, 2597 &hpd); 2598 } 2599 } 2600 2601 /* check TV table */ 2602 if (rdev->family != CHIP_R100 && rdev->family != CHIP_R200) { 2603 uint32_t tv_info = 2604 combios_get_table_offset(dev, COMBIOS_TV_INFO_TABLE); 2605 if (tv_info) { 2606 if (RBIOS8(tv_info + 6) == 'T') { 2607 if (radeon_apply_legacy_tv_quirks(dev)) { 2608 hpd.hpd = RADEON_HPD_NONE; 2609 ddc_i2c.valid = false; 2610 radeon_add_legacy_encoder(dev, 2611 radeon_get_encoder_enum 2612 (dev, 2613 ATOM_DEVICE_TV1_SUPPORT, 2614 2), 2615 ATOM_DEVICE_TV1_SUPPORT); 2616 radeon_add_legacy_connector(dev, 6, 2617 ATOM_DEVICE_TV1_SUPPORT, 2618 DRM_MODE_CONNECTOR_SVIDEO, 2619 &ddc_i2c, 2620 CONNECTOR_OBJECT_ID_SVIDEO, 2621 &hpd); 2622 } 2623 } 2624 } 2625 } 2626 2627 radeon_link_encoder_connector(dev); 2628 2629 return true; 2630} 2631 2632static const char *thermal_controller_names[] = { 2633 "NONE", 2634 "lm63", 2635 "adm1032", 2636}; 2637 2638void radeon_combios_get_power_modes(struct radeon_device *rdev) 2639{ 2640 struct drm_device *dev = rdev->ddev; 2641 u16 offset, misc, misc2 = 0; 2642 u8 rev, tmp; 2643 int state_index = 0; 2644 struct radeon_i2c_bus_rec i2c_bus; 2645 2646 rdev->pm.default_power_state_index = -1; 2647 2648 /* allocate 2 power states */ 2649 rdev->pm.power_state = kcalloc(2, sizeof(struct radeon_power_state), 2650 GFP_KERNEL); 2651 if (rdev->pm.power_state) { 2652 /* allocate 1 clock mode per state */ 2653 rdev->pm.power_state[0].clock_info = 2654 kcalloc(1, sizeof(struct radeon_pm_clock_info), 2655 GFP_KERNEL); 2656 rdev->pm.power_state[1].clock_info = 2657 kcalloc(1, sizeof(struct radeon_pm_clock_info), 2658 GFP_KERNEL); 2659 if (!rdev->pm.power_state[0].clock_info || 2660 !rdev->pm.power_state[1].clock_info) 2661 goto pm_failed; 2662 } else 2663 goto pm_failed; 2664 2665 /* check for a thermal chip */ 2666 offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE); 2667 if (offset) { 2668 u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0; 2669 2670 rev = RBIOS8(offset); 2671 2672 if (rev == 0) { 2673 thermal_controller = RBIOS8(offset + 3); 2674 gpio = RBIOS8(offset + 4) & 0x3f; 2675 i2c_addr = RBIOS8(offset + 5); 2676 } else if (rev == 1) { 2677 thermal_controller = RBIOS8(offset + 4); 2678 gpio = RBIOS8(offset + 5) & 0x3f; 2679 i2c_addr = RBIOS8(offset + 6); 2680 } else if (rev == 2) { 2681 thermal_controller = RBIOS8(offset + 4); 2682 gpio = RBIOS8(offset + 5) & 0x3f; 2683 i2c_addr = RBIOS8(offset + 6); 2684 clk_bit = RBIOS8(offset + 0xa); 2685 data_bit = RBIOS8(offset + 0xb); 2686 } 2687 if ((thermal_controller > 0) && (thermal_controller < 3)) { 2688 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2689 thermal_controller_names[thermal_controller], 2690 i2c_addr >> 1); 2691 if (gpio == DDC_LCD) { 2692 /* MM i2c */ 2693 i2c_bus.valid = true; 2694 i2c_bus.hw_capable = true; 2695 i2c_bus.mm_i2c = true; 2696 i2c_bus.i2c_id = 0xa0; 2697 } else if (gpio == DDC_GPIO) 2698 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit); 2699 else 2700 i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0); 2701 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2702 if (rdev->pm.i2c_bus) { 2703 struct i2c_board_info info = { }; 2704 const char *name = thermal_controller_names[thermal_controller]; 2705 info.addr = i2c_addr >> 1; 2706 strlcpy(info.type, name, sizeof(info.type)); 2707 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2708 } 2709 } 2710 } else { 2711 /* boards with a thermal chip, but no overdrive table */ 2712 2713 /* Asus 9600xt has an f75375 on the monid bus */ 2714 if ((dev->pdev->device == 0x4152) && 2715 (dev->pdev->subsystem_vendor == 0x1043) && 2716 (dev->pdev->subsystem_device == 0xc002)) { 2717 i2c_bus = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0); 2718 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus); 2719 if (rdev->pm.i2c_bus) { 2720 struct i2c_board_info info = { }; 2721 const char *name = "f75375"; 2722 info.addr = 0x28; 2723 strlcpy(info.type, name, sizeof(info.type)); 2724 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info); 2725 DRM_INFO("Possible %s thermal controller at 0x%02x\n", 2726 name, info.addr); 2727 } 2728 } 2729 } 2730 2731 if (rdev->flags & RADEON_IS_MOBILITY) { 2732 offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE); 2733 if (offset) { 2734 rev = RBIOS8(offset); 2735 /* power mode 0 tends to be the only valid one */ 2736 rdev->pm.power_state[state_index].num_clock_modes = 1; 2737 rdev->pm.power_state[state_index].clock_info[0].mclk = RBIOS32(offset + 0x5 + 0x2); 2738 rdev->pm.power_state[state_index].clock_info[0].sclk = RBIOS32(offset + 0x5 + 0x6); 2739 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) || 2740 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0)) 2741 goto default_mode; 2742 rdev->pm.power_state[state_index].type = 2743 POWER_STATE_TYPE_BATTERY; 2744 misc = RBIOS16(offset + 0x5 + 0x0); 2745 if (rev > 4) 2746 misc2 = RBIOS16(offset + 0x5 + 0xe); 2747 rdev->pm.power_state[state_index].misc = misc; 2748 rdev->pm.power_state[state_index].misc2 = misc2; 2749 if (misc & 0x4) { 2750 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_GPIO; 2751 if (misc & 0x8) 2752 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2753 true; 2754 else 2755 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high = 2756 false; 2757 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = true; 2758 if (rev < 6) { 2759 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2760 RBIOS16(offset + 0x5 + 0xb) * 4; 2761 tmp = RBIOS8(offset + 0x5 + 0xd); 2762 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2763 } else { 2764 u8 entries = RBIOS8(offset + 0x5 + 0xb); 2765 u16 voltage_table_offset = RBIOS16(offset + 0x5 + 0xc); 2766 if (entries && voltage_table_offset) { 2767 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.reg = 2768 RBIOS16(voltage_table_offset) * 4; 2769 tmp = RBIOS8(voltage_table_offset + 0x2); 2770 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.mask = (1 << tmp); 2771 } else 2772 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio.valid = false; 2773 } 2774 switch ((misc2 & 0x700) >> 8) { 2775 case 0: 2776 default: 2777 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 0; 2778 break; 2779 case 1: 2780 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 33; 2781 break; 2782 case 2: 2783 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 66; 2784 break; 2785 case 3: 2786 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 99; 2787 break; 2788 case 4: 2789 rdev->pm.power_state[state_index].clock_info[0].voltage.delay = 132; 2790 break; 2791 } 2792 } else 2793 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2794 if (rev > 6) 2795 rdev->pm.power_state[state_index].pcie_lanes = 2796 RBIOS8(offset + 0x5 + 0x10); 2797 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY; 2798 state_index++; 2799 } else { 2800 /* XXX figure out some good default low power mode for mobility cards w/out power tables */ 2801 } 2802 } else { 2803 /* XXX figure out some good default low power mode for desktop cards */ 2804 } 2805 2806default_mode: 2807 /* add the default mode */ 2808 rdev->pm.power_state[state_index].type = 2809 POWER_STATE_TYPE_DEFAULT; 2810 rdev->pm.power_state[state_index].num_clock_modes = 1; 2811 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk; 2812 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk; 2813 rdev->pm.power_state[state_index].default_clock_mode = &rdev->pm.power_state[state_index].clock_info[0]; 2814 if ((state_index > 0) && 2815 (rdev->pm.power_state[0].clock_info[0].voltage.type == VOLTAGE_GPIO)) 2816 rdev->pm.power_state[state_index].clock_info[0].voltage = 2817 rdev->pm.power_state[0].clock_info[0].voltage; 2818 else 2819 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE; 2820 rdev->pm.power_state[state_index].pcie_lanes = 16; 2821 rdev->pm.power_state[state_index].flags = 0; 2822 rdev->pm.default_power_state_index = state_index; 2823 rdev->pm.num_power_states = state_index + 1; 2824 2825 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2826 rdev->pm.current_clock_mode_index = 0; 2827 return; 2828 2829pm_failed: 2830 rdev->pm.default_power_state_index = state_index; 2831 rdev->pm.num_power_states = 0; 2832 2833 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index; 2834 rdev->pm.current_clock_mode_index = 0; 2835} 2836 2837void radeon_external_tmds_setup(struct drm_encoder *encoder) 2838{ 2839 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2840 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2841 2842 if (!tmds) 2843 return; 2844 2845 switch (tmds->dvo_chip) { 2846 case DVO_SIL164: 2847 /* sil 164 */ 2848 radeon_i2c_put_byte(tmds->i2c_bus, 2849 tmds->slave_addr, 2850 0x08, 0x30); 2851 radeon_i2c_put_byte(tmds->i2c_bus, 2852 tmds->slave_addr, 2853 0x09, 0x00); 2854 radeon_i2c_put_byte(tmds->i2c_bus, 2855 tmds->slave_addr, 2856 0x0a, 0x90); 2857 radeon_i2c_put_byte(tmds->i2c_bus, 2858 tmds->slave_addr, 2859 0x0c, 0x89); 2860 radeon_i2c_put_byte(tmds->i2c_bus, 2861 tmds->slave_addr, 2862 0x08, 0x3b); 2863 break; 2864 case DVO_SIL1178: 2865 /* sil 1178 - untested */ 2866 /* 2867 * 0x0f, 0x44 2868 * 0x0f, 0x4c 2869 * 0x0e, 0x01 2870 * 0x0a, 0x80 2871 * 0x09, 0x30 2872 * 0x0c, 0xc9 2873 * 0x0d, 0x70 2874 * 0x08, 0x32 2875 * 0x08, 0x33 2876 */ 2877 break; 2878 default: 2879 break; 2880 } 2881 2882} 2883 2884bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder) 2885{ 2886 struct drm_device *dev = encoder->dev; 2887 struct radeon_device *rdev = dev->dev_private; 2888 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2889 uint16_t offset; 2890 uint8_t blocks, slave_addr, rev; 2891 uint32_t index, id; 2892 uint32_t reg, val, and_mask, or_mask; 2893 struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv; 2894 2895 if (!tmds) 2896 return false; 2897 2898 if (rdev->flags & RADEON_IS_IGP) { 2899 offset = combios_get_table_offset(dev, COMBIOS_TMDS_POWER_ON_TABLE); 2900 rev = RBIOS8(offset); 2901 if (offset) { 2902 rev = RBIOS8(offset); 2903 if (rev > 1) { 2904 blocks = RBIOS8(offset + 3); 2905 index = offset + 4; 2906 while (blocks > 0) { 2907 id = RBIOS16(index); 2908 index += 2; 2909 switch (id >> 13) { 2910 case 0: 2911 reg = (id & 0x1fff) * 4; 2912 val = RBIOS32(index); 2913 index += 4; 2914 WREG32(reg, val); 2915 break; 2916 case 2: 2917 reg = (id & 0x1fff) * 4; 2918 and_mask = RBIOS32(index); 2919 index += 4; 2920 or_mask = RBIOS32(index); 2921 index += 4; 2922 val = RREG32(reg); 2923 val = (val & and_mask) | or_mask; 2924 WREG32(reg, val); 2925 break; 2926 case 3: 2927 val = RBIOS16(index); 2928 index += 2; 2929 udelay(val); 2930 break; 2931 case 4: 2932 val = RBIOS16(index); 2933 index += 2; 2934 mdelay(val); 2935 break; 2936 case 6: 2937 slave_addr = id & 0xff; 2938 slave_addr >>= 1; /* 7 bit addressing */ 2939 index++; 2940 reg = RBIOS8(index); 2941 index++; 2942 val = RBIOS8(index); 2943 index++; 2944 radeon_i2c_put_byte(tmds->i2c_bus, 2945 slave_addr, 2946 reg, val); 2947 break; 2948 default: 2949 DRM_ERROR("Unknown id %d\n", id >> 13); 2950 break; 2951 } 2952 blocks--; 2953 } 2954 return true; 2955 } 2956 } 2957 } else { 2958 offset = combios_get_table_offset(dev, COMBIOS_EXT_TMDS_INFO_TABLE); 2959 if (offset) { 2960 index = offset + 10; 2961 id = RBIOS16(index); 2962 while (id != 0xffff) { 2963 index += 2; 2964 switch (id >> 13) { 2965 case 0: 2966 reg = (id & 0x1fff) * 4; 2967 val = RBIOS32(index); 2968 WREG32(reg, val); 2969 break; 2970 case 2: 2971 reg = (id & 0x1fff) * 4; 2972 and_mask = RBIOS32(index); 2973 index += 4; 2974 or_mask = RBIOS32(index); 2975 index += 4; 2976 val = RREG32(reg); 2977 val = (val & and_mask) | or_mask; 2978 WREG32(reg, val); 2979 break; 2980 case 4: 2981 val = RBIOS16(index); 2982 index += 2; 2983 udelay(val); 2984 break; 2985 case 5: 2986 reg = id & 0x1fff; 2987 and_mask = RBIOS32(index); 2988 index += 4; 2989 or_mask = RBIOS32(index); 2990 index += 4; 2991 val = RREG32_PLL(reg); 2992 val = (val & and_mask) | or_mask; 2993 WREG32_PLL(reg, val); 2994 break; 2995 case 6: 2996 reg = id & 0x1fff; 2997 val = RBIOS8(index); 2998 index += 1; 2999 radeon_i2c_put_byte(tmds->i2c_bus, 3000 tmds->slave_addr, 3001 reg, val); 3002 break; 3003 default: 3004 DRM_ERROR("Unknown id %d\n", id >> 13); 3005 break; 3006 } 3007 id = RBIOS16(index); 3008 } 3009 return true; 3010 } 3011 } 3012 return false; 3013} 3014 3015static void combios_parse_mmio_table(struct drm_device *dev, uint16_t offset) 3016{ 3017 struct radeon_device *rdev = dev->dev_private; 3018 3019 if (offset) { 3020 while (RBIOS16(offset)) { 3021 uint16_t cmd = ((RBIOS16(offset) & 0xe000) >> 13); 3022 uint32_t addr = (RBIOS16(offset) & 0x1fff); 3023 uint32_t val, and_mask, or_mask; 3024 uint32_t tmp; 3025 3026 offset += 2; 3027 switch (cmd) { 3028 case 0: 3029 val = RBIOS32(offset); 3030 offset += 4; 3031 WREG32(addr, val); 3032 break; 3033 case 1: 3034 val = RBIOS32(offset); 3035 offset += 4; 3036 WREG32(addr, val); 3037 break; 3038 case 2: 3039 and_mask = RBIOS32(offset); 3040 offset += 4; 3041 or_mask = RBIOS32(offset); 3042 offset += 4; 3043 tmp = RREG32(addr); 3044 tmp &= and_mask; 3045 tmp |= or_mask; 3046 WREG32(addr, tmp); 3047 break; 3048 case 3: 3049 and_mask = RBIOS32(offset); 3050 offset += 4; 3051 or_mask = RBIOS32(offset); 3052 offset += 4; 3053 tmp = RREG32(addr); 3054 tmp &= and_mask; 3055 tmp |= or_mask; 3056 WREG32(addr, tmp); 3057 break; 3058 case 4: 3059 val = RBIOS16(offset); 3060 offset += 2; 3061 udelay(val); 3062 break; 3063 case 5: 3064 val = RBIOS16(offset); 3065 offset += 2; 3066 switch (addr) { 3067 case 8: 3068 while (val--) { 3069 if (! 3070 (RREG32_PLL 3071 (RADEON_CLK_PWRMGT_CNTL) & 3072 RADEON_MC_BUSY)) 3073 break; 3074 } 3075 break; 3076 case 9: 3077 while (val--) { 3078 if ((RREG32(RADEON_MC_STATUS) & 3079 RADEON_MC_IDLE)) 3080 break; 3081 } 3082 break; 3083 default: 3084 break; 3085 } 3086 break; 3087 default: 3088 break; 3089 } 3090 } 3091 } 3092} 3093 3094static void combios_parse_pll_table(struct drm_device *dev, uint16_t offset) 3095{ 3096 struct radeon_device *rdev = dev->dev_private; 3097 3098 if (offset) { 3099 while (RBIOS8(offset)) { 3100 uint8_t cmd = ((RBIOS8(offset) & 0xc0) >> 6); 3101 uint8_t addr = (RBIOS8(offset) & 0x3f); 3102 uint32_t val, shift, tmp; 3103 uint32_t and_mask, or_mask; 3104 3105 offset++; 3106 switch (cmd) { 3107 case 0: 3108 val = RBIOS32(offset); 3109 offset += 4; 3110 WREG32_PLL(addr, val); 3111 break; 3112 case 1: 3113 shift = RBIOS8(offset) * 8; 3114 offset++; 3115 and_mask = RBIOS8(offset) << shift; 3116 and_mask |= ~(0xff << shift); 3117 offset++; 3118 or_mask = RBIOS8(offset) << shift; 3119 offset++; 3120 tmp = RREG32_PLL(addr); 3121 tmp &= and_mask; 3122 tmp |= or_mask; 3123 WREG32_PLL(addr, tmp); 3124 break; 3125 case 2: 3126 case 3: 3127 tmp = 1000; 3128 switch (addr) { 3129 case 1: 3130 udelay(150); 3131 break; 3132 case 2: 3133 mdelay(1); 3134 break; 3135 case 3: 3136 while (tmp--) { 3137 if (! 3138 (RREG32_PLL 3139 (RADEON_CLK_PWRMGT_CNTL) & 3140 RADEON_MC_BUSY)) 3141 break; 3142 } 3143 break; 3144 case 4: 3145 while (tmp--) { 3146 if (RREG32_PLL 3147 (RADEON_CLK_PWRMGT_CNTL) & 3148 RADEON_DLL_READY) 3149 break; 3150 } 3151 break; 3152 case 5: 3153 tmp = 3154 RREG32_PLL(RADEON_CLK_PWRMGT_CNTL); 3155 if (tmp & RADEON_CG_NO1_DEBUG_0) { 3156#if 0 3157 uint32_t mclk_cntl = 3158 RREG32_PLL 3159 (RADEON_MCLK_CNTL); 3160 mclk_cntl &= 0xffff0000; 3161 /*mclk_cntl |= 0x00001111;*//* ??? */ 3162 WREG32_PLL(RADEON_MCLK_CNTL, 3163 mclk_cntl); 3164 mdelay(10); 3165#endif 3166 WREG32_PLL 3167 (RADEON_CLK_PWRMGT_CNTL, 3168 tmp & 3169 ~RADEON_CG_NO1_DEBUG_0); 3170 mdelay(10); 3171 } 3172 break; 3173 default: 3174 break; 3175 } 3176 break; 3177 default: 3178 break; 3179 } 3180 } 3181 } 3182} 3183 3184static void combios_parse_ram_reset_table(struct drm_device *dev, 3185 uint16_t offset) 3186{ 3187 struct radeon_device *rdev = dev->dev_private; 3188 uint32_t tmp; 3189 3190 if (offset) { 3191 uint8_t val = RBIOS8(offset); 3192 while (val != 0xff) { 3193 offset++; 3194 3195 if (val == 0x0f) { 3196 uint32_t channel_complete_mask; 3197 3198 if (ASIC_IS_R300(rdev)) 3199 channel_complete_mask = 3200 R300_MEM_PWRUP_COMPLETE; 3201 else 3202 channel_complete_mask = 3203 RADEON_MEM_PWRUP_COMPLETE; 3204 tmp = 20000; 3205 while (tmp--) { 3206 if ((RREG32(RADEON_MEM_STR_CNTL) & 3207 channel_complete_mask) == 3208 channel_complete_mask) 3209 break; 3210 } 3211 } else { 3212 uint32_t or_mask = RBIOS16(offset); 3213 offset += 2; 3214 3215 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3216 tmp &= RADEON_SDRAM_MODE_MASK; 3217 tmp |= or_mask; 3218 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3219 3220 or_mask = val << 24; 3221 tmp = RREG32(RADEON_MEM_SDRAM_MODE_REG); 3222 tmp &= RADEON_B3MEM_RESET_MASK; 3223 tmp |= or_mask; 3224 WREG32(RADEON_MEM_SDRAM_MODE_REG, tmp); 3225 } 3226 val = RBIOS8(offset); 3227 } 3228 } 3229} 3230 3231static uint32_t combios_detect_ram(struct drm_device *dev, int ram, 3232 int mem_addr_mapping) 3233{ 3234 struct radeon_device *rdev = dev->dev_private; 3235 uint32_t mem_cntl; 3236 uint32_t mem_size; 3237 uint32_t addr = 0; 3238 3239 mem_cntl = RREG32(RADEON_MEM_CNTL); 3240 if (mem_cntl & RV100_HALF_MODE) 3241 ram /= 2; 3242 mem_size = ram; 3243 mem_cntl &= ~(0xff << 8); 3244 mem_cntl |= (mem_addr_mapping & 0xff) << 8; 3245 WREG32(RADEON_MEM_CNTL, mem_cntl); 3246 RREG32(RADEON_MEM_CNTL); 3247 3248 /* sdram reset ? */ 3249 3250 /* something like this???? */ 3251 while (ram--) { 3252 addr = ram * 1024 * 1024; 3253 /* write to each page */ 3254 WREG32_IDX((addr) | RADEON_MM_APER, 0xdeadbeef); 3255 /* read back and verify */ 3256 if (RREG32_IDX((addr) | RADEON_MM_APER) != 0xdeadbeef) 3257 return 0; 3258 } 3259 3260 return mem_size; 3261} 3262 3263static void combios_write_ram_size(struct drm_device *dev) 3264{ 3265 struct radeon_device *rdev = dev->dev_private; 3266 uint8_t rev; 3267 uint16_t offset; 3268 uint32_t mem_size = 0; 3269 uint32_t mem_cntl = 0; 3270 3271 /* should do something smarter here I guess... */ 3272 if (rdev->flags & RADEON_IS_IGP) 3273 return; 3274 3275 /* first check detected mem table */ 3276 offset = combios_get_table_offset(dev, COMBIOS_DETECTED_MEM_TABLE); 3277 if (offset) { 3278 rev = RBIOS8(offset); 3279 if (rev < 3) { 3280 mem_cntl = RBIOS32(offset + 1); 3281 mem_size = RBIOS16(offset + 5); 3282 if ((rdev->family < CHIP_R200) && 3283 !ASIC_IS_RN50(rdev)) 3284 WREG32(RADEON_MEM_CNTL, mem_cntl); 3285 } 3286 } 3287 3288 if (!mem_size) { 3289 offset = 3290 combios_get_table_offset(dev, COMBIOS_MEM_CONFIG_TABLE); 3291 if (offset) { 3292 rev = RBIOS8(offset - 1); 3293 if (rev < 1) { 3294 if ((rdev->family < CHIP_R200) 3295 && !ASIC_IS_RN50(rdev)) { 3296 int ram = 0; 3297 int mem_addr_mapping = 0; 3298 3299 while (RBIOS8(offset)) { 3300 ram = RBIOS8(offset); 3301 mem_addr_mapping = 3302 RBIOS8(offset + 1); 3303 if (mem_addr_mapping != 0x25) 3304 ram *= 2; 3305 mem_size = 3306 combios_detect_ram(dev, ram, 3307 mem_addr_mapping); 3308 if (mem_size) 3309 break; 3310 offset += 2; 3311 } 3312 } else 3313 mem_size = RBIOS8(offset); 3314 } else { 3315 mem_size = RBIOS8(offset); 3316 mem_size *= 2; /* convert to MB */ 3317 } 3318 } 3319 } 3320 3321 mem_size *= (1024 * 1024); /* convert to bytes */ 3322 WREG32(RADEON_CONFIG_MEMSIZE, mem_size); 3323} 3324 3325void radeon_combios_asic_init(struct drm_device *dev) 3326{ 3327 struct radeon_device *rdev = dev->dev_private; 3328 uint16_t table; 3329 3330 /* port hardcoded mac stuff from radeonfb */ 3331 if (rdev->bios == NULL) 3332 return; 3333 3334 /* ASIC INIT 1 */ 3335 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_1_TABLE); 3336 if (table) 3337 combios_parse_mmio_table(dev, table); 3338 3339 /* PLL INIT */ 3340 table = combios_get_table_offset(dev, COMBIOS_PLL_INIT_TABLE); 3341 if (table) 3342 combios_parse_pll_table(dev, table); 3343 3344 /* ASIC INIT 2 */ 3345 table = combios_get_table_offset(dev, COMBIOS_ASIC_INIT_2_TABLE); 3346 if (table) 3347 combios_parse_mmio_table(dev, table); 3348 3349 if (!(rdev->flags & RADEON_IS_IGP)) { 3350 /* ASIC INIT 4 */ 3351 table = 3352 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_4_TABLE); 3353 if (table) 3354 combios_parse_mmio_table(dev, table); 3355 3356 /* RAM RESET */ 3357 table = combios_get_table_offset(dev, COMBIOS_RAM_RESET_TABLE); 3358 if (table) 3359 combios_parse_ram_reset_table(dev, table); 3360 3361 /* ASIC INIT 3 */ 3362 table = 3363 combios_get_table_offset(dev, COMBIOS_ASIC_INIT_3_TABLE); 3364 if (table) 3365 combios_parse_mmio_table(dev, table); 3366 3367 /* write CONFIG_MEMSIZE */ 3368 combios_write_ram_size(dev); 3369 } 3370 3371 /* quirk for rs4xx HP nx6125 laptop to make it resume 3372 * - it hangs on resume inside the dynclk 1 table. 3373 */ 3374 if (rdev->family == CHIP_RS480 && 3375 rdev->pdev->subsystem_vendor == 0x103c && 3376 rdev->pdev->subsystem_device == 0x308b) 3377 return; 3378 3379 /* quirk for rs4xx HP dv5000 laptop to make it resume 3380 * - it hangs on resume inside the dynclk 1 table. 3381 */ 3382 if (rdev->family == CHIP_RS480 && 3383 rdev->pdev->subsystem_vendor == 0x103c && 3384 rdev->pdev->subsystem_device == 0x30a4) 3385 return; 3386 3387 /* quirk for rs4xx Compaq Presario V5245EU laptop to make it resume 3388 * - it hangs on resume inside the dynclk 1 table. 3389 */ 3390 if (rdev->family == CHIP_RS480 && 3391 rdev->pdev->subsystem_vendor == 0x103c && 3392 rdev->pdev->subsystem_device == 0x30ae) 3393 return; 3394 3395 /* quirk for rs4xx HP Compaq dc5750 Small Form Factor to make it resume 3396 * - it hangs on resume inside the dynclk 1 table. 3397 */ 3398 if (rdev->family == CHIP_RS480 && 3399 rdev->pdev->subsystem_vendor == 0x103c && 3400 rdev->pdev->subsystem_device == 0x280a) 3401 return; 3402 /* quirk for rs4xx Toshiba Sattellite L20-183 latop to make it resume 3403 * - it hangs on resume inside the dynclk 1 table. 3404 */ 3405 if (rdev->family == CHIP_RS400 && 3406 rdev->pdev->subsystem_vendor == 0x1179 && 3407 rdev->pdev->subsystem_device == 0xff31) 3408 return; 3409 3410 /* DYN CLK 1 */ 3411 table = combios_get_table_offset(dev, COMBIOS_DYN_CLK_1_TABLE); 3412 if (table) 3413 combios_parse_pll_table(dev, table); 3414 3415} 3416 3417void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev) 3418{ 3419 struct radeon_device *rdev = dev->dev_private; 3420 uint32_t bios_0_scratch, bios_6_scratch, bios_7_scratch; 3421 3422 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH); 3423 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3424 bios_7_scratch = RREG32(RADEON_BIOS_7_SCRATCH); 3425 3426 /* let the bios control the backlight */ 3427 bios_0_scratch &= ~RADEON_DRIVER_BRIGHTNESS_EN; 3428 3429 /* tell the bios not to handle mode switching */ 3430 bios_6_scratch |= (RADEON_DISPLAY_SWITCHING_DIS | 3431 RADEON_ACC_MODE_CHANGE); 3432 3433 /* tell the bios a driver is loaded */ 3434 bios_7_scratch |= RADEON_DRV_LOADED; 3435 3436 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch); 3437 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3438 WREG32(RADEON_BIOS_7_SCRATCH, bios_7_scratch); 3439} 3440 3441void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock) 3442{ 3443 struct drm_device *dev = encoder->dev; 3444 struct radeon_device *rdev = dev->dev_private; 3445 uint32_t bios_6_scratch; 3446 3447 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3448 3449 if (lock) 3450 bios_6_scratch |= RADEON_DRIVER_CRITICAL; 3451 else 3452 bios_6_scratch &= ~RADEON_DRIVER_CRITICAL; 3453 3454 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3455} 3456 3457void 3458radeon_combios_connected_scratch_regs(struct drm_connector *connector, 3459 struct drm_encoder *encoder, 3460 bool connected) 3461{ 3462 struct drm_device *dev = connector->dev; 3463 struct radeon_device *rdev = dev->dev_private; 3464 struct radeon_connector *radeon_connector = 3465 to_radeon_connector(connector); 3466 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3467 uint32_t bios_4_scratch = RREG32(RADEON_BIOS_4_SCRATCH); 3468 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3469 3470 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) && 3471 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) { 3472 if (connected) { 3473 DRM_DEBUG_KMS("TV1 connected\n"); 3474 /* fix me */ 3475 bios_4_scratch |= RADEON_TV1_ATTACHED_SVIDEO; 3476 /*save->bios_4_scratch |= RADEON_TV1_ATTACHED_COMP; */ 3477 bios_5_scratch |= RADEON_TV1_ON; 3478 bios_5_scratch |= RADEON_ACC_REQ_TV1; 3479 } else { 3480 DRM_DEBUG_KMS("TV1 disconnected\n"); 3481 bios_4_scratch &= ~RADEON_TV1_ATTACHED_MASK; 3482 bios_5_scratch &= ~RADEON_TV1_ON; 3483 bios_5_scratch &= ~RADEON_ACC_REQ_TV1; 3484 } 3485 } 3486 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) && 3487 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) { 3488 if (connected) { 3489 DRM_DEBUG_KMS("LCD1 connected\n"); 3490 bios_4_scratch |= RADEON_LCD1_ATTACHED; 3491 bios_5_scratch |= RADEON_LCD1_ON; 3492 bios_5_scratch |= RADEON_ACC_REQ_LCD1; 3493 } else { 3494 DRM_DEBUG_KMS("LCD1 disconnected\n"); 3495 bios_4_scratch &= ~RADEON_LCD1_ATTACHED; 3496 bios_5_scratch &= ~RADEON_LCD1_ON; 3497 bios_5_scratch &= ~RADEON_ACC_REQ_LCD1; 3498 } 3499 } 3500 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) && 3501 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) { 3502 if (connected) { 3503 DRM_DEBUG_KMS("CRT1 connected\n"); 3504 bios_4_scratch |= RADEON_CRT1_ATTACHED_COLOR; 3505 bios_5_scratch |= RADEON_CRT1_ON; 3506 bios_5_scratch |= RADEON_ACC_REQ_CRT1; 3507 } else { 3508 DRM_DEBUG_KMS("CRT1 disconnected\n"); 3509 bios_4_scratch &= ~RADEON_CRT1_ATTACHED_MASK; 3510 bios_5_scratch &= ~RADEON_CRT1_ON; 3511 bios_5_scratch &= ~RADEON_ACC_REQ_CRT1; 3512 } 3513 } 3514 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) && 3515 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) { 3516 if (connected) { 3517 DRM_DEBUG_KMS("CRT2 connected\n"); 3518 bios_4_scratch |= RADEON_CRT2_ATTACHED_COLOR; 3519 bios_5_scratch |= RADEON_CRT2_ON; 3520 bios_5_scratch |= RADEON_ACC_REQ_CRT2; 3521 } else { 3522 DRM_DEBUG_KMS("CRT2 disconnected\n"); 3523 bios_4_scratch &= ~RADEON_CRT2_ATTACHED_MASK; 3524 bios_5_scratch &= ~RADEON_CRT2_ON; 3525 bios_5_scratch &= ~RADEON_ACC_REQ_CRT2; 3526 } 3527 } 3528 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) && 3529 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) { 3530 if (connected) { 3531 DRM_DEBUG_KMS("DFP1 connected\n"); 3532 bios_4_scratch |= RADEON_DFP1_ATTACHED; 3533 bios_5_scratch |= RADEON_DFP1_ON; 3534 bios_5_scratch |= RADEON_ACC_REQ_DFP1; 3535 } else { 3536 DRM_DEBUG_KMS("DFP1 disconnected\n"); 3537 bios_4_scratch &= ~RADEON_DFP1_ATTACHED; 3538 bios_5_scratch &= ~RADEON_DFP1_ON; 3539 bios_5_scratch &= ~RADEON_ACC_REQ_DFP1; 3540 } 3541 } 3542 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) && 3543 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) { 3544 if (connected) { 3545 DRM_DEBUG_KMS("DFP2 connected\n"); 3546 bios_4_scratch |= RADEON_DFP2_ATTACHED; 3547 bios_5_scratch |= RADEON_DFP2_ON; 3548 bios_5_scratch |= RADEON_ACC_REQ_DFP2; 3549 } else { 3550 DRM_DEBUG_KMS("DFP2 disconnected\n"); 3551 bios_4_scratch &= ~RADEON_DFP2_ATTACHED; 3552 bios_5_scratch &= ~RADEON_DFP2_ON; 3553 bios_5_scratch &= ~RADEON_ACC_REQ_DFP2; 3554 } 3555 } 3556 WREG32(RADEON_BIOS_4_SCRATCH, bios_4_scratch); 3557 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3558} 3559 3560void 3561radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc) 3562{ 3563 struct drm_device *dev = encoder->dev; 3564 struct radeon_device *rdev = dev->dev_private; 3565 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3566 uint32_t bios_5_scratch = RREG32(RADEON_BIOS_5_SCRATCH); 3567 3568 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) { 3569 bios_5_scratch &= ~RADEON_TV1_CRTC_MASK; 3570 bios_5_scratch |= (crtc << RADEON_TV1_CRTC_SHIFT); 3571 } 3572 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) { 3573 bios_5_scratch &= ~RADEON_CRT1_CRTC_MASK; 3574 bios_5_scratch |= (crtc << RADEON_CRT1_CRTC_SHIFT); 3575 } 3576 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) { 3577 bios_5_scratch &= ~RADEON_CRT2_CRTC_MASK; 3578 bios_5_scratch |= (crtc << RADEON_CRT2_CRTC_SHIFT); 3579 } 3580 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) { 3581 bios_5_scratch &= ~RADEON_LCD1_CRTC_MASK; 3582 bios_5_scratch |= (crtc << RADEON_LCD1_CRTC_SHIFT); 3583 } 3584 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) { 3585 bios_5_scratch &= ~RADEON_DFP1_CRTC_MASK; 3586 bios_5_scratch |= (crtc << RADEON_DFP1_CRTC_SHIFT); 3587 } 3588 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) { 3589 bios_5_scratch &= ~RADEON_DFP2_CRTC_MASK; 3590 bios_5_scratch |= (crtc << RADEON_DFP2_CRTC_SHIFT); 3591 } 3592 WREG32(RADEON_BIOS_5_SCRATCH, bios_5_scratch); 3593} 3594 3595void 3596radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on) 3597{ 3598 struct drm_device *dev = encoder->dev; 3599 struct radeon_device *rdev = dev->dev_private; 3600 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 3601 uint32_t bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH); 3602 3603 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT)) { 3604 if (on) 3605 bios_6_scratch |= RADEON_TV_DPMS_ON; 3606 else 3607 bios_6_scratch &= ~RADEON_TV_DPMS_ON; 3608 } 3609 if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) { 3610 if (on) 3611 bios_6_scratch |= RADEON_CRT_DPMS_ON; 3612 else 3613 bios_6_scratch &= ~RADEON_CRT_DPMS_ON; 3614 } 3615 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { 3616 if (on) 3617 bios_6_scratch |= RADEON_LCD_DPMS_ON; 3618 else 3619 bios_6_scratch &= ~RADEON_LCD_DPMS_ON; 3620 } 3621 if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { 3622 if (on) 3623 bios_6_scratch |= RADEON_DFP_DPMS_ON; 3624 else 3625 bios_6_scratch &= ~RADEON_DFP_DPMS_ON; 3626 } 3627 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch); 3628} 3629