18c2ecf20Sopenharmony_ci/* SPDX-License-Identifier: MIT */ 28c2ecf20Sopenharmony_ci 38c2ecf20Sopenharmony_ci#include "radeon.h" 48c2ecf20Sopenharmony_ci 58c2ecf20Sopenharmony_ci#define R100_TRACK_MAX_TEXTURE 3 68c2ecf20Sopenharmony_ci#define R200_TRACK_MAX_TEXTURE 6 78c2ecf20Sopenharmony_ci#define R300_TRACK_MAX_TEXTURE 16 88c2ecf20Sopenharmony_ci 98c2ecf20Sopenharmony_ci#define R100_MAX_CB 1 108c2ecf20Sopenharmony_ci#define R300_MAX_CB 4 118c2ecf20Sopenharmony_ci 128c2ecf20Sopenharmony_ci/* 138c2ecf20Sopenharmony_ci * CS functions 148c2ecf20Sopenharmony_ci */ 158c2ecf20Sopenharmony_cistruct r100_cs_track_cb { 168c2ecf20Sopenharmony_ci struct radeon_bo *robj; 178c2ecf20Sopenharmony_ci unsigned pitch; 188c2ecf20Sopenharmony_ci unsigned cpp; 198c2ecf20Sopenharmony_ci unsigned offset; 208c2ecf20Sopenharmony_ci}; 218c2ecf20Sopenharmony_ci 228c2ecf20Sopenharmony_cistruct r100_cs_track_array { 238c2ecf20Sopenharmony_ci struct radeon_bo *robj; 248c2ecf20Sopenharmony_ci unsigned esize; 258c2ecf20Sopenharmony_ci}; 268c2ecf20Sopenharmony_ci 278c2ecf20Sopenharmony_cistruct r100_cs_cube_info { 288c2ecf20Sopenharmony_ci struct radeon_bo *robj; 298c2ecf20Sopenharmony_ci unsigned offset; 308c2ecf20Sopenharmony_ci unsigned width; 318c2ecf20Sopenharmony_ci unsigned height; 328c2ecf20Sopenharmony_ci}; 338c2ecf20Sopenharmony_ci 348c2ecf20Sopenharmony_ci#define R100_TRACK_COMP_NONE 0 358c2ecf20Sopenharmony_ci#define R100_TRACK_COMP_DXT1 1 368c2ecf20Sopenharmony_ci#define R100_TRACK_COMP_DXT35 2 378c2ecf20Sopenharmony_ci 388c2ecf20Sopenharmony_cistruct r100_cs_track_texture { 398c2ecf20Sopenharmony_ci struct radeon_bo *robj; 408c2ecf20Sopenharmony_ci struct r100_cs_cube_info cube_info[5]; /* info for 5 non-primary faces */ 418c2ecf20Sopenharmony_ci unsigned pitch; 428c2ecf20Sopenharmony_ci unsigned width; 438c2ecf20Sopenharmony_ci unsigned height; 448c2ecf20Sopenharmony_ci unsigned num_levels; 458c2ecf20Sopenharmony_ci unsigned cpp; 468c2ecf20Sopenharmony_ci unsigned tex_coord_type; 478c2ecf20Sopenharmony_ci unsigned txdepth; 488c2ecf20Sopenharmony_ci unsigned width_11; 498c2ecf20Sopenharmony_ci unsigned height_11; 508c2ecf20Sopenharmony_ci bool use_pitch; 518c2ecf20Sopenharmony_ci bool enabled; 528c2ecf20Sopenharmony_ci bool lookup_disable; 538c2ecf20Sopenharmony_ci bool roundup_w; 548c2ecf20Sopenharmony_ci bool roundup_h; 558c2ecf20Sopenharmony_ci unsigned compress_format; 568c2ecf20Sopenharmony_ci}; 578c2ecf20Sopenharmony_ci 588c2ecf20Sopenharmony_cistruct r100_cs_track { 598c2ecf20Sopenharmony_ci unsigned num_cb; 608c2ecf20Sopenharmony_ci unsigned num_texture; 618c2ecf20Sopenharmony_ci unsigned maxy; 628c2ecf20Sopenharmony_ci unsigned vtx_size; 638c2ecf20Sopenharmony_ci unsigned vap_vf_cntl; 648c2ecf20Sopenharmony_ci unsigned vap_alt_nverts; 658c2ecf20Sopenharmony_ci unsigned immd_dwords; 668c2ecf20Sopenharmony_ci unsigned num_arrays; 678c2ecf20Sopenharmony_ci unsigned max_indx; 688c2ecf20Sopenharmony_ci unsigned color_channel_mask; 698c2ecf20Sopenharmony_ci struct r100_cs_track_array arrays[16]; 708c2ecf20Sopenharmony_ci struct r100_cs_track_cb cb[R300_MAX_CB]; 718c2ecf20Sopenharmony_ci struct r100_cs_track_cb zb; 728c2ecf20Sopenharmony_ci struct r100_cs_track_cb aa; 738c2ecf20Sopenharmony_ci struct r100_cs_track_texture textures[R300_TRACK_MAX_TEXTURE]; 748c2ecf20Sopenharmony_ci bool z_enabled; 758c2ecf20Sopenharmony_ci bool separate_cube; 768c2ecf20Sopenharmony_ci bool zb_cb_clear; 778c2ecf20Sopenharmony_ci bool blend_read_enable; 788c2ecf20Sopenharmony_ci bool cb_dirty; 798c2ecf20Sopenharmony_ci bool zb_dirty; 808c2ecf20Sopenharmony_ci bool tex_dirty; 818c2ecf20Sopenharmony_ci bool aa_dirty; 828c2ecf20Sopenharmony_ci bool aaresolve; 838c2ecf20Sopenharmony_ci}; 848c2ecf20Sopenharmony_ci 858c2ecf20Sopenharmony_ciint r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track); 868c2ecf20Sopenharmony_civoid r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track); 878c2ecf20Sopenharmony_ci 888c2ecf20Sopenharmony_ciint r100_cs_packet_parse_vline(struct radeon_cs_parser *p); 898c2ecf20Sopenharmony_ci 908c2ecf20Sopenharmony_ciint r200_packet0_check(struct radeon_cs_parser *p, 918c2ecf20Sopenharmony_ci struct radeon_cs_packet *pkt, 928c2ecf20Sopenharmony_ci unsigned idx, unsigned reg); 938c2ecf20Sopenharmony_ci 948c2ecf20Sopenharmony_ciint r100_reloc_pitch_offset(struct radeon_cs_parser *p, 958c2ecf20Sopenharmony_ci struct radeon_cs_packet *pkt, 968c2ecf20Sopenharmony_ci unsigned idx, 978c2ecf20Sopenharmony_ci unsigned reg); 988c2ecf20Sopenharmony_ciint r100_packet3_load_vbpntr(struct radeon_cs_parser *p, 998c2ecf20Sopenharmony_ci struct radeon_cs_packet *pkt, 1008c2ecf20Sopenharmony_ci int idx); 101