1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2009 Nokia Corporation 4 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com> 5 */ 6 7#define DSS_SUBSYS_NAME "DSI" 8 9#include <linux/kernel.h> 10#include <linux/mfd/syscon.h> 11#include <linux/regmap.h> 12#include <linux/io.h> 13#include <linux/clk.h> 14#include <linux/device.h> 15#include <linux/err.h> 16#include <linux/interrupt.h> 17#include <linux/delay.h> 18#include <linux/mutex.h> 19#include <linux/module.h> 20#include <linux/semaphore.h> 21#include <linux/seq_file.h> 22#include <linux/platform_device.h> 23#include <linux/regulator/consumer.h> 24#include <linux/wait.h> 25#include <linux/workqueue.h> 26#include <linux/sched.h> 27#include <linux/slab.h> 28#include <linux/debugfs.h> 29#include <linux/pm_runtime.h> 30#include <linux/of.h> 31#include <linux/of_graph.h> 32#include <linux/of_platform.h> 33#include <linux/component.h> 34#include <linux/sys_soc.h> 35 36#include <video/mipi_display.h> 37 38#include "omapdss.h" 39#include "dss.h" 40 41#define DSI_CATCH_MISSING_TE 42 43struct dsi_reg { u16 module; u16 idx; }; 44 45#define DSI_REG(mod, idx) ((const struct dsi_reg) { mod, idx }) 46 47/* DSI Protocol Engine */ 48 49#define DSI_PROTO 0 50#define DSI_PROTO_SZ 0x200 51 52#define DSI_REVISION DSI_REG(DSI_PROTO, 0x0000) 53#define DSI_SYSCONFIG DSI_REG(DSI_PROTO, 0x0010) 54#define DSI_SYSSTATUS DSI_REG(DSI_PROTO, 0x0014) 55#define DSI_IRQSTATUS DSI_REG(DSI_PROTO, 0x0018) 56#define DSI_IRQENABLE DSI_REG(DSI_PROTO, 0x001C) 57#define DSI_CTRL DSI_REG(DSI_PROTO, 0x0040) 58#define DSI_GNQ DSI_REG(DSI_PROTO, 0x0044) 59#define DSI_COMPLEXIO_CFG1 DSI_REG(DSI_PROTO, 0x0048) 60#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(DSI_PROTO, 0x004C) 61#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(DSI_PROTO, 0x0050) 62#define DSI_CLK_CTRL DSI_REG(DSI_PROTO, 0x0054) 63#define DSI_TIMING1 DSI_REG(DSI_PROTO, 0x0058) 64#define DSI_TIMING2 DSI_REG(DSI_PROTO, 0x005C) 65#define DSI_VM_TIMING1 DSI_REG(DSI_PROTO, 0x0060) 66#define DSI_VM_TIMING2 DSI_REG(DSI_PROTO, 0x0064) 67#define DSI_VM_TIMING3 DSI_REG(DSI_PROTO, 0x0068) 68#define DSI_CLK_TIMING DSI_REG(DSI_PROTO, 0x006C) 69#define DSI_TX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0070) 70#define DSI_RX_FIFO_VC_SIZE DSI_REG(DSI_PROTO, 0x0074) 71#define DSI_COMPLEXIO_CFG2 DSI_REG(DSI_PROTO, 0x0078) 72#define DSI_RX_FIFO_VC_FULLNESS DSI_REG(DSI_PROTO, 0x007C) 73#define DSI_VM_TIMING4 DSI_REG(DSI_PROTO, 0x0080) 74#define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(DSI_PROTO, 0x0084) 75#define DSI_VM_TIMING5 DSI_REG(DSI_PROTO, 0x0088) 76#define DSI_VM_TIMING6 DSI_REG(DSI_PROTO, 0x008C) 77#define DSI_VM_TIMING7 DSI_REG(DSI_PROTO, 0x0090) 78#define DSI_STOPCLK_TIMING DSI_REG(DSI_PROTO, 0x0094) 79#define DSI_VC_CTRL(n) DSI_REG(DSI_PROTO, 0x0100 + (n * 0x20)) 80#define DSI_VC_TE(n) DSI_REG(DSI_PROTO, 0x0104 + (n * 0x20)) 81#define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0108 + (n * 0x20)) 82#define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(DSI_PROTO, 0x010C + (n * 0x20)) 83#define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(DSI_PROTO, 0x0110 + (n * 0x20)) 84#define DSI_VC_IRQSTATUS(n) DSI_REG(DSI_PROTO, 0x0118 + (n * 0x20)) 85#define DSI_VC_IRQENABLE(n) DSI_REG(DSI_PROTO, 0x011C + (n * 0x20)) 86 87/* DSIPHY_SCP */ 88 89#define DSI_PHY 1 90#define DSI_PHY_OFFSET 0x200 91#define DSI_PHY_SZ 0x40 92 93#define DSI_DSIPHY_CFG0 DSI_REG(DSI_PHY, 0x0000) 94#define DSI_DSIPHY_CFG1 DSI_REG(DSI_PHY, 0x0004) 95#define DSI_DSIPHY_CFG2 DSI_REG(DSI_PHY, 0x0008) 96#define DSI_DSIPHY_CFG5 DSI_REG(DSI_PHY, 0x0014) 97#define DSI_DSIPHY_CFG10 DSI_REG(DSI_PHY, 0x0028) 98 99/* DSI_PLL_CTRL_SCP */ 100 101#define DSI_PLL 2 102#define DSI_PLL_OFFSET 0x300 103#define DSI_PLL_SZ 0x20 104 105#define DSI_PLL_CONTROL DSI_REG(DSI_PLL, 0x0000) 106#define DSI_PLL_STATUS DSI_REG(DSI_PLL, 0x0004) 107#define DSI_PLL_GO DSI_REG(DSI_PLL, 0x0008) 108#define DSI_PLL_CONFIGURATION1 DSI_REG(DSI_PLL, 0x000C) 109#define DSI_PLL_CONFIGURATION2 DSI_REG(DSI_PLL, 0x0010) 110 111#define REG_GET(dsi, idx, start, end) \ 112 FLD_GET(dsi_read_reg(dsi, idx), start, end) 113 114#define REG_FLD_MOD(dsi, idx, val, start, end) \ 115 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end)) 116 117/* Global interrupts */ 118#define DSI_IRQ_VC0 (1 << 0) 119#define DSI_IRQ_VC1 (1 << 1) 120#define DSI_IRQ_VC2 (1 << 2) 121#define DSI_IRQ_VC3 (1 << 3) 122#define DSI_IRQ_WAKEUP (1 << 4) 123#define DSI_IRQ_RESYNC (1 << 5) 124#define DSI_IRQ_PLL_LOCK (1 << 7) 125#define DSI_IRQ_PLL_UNLOCK (1 << 8) 126#define DSI_IRQ_PLL_RECALL (1 << 9) 127#define DSI_IRQ_COMPLEXIO_ERR (1 << 10) 128#define DSI_IRQ_HS_TX_TIMEOUT (1 << 14) 129#define DSI_IRQ_LP_RX_TIMEOUT (1 << 15) 130#define DSI_IRQ_TE_TRIGGER (1 << 16) 131#define DSI_IRQ_ACK_TRIGGER (1 << 17) 132#define DSI_IRQ_SYNC_LOST (1 << 18) 133#define DSI_IRQ_LDO_POWER_GOOD (1 << 19) 134#define DSI_IRQ_TA_TIMEOUT (1 << 20) 135#define DSI_IRQ_ERROR_MASK \ 136 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \ 137 DSI_IRQ_TA_TIMEOUT) 138#define DSI_IRQ_CHANNEL_MASK 0xf 139 140/* Virtual channel interrupts */ 141#define DSI_VC_IRQ_CS (1 << 0) 142#define DSI_VC_IRQ_ECC_CORR (1 << 1) 143#define DSI_VC_IRQ_PACKET_SENT (1 << 2) 144#define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3) 145#define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4) 146#define DSI_VC_IRQ_BTA (1 << 5) 147#define DSI_VC_IRQ_ECC_NO_CORR (1 << 6) 148#define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7) 149#define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8) 150#define DSI_VC_IRQ_ERROR_MASK \ 151 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \ 152 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \ 153 DSI_VC_IRQ_FIFO_TX_UDF) 154 155/* ComplexIO interrupts */ 156#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0) 157#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1) 158#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2) 159#define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3) 160#define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4) 161#define DSI_CIO_IRQ_ERRESC1 (1 << 5) 162#define DSI_CIO_IRQ_ERRESC2 (1 << 6) 163#define DSI_CIO_IRQ_ERRESC3 (1 << 7) 164#define DSI_CIO_IRQ_ERRESC4 (1 << 8) 165#define DSI_CIO_IRQ_ERRESC5 (1 << 9) 166#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10) 167#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11) 168#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12) 169#define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13) 170#define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14) 171#define DSI_CIO_IRQ_STATEULPS1 (1 << 15) 172#define DSI_CIO_IRQ_STATEULPS2 (1 << 16) 173#define DSI_CIO_IRQ_STATEULPS3 (1 << 17) 174#define DSI_CIO_IRQ_STATEULPS4 (1 << 18) 175#define DSI_CIO_IRQ_STATEULPS5 (1 << 19) 176#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20) 177#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21) 178#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22) 179#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23) 180#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24) 181#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25) 182#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26) 183#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27) 184#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28) 185#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29) 186#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30) 187#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31) 188#define DSI_CIO_IRQ_ERROR_MASK \ 189 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \ 190 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \ 191 DSI_CIO_IRQ_ERRSYNCESC5 | \ 192 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \ 193 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \ 194 DSI_CIO_IRQ_ERRESC5 | \ 195 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \ 196 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \ 197 DSI_CIO_IRQ_ERRCONTROL5 | \ 198 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \ 199 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \ 200 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \ 201 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \ 202 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5) 203 204typedef void (*omap_dsi_isr_t) (void *arg, u32 mask); 205struct dsi_data; 206 207static int dsi_display_init_dispc(struct dsi_data *dsi); 208static void dsi_display_uninit_dispc(struct dsi_data *dsi); 209 210static int dsi_vc_send_null(struct dsi_data *dsi, int channel); 211 212/* DSI PLL HSDIV indices */ 213#define HSDIV_DISPC 0 214#define HSDIV_DSI 1 215 216#define DSI_MAX_NR_ISRS 2 217#define DSI_MAX_NR_LANES 5 218 219enum dsi_model { 220 DSI_MODEL_OMAP3, 221 DSI_MODEL_OMAP4, 222 DSI_MODEL_OMAP5, 223}; 224 225enum dsi_lane_function { 226 DSI_LANE_UNUSED = 0, 227 DSI_LANE_CLK, 228 DSI_LANE_DATA1, 229 DSI_LANE_DATA2, 230 DSI_LANE_DATA3, 231 DSI_LANE_DATA4, 232}; 233 234struct dsi_lane_config { 235 enum dsi_lane_function function; 236 u8 polarity; 237}; 238 239struct dsi_isr_data { 240 omap_dsi_isr_t isr; 241 void *arg; 242 u32 mask; 243}; 244 245enum fifo_size { 246 DSI_FIFO_SIZE_0 = 0, 247 DSI_FIFO_SIZE_32 = 1, 248 DSI_FIFO_SIZE_64 = 2, 249 DSI_FIFO_SIZE_96 = 3, 250 DSI_FIFO_SIZE_128 = 4, 251}; 252 253enum dsi_vc_source { 254 DSI_VC_SOURCE_L4 = 0, 255 DSI_VC_SOURCE_VP, 256}; 257 258struct dsi_irq_stats { 259 unsigned long last_reset; 260 unsigned int irq_count; 261 unsigned int dsi_irqs[32]; 262 unsigned int vc_irqs[4][32]; 263 unsigned int cio_irqs[32]; 264}; 265 266struct dsi_isr_tables { 267 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS]; 268 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS]; 269 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS]; 270}; 271 272struct dsi_clk_calc_ctx { 273 struct dsi_data *dsi; 274 struct dss_pll *pll; 275 276 /* inputs */ 277 278 const struct omap_dss_dsi_config *config; 279 280 unsigned long req_pck_min, req_pck_nom, req_pck_max; 281 282 /* outputs */ 283 284 struct dss_pll_clock_info dsi_cinfo; 285 struct dispc_clock_info dispc_cinfo; 286 287 struct videomode vm; 288 struct omap_dss_dsi_videomode_timings dsi_vm; 289}; 290 291struct dsi_lp_clock_info { 292 unsigned long lp_clk; 293 u16 lp_clk_div; 294}; 295 296struct dsi_module_id_data { 297 u32 address; 298 int id; 299}; 300 301enum dsi_quirks { 302 DSI_QUIRK_PLL_PWR_BUG = (1 << 0), /* DSI-PLL power command 0x3 is not working */ 303 DSI_QUIRK_DCS_CMD_CONFIG_VC = (1 << 1), 304 DSI_QUIRK_VC_OCP_WIDTH = (1 << 2), 305 DSI_QUIRK_REVERSE_TXCLKESC = (1 << 3), 306 DSI_QUIRK_GNQ = (1 << 4), 307 DSI_QUIRK_PHY_DCC = (1 << 5), 308}; 309 310struct dsi_of_data { 311 enum dsi_model model; 312 const struct dss_pll_hw *pll_hw; 313 const struct dsi_module_id_data *modules; 314 unsigned int max_fck_freq; 315 unsigned int max_pll_lpdiv; 316 enum dsi_quirks quirks; 317}; 318 319struct dsi_data { 320 struct device *dev; 321 void __iomem *proto_base; 322 void __iomem *phy_base; 323 void __iomem *pll_base; 324 325 const struct dsi_of_data *data; 326 int module_id; 327 328 int irq; 329 330 bool is_enabled; 331 332 struct clk *dss_clk; 333 struct regmap *syscon; 334 struct dss_device *dss; 335 336 struct dispc_clock_info user_dispc_cinfo; 337 struct dss_pll_clock_info user_dsi_cinfo; 338 339 struct dsi_lp_clock_info user_lp_cinfo; 340 struct dsi_lp_clock_info current_lp_cinfo; 341 342 struct dss_pll pll; 343 344 bool vdds_dsi_enabled; 345 struct regulator *vdds_dsi_reg; 346 347 struct { 348 enum dsi_vc_source source; 349 struct omap_dss_device *dssdev; 350 enum fifo_size tx_fifo_size; 351 enum fifo_size rx_fifo_size; 352 int vc_id; 353 } vc[4]; 354 355 struct mutex lock; 356 struct semaphore bus_lock; 357 358 spinlock_t irq_lock; 359 struct dsi_isr_tables isr_tables; 360 /* space for a copy used by the interrupt handler */ 361 struct dsi_isr_tables isr_tables_copy; 362 363 int update_channel; 364#ifdef DSI_PERF_MEASURE 365 unsigned int update_bytes; 366#endif 367 368 bool te_enabled; 369 bool ulps_enabled; 370 371 void (*framedone_callback)(int, void *); 372 void *framedone_data; 373 374 struct delayed_work framedone_timeout_work; 375 376#ifdef DSI_CATCH_MISSING_TE 377 struct timer_list te_timer; 378#endif 379 380 unsigned long cache_req_pck; 381 unsigned long cache_clk_freq; 382 struct dss_pll_clock_info cache_cinfo; 383 384 u32 errors; 385 spinlock_t errors_lock; 386#ifdef DSI_PERF_MEASURE 387 ktime_t perf_setup_time; 388 ktime_t perf_start_time; 389#endif 390 int debug_read; 391 int debug_write; 392 struct { 393 struct dss_debugfs_entry *irqs; 394 struct dss_debugfs_entry *regs; 395 struct dss_debugfs_entry *clks; 396 } debugfs; 397 398#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 399 spinlock_t irq_stats_lock; 400 struct dsi_irq_stats irq_stats; 401#endif 402 403 unsigned int num_lanes_supported; 404 unsigned int line_buffer_size; 405 406 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 407 unsigned int num_lanes_used; 408 409 unsigned int scp_clk_refcount; 410 411 struct dss_lcd_mgr_config mgr_config; 412 struct videomode vm; 413 enum omap_dss_dsi_pixel_format pix_fmt; 414 enum omap_dss_dsi_mode mode; 415 struct omap_dss_dsi_videomode_timings vm_timings; 416 417 struct omap_dss_device output; 418}; 419 420struct dsi_packet_sent_handler_data { 421 struct dsi_data *dsi; 422 struct completion *completion; 423}; 424 425#ifdef DSI_PERF_MEASURE 426static bool dsi_perf; 427module_param(dsi_perf, bool, 0644); 428#endif 429 430static inline struct dsi_data *to_dsi_data(struct omap_dss_device *dssdev) 431{ 432 return dev_get_drvdata(dssdev->dev); 433} 434 435static inline void dsi_write_reg(struct dsi_data *dsi, 436 const struct dsi_reg idx, u32 val) 437{ 438 void __iomem *base; 439 440 switch(idx.module) { 441 case DSI_PROTO: base = dsi->proto_base; break; 442 case DSI_PHY: base = dsi->phy_base; break; 443 case DSI_PLL: base = dsi->pll_base; break; 444 default: return; 445 } 446 447 __raw_writel(val, base + idx.idx); 448} 449 450static inline u32 dsi_read_reg(struct dsi_data *dsi, const struct dsi_reg idx) 451{ 452 void __iomem *base; 453 454 switch(idx.module) { 455 case DSI_PROTO: base = dsi->proto_base; break; 456 case DSI_PHY: base = dsi->phy_base; break; 457 case DSI_PLL: base = dsi->pll_base; break; 458 default: return 0; 459 } 460 461 return __raw_readl(base + idx.idx); 462} 463 464static void dsi_bus_lock(struct omap_dss_device *dssdev) 465{ 466 struct dsi_data *dsi = to_dsi_data(dssdev); 467 468 down(&dsi->bus_lock); 469} 470 471static void dsi_bus_unlock(struct omap_dss_device *dssdev) 472{ 473 struct dsi_data *dsi = to_dsi_data(dssdev); 474 475 up(&dsi->bus_lock); 476} 477 478static bool dsi_bus_is_locked(struct dsi_data *dsi) 479{ 480 return dsi->bus_lock.count == 0; 481} 482 483static void dsi_completion_handler(void *data, u32 mask) 484{ 485 complete((struct completion *)data); 486} 487 488static inline bool wait_for_bit_change(struct dsi_data *dsi, 489 const struct dsi_reg idx, 490 int bitnum, int value) 491{ 492 unsigned long timeout; 493 ktime_t wait; 494 int t; 495 496 /* first busyloop to see if the bit changes right away */ 497 t = 100; 498 while (t-- > 0) { 499 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 500 return true; 501 } 502 503 /* then loop for 500ms, sleeping for 1ms in between */ 504 timeout = jiffies + msecs_to_jiffies(500); 505 while (time_before(jiffies, timeout)) { 506 if (REG_GET(dsi, idx, bitnum, bitnum) == value) 507 return true; 508 509 wait = ns_to_ktime(1000 * 1000); 510 set_current_state(TASK_UNINTERRUPTIBLE); 511 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 512 } 513 514 return false; 515} 516 517static u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt) 518{ 519 switch (fmt) { 520 case OMAP_DSS_DSI_FMT_RGB888: 521 case OMAP_DSS_DSI_FMT_RGB666: 522 return 24; 523 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 524 return 18; 525 case OMAP_DSS_DSI_FMT_RGB565: 526 return 16; 527 default: 528 BUG(); 529 return 0; 530 } 531} 532 533#ifdef DSI_PERF_MEASURE 534static void dsi_perf_mark_setup(struct dsi_data *dsi) 535{ 536 dsi->perf_setup_time = ktime_get(); 537} 538 539static void dsi_perf_mark_start(struct dsi_data *dsi) 540{ 541 dsi->perf_start_time = ktime_get(); 542} 543 544static void dsi_perf_show(struct dsi_data *dsi, const char *name) 545{ 546 ktime_t t, setup_time, trans_time; 547 u32 total_bytes; 548 u32 setup_us, trans_us, total_us; 549 550 if (!dsi_perf) 551 return; 552 553 t = ktime_get(); 554 555 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time); 556 setup_us = (u32)ktime_to_us(setup_time); 557 if (setup_us == 0) 558 setup_us = 1; 559 560 trans_time = ktime_sub(t, dsi->perf_start_time); 561 trans_us = (u32)ktime_to_us(trans_time); 562 if (trans_us == 0) 563 trans_us = 1; 564 565 total_us = setup_us + trans_us; 566 567 total_bytes = dsi->update_bytes; 568 569 pr_info("DSI(%s): %u us + %u us = %u us (%uHz), %u bytes, %u kbytes/sec\n", 570 name, 571 setup_us, 572 trans_us, 573 total_us, 574 1000 * 1000 / total_us, 575 total_bytes, 576 total_bytes * 1000 / total_us); 577} 578#else 579static inline void dsi_perf_mark_setup(struct dsi_data *dsi) 580{ 581} 582 583static inline void dsi_perf_mark_start(struct dsi_data *dsi) 584{ 585} 586 587static inline void dsi_perf_show(struct dsi_data *dsi, const char *name) 588{ 589} 590#endif 591 592static int verbose_irq; 593 594static void print_irq_status(u32 status) 595{ 596 if (status == 0) 597 return; 598 599 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0) 600 return; 601 602#define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : "" 603 604 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 605 status, 606 verbose_irq ? PIS(VC0) : "", 607 verbose_irq ? PIS(VC1) : "", 608 verbose_irq ? PIS(VC2) : "", 609 verbose_irq ? PIS(VC3) : "", 610 PIS(WAKEUP), 611 PIS(RESYNC), 612 PIS(PLL_LOCK), 613 PIS(PLL_UNLOCK), 614 PIS(PLL_RECALL), 615 PIS(COMPLEXIO_ERR), 616 PIS(HS_TX_TIMEOUT), 617 PIS(LP_RX_TIMEOUT), 618 PIS(TE_TRIGGER), 619 PIS(ACK_TRIGGER), 620 PIS(SYNC_LOST), 621 PIS(LDO_POWER_GOOD), 622 PIS(TA_TIMEOUT)); 623#undef PIS 624} 625 626static void print_irq_status_vc(int channel, u32 status) 627{ 628 if (status == 0) 629 return; 630 631 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0) 632 return; 633 634#define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : "" 635 636 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n", 637 channel, 638 status, 639 PIS(CS), 640 PIS(ECC_CORR), 641 PIS(ECC_NO_CORR), 642 verbose_irq ? PIS(PACKET_SENT) : "", 643 PIS(BTA), 644 PIS(FIFO_TX_OVF), 645 PIS(FIFO_RX_OVF), 646 PIS(FIFO_TX_UDF), 647 PIS(PP_BUSY_CHANGE)); 648#undef PIS 649} 650 651static void print_irq_status_cio(u32 status) 652{ 653 if (status == 0) 654 return; 655 656#define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : "" 657 658 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", 659 status, 660 PIS(ERRSYNCESC1), 661 PIS(ERRSYNCESC2), 662 PIS(ERRSYNCESC3), 663 PIS(ERRESC1), 664 PIS(ERRESC2), 665 PIS(ERRESC3), 666 PIS(ERRCONTROL1), 667 PIS(ERRCONTROL2), 668 PIS(ERRCONTROL3), 669 PIS(STATEULPS1), 670 PIS(STATEULPS2), 671 PIS(STATEULPS3), 672 PIS(ERRCONTENTIONLP0_1), 673 PIS(ERRCONTENTIONLP1_1), 674 PIS(ERRCONTENTIONLP0_2), 675 PIS(ERRCONTENTIONLP1_2), 676 PIS(ERRCONTENTIONLP0_3), 677 PIS(ERRCONTENTIONLP1_3), 678 PIS(ULPSACTIVENOT_ALL0), 679 PIS(ULPSACTIVENOT_ALL1)); 680#undef PIS 681} 682 683#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 684static void dsi_collect_irq_stats(struct dsi_data *dsi, u32 irqstatus, 685 u32 *vcstatus, u32 ciostatus) 686{ 687 int i; 688 689 spin_lock(&dsi->irq_stats_lock); 690 691 dsi->irq_stats.irq_count++; 692 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs); 693 694 for (i = 0; i < 4; ++i) 695 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]); 696 697 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs); 698 699 spin_unlock(&dsi->irq_stats_lock); 700} 701#else 702#define dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus) 703#endif 704 705static int debug_irq; 706 707static void dsi_handle_irq_errors(struct dsi_data *dsi, u32 irqstatus, 708 u32 *vcstatus, u32 ciostatus) 709{ 710 int i; 711 712 if (irqstatus & DSI_IRQ_ERROR_MASK) { 713 DSSERR("DSI error, irqstatus %x\n", irqstatus); 714 print_irq_status(irqstatus); 715 spin_lock(&dsi->errors_lock); 716 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK; 717 spin_unlock(&dsi->errors_lock); 718 } else if (debug_irq) { 719 print_irq_status(irqstatus); 720 } 721 722 for (i = 0; i < 4; ++i) { 723 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) { 724 DSSERR("DSI VC(%d) error, vc irqstatus %x\n", 725 i, vcstatus[i]); 726 print_irq_status_vc(i, vcstatus[i]); 727 } else if (debug_irq) { 728 print_irq_status_vc(i, vcstatus[i]); 729 } 730 } 731 732 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) { 733 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus); 734 print_irq_status_cio(ciostatus); 735 } else if (debug_irq) { 736 print_irq_status_cio(ciostatus); 737 } 738} 739 740static void dsi_call_isrs(struct dsi_isr_data *isr_array, 741 unsigned int isr_array_size, u32 irqstatus) 742{ 743 struct dsi_isr_data *isr_data; 744 int i; 745 746 for (i = 0; i < isr_array_size; i++) { 747 isr_data = &isr_array[i]; 748 if (isr_data->isr && isr_data->mask & irqstatus) 749 isr_data->isr(isr_data->arg, irqstatus); 750 } 751} 752 753static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables, 754 u32 irqstatus, u32 *vcstatus, u32 ciostatus) 755{ 756 int i; 757 758 dsi_call_isrs(isr_tables->isr_table, 759 ARRAY_SIZE(isr_tables->isr_table), 760 irqstatus); 761 762 for (i = 0; i < 4; ++i) { 763 if (vcstatus[i] == 0) 764 continue; 765 dsi_call_isrs(isr_tables->isr_table_vc[i], 766 ARRAY_SIZE(isr_tables->isr_table_vc[i]), 767 vcstatus[i]); 768 } 769 770 if (ciostatus != 0) 771 dsi_call_isrs(isr_tables->isr_table_cio, 772 ARRAY_SIZE(isr_tables->isr_table_cio), 773 ciostatus); 774} 775 776static irqreturn_t omap_dsi_irq_handler(int irq, void *arg) 777{ 778 struct dsi_data *dsi = arg; 779 u32 irqstatus, vcstatus[4], ciostatus; 780 int i; 781 782 if (!dsi->is_enabled) 783 return IRQ_NONE; 784 785 spin_lock(&dsi->irq_lock); 786 787 irqstatus = dsi_read_reg(dsi, DSI_IRQSTATUS); 788 789 /* IRQ is not for us */ 790 if (!irqstatus) { 791 spin_unlock(&dsi->irq_lock); 792 return IRQ_NONE; 793 } 794 795 dsi_write_reg(dsi, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK); 796 /* flush posted write */ 797 dsi_read_reg(dsi, DSI_IRQSTATUS); 798 799 for (i = 0; i < 4; ++i) { 800 if ((irqstatus & (1 << i)) == 0) { 801 vcstatus[i] = 0; 802 continue; 803 } 804 805 vcstatus[i] = dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 806 807 dsi_write_reg(dsi, DSI_VC_IRQSTATUS(i), vcstatus[i]); 808 /* flush posted write */ 809 dsi_read_reg(dsi, DSI_VC_IRQSTATUS(i)); 810 } 811 812 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) { 813 ciostatus = dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 814 815 dsi_write_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS, ciostatus); 816 /* flush posted write */ 817 dsi_read_reg(dsi, DSI_COMPLEXIO_IRQ_STATUS); 818 } else { 819 ciostatus = 0; 820 } 821 822#ifdef DSI_CATCH_MISSING_TE 823 if (irqstatus & DSI_IRQ_TE_TRIGGER) 824 del_timer(&dsi->te_timer); 825#endif 826 827 /* make a copy and unlock, so that isrs can unregister 828 * themselves */ 829 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables, 830 sizeof(dsi->isr_tables)); 831 832 spin_unlock(&dsi->irq_lock); 833 834 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus); 835 836 dsi_handle_irq_errors(dsi, irqstatus, vcstatus, ciostatus); 837 838 dsi_collect_irq_stats(dsi, irqstatus, vcstatus, ciostatus); 839 840 return IRQ_HANDLED; 841} 842 843/* dsi->irq_lock has to be locked by the caller */ 844static void _omap_dsi_configure_irqs(struct dsi_data *dsi, 845 struct dsi_isr_data *isr_array, 846 unsigned int isr_array_size, 847 u32 default_mask, 848 const struct dsi_reg enable_reg, 849 const struct dsi_reg status_reg) 850{ 851 struct dsi_isr_data *isr_data; 852 u32 mask; 853 u32 old_mask; 854 int i; 855 856 mask = default_mask; 857 858 for (i = 0; i < isr_array_size; i++) { 859 isr_data = &isr_array[i]; 860 861 if (isr_data->isr == NULL) 862 continue; 863 864 mask |= isr_data->mask; 865 } 866 867 old_mask = dsi_read_reg(dsi, enable_reg); 868 /* clear the irqstatus for newly enabled irqs */ 869 dsi_write_reg(dsi, status_reg, (mask ^ old_mask) & mask); 870 dsi_write_reg(dsi, enable_reg, mask); 871 872 /* flush posted writes */ 873 dsi_read_reg(dsi, enable_reg); 874 dsi_read_reg(dsi, status_reg); 875} 876 877/* dsi->irq_lock has to be locked by the caller */ 878static void _omap_dsi_set_irqs(struct dsi_data *dsi) 879{ 880 u32 mask = DSI_IRQ_ERROR_MASK; 881#ifdef DSI_CATCH_MISSING_TE 882 mask |= DSI_IRQ_TE_TRIGGER; 883#endif 884 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table, 885 ARRAY_SIZE(dsi->isr_tables.isr_table), mask, 886 DSI_IRQENABLE, DSI_IRQSTATUS); 887} 888 889/* dsi->irq_lock has to be locked by the caller */ 890static void _omap_dsi_set_irqs_vc(struct dsi_data *dsi, int vc) 891{ 892 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_vc[vc], 893 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]), 894 DSI_VC_IRQ_ERROR_MASK, 895 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc)); 896} 897 898/* dsi->irq_lock has to be locked by the caller */ 899static void _omap_dsi_set_irqs_cio(struct dsi_data *dsi) 900{ 901 _omap_dsi_configure_irqs(dsi, dsi->isr_tables.isr_table_cio, 902 ARRAY_SIZE(dsi->isr_tables.isr_table_cio), 903 DSI_CIO_IRQ_ERROR_MASK, 904 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS); 905} 906 907static void _dsi_initialize_irq(struct dsi_data *dsi) 908{ 909 unsigned long flags; 910 int vc; 911 912 spin_lock_irqsave(&dsi->irq_lock, flags); 913 914 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables)); 915 916 _omap_dsi_set_irqs(dsi); 917 for (vc = 0; vc < 4; ++vc) 918 _omap_dsi_set_irqs_vc(dsi, vc); 919 _omap_dsi_set_irqs_cio(dsi); 920 921 spin_unlock_irqrestore(&dsi->irq_lock, flags); 922} 923 924static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 925 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 926{ 927 struct dsi_isr_data *isr_data; 928 int free_idx; 929 int i; 930 931 BUG_ON(isr == NULL); 932 933 /* check for duplicate entry and find a free slot */ 934 free_idx = -1; 935 for (i = 0; i < isr_array_size; i++) { 936 isr_data = &isr_array[i]; 937 938 if (isr_data->isr == isr && isr_data->arg == arg && 939 isr_data->mask == mask) { 940 return -EINVAL; 941 } 942 943 if (isr_data->isr == NULL && free_idx == -1) 944 free_idx = i; 945 } 946 947 if (free_idx == -1) 948 return -EBUSY; 949 950 isr_data = &isr_array[free_idx]; 951 isr_data->isr = isr; 952 isr_data->arg = arg; 953 isr_data->mask = mask; 954 955 return 0; 956} 957 958static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask, 959 struct dsi_isr_data *isr_array, unsigned int isr_array_size) 960{ 961 struct dsi_isr_data *isr_data; 962 int i; 963 964 for (i = 0; i < isr_array_size; i++) { 965 isr_data = &isr_array[i]; 966 if (isr_data->isr != isr || isr_data->arg != arg || 967 isr_data->mask != mask) 968 continue; 969 970 isr_data->isr = NULL; 971 isr_data->arg = NULL; 972 isr_data->mask = 0; 973 974 return 0; 975 } 976 977 return -EINVAL; 978} 979 980static int dsi_register_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 981 void *arg, u32 mask) 982{ 983 unsigned long flags; 984 int r; 985 986 spin_lock_irqsave(&dsi->irq_lock, flags); 987 988 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table, 989 ARRAY_SIZE(dsi->isr_tables.isr_table)); 990 991 if (r == 0) 992 _omap_dsi_set_irqs(dsi); 993 994 spin_unlock_irqrestore(&dsi->irq_lock, flags); 995 996 return r; 997} 998 999static int dsi_unregister_isr(struct dsi_data *dsi, omap_dsi_isr_t isr, 1000 void *arg, u32 mask) 1001{ 1002 unsigned long flags; 1003 int r; 1004 1005 spin_lock_irqsave(&dsi->irq_lock, flags); 1006 1007 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table, 1008 ARRAY_SIZE(dsi->isr_tables.isr_table)); 1009 1010 if (r == 0) 1011 _omap_dsi_set_irqs(dsi); 1012 1013 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1014 1015 return r; 1016} 1017 1018static int dsi_register_isr_vc(struct dsi_data *dsi, int channel, 1019 omap_dsi_isr_t isr, void *arg, u32 mask) 1020{ 1021 unsigned long flags; 1022 int r; 1023 1024 spin_lock_irqsave(&dsi->irq_lock, flags); 1025 1026 r = _dsi_register_isr(isr, arg, mask, 1027 dsi->isr_tables.isr_table_vc[channel], 1028 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1029 1030 if (r == 0) 1031 _omap_dsi_set_irqs_vc(dsi, channel); 1032 1033 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1034 1035 return r; 1036} 1037 1038static int dsi_unregister_isr_vc(struct dsi_data *dsi, int channel, 1039 omap_dsi_isr_t isr, void *arg, u32 mask) 1040{ 1041 unsigned long flags; 1042 int r; 1043 1044 spin_lock_irqsave(&dsi->irq_lock, flags); 1045 1046 r = _dsi_unregister_isr(isr, arg, mask, 1047 dsi->isr_tables.isr_table_vc[channel], 1048 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel])); 1049 1050 if (r == 0) 1051 _omap_dsi_set_irqs_vc(dsi, channel); 1052 1053 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1054 1055 return r; 1056} 1057 1058static int dsi_register_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr, 1059 void *arg, u32 mask) 1060{ 1061 unsigned long flags; 1062 int r; 1063 1064 spin_lock_irqsave(&dsi->irq_lock, flags); 1065 1066 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1067 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1068 1069 if (r == 0) 1070 _omap_dsi_set_irqs_cio(dsi); 1071 1072 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1073 1074 return r; 1075} 1076 1077static int dsi_unregister_isr_cio(struct dsi_data *dsi, omap_dsi_isr_t isr, 1078 void *arg, u32 mask) 1079{ 1080 unsigned long flags; 1081 int r; 1082 1083 spin_lock_irqsave(&dsi->irq_lock, flags); 1084 1085 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio, 1086 ARRAY_SIZE(dsi->isr_tables.isr_table_cio)); 1087 1088 if (r == 0) 1089 _omap_dsi_set_irqs_cio(dsi); 1090 1091 spin_unlock_irqrestore(&dsi->irq_lock, flags); 1092 1093 return r; 1094} 1095 1096static u32 dsi_get_errors(struct dsi_data *dsi) 1097{ 1098 unsigned long flags; 1099 u32 e; 1100 1101 spin_lock_irqsave(&dsi->errors_lock, flags); 1102 e = dsi->errors; 1103 dsi->errors = 0; 1104 spin_unlock_irqrestore(&dsi->errors_lock, flags); 1105 return e; 1106} 1107 1108static int dsi_runtime_get(struct dsi_data *dsi) 1109{ 1110 int r; 1111 1112 DSSDBG("dsi_runtime_get\n"); 1113 1114 r = pm_runtime_get_sync(dsi->dev); 1115 WARN_ON(r < 0); 1116 return r < 0 ? r : 0; 1117} 1118 1119static void dsi_runtime_put(struct dsi_data *dsi) 1120{ 1121 int r; 1122 1123 DSSDBG("dsi_runtime_put\n"); 1124 1125 r = pm_runtime_put_sync(dsi->dev); 1126 WARN_ON(r < 0 && r != -ENOSYS); 1127} 1128 1129static void _dsi_print_reset_status(struct dsi_data *dsi) 1130{ 1131 u32 l; 1132 int b0, b1, b2; 1133 1134 /* A dummy read using the SCP interface to any DSIPHY register is 1135 * required after DSIPHY reset to complete the reset of the DSI complex 1136 * I/O. */ 1137 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1138 1139 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) { 1140 b0 = 28; 1141 b1 = 27; 1142 b2 = 26; 1143 } else { 1144 b0 = 24; 1145 b1 = 25; 1146 b2 = 26; 1147 } 1148 1149#define DSI_FLD_GET(fld, start, end)\ 1150 FLD_GET(dsi_read_reg(dsi, DSI_##fld), start, end) 1151 1152 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n", 1153 DSI_FLD_GET(PLL_STATUS, 0, 0), 1154 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29), 1155 DSI_FLD_GET(DSIPHY_CFG5, b0, b0), 1156 DSI_FLD_GET(DSIPHY_CFG5, b1, b1), 1157 DSI_FLD_GET(DSIPHY_CFG5, b2, b2), 1158 DSI_FLD_GET(DSIPHY_CFG5, 29, 29), 1159 DSI_FLD_GET(DSIPHY_CFG5, 30, 30), 1160 DSI_FLD_GET(DSIPHY_CFG5, 31, 31)); 1161 1162#undef DSI_FLD_GET 1163} 1164 1165static inline int dsi_if_enable(struct dsi_data *dsi, bool enable) 1166{ 1167 DSSDBG("dsi_if_enable(%d)\n", enable); 1168 1169 enable = enable ? 1 : 0; 1170 REG_FLD_MOD(dsi, DSI_CTRL, enable, 0, 0); /* IF_EN */ 1171 1172 if (!wait_for_bit_change(dsi, DSI_CTRL, 0, enable)) { 1173 DSSERR("Failed to set dsi_if_enable to %d\n", enable); 1174 return -EIO; 1175 } 1176 1177 return 0; 1178} 1179 1180static unsigned long dsi_get_pll_hsdiv_dispc_rate(struct dsi_data *dsi) 1181{ 1182 return dsi->pll.cinfo.clkout[HSDIV_DISPC]; 1183} 1184 1185static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct dsi_data *dsi) 1186{ 1187 return dsi->pll.cinfo.clkout[HSDIV_DSI]; 1188} 1189 1190static unsigned long dsi_get_txbyteclkhs(struct dsi_data *dsi) 1191{ 1192 return dsi->pll.cinfo.clkdco / 16; 1193} 1194 1195static unsigned long dsi_fclk_rate(struct dsi_data *dsi) 1196{ 1197 unsigned long r; 1198 enum dss_clk_source source; 1199 1200 source = dss_get_dsi_clk_source(dsi->dss, dsi->module_id); 1201 if (source == DSS_CLK_SRC_FCK) { 1202 /* DSI FCLK source is DSS_CLK_FCK */ 1203 r = clk_get_rate(dsi->dss_clk); 1204 } else { 1205 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */ 1206 r = dsi_get_pll_hsdiv_dsi_rate(dsi); 1207 } 1208 1209 return r; 1210} 1211 1212static int dsi_lp_clock_calc(unsigned long dsi_fclk, 1213 unsigned long lp_clk_min, unsigned long lp_clk_max, 1214 struct dsi_lp_clock_info *lp_cinfo) 1215{ 1216 unsigned int lp_clk_div; 1217 unsigned long lp_clk; 1218 1219 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2); 1220 lp_clk = dsi_fclk / 2 / lp_clk_div; 1221 1222 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max) 1223 return -EINVAL; 1224 1225 lp_cinfo->lp_clk_div = lp_clk_div; 1226 lp_cinfo->lp_clk = lp_clk; 1227 1228 return 0; 1229} 1230 1231static int dsi_set_lp_clk_divisor(struct dsi_data *dsi) 1232{ 1233 unsigned long dsi_fclk; 1234 unsigned int lp_clk_div; 1235 unsigned long lp_clk; 1236 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv; 1237 1238 1239 lp_clk_div = dsi->user_lp_cinfo.lp_clk_div; 1240 1241 if (lp_clk_div == 0 || lp_clk_div > lpdiv_max) 1242 return -EINVAL; 1243 1244 dsi_fclk = dsi_fclk_rate(dsi); 1245 1246 lp_clk = dsi_fclk / 2 / lp_clk_div; 1247 1248 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk); 1249 dsi->current_lp_cinfo.lp_clk = lp_clk; 1250 dsi->current_lp_cinfo.lp_clk_div = lp_clk_div; 1251 1252 /* LP_CLK_DIVISOR */ 1253 REG_FLD_MOD(dsi, DSI_CLK_CTRL, lp_clk_div, 12, 0); 1254 1255 /* LP_RX_SYNCHRO_ENABLE */ 1256 REG_FLD_MOD(dsi, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); 1257 1258 return 0; 1259} 1260 1261static void dsi_enable_scp_clk(struct dsi_data *dsi) 1262{ 1263 if (dsi->scp_clk_refcount++ == 0) 1264 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ 1265} 1266 1267static void dsi_disable_scp_clk(struct dsi_data *dsi) 1268{ 1269 WARN_ON(dsi->scp_clk_refcount == 0); 1270 if (--dsi->scp_clk_refcount == 0) 1271 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ 1272} 1273 1274enum dsi_pll_power_state { 1275 DSI_PLL_POWER_OFF = 0x0, 1276 DSI_PLL_POWER_ON_HSCLK = 0x1, 1277 DSI_PLL_POWER_ON_ALL = 0x2, 1278 DSI_PLL_POWER_ON_DIV = 0x3, 1279}; 1280 1281static int dsi_pll_power(struct dsi_data *dsi, enum dsi_pll_power_state state) 1282{ 1283 int t = 0; 1284 1285 /* DSI-PLL power command 0x3 is not working */ 1286 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) && 1287 state == DSI_PLL_POWER_ON_DIV) 1288 state = DSI_PLL_POWER_ON_ALL; 1289 1290 /* PLL_PWR_CMD */ 1291 REG_FLD_MOD(dsi, DSI_CLK_CTRL, state, 31, 30); 1292 1293 /* PLL_PWR_STATUS */ 1294 while (FLD_GET(dsi_read_reg(dsi, DSI_CLK_CTRL), 29, 28) != state) { 1295 if (++t > 1000) { 1296 DSSERR("Failed to set DSI PLL power mode to %d\n", 1297 state); 1298 return -ENODEV; 1299 } 1300 udelay(1); 1301 } 1302 1303 return 0; 1304} 1305 1306 1307static void dsi_pll_calc_dsi_fck(struct dsi_data *dsi, 1308 struct dss_pll_clock_info *cinfo) 1309{ 1310 unsigned long max_dsi_fck; 1311 1312 max_dsi_fck = dsi->data->max_fck_freq; 1313 1314 cinfo->mX[HSDIV_DSI] = DIV_ROUND_UP(cinfo->clkdco, max_dsi_fck); 1315 cinfo->clkout[HSDIV_DSI] = cinfo->clkdco / cinfo->mX[HSDIV_DSI]; 1316} 1317 1318static int dsi_pll_enable(struct dss_pll *pll) 1319{ 1320 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1321 int r = 0; 1322 1323 DSSDBG("PLL init\n"); 1324 1325 r = dsi_runtime_get(dsi); 1326 if (r) 1327 return r; 1328 1329 /* 1330 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4. 1331 */ 1332 dsi_enable_scp_clk(dsi); 1333 1334 r = regulator_enable(dsi->vdds_dsi_reg); 1335 if (r) 1336 goto err0; 1337 1338 /* XXX PLL does not come out of reset without this... */ 1339 dispc_pck_free_enable(dsi->dss->dispc, 1); 1340 1341 if (!wait_for_bit_change(dsi, DSI_PLL_STATUS, 0, 1)) { 1342 DSSERR("PLL not coming out of reset.\n"); 1343 r = -ENODEV; 1344 dispc_pck_free_enable(dsi->dss->dispc, 0); 1345 goto err1; 1346 } 1347 1348 /* XXX ... but if left on, we get problems when planes do not 1349 * fill the whole display. No idea about this */ 1350 dispc_pck_free_enable(dsi->dss->dispc, 0); 1351 1352 r = dsi_pll_power(dsi, DSI_PLL_POWER_ON_ALL); 1353 1354 if (r) 1355 goto err1; 1356 1357 DSSDBG("PLL init done\n"); 1358 1359 return 0; 1360err1: 1361 regulator_disable(dsi->vdds_dsi_reg); 1362err0: 1363 dsi_disable_scp_clk(dsi); 1364 dsi_runtime_put(dsi); 1365 return r; 1366} 1367 1368static void dsi_pll_disable(struct dss_pll *pll) 1369{ 1370 struct dsi_data *dsi = container_of(pll, struct dsi_data, pll); 1371 1372 dsi_pll_power(dsi, DSI_PLL_POWER_OFF); 1373 1374 regulator_disable(dsi->vdds_dsi_reg); 1375 1376 dsi_disable_scp_clk(dsi); 1377 dsi_runtime_put(dsi); 1378 1379 DSSDBG("PLL disable done\n"); 1380} 1381 1382static int dsi_dump_dsi_clocks(struct seq_file *s, void *p) 1383{ 1384 struct dsi_data *dsi = s->private; 1385 struct dss_pll_clock_info *cinfo = &dsi->pll.cinfo; 1386 enum dss_clk_source dispc_clk_src, dsi_clk_src; 1387 int dsi_module = dsi->module_id; 1388 struct dss_pll *pll = &dsi->pll; 1389 1390 dispc_clk_src = dss_get_dispc_clk_source(dsi->dss); 1391 dsi_clk_src = dss_get_dsi_clk_source(dsi->dss, dsi_module); 1392 1393 if (dsi_runtime_get(dsi)) 1394 return 0; 1395 1396 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1); 1397 1398 seq_printf(s, "dsi pll clkin\t%lu\n", clk_get_rate(pll->clkin)); 1399 1400 seq_printf(s, "Fint\t\t%-16lun %u\n", cinfo->fint, cinfo->n); 1401 1402 seq_printf(s, "CLKIN4DDR\t%-16lum %u\n", 1403 cinfo->clkdco, cinfo->m); 1404 1405 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16lum_dispc %u\t(%s)\n", 1406 dss_get_clk_source_name(dsi_module == 0 ? 1407 DSS_CLK_SRC_PLL1_1 : 1408 DSS_CLK_SRC_PLL2_1), 1409 cinfo->clkout[HSDIV_DISPC], 1410 cinfo->mX[HSDIV_DISPC], 1411 dispc_clk_src == DSS_CLK_SRC_FCK ? 1412 "off" : "on"); 1413 1414 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16lum_dsi %u\t(%s)\n", 1415 dss_get_clk_source_name(dsi_module == 0 ? 1416 DSS_CLK_SRC_PLL1_2 : 1417 DSS_CLK_SRC_PLL2_2), 1418 cinfo->clkout[HSDIV_DSI], 1419 cinfo->mX[HSDIV_DSI], 1420 dsi_clk_src == DSS_CLK_SRC_FCK ? 1421 "off" : "on"); 1422 1423 seq_printf(s, "- DSI%d -\n", dsi_module + 1); 1424 1425 seq_printf(s, "dsi fclk source = %s\n", 1426 dss_get_clk_source_name(dsi_clk_src)); 1427 1428 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsi)); 1429 1430 seq_printf(s, "DDR_CLK\t\t%lu\n", 1431 cinfo->clkdco / 4); 1432 1433 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsi)); 1434 1435 seq_printf(s, "LP_CLK\t\t%lu\n", dsi->current_lp_cinfo.lp_clk); 1436 1437 dsi_runtime_put(dsi); 1438 1439 return 0; 1440} 1441 1442#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 1443static int dsi_dump_dsi_irqs(struct seq_file *s, void *p) 1444{ 1445 struct dsi_data *dsi = s->private; 1446 unsigned long flags; 1447 struct dsi_irq_stats *stats; 1448 1449 stats = kmalloc(sizeof(*stats), GFP_KERNEL); 1450 if (!stats) 1451 return -ENOMEM; 1452 1453 spin_lock_irqsave(&dsi->irq_stats_lock, flags); 1454 1455 *stats = dsi->irq_stats; 1456 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats)); 1457 dsi->irq_stats.last_reset = jiffies; 1458 1459 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags); 1460 1461 seq_printf(s, "period %u ms\n", 1462 jiffies_to_msecs(jiffies - stats->last_reset)); 1463 1464 seq_printf(s, "irqs %d\n", stats->irq_count); 1465#define PIS(x) \ 1466 seq_printf(s, "%-20s %10d\n", #x, stats->dsi_irqs[ffs(DSI_IRQ_##x)-1]); 1467 1468 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1); 1469 PIS(VC0); 1470 PIS(VC1); 1471 PIS(VC2); 1472 PIS(VC3); 1473 PIS(WAKEUP); 1474 PIS(RESYNC); 1475 PIS(PLL_LOCK); 1476 PIS(PLL_UNLOCK); 1477 PIS(PLL_RECALL); 1478 PIS(COMPLEXIO_ERR); 1479 PIS(HS_TX_TIMEOUT); 1480 PIS(LP_RX_TIMEOUT); 1481 PIS(TE_TRIGGER); 1482 PIS(ACK_TRIGGER); 1483 PIS(SYNC_LOST); 1484 PIS(LDO_POWER_GOOD); 1485 PIS(TA_TIMEOUT); 1486#undef PIS 1487 1488#define PIS(x) \ 1489 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \ 1490 stats->vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \ 1491 stats->vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \ 1492 stats->vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \ 1493 stats->vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]); 1494 1495 seq_printf(s, "-- VC interrupts --\n"); 1496 PIS(CS); 1497 PIS(ECC_CORR); 1498 PIS(PACKET_SENT); 1499 PIS(FIFO_TX_OVF); 1500 PIS(FIFO_RX_OVF); 1501 PIS(BTA); 1502 PIS(ECC_NO_CORR); 1503 PIS(FIFO_TX_UDF); 1504 PIS(PP_BUSY_CHANGE); 1505#undef PIS 1506 1507#define PIS(x) \ 1508 seq_printf(s, "%-20s %10d\n", #x, \ 1509 stats->cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]); 1510 1511 seq_printf(s, "-- CIO interrupts --\n"); 1512 PIS(ERRSYNCESC1); 1513 PIS(ERRSYNCESC2); 1514 PIS(ERRSYNCESC3); 1515 PIS(ERRESC1); 1516 PIS(ERRESC2); 1517 PIS(ERRESC3); 1518 PIS(ERRCONTROL1); 1519 PIS(ERRCONTROL2); 1520 PIS(ERRCONTROL3); 1521 PIS(STATEULPS1); 1522 PIS(STATEULPS2); 1523 PIS(STATEULPS3); 1524 PIS(ERRCONTENTIONLP0_1); 1525 PIS(ERRCONTENTIONLP1_1); 1526 PIS(ERRCONTENTIONLP0_2); 1527 PIS(ERRCONTENTIONLP1_2); 1528 PIS(ERRCONTENTIONLP0_3); 1529 PIS(ERRCONTENTIONLP1_3); 1530 PIS(ULPSACTIVENOT_ALL0); 1531 PIS(ULPSACTIVENOT_ALL1); 1532#undef PIS 1533 1534 kfree(stats); 1535 1536 return 0; 1537} 1538#endif 1539 1540static int dsi_dump_dsi_regs(struct seq_file *s, void *p) 1541{ 1542 struct dsi_data *dsi = s->private; 1543 1544 if (dsi_runtime_get(dsi)) 1545 return 0; 1546 dsi_enable_scp_clk(dsi); 1547 1548#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsi, r)) 1549 DUMPREG(DSI_REVISION); 1550 DUMPREG(DSI_SYSCONFIG); 1551 DUMPREG(DSI_SYSSTATUS); 1552 DUMPREG(DSI_IRQSTATUS); 1553 DUMPREG(DSI_IRQENABLE); 1554 DUMPREG(DSI_CTRL); 1555 DUMPREG(DSI_COMPLEXIO_CFG1); 1556 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS); 1557 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE); 1558 DUMPREG(DSI_CLK_CTRL); 1559 DUMPREG(DSI_TIMING1); 1560 DUMPREG(DSI_TIMING2); 1561 DUMPREG(DSI_VM_TIMING1); 1562 DUMPREG(DSI_VM_TIMING2); 1563 DUMPREG(DSI_VM_TIMING3); 1564 DUMPREG(DSI_CLK_TIMING); 1565 DUMPREG(DSI_TX_FIFO_VC_SIZE); 1566 DUMPREG(DSI_RX_FIFO_VC_SIZE); 1567 DUMPREG(DSI_COMPLEXIO_CFG2); 1568 DUMPREG(DSI_RX_FIFO_VC_FULLNESS); 1569 DUMPREG(DSI_VM_TIMING4); 1570 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS); 1571 DUMPREG(DSI_VM_TIMING5); 1572 DUMPREG(DSI_VM_TIMING6); 1573 DUMPREG(DSI_VM_TIMING7); 1574 DUMPREG(DSI_STOPCLK_TIMING); 1575 1576 DUMPREG(DSI_VC_CTRL(0)); 1577 DUMPREG(DSI_VC_TE(0)); 1578 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0)); 1579 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0)); 1580 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0)); 1581 DUMPREG(DSI_VC_IRQSTATUS(0)); 1582 DUMPREG(DSI_VC_IRQENABLE(0)); 1583 1584 DUMPREG(DSI_VC_CTRL(1)); 1585 DUMPREG(DSI_VC_TE(1)); 1586 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1)); 1587 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1)); 1588 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1)); 1589 DUMPREG(DSI_VC_IRQSTATUS(1)); 1590 DUMPREG(DSI_VC_IRQENABLE(1)); 1591 1592 DUMPREG(DSI_VC_CTRL(2)); 1593 DUMPREG(DSI_VC_TE(2)); 1594 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2)); 1595 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2)); 1596 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2)); 1597 DUMPREG(DSI_VC_IRQSTATUS(2)); 1598 DUMPREG(DSI_VC_IRQENABLE(2)); 1599 1600 DUMPREG(DSI_VC_CTRL(3)); 1601 DUMPREG(DSI_VC_TE(3)); 1602 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3)); 1603 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3)); 1604 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3)); 1605 DUMPREG(DSI_VC_IRQSTATUS(3)); 1606 DUMPREG(DSI_VC_IRQENABLE(3)); 1607 1608 DUMPREG(DSI_DSIPHY_CFG0); 1609 DUMPREG(DSI_DSIPHY_CFG1); 1610 DUMPREG(DSI_DSIPHY_CFG2); 1611 DUMPREG(DSI_DSIPHY_CFG5); 1612 1613 DUMPREG(DSI_PLL_CONTROL); 1614 DUMPREG(DSI_PLL_STATUS); 1615 DUMPREG(DSI_PLL_GO); 1616 DUMPREG(DSI_PLL_CONFIGURATION1); 1617 DUMPREG(DSI_PLL_CONFIGURATION2); 1618#undef DUMPREG 1619 1620 dsi_disable_scp_clk(dsi); 1621 dsi_runtime_put(dsi); 1622 1623 return 0; 1624} 1625 1626enum dsi_cio_power_state { 1627 DSI_COMPLEXIO_POWER_OFF = 0x0, 1628 DSI_COMPLEXIO_POWER_ON = 0x1, 1629 DSI_COMPLEXIO_POWER_ULPS = 0x2, 1630}; 1631 1632static int dsi_cio_power(struct dsi_data *dsi, enum dsi_cio_power_state state) 1633{ 1634 int t = 0; 1635 1636 /* PWR_CMD */ 1637 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG1, state, 28, 27); 1638 1639 /* PWR_STATUS */ 1640 while (FLD_GET(dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1), 1641 26, 25) != state) { 1642 if (++t > 1000) { 1643 DSSERR("failed to set complexio power state to " 1644 "%d\n", state); 1645 return -ENODEV; 1646 } 1647 udelay(1); 1648 } 1649 1650 return 0; 1651} 1652 1653static unsigned int dsi_get_line_buf_size(struct dsi_data *dsi) 1654{ 1655 int val; 1656 1657 /* line buffer on OMAP3 is 1024 x 24bits */ 1658 /* XXX: for some reason using full buffer size causes 1659 * considerable TX slowdown with update sizes that fill the 1660 * whole buffer */ 1661 if (!(dsi->data->quirks & DSI_QUIRK_GNQ)) 1662 return 1023 * 3; 1663 1664 val = REG_GET(dsi, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ 1665 1666 switch (val) { 1667 case 1: 1668 return 512 * 3; /* 512x24 bits */ 1669 case 2: 1670 return 682 * 3; /* 682x24 bits */ 1671 case 3: 1672 return 853 * 3; /* 853x24 bits */ 1673 case 4: 1674 return 1024 * 3; /* 1024x24 bits */ 1675 case 5: 1676 return 1194 * 3; /* 1194x24 bits */ 1677 case 6: 1678 return 1365 * 3; /* 1365x24 bits */ 1679 case 7: 1680 return 1920 * 3; /* 1920x24 bits */ 1681 default: 1682 BUG(); 1683 return 0; 1684 } 1685} 1686 1687static int dsi_set_lane_config(struct dsi_data *dsi) 1688{ 1689 static const u8 offsets[] = { 0, 4, 8, 12, 16 }; 1690 static const enum dsi_lane_function functions[] = { 1691 DSI_LANE_CLK, 1692 DSI_LANE_DATA1, 1693 DSI_LANE_DATA2, 1694 DSI_LANE_DATA3, 1695 DSI_LANE_DATA4, 1696 }; 1697 u32 r; 1698 int i; 1699 1700 r = dsi_read_reg(dsi, DSI_COMPLEXIO_CFG1); 1701 1702 for (i = 0; i < dsi->num_lanes_used; ++i) { 1703 unsigned int offset = offsets[i]; 1704 unsigned int polarity, lane_number; 1705 unsigned int t; 1706 1707 for (t = 0; t < dsi->num_lanes_supported; ++t) 1708 if (dsi->lanes[t].function == functions[i]) 1709 break; 1710 1711 if (t == dsi->num_lanes_supported) 1712 return -EINVAL; 1713 1714 lane_number = t; 1715 polarity = dsi->lanes[t].polarity; 1716 1717 r = FLD_MOD(r, lane_number + 1, offset + 2, offset); 1718 r = FLD_MOD(r, polarity, offset + 3, offset + 3); 1719 } 1720 1721 /* clear the unused lanes */ 1722 for (; i < dsi->num_lanes_supported; ++i) { 1723 unsigned int offset = offsets[i]; 1724 1725 r = FLD_MOD(r, 0, offset + 2, offset); 1726 r = FLD_MOD(r, 0, offset + 3, offset + 3); 1727 } 1728 1729 dsi_write_reg(dsi, DSI_COMPLEXIO_CFG1, r); 1730 1731 return 0; 1732} 1733 1734static inline unsigned int ns2ddr(struct dsi_data *dsi, unsigned int ns) 1735{ 1736 /* convert time in ns to ddr ticks, rounding up */ 1737 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1738 1739 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000; 1740} 1741 1742static inline unsigned int ddr2ns(struct dsi_data *dsi, unsigned int ddr) 1743{ 1744 unsigned long ddr_clk = dsi->pll.cinfo.clkdco / 4; 1745 1746 return ddr * 1000 * 1000 / (ddr_clk / 1000); 1747} 1748 1749static void dsi_cio_timings(struct dsi_data *dsi) 1750{ 1751 u32 r; 1752 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit; 1753 u32 tlpx_half, tclk_trail, tclk_zero; 1754 u32 tclk_prepare; 1755 1756 /* calculate timings */ 1757 1758 /* 1 * DDR_CLK = 2 * UI */ 1759 1760 /* min 40ns + 4*UI max 85ns + 6*UI */ 1761 ths_prepare = ns2ddr(dsi, 70) + 2; 1762 1763 /* min 145ns + 10*UI */ 1764 ths_prepare_ths_zero = ns2ddr(dsi, 175) + 2; 1765 1766 /* min max(8*UI, 60ns+4*UI) */ 1767 ths_trail = ns2ddr(dsi, 60) + 5; 1768 1769 /* min 100ns */ 1770 ths_exit = ns2ddr(dsi, 145); 1771 1772 /* tlpx min 50n */ 1773 tlpx_half = ns2ddr(dsi, 25); 1774 1775 /* min 60ns */ 1776 tclk_trail = ns2ddr(dsi, 60) + 2; 1777 1778 /* min 38ns, max 95ns */ 1779 tclk_prepare = ns2ddr(dsi, 65); 1780 1781 /* min tclk-prepare + tclk-zero = 300ns */ 1782 tclk_zero = ns2ddr(dsi, 260); 1783 1784 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n", 1785 ths_prepare, ddr2ns(dsi, ths_prepare), 1786 ths_prepare_ths_zero, ddr2ns(dsi, ths_prepare_ths_zero)); 1787 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n", 1788 ths_trail, ddr2ns(dsi, ths_trail), 1789 ths_exit, ddr2ns(dsi, ths_exit)); 1790 1791 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), " 1792 "tclk_zero %u (%uns)\n", 1793 tlpx_half, ddr2ns(dsi, tlpx_half), 1794 tclk_trail, ddr2ns(dsi, tclk_trail), 1795 tclk_zero, ddr2ns(dsi, tclk_zero)); 1796 DSSDBG("tclk_prepare %u (%uns)\n", 1797 tclk_prepare, ddr2ns(dsi, tclk_prepare)); 1798 1799 /* program timings */ 1800 1801 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 1802 r = FLD_MOD(r, ths_prepare, 31, 24); 1803 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16); 1804 r = FLD_MOD(r, ths_trail, 15, 8); 1805 r = FLD_MOD(r, ths_exit, 7, 0); 1806 dsi_write_reg(dsi, DSI_DSIPHY_CFG0, r); 1807 1808 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 1809 r = FLD_MOD(r, tlpx_half, 20, 16); 1810 r = FLD_MOD(r, tclk_trail, 15, 8); 1811 r = FLD_MOD(r, tclk_zero, 7, 0); 1812 1813 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) { 1814 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */ 1815 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */ 1816 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */ 1817 } 1818 1819 dsi_write_reg(dsi, DSI_DSIPHY_CFG1, r); 1820 1821 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 1822 r = FLD_MOD(r, tclk_prepare, 7, 0); 1823 dsi_write_reg(dsi, DSI_DSIPHY_CFG2, r); 1824} 1825 1826/* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */ 1827static void dsi_cio_enable_lane_override(struct dsi_data *dsi, 1828 unsigned int mask_p, 1829 unsigned int mask_n) 1830{ 1831 int i; 1832 u32 l; 1833 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26; 1834 1835 l = 0; 1836 1837 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1838 unsigned int p = dsi->lanes[i].polarity; 1839 1840 if (mask_p & (1 << i)) 1841 l |= 1 << (i * 2 + (p ? 0 : 1)); 1842 1843 if (mask_n & (1 << i)) 1844 l |= 1 << (i * 2 + (p ? 1 : 0)); 1845 } 1846 1847 /* 1848 * Bits in REGLPTXSCPDAT4TO0DXDY: 1849 * 17: DY0 18: DX0 1850 * 19: DY1 20: DX1 1851 * 21: DY2 22: DX2 1852 * 23: DY3 24: DX3 1853 * 25: DY4 26: DX4 1854 */ 1855 1856 /* Set the lane override configuration */ 1857 1858 /* REGLPTXSCPDAT4TO0DXDY */ 1859 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, l, lptxscp_start, 17); 1860 1861 /* Enable lane override */ 1862 1863 /* ENLPTXSCPDAT */ 1864 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 1, 27, 27); 1865} 1866 1867static void dsi_cio_disable_lane_override(struct dsi_data *dsi) 1868{ 1869 /* Disable lane override */ 1870 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */ 1871 /* Reset the lane override configuration */ 1872 /* REGLPTXSCPDAT4TO0DXDY */ 1873 REG_FLD_MOD(dsi, DSI_DSIPHY_CFG10, 0, 22, 17); 1874} 1875 1876static int dsi_cio_wait_tx_clk_esc_reset(struct dsi_data *dsi) 1877{ 1878 int t, i; 1879 bool in_use[DSI_MAX_NR_LANES]; 1880 static const u8 offsets_old[] = { 28, 27, 26 }; 1881 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 }; 1882 const u8 *offsets; 1883 1884 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) 1885 offsets = offsets_old; 1886 else 1887 offsets = offsets_new; 1888 1889 for (i = 0; i < dsi->num_lanes_supported; ++i) 1890 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED; 1891 1892 t = 100000; 1893 while (true) { 1894 u32 l; 1895 int ok; 1896 1897 l = dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 1898 1899 ok = 0; 1900 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1901 if (!in_use[i] || (l & (1 << offsets[i]))) 1902 ok++; 1903 } 1904 1905 if (ok == dsi->num_lanes_supported) 1906 break; 1907 1908 if (--t == 0) { 1909 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1910 if (!in_use[i] || (l & (1 << offsets[i]))) 1911 continue; 1912 1913 DSSERR("CIO TXCLKESC%d domain not coming " \ 1914 "out of reset\n", i); 1915 } 1916 return -EIO; 1917 } 1918 } 1919 1920 return 0; 1921} 1922 1923/* return bitmask of enabled lanes, lane0 being the lsb */ 1924static unsigned int dsi_get_lane_mask(struct dsi_data *dsi) 1925{ 1926 unsigned int mask = 0; 1927 int i; 1928 1929 for (i = 0; i < dsi->num_lanes_supported; ++i) { 1930 if (dsi->lanes[i].function != DSI_LANE_UNUSED) 1931 mask |= 1 << i; 1932 } 1933 1934 return mask; 1935} 1936 1937/* OMAP4 CONTROL_DSIPHY */ 1938#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78 1939 1940#define OMAP4_DSI2_LANEENABLE_SHIFT 29 1941#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) 1942#define OMAP4_DSI1_LANEENABLE_SHIFT 24 1943#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) 1944#define OMAP4_DSI1_PIPD_SHIFT 19 1945#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) 1946#define OMAP4_DSI2_PIPD_SHIFT 14 1947#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) 1948 1949static int dsi_omap4_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1950{ 1951 u32 enable_mask, enable_shift; 1952 u32 pipd_mask, pipd_shift; 1953 1954 if (dsi->module_id == 0) { 1955 enable_mask = OMAP4_DSI1_LANEENABLE_MASK; 1956 enable_shift = OMAP4_DSI1_LANEENABLE_SHIFT; 1957 pipd_mask = OMAP4_DSI1_PIPD_MASK; 1958 pipd_shift = OMAP4_DSI1_PIPD_SHIFT; 1959 } else if (dsi->module_id == 1) { 1960 enable_mask = OMAP4_DSI2_LANEENABLE_MASK; 1961 enable_shift = OMAP4_DSI2_LANEENABLE_SHIFT; 1962 pipd_mask = OMAP4_DSI2_PIPD_MASK; 1963 pipd_shift = OMAP4_DSI2_PIPD_SHIFT; 1964 } else { 1965 return -ENODEV; 1966 } 1967 1968 return regmap_update_bits(dsi->syscon, OMAP4_DSIPHY_SYSCON_OFFSET, 1969 enable_mask | pipd_mask, 1970 (lanes << enable_shift) | (lanes << pipd_shift)); 1971} 1972 1973/* OMAP5 CONTROL_DSIPHY */ 1974 1975#define OMAP5_DSIPHY_SYSCON_OFFSET 0x74 1976 1977#define OMAP5_DSI1_LANEENABLE_SHIFT 24 1978#define OMAP5_DSI2_LANEENABLE_SHIFT 19 1979#define OMAP5_DSI_LANEENABLE_MASK 0x1f 1980 1981static int dsi_omap5_mux_pads(struct dsi_data *dsi, unsigned int lanes) 1982{ 1983 u32 enable_shift; 1984 1985 if (dsi->module_id == 0) 1986 enable_shift = OMAP5_DSI1_LANEENABLE_SHIFT; 1987 else if (dsi->module_id == 1) 1988 enable_shift = OMAP5_DSI2_LANEENABLE_SHIFT; 1989 else 1990 return -ENODEV; 1991 1992 return regmap_update_bits(dsi->syscon, OMAP5_DSIPHY_SYSCON_OFFSET, 1993 OMAP5_DSI_LANEENABLE_MASK << enable_shift, 1994 lanes << enable_shift); 1995} 1996 1997static int dsi_enable_pads(struct dsi_data *dsi, unsigned int lane_mask) 1998{ 1999 if (dsi->data->model == DSI_MODEL_OMAP4) 2000 return dsi_omap4_mux_pads(dsi, lane_mask); 2001 if (dsi->data->model == DSI_MODEL_OMAP5) 2002 return dsi_omap5_mux_pads(dsi, lane_mask); 2003 return 0; 2004} 2005 2006static void dsi_disable_pads(struct dsi_data *dsi) 2007{ 2008 if (dsi->data->model == DSI_MODEL_OMAP4) 2009 dsi_omap4_mux_pads(dsi, 0); 2010 else if (dsi->data->model == DSI_MODEL_OMAP5) 2011 dsi_omap5_mux_pads(dsi, 0); 2012} 2013 2014static int dsi_cio_init(struct dsi_data *dsi) 2015{ 2016 int r; 2017 u32 l; 2018 2019 DSSDBG("DSI CIO init starts"); 2020 2021 r = dsi_enable_pads(dsi, dsi_get_lane_mask(dsi)); 2022 if (r) 2023 return r; 2024 2025 dsi_enable_scp_clk(dsi); 2026 2027 /* A dummy read using the SCP interface to any DSIPHY register is 2028 * required after DSIPHY reset to complete the reset of the DSI complex 2029 * I/O. */ 2030 dsi_read_reg(dsi, DSI_DSIPHY_CFG5); 2031 2032 if (!wait_for_bit_change(dsi, DSI_DSIPHY_CFG5, 30, 1)) { 2033 DSSERR("CIO SCP Clock domain not coming out of reset.\n"); 2034 r = -EIO; 2035 goto err_scp_clk_dom; 2036 } 2037 2038 r = dsi_set_lane_config(dsi); 2039 if (r) 2040 goto err_scp_clk_dom; 2041 2042 /* set TX STOP MODE timer to maximum for this operation */ 2043 l = dsi_read_reg(dsi, DSI_TIMING1); 2044 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2045 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */ 2046 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */ 2047 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */ 2048 dsi_write_reg(dsi, DSI_TIMING1, l); 2049 2050 if (dsi->ulps_enabled) { 2051 unsigned int mask_p; 2052 int i; 2053 2054 DSSDBG("manual ulps exit\n"); 2055 2056 /* ULPS is exited by Mark-1 state for 1ms, followed by 2057 * stop state. DSS HW cannot do this via the normal 2058 * ULPS exit sequence, as after reset the DSS HW thinks 2059 * that we are not in ULPS mode, and refuses to send the 2060 * sequence. So we need to send the ULPS exit sequence 2061 * manually by setting positive lines high and negative lines 2062 * low for 1ms. 2063 */ 2064 2065 mask_p = 0; 2066 2067 for (i = 0; i < dsi->num_lanes_supported; ++i) { 2068 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 2069 continue; 2070 mask_p |= 1 << i; 2071 } 2072 2073 dsi_cio_enable_lane_override(dsi, mask_p, 0); 2074 } 2075 2076 r = dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ON); 2077 if (r) 2078 goto err_cio_pwr; 2079 2080 if (!wait_for_bit_change(dsi, DSI_COMPLEXIO_CFG1, 29, 1)) { 2081 DSSERR("CIO PWR clock domain not coming out of reset.\n"); 2082 r = -ENODEV; 2083 goto err_cio_pwr_dom; 2084 } 2085 2086 dsi_if_enable(dsi, true); 2087 dsi_if_enable(dsi, false); 2088 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */ 2089 2090 r = dsi_cio_wait_tx_clk_esc_reset(dsi); 2091 if (r) 2092 goto err_tx_clk_esc_rst; 2093 2094 if (dsi->ulps_enabled) { 2095 /* Keep Mark-1 state for 1ms (as per DSI spec) */ 2096 ktime_t wait = ns_to_ktime(1000 * 1000); 2097 set_current_state(TASK_UNINTERRUPTIBLE); 2098 schedule_hrtimeout(&wait, HRTIMER_MODE_REL); 2099 2100 /* Disable the override. The lanes should be set to Mark-11 2101 * state by the HW */ 2102 dsi_cio_disable_lane_override(dsi); 2103 } 2104 2105 /* FORCE_TX_STOP_MODE_IO */ 2106 REG_FLD_MOD(dsi, DSI_TIMING1, 0, 15, 15); 2107 2108 dsi_cio_timings(dsi); 2109 2110 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 2111 /* DDR_CLK_ALWAYS_ON */ 2112 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 2113 dsi->vm_timings.ddr_clk_always_on, 13, 13); 2114 } 2115 2116 dsi->ulps_enabled = false; 2117 2118 DSSDBG("CIO init done\n"); 2119 2120 return 0; 2121 2122err_tx_clk_esc_rst: 2123 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */ 2124err_cio_pwr_dom: 2125 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 2126err_cio_pwr: 2127 if (dsi->ulps_enabled) 2128 dsi_cio_disable_lane_override(dsi); 2129err_scp_clk_dom: 2130 dsi_disable_scp_clk(dsi); 2131 dsi_disable_pads(dsi); 2132 return r; 2133} 2134 2135static void dsi_cio_uninit(struct dsi_data *dsi) 2136{ 2137 /* DDR_CLK_ALWAYS_ON */ 2138 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); 2139 2140 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_OFF); 2141 dsi_disable_scp_clk(dsi); 2142 dsi_disable_pads(dsi); 2143} 2144 2145static void dsi_config_tx_fifo(struct dsi_data *dsi, 2146 enum fifo_size size1, enum fifo_size size2, 2147 enum fifo_size size3, enum fifo_size size4) 2148{ 2149 u32 r = 0; 2150 int add = 0; 2151 int i; 2152 2153 dsi->vc[0].tx_fifo_size = size1; 2154 dsi->vc[1].tx_fifo_size = size2; 2155 dsi->vc[2].tx_fifo_size = size3; 2156 dsi->vc[3].tx_fifo_size = size4; 2157 2158 for (i = 0; i < 4; i++) { 2159 u8 v; 2160 int size = dsi->vc[i].tx_fifo_size; 2161 2162 if (add + size > 4) { 2163 DSSERR("Illegal FIFO configuration\n"); 2164 BUG(); 2165 return; 2166 } 2167 2168 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2169 r |= v << (8 * i); 2170 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2171 add += size; 2172 } 2173 2174 dsi_write_reg(dsi, DSI_TX_FIFO_VC_SIZE, r); 2175} 2176 2177static void dsi_config_rx_fifo(struct dsi_data *dsi, 2178 enum fifo_size size1, enum fifo_size size2, 2179 enum fifo_size size3, enum fifo_size size4) 2180{ 2181 u32 r = 0; 2182 int add = 0; 2183 int i; 2184 2185 dsi->vc[0].rx_fifo_size = size1; 2186 dsi->vc[1].rx_fifo_size = size2; 2187 dsi->vc[2].rx_fifo_size = size3; 2188 dsi->vc[3].rx_fifo_size = size4; 2189 2190 for (i = 0; i < 4; i++) { 2191 u8 v; 2192 int size = dsi->vc[i].rx_fifo_size; 2193 2194 if (add + size > 4) { 2195 DSSERR("Illegal FIFO configuration\n"); 2196 BUG(); 2197 return; 2198 } 2199 2200 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4); 2201 r |= v << (8 * i); 2202 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */ 2203 add += size; 2204 } 2205 2206 dsi_write_reg(dsi, DSI_RX_FIFO_VC_SIZE, r); 2207} 2208 2209static int dsi_force_tx_stop_mode_io(struct dsi_data *dsi) 2210{ 2211 u32 r; 2212 2213 r = dsi_read_reg(dsi, DSI_TIMING1); 2214 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 2215 dsi_write_reg(dsi, DSI_TIMING1, r); 2216 2217 if (!wait_for_bit_change(dsi, DSI_TIMING1, 15, 0)) { 2218 DSSERR("TX_STOP bit not going down\n"); 2219 return -EIO; 2220 } 2221 2222 return 0; 2223} 2224 2225static bool dsi_vc_is_enabled(struct dsi_data *dsi, int channel) 2226{ 2227 return REG_GET(dsi, DSI_VC_CTRL(channel), 0, 0); 2228} 2229 2230static void dsi_packet_sent_handler_vp(void *data, u32 mask) 2231{ 2232 struct dsi_packet_sent_handler_data *vp_data = 2233 (struct dsi_packet_sent_handler_data *) data; 2234 struct dsi_data *dsi = vp_data->dsi; 2235 const int channel = dsi->update_channel; 2236 u8 bit = dsi->te_enabled ? 30 : 31; 2237 2238 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit) == 0) 2239 complete(vp_data->completion); 2240} 2241 2242static int dsi_sync_vc_vp(struct dsi_data *dsi, int channel) 2243{ 2244 DECLARE_COMPLETION_ONSTACK(completion); 2245 struct dsi_packet_sent_handler_data vp_data = { 2246 .dsi = dsi, 2247 .completion = &completion 2248 }; 2249 int r = 0; 2250 u8 bit; 2251 2252 bit = dsi->te_enabled ? 30 : 31; 2253 2254 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, 2255 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2256 if (r) 2257 goto err0; 2258 2259 /* Wait for completion only if TE_EN/TE_START is still set */ 2260 if (REG_GET(dsi, DSI_VC_TE(channel), bit, bit)) { 2261 if (wait_for_completion_timeout(&completion, 2262 msecs_to_jiffies(10)) == 0) { 2263 DSSERR("Failed to complete previous frame transfer\n"); 2264 r = -EIO; 2265 goto err1; 2266 } 2267 } 2268 2269 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, 2270 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2271 2272 return 0; 2273err1: 2274 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_vp, 2275 &vp_data, DSI_VC_IRQ_PACKET_SENT); 2276err0: 2277 return r; 2278} 2279 2280static void dsi_packet_sent_handler_l4(void *data, u32 mask) 2281{ 2282 struct dsi_packet_sent_handler_data *l4_data = 2283 (struct dsi_packet_sent_handler_data *) data; 2284 struct dsi_data *dsi = l4_data->dsi; 2285 const int channel = dsi->update_channel; 2286 2287 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5) == 0) 2288 complete(l4_data->completion); 2289} 2290 2291static int dsi_sync_vc_l4(struct dsi_data *dsi, int channel) 2292{ 2293 DECLARE_COMPLETION_ONSTACK(completion); 2294 struct dsi_packet_sent_handler_data l4_data = { 2295 .dsi = dsi, 2296 .completion = &completion 2297 }; 2298 int r = 0; 2299 2300 r = dsi_register_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, 2301 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2302 if (r) 2303 goto err0; 2304 2305 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */ 2306 if (REG_GET(dsi, DSI_VC_CTRL(channel), 5, 5)) { 2307 if (wait_for_completion_timeout(&completion, 2308 msecs_to_jiffies(10)) == 0) { 2309 DSSERR("Failed to complete previous l4 transfer\n"); 2310 r = -EIO; 2311 goto err1; 2312 } 2313 } 2314 2315 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, 2316 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2317 2318 return 0; 2319err1: 2320 dsi_unregister_isr_vc(dsi, channel, dsi_packet_sent_handler_l4, 2321 &l4_data, DSI_VC_IRQ_PACKET_SENT); 2322err0: 2323 return r; 2324} 2325 2326static int dsi_sync_vc(struct dsi_data *dsi, int channel) 2327{ 2328 WARN_ON(!dsi_bus_is_locked(dsi)); 2329 2330 WARN_ON(in_interrupt()); 2331 2332 if (!dsi_vc_is_enabled(dsi, channel)) 2333 return 0; 2334 2335 switch (dsi->vc[channel].source) { 2336 case DSI_VC_SOURCE_VP: 2337 return dsi_sync_vc_vp(dsi, channel); 2338 case DSI_VC_SOURCE_L4: 2339 return dsi_sync_vc_l4(dsi, channel); 2340 default: 2341 BUG(); 2342 return -EINVAL; 2343 } 2344} 2345 2346static int dsi_vc_enable(struct dsi_data *dsi, int channel, bool enable) 2347{ 2348 DSSDBG("dsi_vc_enable channel %d, enable %d\n", 2349 channel, enable); 2350 2351 enable = enable ? 1 : 0; 2352 2353 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 0, 0); 2354 2355 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 0, enable)) { 2356 DSSERR("Failed to set dsi_vc_enable to %d\n", enable); 2357 return -EIO; 2358 } 2359 2360 return 0; 2361} 2362 2363static void dsi_vc_initial_config(struct dsi_data *dsi, int channel) 2364{ 2365 u32 r; 2366 2367 DSSDBG("Initial config of virtual channel %d", channel); 2368 2369 r = dsi_read_reg(dsi, DSI_VC_CTRL(channel)); 2370 2371 if (FLD_GET(r, 15, 15)) /* VC_BUSY */ 2372 DSSERR("VC(%d) busy when trying to configure it!\n", 2373 channel); 2374 2375 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */ 2376 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */ 2377 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */ 2378 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */ 2379 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */ 2380 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */ 2381 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */ 2382 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH) 2383 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */ 2384 2385 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */ 2386 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */ 2387 2388 dsi_write_reg(dsi, DSI_VC_CTRL(channel), r); 2389 2390 dsi->vc[channel].source = DSI_VC_SOURCE_L4; 2391} 2392 2393static int dsi_vc_config_source(struct dsi_data *dsi, int channel, 2394 enum dsi_vc_source source) 2395{ 2396 if (dsi->vc[channel].source == source) 2397 return 0; 2398 2399 DSSDBG("Source config of virtual channel %d", channel); 2400 2401 dsi_sync_vc(dsi, channel); 2402 2403 dsi_vc_enable(dsi, channel, 0); 2404 2405 /* VC_BUSY */ 2406 if (!wait_for_bit_change(dsi, DSI_VC_CTRL(channel), 15, 0)) { 2407 DSSERR("vc(%d) busy when trying to config for VP\n", channel); 2408 return -EIO; 2409 } 2410 2411 /* SOURCE, 0 = L4, 1 = video port */ 2412 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), source, 1, 1); 2413 2414 /* DCS_CMD_ENABLE */ 2415 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) { 2416 bool enable = source == DSI_VC_SOURCE_VP; 2417 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 30, 30); 2418 } 2419 2420 dsi_vc_enable(dsi, channel, 1); 2421 2422 dsi->vc[channel].source = source; 2423 2424 return 0; 2425} 2426 2427static void dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel, 2428 bool enable) 2429{ 2430 struct dsi_data *dsi = to_dsi_data(dssdev); 2431 2432 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable); 2433 2434 WARN_ON(!dsi_bus_is_locked(dsi)); 2435 2436 dsi_vc_enable(dsi, channel, 0); 2437 dsi_if_enable(dsi, 0); 2438 2439 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), enable, 9, 9); 2440 2441 dsi_vc_enable(dsi, channel, 1); 2442 dsi_if_enable(dsi, 1); 2443 2444 dsi_force_tx_stop_mode_io(dsi); 2445 2446 /* start the DDR clock by sending a NULL packet */ 2447 if (dsi->vm_timings.ddr_clk_always_on && enable) 2448 dsi_vc_send_null(dsi, channel); 2449} 2450 2451static void dsi_vc_flush_long_data(struct dsi_data *dsi, int channel) 2452{ 2453 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2454 u32 val; 2455 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); 2456 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n", 2457 (val >> 0) & 0xff, 2458 (val >> 8) & 0xff, 2459 (val >> 16) & 0xff, 2460 (val >> 24) & 0xff); 2461 } 2462} 2463 2464static void dsi_show_rx_ack_with_err(u16 err) 2465{ 2466 DSSERR("\tACK with ERROR (%#x):\n", err); 2467 if (err & (1 << 0)) 2468 DSSERR("\t\tSoT Error\n"); 2469 if (err & (1 << 1)) 2470 DSSERR("\t\tSoT Sync Error\n"); 2471 if (err & (1 << 2)) 2472 DSSERR("\t\tEoT Sync Error\n"); 2473 if (err & (1 << 3)) 2474 DSSERR("\t\tEscape Mode Entry Command Error\n"); 2475 if (err & (1 << 4)) 2476 DSSERR("\t\tLP Transmit Sync Error\n"); 2477 if (err & (1 << 5)) 2478 DSSERR("\t\tHS Receive Timeout Error\n"); 2479 if (err & (1 << 6)) 2480 DSSERR("\t\tFalse Control Error\n"); 2481 if (err & (1 << 7)) 2482 DSSERR("\t\t(reserved7)\n"); 2483 if (err & (1 << 8)) 2484 DSSERR("\t\tECC Error, single-bit (corrected)\n"); 2485 if (err & (1 << 9)) 2486 DSSERR("\t\tECC Error, multi-bit (not corrected)\n"); 2487 if (err & (1 << 10)) 2488 DSSERR("\t\tChecksum Error\n"); 2489 if (err & (1 << 11)) 2490 DSSERR("\t\tData type not recognized\n"); 2491 if (err & (1 << 12)) 2492 DSSERR("\t\tInvalid VC ID\n"); 2493 if (err & (1 << 13)) 2494 DSSERR("\t\tInvalid Transmission Length\n"); 2495 if (err & (1 << 14)) 2496 DSSERR("\t\t(reserved14)\n"); 2497 if (err & (1 << 15)) 2498 DSSERR("\t\tDSI Protocol Violation\n"); 2499} 2500 2501static u16 dsi_vc_flush_receive_data(struct dsi_data *dsi, int channel) 2502{ 2503 /* RX_FIFO_NOT_EMPTY */ 2504 while (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2505 u32 val; 2506 u8 dt; 2507 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); 2508 DSSERR("\trawval %#08x\n", val); 2509 dt = FLD_GET(val, 5, 0); 2510 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2511 u16 err = FLD_GET(val, 23, 8); 2512 dsi_show_rx_ack_with_err(err); 2513 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) { 2514 DSSERR("\tDCS short response, 1 byte: %#x\n", 2515 FLD_GET(val, 23, 8)); 2516 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) { 2517 DSSERR("\tDCS short response, 2 byte: %#x\n", 2518 FLD_GET(val, 23, 8)); 2519 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) { 2520 DSSERR("\tDCS long response, len %d\n", 2521 FLD_GET(val, 23, 8)); 2522 dsi_vc_flush_long_data(dsi, channel); 2523 } else { 2524 DSSERR("\tunknown datatype 0x%02x\n", dt); 2525 } 2526 } 2527 return 0; 2528} 2529 2530static int dsi_vc_send_bta(struct dsi_data *dsi, int channel) 2531{ 2532 if (dsi->debug_write || dsi->debug_read) 2533 DSSDBG("dsi_vc_send_bta %d\n", channel); 2534 2535 WARN_ON(!dsi_bus_is_locked(dsi)); 2536 2537 /* RX_FIFO_NOT_EMPTY */ 2538 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2539 DSSERR("rx fifo not empty when sending BTA, dumping data:\n"); 2540 dsi_vc_flush_receive_data(dsi, channel); 2541 } 2542 2543 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */ 2544 2545 /* flush posted write */ 2546 dsi_read_reg(dsi, DSI_VC_CTRL(channel)); 2547 2548 return 0; 2549} 2550 2551static int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel) 2552{ 2553 struct dsi_data *dsi = to_dsi_data(dssdev); 2554 DECLARE_COMPLETION_ONSTACK(completion); 2555 int r = 0; 2556 u32 err; 2557 2558 r = dsi_register_isr_vc(dsi, channel, dsi_completion_handler, 2559 &completion, DSI_VC_IRQ_BTA); 2560 if (r) 2561 goto err0; 2562 2563 r = dsi_register_isr(dsi, dsi_completion_handler, &completion, 2564 DSI_IRQ_ERROR_MASK); 2565 if (r) 2566 goto err1; 2567 2568 r = dsi_vc_send_bta(dsi, channel); 2569 if (r) 2570 goto err2; 2571 2572 if (wait_for_completion_timeout(&completion, 2573 msecs_to_jiffies(500)) == 0) { 2574 DSSERR("Failed to receive BTA\n"); 2575 r = -EIO; 2576 goto err2; 2577 } 2578 2579 err = dsi_get_errors(dsi); 2580 if (err) { 2581 DSSERR("Error while sending BTA: %x\n", err); 2582 r = -EIO; 2583 goto err2; 2584 } 2585err2: 2586 dsi_unregister_isr(dsi, dsi_completion_handler, &completion, 2587 DSI_IRQ_ERROR_MASK); 2588err1: 2589 dsi_unregister_isr_vc(dsi, channel, dsi_completion_handler, 2590 &completion, DSI_VC_IRQ_BTA); 2591err0: 2592 return r; 2593} 2594 2595static inline void dsi_vc_write_long_header(struct dsi_data *dsi, int channel, 2596 u8 data_type, u16 len, u8 ecc) 2597{ 2598 u32 val; 2599 u8 data_id; 2600 2601 WARN_ON(!dsi_bus_is_locked(dsi)); 2602 2603 data_id = data_type | dsi->vc[channel].vc_id << 6; 2604 2605 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) | 2606 FLD_VAL(ecc, 31, 24); 2607 2608 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_HEADER(channel), val); 2609} 2610 2611static inline void dsi_vc_write_long_payload(struct dsi_data *dsi, int channel, 2612 u8 b1, u8 b2, u8 b3, u8 b4) 2613{ 2614 u32 val; 2615 2616 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0; 2617 2618/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n", 2619 b1, b2, b3, b4, val); */ 2620 2621 dsi_write_reg(dsi, DSI_VC_LONG_PACKET_PAYLOAD(channel), val); 2622} 2623 2624static int dsi_vc_send_long(struct dsi_data *dsi, int channel, u8 data_type, 2625 u8 *data, u16 len, u8 ecc) 2626{ 2627 /*u32 val; */ 2628 int i; 2629 u8 *p; 2630 int r = 0; 2631 u8 b1, b2, b3, b4; 2632 2633 if (dsi->debug_write) 2634 DSSDBG("dsi_vc_send_long, %d bytes\n", len); 2635 2636 /* len + header */ 2637 if (dsi->vc[channel].tx_fifo_size * 32 * 4 < len + 4) { 2638 DSSERR("unable to send long packet: packet too long.\n"); 2639 return -EINVAL; 2640 } 2641 2642 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4); 2643 2644 dsi_vc_write_long_header(dsi, channel, data_type, len, ecc); 2645 2646 p = data; 2647 for (i = 0; i < len >> 2; i++) { 2648 if (dsi->debug_write) 2649 DSSDBG("\tsending full packet %d\n", i); 2650 2651 b1 = *p++; 2652 b2 = *p++; 2653 b3 = *p++; 2654 b4 = *p++; 2655 2656 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, b4); 2657 } 2658 2659 i = len % 4; 2660 if (i) { 2661 b1 = 0; b2 = 0; b3 = 0; 2662 2663 if (dsi->debug_write) 2664 DSSDBG("\tsending remainder bytes %d\n", i); 2665 2666 switch (i) { 2667 case 3: 2668 b1 = *p++; 2669 b2 = *p++; 2670 b3 = *p++; 2671 break; 2672 case 2: 2673 b1 = *p++; 2674 b2 = *p++; 2675 break; 2676 case 1: 2677 b1 = *p++; 2678 break; 2679 } 2680 2681 dsi_vc_write_long_payload(dsi, channel, b1, b2, b3, 0); 2682 } 2683 2684 return r; 2685} 2686 2687static int dsi_vc_send_short(struct dsi_data *dsi, int channel, u8 data_type, 2688 u16 data, u8 ecc) 2689{ 2690 u32 r; 2691 u8 data_id; 2692 2693 WARN_ON(!dsi_bus_is_locked(dsi)); 2694 2695 if (dsi->debug_write) 2696 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n", 2697 channel, 2698 data_type, data & 0xff, (data >> 8) & 0xff); 2699 2700 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_L4); 2701 2702 if (FLD_GET(dsi_read_reg(dsi, DSI_VC_CTRL(channel)), 16, 16)) { 2703 DSSERR("ERROR FIFO FULL, aborting transfer\n"); 2704 return -EINVAL; 2705 } 2706 2707 data_id = data_type | dsi->vc[channel].vc_id << 6; 2708 2709 r = (data_id << 0) | (data << 8) | (ecc << 24); 2710 2711 dsi_write_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel), r); 2712 2713 return 0; 2714} 2715 2716static int dsi_vc_send_null(struct dsi_data *dsi, int channel) 2717{ 2718 return dsi_vc_send_long(dsi, channel, MIPI_DSI_NULL_PACKET, NULL, 0, 0); 2719} 2720 2721static int dsi_vc_write_nosync_common(struct dsi_data *dsi, int channel, 2722 u8 *data, int len, 2723 enum dss_dsi_content_type type) 2724{ 2725 int r; 2726 2727 if (len == 0) { 2728 BUG_ON(type == DSS_DSI_CONTENT_DCS); 2729 r = dsi_vc_send_short(dsi, channel, 2730 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0); 2731 } else if (len == 1) { 2732 r = dsi_vc_send_short(dsi, channel, 2733 type == DSS_DSI_CONTENT_GENERIC ? 2734 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM : 2735 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0); 2736 } else if (len == 2) { 2737 r = dsi_vc_send_short(dsi, channel, 2738 type == DSS_DSI_CONTENT_GENERIC ? 2739 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM : 2740 MIPI_DSI_DCS_SHORT_WRITE_PARAM, 2741 data[0] | (data[1] << 8), 0); 2742 } else { 2743 r = dsi_vc_send_long(dsi, channel, 2744 type == DSS_DSI_CONTENT_GENERIC ? 2745 MIPI_DSI_GENERIC_LONG_WRITE : 2746 MIPI_DSI_DCS_LONG_WRITE, data, len, 0); 2747 } 2748 2749 return r; 2750} 2751 2752static int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel, 2753 u8 *data, int len) 2754{ 2755 struct dsi_data *dsi = to_dsi_data(dssdev); 2756 2757 return dsi_vc_write_nosync_common(dsi, channel, data, len, 2758 DSS_DSI_CONTENT_DCS); 2759} 2760 2761static int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel, 2762 u8 *data, int len) 2763{ 2764 struct dsi_data *dsi = to_dsi_data(dssdev); 2765 2766 return dsi_vc_write_nosync_common(dsi, channel, data, len, 2767 DSS_DSI_CONTENT_GENERIC); 2768} 2769 2770static int dsi_vc_write_common(struct omap_dss_device *dssdev, 2771 int channel, u8 *data, int len, 2772 enum dss_dsi_content_type type) 2773{ 2774 struct dsi_data *dsi = to_dsi_data(dssdev); 2775 int r; 2776 2777 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type); 2778 if (r) 2779 goto err; 2780 2781 r = dsi_vc_send_bta_sync(dssdev, channel); 2782 if (r) 2783 goto err; 2784 2785 /* RX_FIFO_NOT_EMPTY */ 2786 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20)) { 2787 DSSERR("rx fifo not empty after write, dumping data:\n"); 2788 dsi_vc_flush_receive_data(dsi, channel); 2789 r = -EIO; 2790 goto err; 2791 } 2792 2793 return 0; 2794err: 2795 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n", 2796 channel, data[0], len); 2797 return r; 2798} 2799 2800static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2801 int len) 2802{ 2803 return dsi_vc_write_common(dssdev, channel, data, len, 2804 DSS_DSI_CONTENT_DCS); 2805} 2806 2807static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data, 2808 int len) 2809{ 2810 return dsi_vc_write_common(dssdev, channel, data, len, 2811 DSS_DSI_CONTENT_GENERIC); 2812} 2813 2814static int dsi_vc_dcs_send_read_request(struct dsi_data *dsi, int channel, 2815 u8 dcs_cmd) 2816{ 2817 int r; 2818 2819 if (dsi->debug_read) 2820 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n", 2821 channel, dcs_cmd); 2822 2823 r = dsi_vc_send_short(dsi, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0); 2824 if (r) { 2825 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)" 2826 " failed\n", channel, dcs_cmd); 2827 return r; 2828 } 2829 2830 return 0; 2831} 2832 2833static int dsi_vc_generic_send_read_request(struct dsi_data *dsi, int channel, 2834 u8 *reqdata, int reqlen) 2835{ 2836 u16 data; 2837 u8 data_type; 2838 int r; 2839 2840 if (dsi->debug_read) 2841 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n", 2842 channel, reqlen); 2843 2844 if (reqlen == 0) { 2845 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; 2846 data = 0; 2847 } else if (reqlen == 1) { 2848 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; 2849 data = reqdata[0]; 2850 } else if (reqlen == 2) { 2851 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; 2852 data = reqdata[0] | (reqdata[1] << 8); 2853 } else { 2854 BUG(); 2855 return -EINVAL; 2856 } 2857 2858 r = dsi_vc_send_short(dsi, channel, data_type, data, 0); 2859 if (r) { 2860 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)" 2861 " failed\n", channel, reqlen); 2862 return r; 2863 } 2864 2865 return 0; 2866} 2867 2868static int dsi_vc_read_rx_fifo(struct dsi_data *dsi, int channel, u8 *buf, 2869 int buflen, enum dss_dsi_content_type type) 2870{ 2871 u32 val; 2872 u8 dt; 2873 int r; 2874 2875 /* RX_FIFO_NOT_EMPTY */ 2876 if (REG_GET(dsi, DSI_VC_CTRL(channel), 20, 20) == 0) { 2877 DSSERR("RX fifo empty when trying to read.\n"); 2878 r = -EIO; 2879 goto err; 2880 } 2881 2882 val = dsi_read_reg(dsi, DSI_VC_SHORT_PACKET_HEADER(channel)); 2883 if (dsi->debug_read) 2884 DSSDBG("\theader: %08x\n", val); 2885 dt = FLD_GET(val, 5, 0); 2886 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) { 2887 u16 err = FLD_GET(val, 23, 8); 2888 dsi_show_rx_ack_with_err(err); 2889 r = -EIO; 2890 goto err; 2891 2892 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2893 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE : 2894 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) { 2895 u8 data = FLD_GET(val, 15, 8); 2896 if (dsi->debug_read) 2897 DSSDBG("\t%s short response, 1 byte: %02x\n", 2898 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2899 "DCS", data); 2900 2901 if (buflen < 1) { 2902 r = -EIO; 2903 goto err; 2904 } 2905 2906 buf[0] = data; 2907 2908 return 1; 2909 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2910 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE : 2911 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) { 2912 u16 data = FLD_GET(val, 23, 8); 2913 if (dsi->debug_read) 2914 DSSDBG("\t%s short response, 2 byte: %04x\n", 2915 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2916 "DCS", data); 2917 2918 if (buflen < 2) { 2919 r = -EIO; 2920 goto err; 2921 } 2922 2923 buf[0] = data & 0xff; 2924 buf[1] = (data >> 8) & 0xff; 2925 2926 return 2; 2927 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ? 2928 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE : 2929 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) { 2930 int w; 2931 int len = FLD_GET(val, 23, 8); 2932 if (dsi->debug_read) 2933 DSSDBG("\t%s long response, len %d\n", 2934 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : 2935 "DCS", len); 2936 2937 if (len > buflen) { 2938 r = -EIO; 2939 goto err; 2940 } 2941 2942 /* two byte checksum ends the packet, not included in len */ 2943 for (w = 0; w < len + 2;) { 2944 int b; 2945 val = dsi_read_reg(dsi, 2946 DSI_VC_SHORT_PACKET_HEADER(channel)); 2947 if (dsi->debug_read) 2948 DSSDBG("\t\t%02x %02x %02x %02x\n", 2949 (val >> 0) & 0xff, 2950 (val >> 8) & 0xff, 2951 (val >> 16) & 0xff, 2952 (val >> 24) & 0xff); 2953 2954 for (b = 0; b < 4; ++b) { 2955 if (w < len) 2956 buf[w] = (val >> (b * 8)) & 0xff; 2957 /* we discard the 2 byte checksum */ 2958 ++w; 2959 } 2960 } 2961 2962 return len; 2963 } else { 2964 DSSERR("\tunknown datatype 0x%02x\n", dt); 2965 r = -EIO; 2966 goto err; 2967 } 2968 2969err: 2970 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel, 2971 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS"); 2972 2973 return r; 2974} 2975 2976static int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd, 2977 u8 *buf, int buflen) 2978{ 2979 struct dsi_data *dsi = to_dsi_data(dssdev); 2980 int r; 2981 2982 r = dsi_vc_dcs_send_read_request(dsi, channel, dcs_cmd); 2983 if (r) 2984 goto err; 2985 2986 r = dsi_vc_send_bta_sync(dssdev, channel); 2987 if (r) 2988 goto err; 2989 2990 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen, 2991 DSS_DSI_CONTENT_DCS); 2992 if (r < 0) 2993 goto err; 2994 2995 if (r != buflen) { 2996 r = -EIO; 2997 goto err; 2998 } 2999 3000 return 0; 3001err: 3002 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd); 3003 return r; 3004} 3005 3006static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel, 3007 u8 *reqdata, int reqlen, u8 *buf, int buflen) 3008{ 3009 struct dsi_data *dsi = to_dsi_data(dssdev); 3010 int r; 3011 3012 r = dsi_vc_generic_send_read_request(dsi, channel, reqdata, reqlen); 3013 if (r) 3014 return r; 3015 3016 r = dsi_vc_send_bta_sync(dssdev, channel); 3017 if (r) 3018 return r; 3019 3020 r = dsi_vc_read_rx_fifo(dsi, channel, buf, buflen, 3021 DSS_DSI_CONTENT_GENERIC); 3022 if (r < 0) 3023 return r; 3024 3025 if (r != buflen) { 3026 r = -EIO; 3027 return r; 3028 } 3029 3030 return 0; 3031} 3032 3033static int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel, 3034 u16 len) 3035{ 3036 struct dsi_data *dsi = to_dsi_data(dssdev); 3037 3038 return dsi_vc_send_short(dsi, channel, 3039 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0); 3040} 3041 3042static int dsi_enter_ulps(struct dsi_data *dsi) 3043{ 3044 DECLARE_COMPLETION_ONSTACK(completion); 3045 int r, i; 3046 unsigned int mask; 3047 3048 DSSDBG("Entering ULPS"); 3049 3050 WARN_ON(!dsi_bus_is_locked(dsi)); 3051 3052 WARN_ON(dsi->ulps_enabled); 3053 3054 if (dsi->ulps_enabled) 3055 return 0; 3056 3057 /* DDR_CLK_ALWAYS_ON */ 3058 if (REG_GET(dsi, DSI_CLK_CTRL, 13, 13)) { 3059 dsi_if_enable(dsi, 0); 3060 REG_FLD_MOD(dsi, DSI_CLK_CTRL, 0, 13, 13); 3061 dsi_if_enable(dsi, 1); 3062 } 3063 3064 dsi_sync_vc(dsi, 0); 3065 dsi_sync_vc(dsi, 1); 3066 dsi_sync_vc(dsi, 2); 3067 dsi_sync_vc(dsi, 3); 3068 3069 dsi_force_tx_stop_mode_io(dsi); 3070 3071 dsi_vc_enable(dsi, 0, false); 3072 dsi_vc_enable(dsi, 1, false); 3073 dsi_vc_enable(dsi, 2, false); 3074 dsi_vc_enable(dsi, 3, false); 3075 3076 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */ 3077 DSSERR("HS busy when enabling ULPS\n"); 3078 return -EIO; 3079 } 3080 3081 if (REG_GET(dsi, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */ 3082 DSSERR("LP busy when enabling ULPS\n"); 3083 return -EIO; 3084 } 3085 3086 r = dsi_register_isr_cio(dsi, dsi_completion_handler, &completion, 3087 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3088 if (r) 3089 return r; 3090 3091 mask = 0; 3092 3093 for (i = 0; i < dsi->num_lanes_supported; ++i) { 3094 if (dsi->lanes[i].function == DSI_LANE_UNUSED) 3095 continue; 3096 mask |= 1 << i; 3097 } 3098 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */ 3099 /* LANEx_ULPS_SIG2 */ 3100 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, mask, 9, 5); 3101 3102 /* flush posted write and wait for SCP interface to finish the write */ 3103 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2); 3104 3105 if (wait_for_completion_timeout(&completion, 3106 msecs_to_jiffies(1000)) == 0) { 3107 DSSERR("ULPS enable timeout\n"); 3108 r = -EIO; 3109 goto err; 3110 } 3111 3112 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion, 3113 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3114 3115 /* Reset LANEx_ULPS_SIG2 */ 3116 REG_FLD_MOD(dsi, DSI_COMPLEXIO_CFG2, 0, 9, 5); 3117 3118 /* flush posted write and wait for SCP interface to finish the write */ 3119 dsi_read_reg(dsi, DSI_COMPLEXIO_CFG2); 3120 3121 dsi_cio_power(dsi, DSI_COMPLEXIO_POWER_ULPS); 3122 3123 dsi_if_enable(dsi, false); 3124 3125 dsi->ulps_enabled = true; 3126 3127 return 0; 3128 3129err: 3130 dsi_unregister_isr_cio(dsi, dsi_completion_handler, &completion, 3131 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0); 3132 return r; 3133} 3134 3135static void dsi_set_lp_rx_timeout(struct dsi_data *dsi, unsigned int ticks, 3136 bool x4, bool x16) 3137{ 3138 unsigned long fck; 3139 unsigned long total_ticks; 3140 u32 r; 3141 3142 BUG_ON(ticks > 0x1fff); 3143 3144 /* ticks in DSI_FCK */ 3145 fck = dsi_fclk_rate(dsi); 3146 3147 r = dsi_read_reg(dsi, DSI_TIMING2); 3148 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */ 3149 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */ 3150 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */ 3151 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */ 3152 dsi_write_reg(dsi, DSI_TIMING2, r); 3153 3154 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3155 3156 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3157 total_ticks, 3158 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3159 (total_ticks * 1000) / (fck / 1000 / 1000)); 3160} 3161 3162static void dsi_set_ta_timeout(struct dsi_data *dsi, unsigned int ticks, 3163 bool x8, bool x16) 3164{ 3165 unsigned long fck; 3166 unsigned long total_ticks; 3167 u32 r; 3168 3169 BUG_ON(ticks > 0x1fff); 3170 3171 /* ticks in DSI_FCK */ 3172 fck = dsi_fclk_rate(dsi); 3173 3174 r = dsi_read_reg(dsi, DSI_TIMING1); 3175 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */ 3176 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */ 3177 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */ 3178 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */ 3179 dsi_write_reg(dsi, DSI_TIMING1, r); 3180 3181 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1); 3182 3183 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n", 3184 total_ticks, 3185 ticks, x8 ? " x8" : "", x16 ? " x16" : "", 3186 (total_ticks * 1000) / (fck / 1000 / 1000)); 3187} 3188 3189static void dsi_set_stop_state_counter(struct dsi_data *dsi, unsigned int ticks, 3190 bool x4, bool x16) 3191{ 3192 unsigned long fck; 3193 unsigned long total_ticks; 3194 u32 r; 3195 3196 BUG_ON(ticks > 0x1fff); 3197 3198 /* ticks in DSI_FCK */ 3199 fck = dsi_fclk_rate(dsi); 3200 3201 r = dsi_read_reg(dsi, DSI_TIMING1); 3202 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */ 3203 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */ 3204 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */ 3205 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */ 3206 dsi_write_reg(dsi, DSI_TIMING1, r); 3207 3208 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3209 3210 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n", 3211 total_ticks, 3212 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3213 (total_ticks * 1000) / (fck / 1000 / 1000)); 3214} 3215 3216static void dsi_set_hs_tx_timeout(struct dsi_data *dsi, unsigned int ticks, 3217 bool x4, bool x16) 3218{ 3219 unsigned long fck; 3220 unsigned long total_ticks; 3221 u32 r; 3222 3223 BUG_ON(ticks > 0x1fff); 3224 3225 /* ticks in TxByteClkHS */ 3226 fck = dsi_get_txbyteclkhs(dsi); 3227 3228 r = dsi_read_reg(dsi, DSI_TIMING2); 3229 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */ 3230 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */ 3231 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */ 3232 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */ 3233 dsi_write_reg(dsi, DSI_TIMING2, r); 3234 3235 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1); 3236 3237 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n", 3238 total_ticks, 3239 ticks, x4 ? " x4" : "", x16 ? " x16" : "", 3240 (total_ticks * 1000) / (fck / 1000 / 1000)); 3241} 3242 3243static void dsi_config_vp_num_line_buffers(struct dsi_data *dsi) 3244{ 3245 int num_line_buffers; 3246 3247 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3248 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3249 const struct videomode *vm = &dsi->vm; 3250 /* 3251 * Don't use line buffers if width is greater than the video 3252 * port's line buffer size 3253 */ 3254 if (dsi->line_buffer_size <= vm->hactive * bpp / 8) 3255 num_line_buffers = 0; 3256 else 3257 num_line_buffers = 2; 3258 } else { 3259 /* Use maximum number of line buffers in command mode */ 3260 num_line_buffers = 2; 3261 } 3262 3263 /* LINE_BUFFER */ 3264 REG_FLD_MOD(dsi, DSI_CTRL, num_line_buffers, 13, 12); 3265} 3266 3267static void dsi_config_vp_sync_events(struct dsi_data *dsi) 3268{ 3269 bool sync_end; 3270 u32 r; 3271 3272 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE) 3273 sync_end = true; 3274 else 3275 sync_end = false; 3276 3277 r = dsi_read_reg(dsi, DSI_CTRL); 3278 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */ 3279 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */ 3280 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */ 3281 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */ 3282 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */ 3283 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */ 3284 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */ 3285 dsi_write_reg(dsi, DSI_CTRL, r); 3286} 3287 3288static void dsi_config_blanking_modes(struct dsi_data *dsi) 3289{ 3290 int blanking_mode = dsi->vm_timings.blanking_mode; 3291 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode; 3292 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode; 3293 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode; 3294 u32 r; 3295 3296 /* 3297 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods 3298 * 1 = Long blanking packets are sent in corresponding blanking periods 3299 */ 3300 r = dsi_read_reg(dsi, DSI_CTRL); 3301 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */ 3302 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */ 3303 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */ 3304 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */ 3305 dsi_write_reg(dsi, DSI_CTRL, r); 3306} 3307 3308/* 3309 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3 3310 * results in maximum transition time for data and clock lanes to enter and 3311 * exit HS mode. Hence, this is the scenario where the least amount of command 3312 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS 3313 * clock cycles that can be used to interleave command mode data in HS so that 3314 * all scenarios are satisfied. 3315 */ 3316static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs, 3317 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post) 3318{ 3319 int transition; 3320 3321 /* 3322 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition 3323 * time of data lanes only, if it isn't set, we need to consider HS 3324 * transition time of both data and clock lanes. HS transition time 3325 * of Scenario 3 is considered. 3326 */ 3327 if (ddr_alwon) { 3328 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1; 3329 } else { 3330 int trans1, trans2; 3331 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1; 3332 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre + 3333 enter_hs + 1; 3334 transition = max(trans1, trans2); 3335 } 3336 3337 return blank > transition ? blank - transition : 0; 3338} 3339 3340/* 3341 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1 3342 * results in maximum transition time for data lanes to enter and exit LP mode. 3343 * Hence, this is the scenario where the least amount of command mode data can 3344 * be interleaved. We program the minimum amount of bytes that can be 3345 * interleaved in LP so that all scenarios are satisfied. 3346 */ 3347static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs, 3348 int lp_clk_div, int tdsi_fclk) 3349{ 3350 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */ 3351 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */ 3352 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */ 3353 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */ 3354 int lp_inter; /* cmd mode data that can be interleaved, in bytes */ 3355 3356 /* maximum LP transition time according to Scenario 1 */ 3357 trans_lp = exit_hs + max(enter_hs, 2) + 1; 3358 3359 /* CLKIN4DDR = 16 * TXBYTECLKHS */ 3360 tlp_avail = thsbyte_clk * (blank - trans_lp); 3361 3362 ttxclkesc = tdsi_fclk * lp_clk_div; 3363 3364 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc - 3365 26) / 16; 3366 3367 return max(lp_inter, 0); 3368} 3369 3370static void dsi_config_cmd_mode_interleaving(struct dsi_data *dsi) 3371{ 3372 int blanking_mode; 3373 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode; 3374 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div; 3375 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat; 3376 int tclk_trail, ths_exit, exiths_clk; 3377 bool ddr_alwon; 3378 const struct videomode *vm = &dsi->vm; 3379 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3380 int ndl = dsi->num_lanes_used - 1; 3381 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.mX[HSDIV_DSI] + 1; 3382 int hsa_interleave_hs = 0, hsa_interleave_lp = 0; 3383 int hfp_interleave_hs = 0, hfp_interleave_lp = 0; 3384 int hbp_interleave_hs = 0, hbp_interleave_lp = 0; 3385 int bl_interleave_hs = 0, bl_interleave_lp = 0; 3386 u32 r; 3387 3388 r = dsi_read_reg(dsi, DSI_CTRL); 3389 blanking_mode = FLD_GET(r, 20, 20); 3390 hfp_blanking_mode = FLD_GET(r, 21, 21); 3391 hbp_blanking_mode = FLD_GET(r, 22, 22); 3392 hsa_blanking_mode = FLD_GET(r, 23, 23); 3393 3394 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 3395 hbp = FLD_GET(r, 11, 0); 3396 hfp = FLD_GET(r, 23, 12); 3397 hsa = FLD_GET(r, 31, 24); 3398 3399 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 3400 ddr_clk_post = FLD_GET(r, 7, 0); 3401 ddr_clk_pre = FLD_GET(r, 15, 8); 3402 3403 r = dsi_read_reg(dsi, DSI_VM_TIMING7); 3404 exit_hs_mode_lat = FLD_GET(r, 15, 0); 3405 enter_hs_mode_lat = FLD_GET(r, 31, 16); 3406 3407 r = dsi_read_reg(dsi, DSI_CLK_CTRL); 3408 lp_clk_div = FLD_GET(r, 12, 0); 3409 ddr_alwon = FLD_GET(r, 13, 13); 3410 3411 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 3412 ths_exit = FLD_GET(r, 7, 0); 3413 3414 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 3415 tclk_trail = FLD_GET(r, 15, 8); 3416 3417 exiths_clk = ths_exit + tclk_trail; 3418 3419 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3420 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl); 3421 3422 if (!hsa_blanking_mode) { 3423 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon, 3424 enter_hs_mode_lat, exit_hs_mode_lat, 3425 exiths_clk, ddr_clk_pre, ddr_clk_post); 3426 hsa_interleave_lp = dsi_compute_interleave_lp(hsa, 3427 enter_hs_mode_lat, exit_hs_mode_lat, 3428 lp_clk_div, dsi_fclk_hsdiv); 3429 } 3430 3431 if (!hfp_blanking_mode) { 3432 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon, 3433 enter_hs_mode_lat, exit_hs_mode_lat, 3434 exiths_clk, ddr_clk_pre, ddr_clk_post); 3435 hfp_interleave_lp = dsi_compute_interleave_lp(hfp, 3436 enter_hs_mode_lat, exit_hs_mode_lat, 3437 lp_clk_div, dsi_fclk_hsdiv); 3438 } 3439 3440 if (!hbp_blanking_mode) { 3441 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon, 3442 enter_hs_mode_lat, exit_hs_mode_lat, 3443 exiths_clk, ddr_clk_pre, ddr_clk_post); 3444 3445 hbp_interleave_lp = dsi_compute_interleave_lp(hbp, 3446 enter_hs_mode_lat, exit_hs_mode_lat, 3447 lp_clk_div, dsi_fclk_hsdiv); 3448 } 3449 3450 if (!blanking_mode) { 3451 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon, 3452 enter_hs_mode_lat, exit_hs_mode_lat, 3453 exiths_clk, ddr_clk_pre, ddr_clk_post); 3454 3455 bl_interleave_lp = dsi_compute_interleave_lp(bllp, 3456 enter_hs_mode_lat, exit_hs_mode_lat, 3457 lp_clk_div, dsi_fclk_hsdiv); 3458 } 3459 3460 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3461 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs, 3462 bl_interleave_hs); 3463 3464 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n", 3465 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp, 3466 bl_interleave_lp); 3467 3468 r = dsi_read_reg(dsi, DSI_VM_TIMING4); 3469 r = FLD_MOD(r, hsa_interleave_hs, 23, 16); 3470 r = FLD_MOD(r, hfp_interleave_hs, 15, 8); 3471 r = FLD_MOD(r, hbp_interleave_hs, 7, 0); 3472 dsi_write_reg(dsi, DSI_VM_TIMING4, r); 3473 3474 r = dsi_read_reg(dsi, DSI_VM_TIMING5); 3475 r = FLD_MOD(r, hsa_interleave_lp, 23, 16); 3476 r = FLD_MOD(r, hfp_interleave_lp, 15, 8); 3477 r = FLD_MOD(r, hbp_interleave_lp, 7, 0); 3478 dsi_write_reg(dsi, DSI_VM_TIMING5, r); 3479 3480 r = dsi_read_reg(dsi, DSI_VM_TIMING6); 3481 r = FLD_MOD(r, bl_interleave_hs, 31, 15); 3482 r = FLD_MOD(r, bl_interleave_lp, 16, 0); 3483 dsi_write_reg(dsi, DSI_VM_TIMING6, r); 3484} 3485 3486static int dsi_proto_config(struct dsi_data *dsi) 3487{ 3488 u32 r; 3489 int buswidth = 0; 3490 3491 dsi_config_tx_fifo(dsi, DSI_FIFO_SIZE_32, 3492 DSI_FIFO_SIZE_32, 3493 DSI_FIFO_SIZE_32, 3494 DSI_FIFO_SIZE_32); 3495 3496 dsi_config_rx_fifo(dsi, DSI_FIFO_SIZE_32, 3497 DSI_FIFO_SIZE_32, 3498 DSI_FIFO_SIZE_32, 3499 DSI_FIFO_SIZE_32); 3500 3501 /* XXX what values for the timeouts? */ 3502 dsi_set_stop_state_counter(dsi, 0x1000, false, false); 3503 dsi_set_ta_timeout(dsi, 0x1fff, true, true); 3504 dsi_set_lp_rx_timeout(dsi, 0x1fff, true, true); 3505 dsi_set_hs_tx_timeout(dsi, 0x1fff, true, true); 3506 3507 switch (dsi_get_pixel_size(dsi->pix_fmt)) { 3508 case 16: 3509 buswidth = 0; 3510 break; 3511 case 18: 3512 buswidth = 1; 3513 break; 3514 case 24: 3515 buswidth = 2; 3516 break; 3517 default: 3518 BUG(); 3519 return -EINVAL; 3520 } 3521 3522 r = dsi_read_reg(dsi, DSI_CTRL); 3523 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */ 3524 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */ 3525 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */ 3526 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/ 3527 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */ 3528 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */ 3529 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */ 3530 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */ 3531 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) { 3532 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */ 3533 /* DCS_CMD_CODE, 1=start, 0=continue */ 3534 r = FLD_MOD(r, 0, 25, 25); 3535 } 3536 3537 dsi_write_reg(dsi, DSI_CTRL, r); 3538 3539 dsi_config_vp_num_line_buffers(dsi); 3540 3541 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3542 dsi_config_vp_sync_events(dsi); 3543 dsi_config_blanking_modes(dsi); 3544 dsi_config_cmd_mode_interleaving(dsi); 3545 } 3546 3547 dsi_vc_initial_config(dsi, 0); 3548 dsi_vc_initial_config(dsi, 1); 3549 dsi_vc_initial_config(dsi, 2); 3550 dsi_vc_initial_config(dsi, 3); 3551 3552 return 0; 3553} 3554 3555static void dsi_proto_timings(struct dsi_data *dsi) 3556{ 3557 unsigned int tlpx, tclk_zero, tclk_prepare; 3558 unsigned int tclk_pre, tclk_post; 3559 unsigned int ths_prepare, ths_prepare_ths_zero, ths_zero; 3560 unsigned int ths_trail, ths_exit; 3561 unsigned int ddr_clk_pre, ddr_clk_post; 3562 unsigned int enter_hs_mode_lat, exit_hs_mode_lat; 3563 unsigned int ths_eot; 3564 int ndl = dsi->num_lanes_used - 1; 3565 u32 r; 3566 3567 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG0); 3568 ths_prepare = FLD_GET(r, 31, 24); 3569 ths_prepare_ths_zero = FLD_GET(r, 23, 16); 3570 ths_zero = ths_prepare_ths_zero - ths_prepare; 3571 ths_trail = FLD_GET(r, 15, 8); 3572 ths_exit = FLD_GET(r, 7, 0); 3573 3574 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG1); 3575 tlpx = FLD_GET(r, 20, 16) * 2; 3576 tclk_zero = FLD_GET(r, 7, 0); 3577 3578 r = dsi_read_reg(dsi, DSI_DSIPHY_CFG2); 3579 tclk_prepare = FLD_GET(r, 7, 0); 3580 3581 /* min 8*UI */ 3582 tclk_pre = 20; 3583 /* min 60ns + 52*UI */ 3584 tclk_post = ns2ddr(dsi, 60) + 26; 3585 3586 ths_eot = DIV_ROUND_UP(4, ndl); 3587 3588 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare, 3589 4); 3590 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot; 3591 3592 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255); 3593 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255); 3594 3595 r = dsi_read_reg(dsi, DSI_CLK_TIMING); 3596 r = FLD_MOD(r, ddr_clk_pre, 15, 8); 3597 r = FLD_MOD(r, ddr_clk_post, 7, 0); 3598 dsi_write_reg(dsi, DSI_CLK_TIMING, r); 3599 3600 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n", 3601 ddr_clk_pre, 3602 ddr_clk_post); 3603 3604 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) + 3605 DIV_ROUND_UP(ths_prepare, 4) + 3606 DIV_ROUND_UP(ths_zero + 3, 4); 3607 3608 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot; 3609 3610 r = FLD_VAL(enter_hs_mode_lat, 31, 16) | 3611 FLD_VAL(exit_hs_mode_lat, 15, 0); 3612 dsi_write_reg(dsi, DSI_VM_TIMING7, r); 3613 3614 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n", 3615 enter_hs_mode_lat, exit_hs_mode_lat); 3616 3617 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3618 /* TODO: Implement a video mode check_timings function */ 3619 int hsa = dsi->vm_timings.hsa; 3620 int hfp = dsi->vm_timings.hfp; 3621 int hbp = dsi->vm_timings.hbp; 3622 int vsa = dsi->vm_timings.vsa; 3623 int vfp = dsi->vm_timings.vfp; 3624 int vbp = dsi->vm_timings.vbp; 3625 int window_sync = dsi->vm_timings.window_sync; 3626 bool hsync_end; 3627 const struct videomode *vm = &dsi->vm; 3628 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3629 int tl, t_he, width_bytes; 3630 3631 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE; 3632 t_he = hsync_end ? 3633 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0; 3634 3635 width_bytes = DIV_ROUND_UP(vm->hactive * bpp, 8); 3636 3637 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */ 3638 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp + 3639 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp; 3640 3641 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp, 3642 hfp, hsync_end ? hsa : 0, tl); 3643 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp, 3644 vsa, vm->vactive); 3645 3646 r = dsi_read_reg(dsi, DSI_VM_TIMING1); 3647 r = FLD_MOD(r, hbp, 11, 0); /* HBP */ 3648 r = FLD_MOD(r, hfp, 23, 12); /* HFP */ 3649 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */ 3650 dsi_write_reg(dsi, DSI_VM_TIMING1, r); 3651 3652 r = dsi_read_reg(dsi, DSI_VM_TIMING2); 3653 r = FLD_MOD(r, vbp, 7, 0); /* VBP */ 3654 r = FLD_MOD(r, vfp, 15, 8); /* VFP */ 3655 r = FLD_MOD(r, vsa, 23, 16); /* VSA */ 3656 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */ 3657 dsi_write_reg(dsi, DSI_VM_TIMING2, r); 3658 3659 r = dsi_read_reg(dsi, DSI_VM_TIMING3); 3660 r = FLD_MOD(r, vm->vactive, 14, 0); /* VACT */ 3661 r = FLD_MOD(r, tl, 31, 16); /* TL */ 3662 dsi_write_reg(dsi, DSI_VM_TIMING3, r); 3663 } 3664} 3665 3666static int dsi_configure_pins(struct omap_dss_device *dssdev, 3667 const struct omap_dsi_pin_config *pin_cfg) 3668{ 3669 struct dsi_data *dsi = to_dsi_data(dssdev); 3670 int num_pins; 3671 const int *pins; 3672 struct dsi_lane_config lanes[DSI_MAX_NR_LANES]; 3673 int num_lanes; 3674 int i; 3675 3676 static const enum dsi_lane_function functions[] = { 3677 DSI_LANE_CLK, 3678 DSI_LANE_DATA1, 3679 DSI_LANE_DATA2, 3680 DSI_LANE_DATA3, 3681 DSI_LANE_DATA4, 3682 }; 3683 3684 num_pins = pin_cfg->num_pins; 3685 pins = pin_cfg->pins; 3686 3687 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2 3688 || num_pins % 2 != 0) 3689 return -EINVAL; 3690 3691 for (i = 0; i < DSI_MAX_NR_LANES; ++i) 3692 lanes[i].function = DSI_LANE_UNUSED; 3693 3694 num_lanes = 0; 3695 3696 for (i = 0; i < num_pins; i += 2) { 3697 u8 lane, pol; 3698 int dx, dy; 3699 3700 dx = pins[i]; 3701 dy = pins[i + 1]; 3702 3703 if (dx < 0 || dx >= dsi->num_lanes_supported * 2) 3704 return -EINVAL; 3705 3706 if (dy < 0 || dy >= dsi->num_lanes_supported * 2) 3707 return -EINVAL; 3708 3709 if (dx & 1) { 3710 if (dy != dx - 1) 3711 return -EINVAL; 3712 pol = 1; 3713 } else { 3714 if (dy != dx + 1) 3715 return -EINVAL; 3716 pol = 0; 3717 } 3718 3719 lane = dx / 2; 3720 3721 lanes[lane].function = functions[i / 2]; 3722 lanes[lane].polarity = pol; 3723 num_lanes++; 3724 } 3725 3726 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes)); 3727 dsi->num_lanes_used = num_lanes; 3728 3729 return 0; 3730} 3731 3732static int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel) 3733{ 3734 struct dsi_data *dsi = to_dsi_data(dssdev); 3735 int bpp = dsi_get_pixel_size(dsi->pix_fmt); 3736 u8 data_type; 3737 u16 word_count; 3738 int r; 3739 3740 r = dsi_display_init_dispc(dsi); 3741 if (r) 3742 return r; 3743 3744 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3745 switch (dsi->pix_fmt) { 3746 case OMAP_DSS_DSI_FMT_RGB888: 3747 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 3748 break; 3749 case OMAP_DSS_DSI_FMT_RGB666: 3750 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 3751 break; 3752 case OMAP_DSS_DSI_FMT_RGB666_PACKED: 3753 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 3754 break; 3755 case OMAP_DSS_DSI_FMT_RGB565: 3756 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 3757 break; 3758 default: 3759 r = -EINVAL; 3760 goto err_pix_fmt; 3761 } 3762 3763 dsi_if_enable(dsi, false); 3764 dsi_vc_enable(dsi, channel, false); 3765 3766 /* MODE, 1 = video mode */ 3767 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 1, 4, 4); 3768 3769 word_count = DIV_ROUND_UP(dsi->vm.hactive * bpp, 8); 3770 3771 dsi_vc_write_long_header(dsi, channel, data_type, 3772 word_count, 0); 3773 3774 dsi_vc_enable(dsi, channel, true); 3775 dsi_if_enable(dsi, true); 3776 } 3777 3778 r = dss_mgr_enable(&dsi->output); 3779 if (r) 3780 goto err_mgr_enable; 3781 3782 return 0; 3783 3784err_mgr_enable: 3785 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3786 dsi_if_enable(dsi, false); 3787 dsi_vc_enable(dsi, channel, false); 3788 } 3789err_pix_fmt: 3790 dsi_display_uninit_dispc(dsi); 3791 return r; 3792} 3793 3794static void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel) 3795{ 3796 struct dsi_data *dsi = to_dsi_data(dssdev); 3797 3798 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) { 3799 dsi_if_enable(dsi, false); 3800 dsi_vc_enable(dsi, channel, false); 3801 3802 /* MODE, 0 = command mode */ 3803 REG_FLD_MOD(dsi, DSI_VC_CTRL(channel), 0, 4, 4); 3804 3805 dsi_vc_enable(dsi, channel, true); 3806 dsi_if_enable(dsi, true); 3807 } 3808 3809 dss_mgr_disable(&dsi->output); 3810 3811 dsi_display_uninit_dispc(dsi); 3812} 3813 3814static void dsi_update_screen_dispc(struct dsi_data *dsi) 3815{ 3816 unsigned int bytespp; 3817 unsigned int bytespl; 3818 unsigned int bytespf; 3819 unsigned int total_len; 3820 unsigned int packet_payload; 3821 unsigned int packet_len; 3822 u32 l; 3823 int r; 3824 const unsigned channel = dsi->update_channel; 3825 const unsigned int line_buf_size = dsi->line_buffer_size; 3826 u16 w = dsi->vm.hactive; 3827 u16 h = dsi->vm.vactive; 3828 3829 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h); 3830 3831 dsi_vc_config_source(dsi, channel, DSI_VC_SOURCE_VP); 3832 3833 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8; 3834 bytespl = w * bytespp; 3835 bytespf = bytespl * h; 3836 3837 /* NOTE: packet_payload has to be equal to N * bytespl, where N is 3838 * number of lines in a packet. See errata about VP_CLK_RATIO */ 3839 3840 if (bytespf < line_buf_size) 3841 packet_payload = bytespf; 3842 else 3843 packet_payload = (line_buf_size) / bytespl * bytespl; 3844 3845 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */ 3846 total_len = (bytespf / packet_payload) * packet_len; 3847 3848 if (bytespf % packet_payload) 3849 total_len += (bytespf % packet_payload) + 1; 3850 3851 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */ 3852 dsi_write_reg(dsi, DSI_VC_TE(channel), l); 3853 3854 dsi_vc_write_long_header(dsi, channel, MIPI_DSI_DCS_LONG_WRITE, 3855 packet_len, 0); 3856 3857 if (dsi->te_enabled) 3858 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */ 3859 else 3860 l = FLD_MOD(l, 1, 31, 31); /* TE_START */ 3861 dsi_write_reg(dsi, DSI_VC_TE(channel), l); 3862 3863 /* We put SIDLEMODE to no-idle for the duration of the transfer, 3864 * because DSS interrupts are not capable of waking up the CPU and the 3865 * framedone interrupt could be delayed for quite a long time. I think 3866 * the same goes for any DSS interrupts, but for some reason I have not 3867 * seen the problem anywhere else than here. 3868 */ 3869 dispc_disable_sidle(dsi->dss->dispc); 3870 3871 dsi_perf_mark_start(dsi); 3872 3873 r = schedule_delayed_work(&dsi->framedone_timeout_work, 3874 msecs_to_jiffies(250)); 3875 BUG_ON(r == 0); 3876 3877 dss_mgr_start_update(&dsi->output); 3878 3879 if (dsi->te_enabled) { 3880 /* disable LP_RX_TO, so that we can receive TE. Time to wait 3881 * for TE is longer than the timer allows */ 3882 REG_FLD_MOD(dsi, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */ 3883 3884 dsi_vc_send_bta(dsi, channel); 3885 3886#ifdef DSI_CATCH_MISSING_TE 3887 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250)); 3888#endif 3889 } 3890} 3891 3892#ifdef DSI_CATCH_MISSING_TE 3893static void dsi_te_timeout(struct timer_list *unused) 3894{ 3895 DSSERR("TE not received for 250ms!\n"); 3896} 3897#endif 3898 3899static void dsi_handle_framedone(struct dsi_data *dsi, int error) 3900{ 3901 /* SIDLEMODE back to smart-idle */ 3902 dispc_enable_sidle(dsi->dss->dispc); 3903 3904 if (dsi->te_enabled) { 3905 /* enable LP_RX_TO again after the TE */ 3906 REG_FLD_MOD(dsi, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */ 3907 } 3908 3909 dsi->framedone_callback(error, dsi->framedone_data); 3910 3911 if (!error) 3912 dsi_perf_show(dsi, "DISPC"); 3913} 3914 3915static void dsi_framedone_timeout_work_callback(struct work_struct *work) 3916{ 3917 struct dsi_data *dsi = container_of(work, struct dsi_data, 3918 framedone_timeout_work.work); 3919 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after 3920 * 250ms which would conflict with this timeout work. What should be 3921 * done is first cancel the transfer on the HW, and then cancel the 3922 * possibly scheduled framedone work. However, cancelling the transfer 3923 * on the HW is buggy, and would probably require resetting the whole 3924 * DSI */ 3925 3926 DSSERR("Framedone not received for 250ms!\n"); 3927 3928 dsi_handle_framedone(dsi, -ETIMEDOUT); 3929} 3930 3931static void dsi_framedone_irq_callback(void *data) 3932{ 3933 struct dsi_data *dsi = data; 3934 3935 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and 3936 * turns itself off. However, DSI still has the pixels in its buffers, 3937 * and is sending the data. 3938 */ 3939 3940 cancel_delayed_work(&dsi->framedone_timeout_work); 3941 3942 dsi_handle_framedone(dsi, 0); 3943} 3944 3945static int dsi_update(struct omap_dss_device *dssdev, int channel, 3946 void (*callback)(int, void *), void *data) 3947{ 3948 struct dsi_data *dsi = to_dsi_data(dssdev); 3949 u16 dw, dh; 3950 3951 dsi_perf_mark_setup(dsi); 3952 3953 dsi->update_channel = channel; 3954 3955 dsi->framedone_callback = callback; 3956 dsi->framedone_data = data; 3957 3958 dw = dsi->vm.hactive; 3959 dh = dsi->vm.vactive; 3960 3961#ifdef DSI_PERF_MEASURE 3962 dsi->update_bytes = dw * dh * 3963 dsi_get_pixel_size(dsi->pix_fmt) / 8; 3964#endif 3965 dsi_update_screen_dispc(dsi); 3966 3967 return 0; 3968} 3969 3970/* Display funcs */ 3971 3972static int dsi_configure_dispc_clocks(struct dsi_data *dsi) 3973{ 3974 struct dispc_clock_info dispc_cinfo; 3975 int r; 3976 unsigned long fck; 3977 3978 fck = dsi_get_pll_hsdiv_dispc_rate(dsi); 3979 3980 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div; 3981 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div; 3982 3983 r = dispc_calc_clock_rates(dsi->dss->dispc, fck, &dispc_cinfo); 3984 if (r) { 3985 DSSERR("Failed to calc dispc clocks\n"); 3986 return r; 3987 } 3988 3989 dsi->mgr_config.clock_info = dispc_cinfo; 3990 3991 return 0; 3992} 3993 3994static int dsi_display_init_dispc(struct dsi_data *dsi) 3995{ 3996 enum omap_channel channel = dsi->output.dispc_channel; 3997 int r; 3998 3999 dss_select_lcd_clk_source(dsi->dss, channel, dsi->module_id == 0 ? 4000 DSS_CLK_SRC_PLL1_1 : 4001 DSS_CLK_SRC_PLL2_1); 4002 4003 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) { 4004 r = dss_mgr_register_framedone_handler(&dsi->output, 4005 dsi_framedone_irq_callback, dsi); 4006 if (r) { 4007 DSSERR("can't register FRAMEDONE handler\n"); 4008 goto err; 4009 } 4010 4011 dsi->mgr_config.stallmode = true; 4012 dsi->mgr_config.fifohandcheck = true; 4013 } else { 4014 dsi->mgr_config.stallmode = false; 4015 dsi->mgr_config.fifohandcheck = false; 4016 } 4017 4018 r = dsi_configure_dispc_clocks(dsi); 4019 if (r) 4020 goto err1; 4021 4022 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS; 4023 dsi->mgr_config.video_port_width = 4024 dsi_get_pixel_size(dsi->pix_fmt); 4025 dsi->mgr_config.lcden_sig_polarity = 0; 4026 4027 dss_mgr_set_lcd_config(&dsi->output, &dsi->mgr_config); 4028 4029 return 0; 4030err1: 4031 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4032 dss_mgr_unregister_framedone_handler(&dsi->output, 4033 dsi_framedone_irq_callback, dsi); 4034err: 4035 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); 4036 return r; 4037} 4038 4039static void dsi_display_uninit_dispc(struct dsi_data *dsi) 4040{ 4041 enum omap_channel channel = dsi->output.dispc_channel; 4042 4043 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) 4044 dss_mgr_unregister_framedone_handler(&dsi->output, 4045 dsi_framedone_irq_callback, dsi); 4046 4047 dss_select_lcd_clk_source(dsi->dss, channel, DSS_CLK_SRC_FCK); 4048} 4049 4050static int dsi_configure_dsi_clocks(struct dsi_data *dsi) 4051{ 4052 struct dss_pll_clock_info cinfo; 4053 int r; 4054 4055 cinfo = dsi->user_dsi_cinfo; 4056 4057 r = dss_pll_set_config(&dsi->pll, &cinfo); 4058 if (r) { 4059 DSSERR("Failed to set dsi clocks\n"); 4060 return r; 4061 } 4062 4063 return 0; 4064} 4065 4066static int dsi_display_init_dsi(struct dsi_data *dsi) 4067{ 4068 int r; 4069 4070 r = dss_pll_enable(&dsi->pll); 4071 if (r) 4072 return r; 4073 4074 r = dsi_configure_dsi_clocks(dsi); 4075 if (r) 4076 goto err0; 4077 4078 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, 4079 dsi->module_id == 0 ? 4080 DSS_CLK_SRC_PLL1_2 : DSS_CLK_SRC_PLL2_2); 4081 4082 DSSDBG("PLL OK\n"); 4083 4084 if (!dsi->vdds_dsi_enabled) { 4085 r = regulator_enable(dsi->vdds_dsi_reg); 4086 if (r) 4087 goto err1; 4088 4089 dsi->vdds_dsi_enabled = true; 4090 } 4091 4092 r = dsi_cio_init(dsi); 4093 if (r) 4094 goto err2; 4095 4096 _dsi_print_reset_status(dsi); 4097 4098 dsi_proto_timings(dsi); 4099 dsi_set_lp_clk_divisor(dsi); 4100 4101 if (1) 4102 _dsi_print_reset_status(dsi); 4103 4104 r = dsi_proto_config(dsi); 4105 if (r) 4106 goto err3; 4107 4108 /* enable interface */ 4109 dsi_vc_enable(dsi, 0, 1); 4110 dsi_vc_enable(dsi, 1, 1); 4111 dsi_vc_enable(dsi, 2, 1); 4112 dsi_vc_enable(dsi, 3, 1); 4113 dsi_if_enable(dsi, 1); 4114 dsi_force_tx_stop_mode_io(dsi); 4115 4116 return 0; 4117err3: 4118 dsi_cio_uninit(dsi); 4119err2: 4120 regulator_disable(dsi->vdds_dsi_reg); 4121 dsi->vdds_dsi_enabled = false; 4122err1: 4123 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 4124err0: 4125 dss_pll_disable(&dsi->pll); 4126 4127 return r; 4128} 4129 4130static void dsi_display_uninit_dsi(struct dsi_data *dsi, bool disconnect_lanes, 4131 bool enter_ulps) 4132{ 4133 if (enter_ulps && !dsi->ulps_enabled) 4134 dsi_enter_ulps(dsi); 4135 4136 /* disable interface */ 4137 dsi_if_enable(dsi, 0); 4138 dsi_vc_enable(dsi, 0, 0); 4139 dsi_vc_enable(dsi, 1, 0); 4140 dsi_vc_enable(dsi, 2, 0); 4141 dsi_vc_enable(dsi, 3, 0); 4142 4143 dss_select_dsi_clk_source(dsi->dss, dsi->module_id, DSS_CLK_SRC_FCK); 4144 dsi_cio_uninit(dsi); 4145 dss_pll_disable(&dsi->pll); 4146 4147 if (disconnect_lanes) { 4148 regulator_disable(dsi->vdds_dsi_reg); 4149 dsi->vdds_dsi_enabled = false; 4150 } 4151} 4152 4153static void dsi_display_enable(struct omap_dss_device *dssdev) 4154{ 4155 struct dsi_data *dsi = to_dsi_data(dssdev); 4156 int r; 4157 4158 DSSDBG("dsi_display_enable\n"); 4159 4160 WARN_ON(!dsi_bus_is_locked(dsi)); 4161 4162 mutex_lock(&dsi->lock); 4163 4164 r = dsi_runtime_get(dsi); 4165 if (r) 4166 goto err_get_dsi; 4167 4168 _dsi_initialize_irq(dsi); 4169 4170 r = dsi_display_init_dsi(dsi); 4171 if (r) 4172 goto err_init_dsi; 4173 4174 mutex_unlock(&dsi->lock); 4175 4176 return; 4177 4178err_init_dsi: 4179 dsi_runtime_put(dsi); 4180err_get_dsi: 4181 mutex_unlock(&dsi->lock); 4182 DSSDBG("dsi_display_enable FAILED\n"); 4183} 4184 4185static void dsi_display_disable(struct omap_dss_device *dssdev, 4186 bool disconnect_lanes, bool enter_ulps) 4187{ 4188 struct dsi_data *dsi = to_dsi_data(dssdev); 4189 4190 DSSDBG("dsi_display_disable\n"); 4191 4192 WARN_ON(!dsi_bus_is_locked(dsi)); 4193 4194 mutex_lock(&dsi->lock); 4195 4196 dsi_sync_vc(dsi, 0); 4197 dsi_sync_vc(dsi, 1); 4198 dsi_sync_vc(dsi, 2); 4199 dsi_sync_vc(dsi, 3); 4200 4201 dsi_display_uninit_dsi(dsi, disconnect_lanes, enter_ulps); 4202 4203 dsi_runtime_put(dsi); 4204 4205 mutex_unlock(&dsi->lock); 4206} 4207 4208static int dsi_enable_te(struct omap_dss_device *dssdev, bool enable) 4209{ 4210 struct dsi_data *dsi = to_dsi_data(dssdev); 4211 4212 dsi->te_enabled = enable; 4213 return 0; 4214} 4215 4216#ifdef PRINT_VERBOSE_VM_TIMINGS 4217static void print_dsi_vm(const char *str, 4218 const struct omap_dss_dsi_videomode_timings *t) 4219{ 4220 unsigned long byteclk = t->hsclk / 4; 4221 int bl, wc, pps, tot; 4222 4223 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8); 4224 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ 4225 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp; 4226 tot = bl + pps; 4227 4228#define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk)) 4229 4230 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, " 4231 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n", 4232 str, 4233 byteclk, 4234 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, 4235 bl, pps, tot, 4236 TO_DSI_T(t->hss), 4237 TO_DSI_T(t->hsa), 4238 TO_DSI_T(t->hse), 4239 TO_DSI_T(t->hbp), 4240 TO_DSI_T(pps), 4241 TO_DSI_T(t->hfp), 4242 4243 TO_DSI_T(bl), 4244 TO_DSI_T(pps), 4245 4246 TO_DSI_T(tot)); 4247#undef TO_DSI_T 4248} 4249 4250static void print_dispc_vm(const char *str, const struct videomode *vm) 4251{ 4252 unsigned long pck = vm->pixelclock; 4253 int hact, bl, tot; 4254 4255 hact = vm->hactive; 4256 bl = vm->hsync_len + vm->hback_porch + vm->hfront_porch; 4257 tot = hact + bl; 4258 4259#define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck)) 4260 4261 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, " 4262 "%u/%u/%u/%u = %u + %u = %u\n", 4263 str, 4264 pck, 4265 vm->hsync_len, vm->hback_porch, hact, vm->hfront_porch, 4266 bl, hact, tot, 4267 TO_DISPC_T(vm->hsync_len), 4268 TO_DISPC_T(vm->hback_porch), 4269 TO_DISPC_T(hact), 4270 TO_DISPC_T(vm->hfront_porch), 4271 TO_DISPC_T(bl), 4272 TO_DISPC_T(hact), 4273 TO_DISPC_T(tot)); 4274#undef TO_DISPC_T 4275} 4276 4277/* note: this is not quite accurate */ 4278static void print_dsi_dispc_vm(const char *str, 4279 const struct omap_dss_dsi_videomode_timings *t) 4280{ 4281 struct videomode vm = { 0 }; 4282 unsigned long byteclk = t->hsclk / 4; 4283 unsigned long pck; 4284 u64 dsi_tput; 4285 int dsi_hact, dsi_htot; 4286 4287 dsi_tput = (u64)byteclk * t->ndl * 8; 4288 pck = (u32)div64_u64(dsi_tput, t->bitspp); 4289 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl); 4290 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp; 4291 4292 vm.pixelclock = pck; 4293 vm.hsync_len = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk); 4294 vm.hback_porch = div64_u64((u64)t->hbp * pck, byteclk); 4295 vm.hfront_porch = div64_u64((u64)t->hfp * pck, byteclk); 4296 vm.hactive = t->hact; 4297 4298 print_dispc_vm(str, &vm); 4299} 4300#endif /* PRINT_VERBOSE_VM_TIMINGS */ 4301 4302static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4303 unsigned long pck, void *data) 4304{ 4305 struct dsi_clk_calc_ctx *ctx = data; 4306 struct videomode *vm = &ctx->vm; 4307 4308 ctx->dispc_cinfo.lck_div = lckd; 4309 ctx->dispc_cinfo.pck_div = pckd; 4310 ctx->dispc_cinfo.lck = lck; 4311 ctx->dispc_cinfo.pck = pck; 4312 4313 *vm = *ctx->config->vm; 4314 vm->pixelclock = pck; 4315 vm->hactive = ctx->config->vm->hactive; 4316 vm->vactive = ctx->config->vm->vactive; 4317 vm->hsync_len = vm->hfront_porch = vm->hback_porch = vm->vsync_len = 1; 4318 vm->vfront_porch = vm->vback_porch = 0; 4319 4320 return true; 4321} 4322 4323static bool dsi_cm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4324 void *data) 4325{ 4326 struct dsi_clk_calc_ctx *ctx = data; 4327 4328 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4329 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4330 4331 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 4332 ctx->req_pck_min, ctx->req_pck_max, 4333 dsi_cm_calc_dispc_cb, ctx); 4334} 4335 4336static bool dsi_cm_calc_pll_cb(int n, int m, unsigned long fint, 4337 unsigned long clkdco, void *data) 4338{ 4339 struct dsi_clk_calc_ctx *ctx = data; 4340 struct dsi_data *dsi = ctx->dsi; 4341 4342 ctx->dsi_cinfo.n = n; 4343 ctx->dsi_cinfo.m = m; 4344 ctx->dsi_cinfo.fint = fint; 4345 ctx->dsi_cinfo.clkdco = clkdco; 4346 4347 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4348 dsi->data->max_fck_freq, 4349 dsi_cm_calc_hsdiv_cb, ctx); 4350} 4351 4352static bool dsi_cm_calc(struct dsi_data *dsi, 4353 const struct omap_dss_dsi_config *cfg, 4354 struct dsi_clk_calc_ctx *ctx) 4355{ 4356 unsigned long clkin; 4357 int bitspp, ndl; 4358 unsigned long pll_min, pll_max; 4359 unsigned long pck, txbyteclk; 4360 4361 clkin = clk_get_rate(dsi->pll.clkin); 4362 bitspp = dsi_get_pixel_size(cfg->pixel_format); 4363 ndl = dsi->num_lanes_used - 1; 4364 4365 /* 4366 * Here we should calculate minimum txbyteclk to be able to send the 4367 * frame in time, and also to handle TE. That's not very simple, though, 4368 * especially as we go to LP between each pixel packet due to HW 4369 * "feature". So let's just estimate very roughly and multiply by 1.5. 4370 */ 4371 pck = cfg->vm->pixelclock; 4372 pck = pck * 3 / 2; 4373 txbyteclk = pck * bitspp / 8 / ndl; 4374 4375 memset(ctx, 0, sizeof(*ctx)); 4376 ctx->dsi = dsi; 4377 ctx->pll = &dsi->pll; 4378 ctx->config = cfg; 4379 ctx->req_pck_min = pck; 4380 ctx->req_pck_nom = pck; 4381 ctx->req_pck_max = pck * 3 / 2; 4382 4383 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4); 4384 pll_max = cfg->hs_clk_max * 4; 4385 4386 return dss_pll_calc_a(ctx->pll, clkin, 4387 pll_min, pll_max, 4388 dsi_cm_calc_pll_cb, ctx); 4389} 4390 4391static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx) 4392{ 4393 struct dsi_data *dsi = ctx->dsi; 4394 const struct omap_dss_dsi_config *cfg = ctx->config; 4395 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4396 int ndl = dsi->num_lanes_used - 1; 4397 unsigned long hsclk = ctx->dsi_cinfo.clkdco / 4; 4398 unsigned long byteclk = hsclk / 4; 4399 4400 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max; 4401 int xres; 4402 int panel_htot, panel_hbl; /* pixels */ 4403 int dispc_htot, dispc_hbl; /* pixels */ 4404 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */ 4405 int hfp, hsa, hbp; 4406 const struct videomode *req_vm; 4407 struct videomode *dispc_vm; 4408 struct omap_dss_dsi_videomode_timings *dsi_vm; 4409 u64 dsi_tput, dispc_tput; 4410 4411 dsi_tput = (u64)byteclk * ndl * 8; 4412 4413 req_vm = cfg->vm; 4414 req_pck_min = ctx->req_pck_min; 4415 req_pck_max = ctx->req_pck_max; 4416 req_pck_nom = ctx->req_pck_nom; 4417 4418 dispc_pck = ctx->dispc_cinfo.pck; 4419 dispc_tput = (u64)dispc_pck * bitspp; 4420 4421 xres = req_vm->hactive; 4422 4423 panel_hbl = req_vm->hfront_porch + req_vm->hback_porch + 4424 req_vm->hsync_len; 4425 panel_htot = xres + panel_hbl; 4426 4427 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl); 4428 4429 /* 4430 * When there are no line buffers, DISPC and DSI must have the 4431 * same tput. Otherwise DISPC tput needs to be higher than DSI's. 4432 */ 4433 if (dsi->line_buffer_size < xres * bitspp / 8) { 4434 if (dispc_tput != dsi_tput) 4435 return false; 4436 } else { 4437 if (dispc_tput < dsi_tput) 4438 return false; 4439 } 4440 4441 /* DSI tput must be over the min requirement */ 4442 if (dsi_tput < (u64)bitspp * req_pck_min) 4443 return false; 4444 4445 /* When non-burst mode, DSI tput must be below max requirement. */ 4446 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) { 4447 if (dsi_tput > (u64)bitspp * req_pck_max) 4448 return false; 4449 } 4450 4451 hss = DIV_ROUND_UP(4, ndl); 4452 4453 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4454 if (ndl == 3 && req_vm->hsync_len == 0) 4455 hse = 1; 4456 else 4457 hse = DIV_ROUND_UP(4, ndl); 4458 } else { 4459 hse = 0; 4460 } 4461 4462 /* DSI htot to match the panel's nominal pck */ 4463 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom); 4464 4465 /* fail if there would be no time for blanking */ 4466 if (dsi_htot < hss + hse + dsi_hact) 4467 return false; 4468 4469 /* total DSI blanking needed to achieve panel's TL */ 4470 dsi_hbl = dsi_htot - dsi_hact; 4471 4472 /* DISPC htot to match the DSI TL */ 4473 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk); 4474 4475 /* verify that the DSI and DISPC TLs are the same */ 4476 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk) 4477 return false; 4478 4479 dispc_hbl = dispc_htot - xres; 4480 4481 /* setup DSI videomode */ 4482 4483 dsi_vm = &ctx->dsi_vm; 4484 memset(dsi_vm, 0, sizeof(*dsi_vm)); 4485 4486 dsi_vm->hsclk = hsclk; 4487 4488 dsi_vm->ndl = ndl; 4489 dsi_vm->bitspp = bitspp; 4490 4491 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) { 4492 hsa = 0; 4493 } else if (ndl == 3 && req_vm->hsync_len == 0) { 4494 hsa = 0; 4495 } else { 4496 hsa = div64_u64((u64)req_vm->hsync_len * byteclk, req_pck_nom); 4497 hsa = max(hsa - hse, 1); 4498 } 4499 4500 hbp = div64_u64((u64)req_vm->hback_porch * byteclk, req_pck_nom); 4501 hbp = max(hbp, 1); 4502 4503 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4504 if (hfp < 1) { 4505 int t; 4506 /* we need to take cycles from hbp */ 4507 4508 t = 1 - hfp; 4509 hbp = max(hbp - t, 1); 4510 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4511 4512 if (hfp < 1 && hsa > 0) { 4513 /* we need to take cycles from hsa */ 4514 t = 1 - hfp; 4515 hsa = max(hsa - t, 1); 4516 hfp = dsi_hbl - (hss + hsa + hse + hbp); 4517 } 4518 } 4519 4520 if (hfp < 1) 4521 return false; 4522 4523 dsi_vm->hss = hss; 4524 dsi_vm->hsa = hsa; 4525 dsi_vm->hse = hse; 4526 dsi_vm->hbp = hbp; 4527 dsi_vm->hact = xres; 4528 dsi_vm->hfp = hfp; 4529 4530 dsi_vm->vsa = req_vm->vsync_len; 4531 dsi_vm->vbp = req_vm->vback_porch; 4532 dsi_vm->vact = req_vm->vactive; 4533 dsi_vm->vfp = req_vm->vfront_porch; 4534 4535 dsi_vm->trans_mode = cfg->trans_mode; 4536 4537 dsi_vm->blanking_mode = 0; 4538 dsi_vm->hsa_blanking_mode = 1; 4539 dsi_vm->hfp_blanking_mode = 1; 4540 dsi_vm->hbp_blanking_mode = 1; 4541 4542 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on; 4543 dsi_vm->window_sync = 4; 4544 4545 /* setup DISPC videomode */ 4546 4547 dispc_vm = &ctx->vm; 4548 *dispc_vm = *req_vm; 4549 dispc_vm->pixelclock = dispc_pck; 4550 4551 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) { 4552 hsa = div64_u64((u64)req_vm->hsync_len * dispc_pck, 4553 req_pck_nom); 4554 hsa = max(hsa, 1); 4555 } else { 4556 hsa = 1; 4557 } 4558 4559 hbp = div64_u64((u64)req_vm->hback_porch * dispc_pck, req_pck_nom); 4560 hbp = max(hbp, 1); 4561 4562 hfp = dispc_hbl - hsa - hbp; 4563 if (hfp < 1) { 4564 int t; 4565 /* we need to take cycles from hbp */ 4566 4567 t = 1 - hfp; 4568 hbp = max(hbp - t, 1); 4569 hfp = dispc_hbl - hsa - hbp; 4570 4571 if (hfp < 1) { 4572 /* we need to take cycles from hsa */ 4573 t = 1 - hfp; 4574 hsa = max(hsa - t, 1); 4575 hfp = dispc_hbl - hsa - hbp; 4576 } 4577 } 4578 4579 if (hfp < 1) 4580 return false; 4581 4582 dispc_vm->hfront_porch = hfp; 4583 dispc_vm->hsync_len = hsa; 4584 dispc_vm->hback_porch = hbp; 4585 4586 return true; 4587} 4588 4589 4590static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck, 4591 unsigned long pck, void *data) 4592{ 4593 struct dsi_clk_calc_ctx *ctx = data; 4594 4595 ctx->dispc_cinfo.lck_div = lckd; 4596 ctx->dispc_cinfo.pck_div = pckd; 4597 ctx->dispc_cinfo.lck = lck; 4598 ctx->dispc_cinfo.pck = pck; 4599 4600 if (dsi_vm_calc_blanking(ctx) == false) 4601 return false; 4602 4603#ifdef PRINT_VERBOSE_VM_TIMINGS 4604 print_dispc_vm("dispc", &ctx->vm); 4605 print_dsi_vm("dsi ", &ctx->dsi_vm); 4606 print_dispc_vm("req ", ctx->config->vm); 4607 print_dsi_dispc_vm("act ", &ctx->dsi_vm); 4608#endif 4609 4610 return true; 4611} 4612 4613static bool dsi_vm_calc_hsdiv_cb(int m_dispc, unsigned long dispc, 4614 void *data) 4615{ 4616 struct dsi_clk_calc_ctx *ctx = data; 4617 unsigned long pck_max; 4618 4619 ctx->dsi_cinfo.mX[HSDIV_DISPC] = m_dispc; 4620 ctx->dsi_cinfo.clkout[HSDIV_DISPC] = dispc; 4621 4622 /* 4623 * In burst mode we can let the dispc pck be arbitrarily high, but it 4624 * limits our scaling abilities. So for now, don't aim too high. 4625 */ 4626 4627 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE) 4628 pck_max = ctx->req_pck_max + 10000000; 4629 else 4630 pck_max = ctx->req_pck_max; 4631 4632 return dispc_div_calc(ctx->dsi->dss->dispc, dispc, 4633 ctx->req_pck_min, pck_max, 4634 dsi_vm_calc_dispc_cb, ctx); 4635} 4636 4637static bool dsi_vm_calc_pll_cb(int n, int m, unsigned long fint, 4638 unsigned long clkdco, void *data) 4639{ 4640 struct dsi_clk_calc_ctx *ctx = data; 4641 struct dsi_data *dsi = ctx->dsi; 4642 4643 ctx->dsi_cinfo.n = n; 4644 ctx->dsi_cinfo.m = m; 4645 ctx->dsi_cinfo.fint = fint; 4646 ctx->dsi_cinfo.clkdco = clkdco; 4647 4648 return dss_pll_hsdiv_calc_a(ctx->pll, clkdco, ctx->req_pck_min, 4649 dsi->data->max_fck_freq, 4650 dsi_vm_calc_hsdiv_cb, ctx); 4651} 4652 4653static bool dsi_vm_calc(struct dsi_data *dsi, 4654 const struct omap_dss_dsi_config *cfg, 4655 struct dsi_clk_calc_ctx *ctx) 4656{ 4657 const struct videomode *vm = cfg->vm; 4658 unsigned long clkin; 4659 unsigned long pll_min; 4660 unsigned long pll_max; 4661 int ndl = dsi->num_lanes_used - 1; 4662 int bitspp = dsi_get_pixel_size(cfg->pixel_format); 4663 unsigned long byteclk_min; 4664 4665 clkin = clk_get_rate(dsi->pll.clkin); 4666 4667 memset(ctx, 0, sizeof(*ctx)); 4668 ctx->dsi = dsi; 4669 ctx->pll = &dsi->pll; 4670 ctx->config = cfg; 4671 4672 /* these limits should come from the panel driver */ 4673 ctx->req_pck_min = vm->pixelclock - 1000; 4674 ctx->req_pck_nom = vm->pixelclock; 4675 ctx->req_pck_max = vm->pixelclock + 1000; 4676 4677 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8); 4678 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4); 4679 4680 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) { 4681 pll_max = cfg->hs_clk_max * 4; 4682 } else { 4683 unsigned long byteclk_max; 4684 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp, 4685 ndl * 8); 4686 4687 pll_max = byteclk_max * 4 * 4; 4688 } 4689 4690 return dss_pll_calc_a(ctx->pll, clkin, 4691 pll_min, pll_max, 4692 dsi_vm_calc_pll_cb, ctx); 4693} 4694 4695static int dsi_set_config(struct omap_dss_device *dssdev, 4696 const struct omap_dss_dsi_config *config) 4697{ 4698 struct dsi_data *dsi = to_dsi_data(dssdev); 4699 struct dsi_clk_calc_ctx ctx; 4700 bool ok; 4701 int r; 4702 4703 mutex_lock(&dsi->lock); 4704 4705 dsi->pix_fmt = config->pixel_format; 4706 dsi->mode = config->mode; 4707 4708 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE) 4709 ok = dsi_vm_calc(dsi, config, &ctx); 4710 else 4711 ok = dsi_cm_calc(dsi, config, &ctx); 4712 4713 if (!ok) { 4714 DSSERR("failed to find suitable DSI clock settings\n"); 4715 r = -EINVAL; 4716 goto err; 4717 } 4718 4719 dsi_pll_calc_dsi_fck(dsi, &ctx.dsi_cinfo); 4720 4721 r = dsi_lp_clock_calc(ctx.dsi_cinfo.clkout[HSDIV_DSI], 4722 config->lp_clk_min, config->lp_clk_max, &dsi->user_lp_cinfo); 4723 if (r) { 4724 DSSERR("failed to find suitable DSI LP clock settings\n"); 4725 goto err; 4726 } 4727 4728 dsi->user_dsi_cinfo = ctx.dsi_cinfo; 4729 dsi->user_dispc_cinfo = ctx.dispc_cinfo; 4730 4731 dsi->vm = ctx.vm; 4732 4733 /* 4734 * override interlace, logic level and edge related parameters in 4735 * videomode with default values 4736 */ 4737 dsi->vm.flags &= ~DISPLAY_FLAGS_INTERLACED; 4738 dsi->vm.flags &= ~DISPLAY_FLAGS_HSYNC_LOW; 4739 dsi->vm.flags |= DISPLAY_FLAGS_HSYNC_HIGH; 4740 dsi->vm.flags &= ~DISPLAY_FLAGS_VSYNC_LOW; 4741 dsi->vm.flags |= DISPLAY_FLAGS_VSYNC_HIGH; 4742 /* 4743 * HACK: These flags should be handled through the omap_dss_device bus 4744 * flags, but this will only be possible when the DSI encoder will be 4745 * converted to the omapdrm-managed encoder model. 4746 */ 4747 dsi->vm.flags &= ~DISPLAY_FLAGS_PIXDATA_NEGEDGE; 4748 dsi->vm.flags |= DISPLAY_FLAGS_PIXDATA_POSEDGE; 4749 dsi->vm.flags &= ~DISPLAY_FLAGS_DE_LOW; 4750 dsi->vm.flags |= DISPLAY_FLAGS_DE_HIGH; 4751 dsi->vm.flags &= ~DISPLAY_FLAGS_SYNC_POSEDGE; 4752 dsi->vm.flags |= DISPLAY_FLAGS_SYNC_NEGEDGE; 4753 4754 dss_mgr_set_timings(&dsi->output, &dsi->vm); 4755 4756 dsi->vm_timings = ctx.dsi_vm; 4757 4758 mutex_unlock(&dsi->lock); 4759 4760 return 0; 4761err: 4762 mutex_unlock(&dsi->lock); 4763 4764 return r; 4765} 4766 4767/* 4768 * Return a hardcoded channel for the DSI output. This should work for 4769 * current use cases, but this can be later expanded to either resolve 4770 * the channel in some more dynamic manner, or get the channel as a user 4771 * parameter. 4772 */ 4773static enum omap_channel dsi_get_channel(struct dsi_data *dsi) 4774{ 4775 switch (dsi->data->model) { 4776 case DSI_MODEL_OMAP3: 4777 return OMAP_DSS_CHANNEL_LCD; 4778 4779 case DSI_MODEL_OMAP4: 4780 switch (dsi->module_id) { 4781 case 0: 4782 return OMAP_DSS_CHANNEL_LCD; 4783 case 1: 4784 return OMAP_DSS_CHANNEL_LCD2; 4785 default: 4786 DSSWARN("unsupported module id\n"); 4787 return OMAP_DSS_CHANNEL_LCD; 4788 } 4789 4790 case DSI_MODEL_OMAP5: 4791 switch (dsi->module_id) { 4792 case 0: 4793 return OMAP_DSS_CHANNEL_LCD; 4794 case 1: 4795 return OMAP_DSS_CHANNEL_LCD3; 4796 default: 4797 DSSWARN("unsupported module id\n"); 4798 return OMAP_DSS_CHANNEL_LCD; 4799 } 4800 4801 default: 4802 DSSWARN("unsupported DSS version\n"); 4803 return OMAP_DSS_CHANNEL_LCD; 4804 } 4805} 4806 4807static int dsi_request_vc(struct omap_dss_device *dssdev, int *channel) 4808{ 4809 struct dsi_data *dsi = to_dsi_data(dssdev); 4810 int i; 4811 4812 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 4813 if (!dsi->vc[i].dssdev) { 4814 dsi->vc[i].dssdev = dssdev; 4815 *channel = i; 4816 return 0; 4817 } 4818 } 4819 4820 DSSERR("cannot get VC for display %s", dssdev->name); 4821 return -ENOSPC; 4822} 4823 4824static int dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id) 4825{ 4826 struct dsi_data *dsi = to_dsi_data(dssdev); 4827 4828 if (vc_id < 0 || vc_id > 3) { 4829 DSSERR("VC ID out of range\n"); 4830 return -EINVAL; 4831 } 4832 4833 if (channel < 0 || channel > 3) { 4834 DSSERR("Virtual Channel out of range\n"); 4835 return -EINVAL; 4836 } 4837 4838 if (dsi->vc[channel].dssdev != dssdev) { 4839 DSSERR("Virtual Channel not allocated to display %s\n", 4840 dssdev->name); 4841 return -EINVAL; 4842 } 4843 4844 dsi->vc[channel].vc_id = vc_id; 4845 4846 return 0; 4847} 4848 4849static void dsi_release_vc(struct omap_dss_device *dssdev, int channel) 4850{ 4851 struct dsi_data *dsi = to_dsi_data(dssdev); 4852 4853 if ((channel >= 0 && channel <= 3) && 4854 dsi->vc[channel].dssdev == dssdev) { 4855 dsi->vc[channel].dssdev = NULL; 4856 dsi->vc[channel].vc_id = 0; 4857 } 4858} 4859 4860 4861static int dsi_get_clocks(struct dsi_data *dsi) 4862{ 4863 struct clk *clk; 4864 4865 clk = devm_clk_get(dsi->dev, "fck"); 4866 if (IS_ERR(clk)) { 4867 DSSERR("can't get fck\n"); 4868 return PTR_ERR(clk); 4869 } 4870 4871 dsi->dss_clk = clk; 4872 4873 return 0; 4874} 4875 4876static int dsi_connect(struct omap_dss_device *src, 4877 struct omap_dss_device *dst) 4878{ 4879 return omapdss_device_connect(dst->dss, dst, dst->next); 4880} 4881 4882static void dsi_disconnect(struct omap_dss_device *src, 4883 struct omap_dss_device *dst) 4884{ 4885 omapdss_device_disconnect(dst, dst->next); 4886} 4887 4888static const struct omap_dss_device_ops dsi_ops = { 4889 .connect = dsi_connect, 4890 .disconnect = dsi_disconnect, 4891 .enable = dsi_display_enable, 4892 4893 .dsi = { 4894 .bus_lock = dsi_bus_lock, 4895 .bus_unlock = dsi_bus_unlock, 4896 4897 .disable = dsi_display_disable, 4898 4899 .enable_hs = dsi_vc_enable_hs, 4900 4901 .configure_pins = dsi_configure_pins, 4902 .set_config = dsi_set_config, 4903 4904 .enable_video_output = dsi_enable_video_output, 4905 .disable_video_output = dsi_disable_video_output, 4906 4907 .update = dsi_update, 4908 4909 .enable_te = dsi_enable_te, 4910 4911 .request_vc = dsi_request_vc, 4912 .set_vc_id = dsi_set_vc_id, 4913 .release_vc = dsi_release_vc, 4914 4915 .dcs_write = dsi_vc_dcs_write, 4916 .dcs_write_nosync = dsi_vc_dcs_write_nosync, 4917 .dcs_read = dsi_vc_dcs_read, 4918 4919 .gen_write = dsi_vc_generic_write, 4920 .gen_write_nosync = dsi_vc_generic_write_nosync, 4921 .gen_read = dsi_vc_generic_read, 4922 4923 .bta_sync = dsi_vc_send_bta_sync, 4924 4925 .set_max_rx_packet_size = dsi_vc_set_max_rx_packet_size, 4926 }, 4927}; 4928 4929/* ----------------------------------------------------------------------------- 4930 * PLL 4931 */ 4932 4933static const struct dss_pll_ops dsi_pll_ops = { 4934 .enable = dsi_pll_enable, 4935 .disable = dsi_pll_disable, 4936 .set_config = dss_pll_write_config_type_a, 4937}; 4938 4939static const struct dss_pll_hw dss_omap3_dsi_pll_hw = { 4940 .type = DSS_PLL_TYPE_A, 4941 4942 .n_max = (1 << 7) - 1, 4943 .m_max = (1 << 11) - 1, 4944 .mX_max = (1 << 4) - 1, 4945 .fint_min = 750000, 4946 .fint_max = 2100000, 4947 .clkdco_low = 1000000000, 4948 .clkdco_max = 1800000000, 4949 4950 .n_msb = 7, 4951 .n_lsb = 1, 4952 .m_msb = 18, 4953 .m_lsb = 8, 4954 4955 .mX_msb[0] = 22, 4956 .mX_lsb[0] = 19, 4957 .mX_msb[1] = 26, 4958 .mX_lsb[1] = 23, 4959 4960 .has_stopmode = true, 4961 .has_freqsel = true, 4962 .has_selfreqdco = false, 4963 .has_refsel = false, 4964}; 4965 4966static const struct dss_pll_hw dss_omap4_dsi_pll_hw = { 4967 .type = DSS_PLL_TYPE_A, 4968 4969 .n_max = (1 << 8) - 1, 4970 .m_max = (1 << 12) - 1, 4971 .mX_max = (1 << 5) - 1, 4972 .fint_min = 500000, 4973 .fint_max = 2500000, 4974 .clkdco_low = 1000000000, 4975 .clkdco_max = 1800000000, 4976 4977 .n_msb = 8, 4978 .n_lsb = 1, 4979 .m_msb = 20, 4980 .m_lsb = 9, 4981 4982 .mX_msb[0] = 25, 4983 .mX_lsb[0] = 21, 4984 .mX_msb[1] = 30, 4985 .mX_lsb[1] = 26, 4986 4987 .has_stopmode = true, 4988 .has_freqsel = false, 4989 .has_selfreqdco = false, 4990 .has_refsel = false, 4991}; 4992 4993static const struct dss_pll_hw dss_omap5_dsi_pll_hw = { 4994 .type = DSS_PLL_TYPE_A, 4995 4996 .n_max = (1 << 8) - 1, 4997 .m_max = (1 << 12) - 1, 4998 .mX_max = (1 << 5) - 1, 4999 .fint_min = 150000, 5000 .fint_max = 52000000, 5001 .clkdco_low = 1000000000, 5002 .clkdco_max = 1800000000, 5003 5004 .n_msb = 8, 5005 .n_lsb = 1, 5006 .m_msb = 20, 5007 .m_lsb = 9, 5008 5009 .mX_msb[0] = 25, 5010 .mX_lsb[0] = 21, 5011 .mX_msb[1] = 30, 5012 .mX_lsb[1] = 26, 5013 5014 .has_stopmode = true, 5015 .has_freqsel = false, 5016 .has_selfreqdco = true, 5017 .has_refsel = true, 5018}; 5019 5020static int dsi_init_pll_data(struct dss_device *dss, struct dsi_data *dsi) 5021{ 5022 struct dss_pll *pll = &dsi->pll; 5023 struct clk *clk; 5024 int r; 5025 5026 clk = devm_clk_get(dsi->dev, "sys_clk"); 5027 if (IS_ERR(clk)) { 5028 DSSERR("can't get sys_clk\n"); 5029 return PTR_ERR(clk); 5030 } 5031 5032 pll->name = dsi->module_id == 0 ? "dsi0" : "dsi1"; 5033 pll->id = dsi->module_id == 0 ? DSS_PLL_DSI1 : DSS_PLL_DSI2; 5034 pll->clkin = clk; 5035 pll->base = dsi->pll_base; 5036 pll->hw = dsi->data->pll_hw; 5037 pll->ops = &dsi_pll_ops; 5038 5039 r = dss_pll_register(dss, pll); 5040 if (r) 5041 return r; 5042 5043 return 0; 5044} 5045 5046/* ----------------------------------------------------------------------------- 5047 * Component Bind & Unbind 5048 */ 5049 5050static int dsi_bind(struct device *dev, struct device *master, void *data) 5051{ 5052 struct dss_device *dss = dss_get_device(master); 5053 struct dsi_data *dsi = dev_get_drvdata(dev); 5054 char name[10]; 5055 u32 rev; 5056 int r; 5057 5058 dsi->dss = dss; 5059 5060 dsi_init_pll_data(dss, dsi); 5061 5062 r = dsi_runtime_get(dsi); 5063 if (r) 5064 return r; 5065 5066 rev = dsi_read_reg(dsi, DSI_REVISION); 5067 dev_dbg(dev, "OMAP DSI rev %d.%d\n", 5068 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0)); 5069 5070 dsi->line_buffer_size = dsi_get_line_buf_size(dsi); 5071 5072 dsi_runtime_put(dsi); 5073 5074 snprintf(name, sizeof(name), "dsi%u_regs", dsi->module_id + 1); 5075 dsi->debugfs.regs = dss_debugfs_create_file(dss, name, 5076 dsi_dump_dsi_regs, dsi); 5077#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5078 snprintf(name, sizeof(name), "dsi%u_irqs", dsi->module_id + 1); 5079 dsi->debugfs.irqs = dss_debugfs_create_file(dss, name, 5080 dsi_dump_dsi_irqs, dsi); 5081#endif 5082 snprintf(name, sizeof(name), "dsi%u_clks", dsi->module_id + 1); 5083 dsi->debugfs.clks = dss_debugfs_create_file(dss, name, 5084 dsi_dump_dsi_clocks, dsi); 5085 5086 return 0; 5087} 5088 5089static void dsi_unbind(struct device *dev, struct device *master, void *data) 5090{ 5091 struct dsi_data *dsi = dev_get_drvdata(dev); 5092 5093 dss_debugfs_remove_file(dsi->debugfs.clks); 5094 dss_debugfs_remove_file(dsi->debugfs.irqs); 5095 dss_debugfs_remove_file(dsi->debugfs.regs); 5096 5097 WARN_ON(dsi->scp_clk_refcount > 0); 5098 5099 dss_pll_unregister(&dsi->pll); 5100} 5101 5102static const struct component_ops dsi_component_ops = { 5103 .bind = dsi_bind, 5104 .unbind = dsi_unbind, 5105}; 5106 5107/* ----------------------------------------------------------------------------- 5108 * Probe & Remove, Suspend & Resume 5109 */ 5110 5111static int dsi_init_output(struct dsi_data *dsi) 5112{ 5113 struct omap_dss_device *out = &dsi->output; 5114 int r; 5115 5116 out->dev = dsi->dev; 5117 out->id = dsi->module_id == 0 ? 5118 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2; 5119 5120 out->type = OMAP_DISPLAY_TYPE_DSI; 5121 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1"; 5122 out->dispc_channel = dsi_get_channel(dsi); 5123 out->ops = &dsi_ops; 5124 out->owner = THIS_MODULE; 5125 out->of_port = 0; 5126 out->bus_flags = DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE 5127 | DRM_BUS_FLAG_DE_HIGH 5128 | DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 5129 5130 r = omapdss_device_init_output(out, NULL); 5131 if (r < 0) 5132 return r; 5133 5134 omapdss_device_register(out); 5135 5136 return 0; 5137} 5138 5139static void dsi_uninit_output(struct dsi_data *dsi) 5140{ 5141 struct omap_dss_device *out = &dsi->output; 5142 5143 omapdss_device_unregister(out); 5144 omapdss_device_cleanup_output(out); 5145} 5146 5147static int dsi_probe_of(struct dsi_data *dsi) 5148{ 5149 struct device_node *node = dsi->dev->of_node; 5150 struct property *prop; 5151 u32 lane_arr[10]; 5152 int len, num_pins; 5153 int r, i; 5154 struct device_node *ep; 5155 struct omap_dsi_pin_config pin_cfg; 5156 5157 ep = of_graph_get_endpoint_by_regs(node, 0, 0); 5158 if (!ep) 5159 return 0; 5160 5161 prop = of_find_property(ep, "lanes", &len); 5162 if (prop == NULL) { 5163 dev_err(dsi->dev, "failed to find lane data\n"); 5164 r = -EINVAL; 5165 goto err; 5166 } 5167 5168 num_pins = len / sizeof(u32); 5169 5170 if (num_pins < 4 || num_pins % 2 != 0 || 5171 num_pins > dsi->num_lanes_supported * 2) { 5172 dev_err(dsi->dev, "bad number of lanes\n"); 5173 r = -EINVAL; 5174 goto err; 5175 } 5176 5177 r = of_property_read_u32_array(ep, "lanes", lane_arr, num_pins); 5178 if (r) { 5179 dev_err(dsi->dev, "failed to read lane data\n"); 5180 goto err; 5181 } 5182 5183 pin_cfg.num_pins = num_pins; 5184 for (i = 0; i < num_pins; ++i) 5185 pin_cfg.pins[i] = (int)lane_arr[i]; 5186 5187 r = dsi_configure_pins(&dsi->output, &pin_cfg); 5188 if (r) { 5189 dev_err(dsi->dev, "failed to configure pins"); 5190 goto err; 5191 } 5192 5193 of_node_put(ep); 5194 5195 return 0; 5196 5197err: 5198 of_node_put(ep); 5199 return r; 5200} 5201 5202static const struct dsi_of_data dsi_of_data_omap34xx = { 5203 .model = DSI_MODEL_OMAP3, 5204 .pll_hw = &dss_omap3_dsi_pll_hw, 5205 .modules = (const struct dsi_module_id_data[]) { 5206 { .address = 0x4804fc00, .id = 0, }, 5207 { }, 5208 }, 5209 .max_fck_freq = 173000000, 5210 .max_pll_lpdiv = (1 << 13) - 1, 5211 .quirks = DSI_QUIRK_REVERSE_TXCLKESC, 5212}; 5213 5214static const struct dsi_of_data dsi_of_data_omap36xx = { 5215 .model = DSI_MODEL_OMAP3, 5216 .pll_hw = &dss_omap3_dsi_pll_hw, 5217 .modules = (const struct dsi_module_id_data[]) { 5218 { .address = 0x4804fc00, .id = 0, }, 5219 { }, 5220 }, 5221 .max_fck_freq = 173000000, 5222 .max_pll_lpdiv = (1 << 13) - 1, 5223 .quirks = DSI_QUIRK_PLL_PWR_BUG, 5224}; 5225 5226static const struct dsi_of_data dsi_of_data_omap4 = { 5227 .model = DSI_MODEL_OMAP4, 5228 .pll_hw = &dss_omap4_dsi_pll_hw, 5229 .modules = (const struct dsi_module_id_data[]) { 5230 { .address = 0x58004000, .id = 0, }, 5231 { .address = 0x58005000, .id = 1, }, 5232 { }, 5233 }, 5234 .max_fck_freq = 170000000, 5235 .max_pll_lpdiv = (1 << 13) - 1, 5236 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 5237 | DSI_QUIRK_GNQ, 5238}; 5239 5240static const struct dsi_of_data dsi_of_data_omap5 = { 5241 .model = DSI_MODEL_OMAP5, 5242 .pll_hw = &dss_omap5_dsi_pll_hw, 5243 .modules = (const struct dsi_module_id_data[]) { 5244 { .address = 0x58004000, .id = 0, }, 5245 { .address = 0x58009000, .id = 1, }, 5246 { }, 5247 }, 5248 .max_fck_freq = 209250000, 5249 .max_pll_lpdiv = (1 << 13) - 1, 5250 .quirks = DSI_QUIRK_DCS_CMD_CONFIG_VC | DSI_QUIRK_VC_OCP_WIDTH 5251 | DSI_QUIRK_GNQ | DSI_QUIRK_PHY_DCC, 5252}; 5253 5254static const struct of_device_id dsi_of_match[] = { 5255 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, }, 5256 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, }, 5257 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, }, 5258 {}, 5259}; 5260 5261static const struct soc_device_attribute dsi_soc_devices[] = { 5262 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx }, 5263 { .machine = "AM35*", .data = &dsi_of_data_omap34xx }, 5264 { /* sentinel */ } 5265}; 5266 5267static int dsi_probe(struct platform_device *pdev) 5268{ 5269 const struct soc_device_attribute *soc; 5270 const struct dsi_module_id_data *d; 5271 struct device *dev = &pdev->dev; 5272 struct dsi_data *dsi; 5273 struct resource *dsi_mem; 5274 struct resource *res; 5275 unsigned int i; 5276 int r; 5277 5278 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 5279 if (!dsi) 5280 return -ENOMEM; 5281 5282 dsi->dev = dev; 5283 dev_set_drvdata(dev, dsi); 5284 5285 spin_lock_init(&dsi->irq_lock); 5286 spin_lock_init(&dsi->errors_lock); 5287 dsi->errors = 0; 5288 5289#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS 5290 spin_lock_init(&dsi->irq_stats_lock); 5291 dsi->irq_stats.last_reset = jiffies; 5292#endif 5293 5294 mutex_init(&dsi->lock); 5295 sema_init(&dsi->bus_lock, 1); 5296 5297 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work, 5298 dsi_framedone_timeout_work_callback); 5299 5300#ifdef DSI_CATCH_MISSING_TE 5301 timer_setup(&dsi->te_timer, dsi_te_timeout, 0); 5302#endif 5303 5304 dsi_mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proto"); 5305 dsi->proto_base = devm_ioremap_resource(dev, dsi_mem); 5306 if (IS_ERR(dsi->proto_base)) 5307 return PTR_ERR(dsi->proto_base); 5308 5309 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 5310 dsi->phy_base = devm_ioremap_resource(dev, res); 5311 if (IS_ERR(dsi->phy_base)) 5312 return PTR_ERR(dsi->phy_base); 5313 5314 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll"); 5315 dsi->pll_base = devm_ioremap_resource(dev, res); 5316 if (IS_ERR(dsi->pll_base)) 5317 return PTR_ERR(dsi->pll_base); 5318 5319 dsi->irq = platform_get_irq(pdev, 0); 5320 if (dsi->irq < 0) { 5321 DSSERR("platform_get_irq failed\n"); 5322 return -ENODEV; 5323 } 5324 5325 r = devm_request_irq(dev, dsi->irq, omap_dsi_irq_handler, 5326 IRQF_SHARED, dev_name(dev), dsi); 5327 if (r < 0) { 5328 DSSERR("request_irq failed\n"); 5329 return r; 5330 } 5331 5332 dsi->vdds_dsi_reg = devm_regulator_get(dev, "vdd"); 5333 if (IS_ERR(dsi->vdds_dsi_reg)) { 5334 if (PTR_ERR(dsi->vdds_dsi_reg) != -EPROBE_DEFER) 5335 DSSERR("can't get DSI VDD regulator\n"); 5336 return PTR_ERR(dsi->vdds_dsi_reg); 5337 } 5338 5339 soc = soc_device_match(dsi_soc_devices); 5340 if (soc) 5341 dsi->data = soc->data; 5342 else 5343 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data; 5344 5345 d = dsi->data->modules; 5346 while (d->address != 0 && d->address != dsi_mem->start) 5347 d++; 5348 5349 if (d->address == 0) { 5350 DSSERR("unsupported DSI module\n"); 5351 return -ENODEV; 5352 } 5353 5354 dsi->module_id = d->id; 5355 5356 if (dsi->data->model == DSI_MODEL_OMAP4 || 5357 dsi->data->model == DSI_MODEL_OMAP5) { 5358 struct device_node *np; 5359 5360 /* 5361 * The OMAP4/5 display DT bindings don't reference the padconf 5362 * syscon. Our only option to retrieve it is to find it by name. 5363 */ 5364 np = of_find_node_by_name(NULL, 5365 dsi->data->model == DSI_MODEL_OMAP4 ? 5366 "omap4_padconf_global" : "omap5_padconf_global"); 5367 if (!np) 5368 return -ENODEV; 5369 5370 dsi->syscon = syscon_node_to_regmap(np); 5371 of_node_put(np); 5372 } 5373 5374 /* DSI VCs initialization */ 5375 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) { 5376 dsi->vc[i].source = DSI_VC_SOURCE_L4; 5377 dsi->vc[i].dssdev = NULL; 5378 dsi->vc[i].vc_id = 0; 5379 } 5380 5381 r = dsi_get_clocks(dsi); 5382 if (r) 5383 return r; 5384 5385 pm_runtime_enable(dev); 5386 5387 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number 5388 * of data to 3 by default */ 5389 if (dsi->data->quirks & DSI_QUIRK_GNQ) { 5390 dsi_runtime_get(dsi); 5391 /* NB_DATA_LANES */ 5392 dsi->num_lanes_supported = 1 + REG_GET(dsi, DSI_GNQ, 11, 9); 5393 dsi_runtime_put(dsi); 5394 } else { 5395 dsi->num_lanes_supported = 3; 5396 } 5397 5398 r = of_platform_populate(dev->of_node, NULL, NULL, dev); 5399 if (r) { 5400 DSSERR("Failed to populate DSI child devices: %d\n", r); 5401 goto err_pm_disable; 5402 } 5403 5404 r = dsi_init_output(dsi); 5405 if (r) 5406 goto err_of_depopulate; 5407 5408 r = dsi_probe_of(dsi); 5409 if (r) { 5410 DSSERR("Invalid DSI DT data\n"); 5411 goto err_uninit_output; 5412 } 5413 5414 r = component_add(&pdev->dev, &dsi_component_ops); 5415 if (r) 5416 goto err_uninit_output; 5417 5418 return 0; 5419 5420err_uninit_output: 5421 dsi_uninit_output(dsi); 5422err_of_depopulate: 5423 of_platform_depopulate(dev); 5424err_pm_disable: 5425 pm_runtime_disable(dev); 5426 return r; 5427} 5428 5429static int dsi_remove(struct platform_device *pdev) 5430{ 5431 struct dsi_data *dsi = platform_get_drvdata(pdev); 5432 5433 component_del(&pdev->dev, &dsi_component_ops); 5434 5435 dsi_uninit_output(dsi); 5436 5437 of_platform_depopulate(&pdev->dev); 5438 5439 pm_runtime_disable(&pdev->dev); 5440 5441 if (dsi->vdds_dsi_reg != NULL && dsi->vdds_dsi_enabled) { 5442 regulator_disable(dsi->vdds_dsi_reg); 5443 dsi->vdds_dsi_enabled = false; 5444 } 5445 5446 return 0; 5447} 5448 5449static int dsi_runtime_suspend(struct device *dev) 5450{ 5451 struct dsi_data *dsi = dev_get_drvdata(dev); 5452 5453 dsi->is_enabled = false; 5454 /* ensure the irq handler sees the is_enabled value */ 5455 smp_wmb(); 5456 /* wait for current handler to finish before turning the DSI off */ 5457 synchronize_irq(dsi->irq); 5458 5459 return 0; 5460} 5461 5462static int dsi_runtime_resume(struct device *dev) 5463{ 5464 struct dsi_data *dsi = dev_get_drvdata(dev); 5465 5466 dsi->is_enabled = true; 5467 /* ensure the irq handler sees the is_enabled value */ 5468 smp_wmb(); 5469 5470 return 0; 5471} 5472 5473static const struct dev_pm_ops dsi_pm_ops = { 5474 .runtime_suspend = dsi_runtime_suspend, 5475 .runtime_resume = dsi_runtime_resume, 5476 SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 5477}; 5478 5479struct platform_driver omap_dsihw_driver = { 5480 .probe = dsi_probe, 5481 .remove = dsi_remove, 5482 .driver = { 5483 .name = "omapdss_dsi", 5484 .pm = &dsi_pm_ops, 5485 .of_match_table = dsi_of_match, 5486 .suppress_bind_attrs = true, 5487 }, 5488}; 5489