1#ifndef __NVFW_SEC2_H__ 2#define __NVFW_SEC2_H__ 3 4struct nv_sec2_args { 5 u32 freq_hz; 6 u32 falc_trace_size; 7 u32 falc_trace_dma_base; 8 u32 falc_trace_dma_idx; 9 bool secure_mode; 10}; 11 12#define NV_SEC2_UNIT_INIT 0x01 13#define NV_SEC2_UNIT_ACR 0x08 14 15struct nv_sec2_init_msg { 16 struct nvfw_falcon_msg hdr; 17#define NV_SEC2_INIT_MSG_INIT 0x00 18 u8 msg_type; 19 20 u8 num_queues; 21 u16 os_debug_entry_point; 22 23 struct { 24 u32 offset; 25 u16 size; 26 u8 index; 27#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00 28#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01 29 u8 id; 30 } queue_info[2]; 31 32 u32 sw_managed_area_offset; 33 u16 sw_managed_area_size; 34}; 35 36struct nv_sec2_acr_cmd { 37 struct nvfw_falcon_cmd hdr; 38#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00 39 u8 cmd_type; 40}; 41 42struct nv_sec2_acr_msg { 43 struct nvfw_falcon_cmd hdr; 44 u8 msg_type; 45}; 46 47struct nv_sec2_acr_bootstrap_falcon_cmd { 48 struct nv_sec2_acr_cmd cmd; 49#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000 50#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001 51 u32 flags; 52 u32 falcon_id; 53}; 54 55struct nv_sec2_acr_bootstrap_falcon_msg { 56 struct nv_sec2_acr_msg msg; 57 u32 error_code; 58 u32 falcon_id; 59}; 60#endif 61