1#ifndef __NVFW_PMU_H__
2#define __NVFW_PMU_H__
3
4struct nv_pmu_args {
5	u32 reserved;
6	u32 freq_hz;
7	u32 trace_size;
8	u32 trace_dma_base;
9	u16 trace_dma_base1;
10	u8 trace_dma_offset;
11	u32 trace_dma_idx;
12	bool secure_mode;
13	bool raise_priv_sec;
14	struct {
15		u32 dma_base;
16		u16 dma_base1;
17		u8 dma_offset;
18		u16 fb_size;
19		u8 dma_idx;
20	} gc6_ctx;
21	u8 pad;
22};
23
24#define NV_PMU_UNIT_INIT                                                   0x07
25#define NV_PMU_UNIT_ACR                                                    0x0a
26
27struct nv_pmu_init_msg {
28	struct nvfw_falcon_msg hdr;
29#define NV_PMU_INIT_MSG_INIT                                               0x00
30	u8 msg_type;
31
32	u8 pad;
33	u16 os_debug_entry_point;
34
35	struct {
36		u16 size;
37		u16 offset;
38		u8 index;
39		u8 pad;
40	} queue_info[5];
41
42	u16 sw_managed_area_offset;
43	u16 sw_managed_area_size;
44};
45
46struct nv_pmu_acr_cmd {
47	struct nvfw_falcon_cmd hdr;
48#define NV_PMU_ACR_CMD_INIT_WPR_REGION                                     0x00
49#define NV_PMU_ACR_CMD_BOOTSTRAP_FALCON                                    0x01
50#define NV_PMU_ACR_CMD_BOOTSTRAP_MULTIPLE_FALCONS                          0x03
51	u8 cmd_type;
52};
53
54struct nv_pmu_acr_msg {
55	struct nvfw_falcon_cmd hdr;
56	u8 msg_type;
57};
58
59struct nv_pmu_acr_init_wpr_region_cmd {
60	struct nv_pmu_acr_cmd cmd;
61	u32 region_id;
62	u32 wpr_offset;
63};
64
65struct nv_pmu_acr_init_wpr_region_msg {
66	struct nv_pmu_acr_msg msg;
67	u32 error_code;
68};
69
70struct nv_pmu_acr_bootstrap_falcon_cmd {
71	struct nv_pmu_acr_cmd cmd;
72#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES                  0x00000000
73#define NV_PMU_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO                   0x00000001
74	u32 flags;
75	u32 falcon_id;
76};
77
78struct nv_pmu_acr_bootstrap_falcon_msg {
79	struct nv_pmu_acr_msg msg;
80	u32 falcon_id;
81};
82
83struct nv_pmu_acr_bootstrap_multiple_falcons_cmd {
84	struct nv_pmu_acr_cmd cmd;
85#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_YES        0x00000000
86#define NV_PMU_ACR_BOOTSTRAP_MULTIPLE_FALCONS_FLAGS_RESET_NO         0x00000001
87	u32 flags;
88	u32 falcon_mask;
89	u32 use_va_mask;
90	u32 wpr_lo;
91	u32 wpr_hi;
92};
93
94struct nv_pmu_acr_bootstrap_multiple_falcons_msg {
95	struct nv_pmu_acr_msg msg;
96	u32 falcon_mask;
97};
98#endif
99