1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 */ 7 8#include <linux/dma-mapping.h> 9#include <linux/kthread.h> 10#include <linux/uaccess.h> 11#include <uapi/linux/sched/types.h> 12 13#include <drm/drm_bridge.h> 14#include <drm/drm_drv.h> 15#include <drm/drm_file.h> 16#include <drm/drm_ioctl.h> 17#include <drm/drm_irq.h> 18#include <drm/drm_prime.h> 19#include <drm/drm_of.h> 20#include <drm/drm_vblank.h> 21 22#include "msm_drv.h" 23#include "msm_debugfs.h" 24#include "msm_fence.h" 25#include "msm_gem.h" 26#include "msm_gpu.h" 27#include "msm_kms.h" 28#include "adreno/adreno_gpu.h" 29 30/* 31 * MSM driver version: 32 * - 1.0.0 - initial interface 33 * - 1.1.0 - adds madvise, and support for submits with > 4 cmd buffers 34 * - 1.2.0 - adds explicit fence support for submit ioctl 35 * - 1.3.0 - adds GMEM_BASE + NR_RINGS params, SUBMITQUEUE_NEW + 36 * SUBMITQUEUE_CLOSE ioctls, and MSM_INFO_IOVA flag for 37 * MSM_GEM_INFO ioctl. 38 * - 1.4.0 - softpin, MSM_RELOC_BO_DUMP, and GEM_INFO support to set/get 39 * GEM object's debug name 40 * - 1.5.0 - Add SUBMITQUERY_QUERY ioctl 41 * - 1.6.0 - Syncobj support 42 */ 43#define MSM_VERSION_MAJOR 1 44#define MSM_VERSION_MINOR 6 45#define MSM_VERSION_PATCHLEVEL 0 46 47static const struct drm_mode_config_funcs mode_config_funcs = { 48 .fb_create = msm_framebuffer_create, 49 .output_poll_changed = drm_fb_helper_output_poll_changed, 50 .atomic_check = drm_atomic_helper_check, 51 .atomic_commit = drm_atomic_helper_commit, 52}; 53 54static const struct drm_mode_config_helper_funcs mode_config_helper_funcs = { 55 .atomic_commit_tail = msm_atomic_commit_tail, 56}; 57 58#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING 59static bool reglog = false; 60MODULE_PARM_DESC(reglog, "Enable register read/write logging"); 61module_param(reglog, bool, 0600); 62#else 63#define reglog 0 64#endif 65 66#ifdef CONFIG_DRM_FBDEV_EMULATION 67static bool fbdev = true; 68MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer"); 69module_param(fbdev, bool, 0600); 70#endif 71 72static char *vram = "16m"; 73MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU)"); 74module_param(vram, charp, 0); 75 76bool dumpstate = false; 77MODULE_PARM_DESC(dumpstate, "Dump KMS state on errors"); 78module_param(dumpstate, bool, 0600); 79 80static bool modeset = true; 81MODULE_PARM_DESC(modeset, "Use kernel modesetting [KMS] (1=on (default), 0=disable)"); 82module_param(modeset, bool, 0600); 83 84/* 85 * Util/helpers: 86 */ 87 88struct clk *msm_clk_bulk_get_clock(struct clk_bulk_data *bulk, int count, 89 const char *name) 90{ 91 int i; 92 char n[32]; 93 94 snprintf(n, sizeof(n), "%s_clk", name); 95 96 for (i = 0; bulk && i < count; i++) { 97 if (!strcmp(bulk[i].id, name) || !strcmp(bulk[i].id, n)) 98 return bulk[i].clk; 99 } 100 101 102 return NULL; 103} 104 105struct clk *msm_clk_get(struct platform_device *pdev, const char *name) 106{ 107 struct clk *clk; 108 char name2[32]; 109 110 clk = devm_clk_get(&pdev->dev, name); 111 if (!IS_ERR(clk) || PTR_ERR(clk) == -EPROBE_DEFER) 112 return clk; 113 114 snprintf(name2, sizeof(name2), "%s_clk", name); 115 116 clk = devm_clk_get(&pdev->dev, name2); 117 if (!IS_ERR(clk)) 118 dev_warn(&pdev->dev, "Using legacy clk name binding. Use " 119 "\"%s\" instead of \"%s\"\n", name, name2); 120 121 return clk; 122} 123 124void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name, 125 const char *dbgname, bool quiet) 126{ 127 struct resource *res; 128 unsigned long size; 129 void __iomem *ptr; 130 131 if (name) 132 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 133 else 134 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 135 136 if (!res) { 137 if (!quiet) 138 DRM_DEV_ERROR(&pdev->dev, "failed to get memory resource: %s\n", name); 139 return ERR_PTR(-EINVAL); 140 } 141 142 size = resource_size(res); 143 144 ptr = devm_ioremap(&pdev->dev, res->start, size); 145 if (!ptr) { 146 if (!quiet) 147 DRM_DEV_ERROR(&pdev->dev, "failed to ioremap: %s\n", name); 148 return ERR_PTR(-ENOMEM); 149 } 150 151 if (reglog) 152 printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size); 153 154 return ptr; 155} 156 157void __iomem *msm_ioremap(struct platform_device *pdev, const char *name, 158 const char *dbgname) 159{ 160 return _msm_ioremap(pdev, name, dbgname, false); 161} 162 163void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name, 164 const char *dbgname) 165{ 166 return _msm_ioremap(pdev, name, dbgname, true); 167} 168 169void msm_writel(u32 data, void __iomem *addr) 170{ 171 if (reglog) 172 printk(KERN_DEBUG "IO:W %p %08x\n", addr, data); 173 writel(data, addr); 174} 175 176u32 msm_readl(const void __iomem *addr) 177{ 178 u32 val = readl(addr); 179 if (reglog) 180 pr_err("IO:R %p %08x\n", addr, val); 181 return val; 182} 183 184struct msm_vblank_work { 185 struct work_struct work; 186 int crtc_id; 187 bool enable; 188 struct msm_drm_private *priv; 189}; 190 191static void vblank_ctrl_worker(struct work_struct *work) 192{ 193 struct msm_vblank_work *vbl_work = container_of(work, 194 struct msm_vblank_work, work); 195 struct msm_drm_private *priv = vbl_work->priv; 196 struct msm_kms *kms = priv->kms; 197 198 if (vbl_work->enable) 199 kms->funcs->enable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 200 else 201 kms->funcs->disable_vblank(kms, priv->crtcs[vbl_work->crtc_id]); 202 203 kfree(vbl_work); 204} 205 206static int vblank_ctrl_queue_work(struct msm_drm_private *priv, 207 int crtc_id, bool enable) 208{ 209 struct msm_vblank_work *vbl_work; 210 211 vbl_work = kzalloc(sizeof(*vbl_work), GFP_ATOMIC); 212 if (!vbl_work) 213 return -ENOMEM; 214 215 INIT_WORK(&vbl_work->work, vblank_ctrl_worker); 216 217 vbl_work->crtc_id = crtc_id; 218 vbl_work->enable = enable; 219 vbl_work->priv = priv; 220 221 queue_work(priv->wq, &vbl_work->work); 222 223 return 0; 224} 225 226static int msm_drm_uninit(struct device *dev) 227{ 228 struct platform_device *pdev = to_platform_device(dev); 229 struct drm_device *ddev = platform_get_drvdata(pdev); 230 struct msm_drm_private *priv = ddev->dev_private; 231 struct msm_kms *kms = priv->kms; 232 struct msm_mdss *mdss = priv->mdss; 233 int i; 234 235 /* 236 * Shutdown the hw if we're far enough along where things might be on. 237 * If we run this too early, we'll end up panicking in any variety of 238 * places. Since we don't register the drm device until late in 239 * msm_drm_init, drm_dev->registered is used as an indicator that the 240 * shutdown will be successful. 241 */ 242 if (ddev->registered) { 243 drm_dev_unregister(ddev); 244 drm_atomic_helper_shutdown(ddev); 245 } 246 247 /* We must cancel and cleanup any pending vblank enable/disable 248 * work before drm_irq_uninstall() to avoid work re-enabling an 249 * irq after uninstall has disabled it. 250 */ 251 252 flush_workqueue(priv->wq); 253 254 /* clean up event worker threads */ 255 for (i = 0; i < priv->num_crtcs; i++) { 256 if (priv->event_thread[i].worker) 257 kthread_destroy_worker(priv->event_thread[i].worker); 258 } 259 260 msm_gem_shrinker_cleanup(ddev); 261 262 drm_kms_helper_poll_fini(ddev); 263 264 msm_perf_debugfs_cleanup(priv); 265 msm_rd_debugfs_cleanup(priv); 266 267#ifdef CONFIG_DRM_FBDEV_EMULATION 268 if (fbdev && priv->fbdev) 269 msm_fbdev_free(ddev); 270#endif 271 272 drm_mode_config_cleanup(ddev); 273 274 pm_runtime_get_sync(dev); 275 drm_irq_uninstall(ddev); 276 pm_runtime_put_sync(dev); 277 278 if (kms && kms->funcs) 279 kms->funcs->destroy(kms); 280 281 if (priv->vram.paddr) { 282 unsigned long attrs = DMA_ATTR_NO_KERNEL_MAPPING; 283 drm_mm_takedown(&priv->vram.mm); 284 dma_free_attrs(dev, priv->vram.size, NULL, 285 priv->vram.paddr, attrs); 286 } 287 288 component_unbind_all(dev, ddev); 289 290 if (mdss && mdss->funcs) 291 mdss->funcs->destroy(ddev); 292 293 ddev->dev_private = NULL; 294 drm_dev_put(ddev); 295 296 destroy_workqueue(priv->wq); 297 kfree(priv); 298 299 return 0; 300} 301 302#define KMS_MDP4 4 303#define KMS_MDP5 5 304#define KMS_DPU 3 305 306static int get_mdp_ver(struct platform_device *pdev) 307{ 308 struct device *dev = &pdev->dev; 309 310 return (int) (unsigned long) of_device_get_match_data(dev); 311} 312 313#include <linux/of_address.h> 314 315bool msm_use_mmu(struct drm_device *dev) 316{ 317 struct msm_drm_private *priv = dev->dev_private; 318 319 /* a2xx comes with its own MMU */ 320 return priv->is_a2xx || iommu_present(&platform_bus_type); 321} 322 323static int msm_init_vram(struct drm_device *dev) 324{ 325 struct msm_drm_private *priv = dev->dev_private; 326 struct device_node *node; 327 unsigned long size = 0; 328 int ret = 0; 329 330 /* In the device-tree world, we could have a 'memory-region' 331 * phandle, which gives us a link to our "vram". Allocating 332 * is all nicely abstracted behind the dma api, but we need 333 * to know the entire size to allocate it all in one go. There 334 * are two cases: 335 * 1) device with no IOMMU, in which case we need exclusive 336 * access to a VRAM carveout big enough for all gpu 337 * buffers 338 * 2) device with IOMMU, but where the bootloader puts up 339 * a splash screen. In this case, the VRAM carveout 340 * need only be large enough for fbdev fb. But we need 341 * exclusive access to the buffer to avoid the kernel 342 * using those pages for other purposes (which appears 343 * as corruption on screen before we have a chance to 344 * load and do initial modeset) 345 */ 346 347 node = of_parse_phandle(dev->dev->of_node, "memory-region", 0); 348 if (node) { 349 struct resource r; 350 ret = of_address_to_resource(node, 0, &r); 351 of_node_put(node); 352 if (ret) 353 return ret; 354 size = r.end - r.start + 1; 355 DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start); 356 357 /* if we have no IOMMU, then we need to use carveout allocator. 358 * Grab the entire CMA chunk carved out in early startup in 359 * mach-msm: 360 */ 361 } else if (!msm_use_mmu(dev)) { 362 DRM_INFO("using %s VRAM carveout\n", vram); 363 size = memparse(vram, NULL); 364 } 365 366 if (size) { 367 unsigned long attrs = 0; 368 void *p; 369 370 priv->vram.size = size; 371 372 drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1); 373 spin_lock_init(&priv->vram.lock); 374 375 attrs |= DMA_ATTR_NO_KERNEL_MAPPING; 376 attrs |= DMA_ATTR_WRITE_COMBINE; 377 378 /* note that for no-kernel-mapping, the vaddr returned 379 * is bogus, but non-null if allocation succeeded: 380 */ 381 p = dma_alloc_attrs(dev->dev, size, 382 &priv->vram.paddr, GFP_KERNEL, attrs); 383 if (!p) { 384 DRM_DEV_ERROR(dev->dev, "failed to allocate VRAM\n"); 385 priv->vram.paddr = 0; 386 return -ENOMEM; 387 } 388 389 DRM_DEV_INFO(dev->dev, "VRAM: %08x->%08x\n", 390 (uint32_t)priv->vram.paddr, 391 (uint32_t)(priv->vram.paddr + size)); 392 } 393 394 return ret; 395} 396 397static int msm_drm_init(struct device *dev, struct drm_driver *drv) 398{ 399 struct platform_device *pdev = to_platform_device(dev); 400 struct drm_device *ddev; 401 struct msm_drm_private *priv; 402 struct msm_kms *kms; 403 struct msm_mdss *mdss; 404 int ret, i; 405 406 ddev = drm_dev_alloc(drv, dev); 407 if (IS_ERR(ddev)) { 408 DRM_DEV_ERROR(dev, "failed to allocate drm_device\n"); 409 return PTR_ERR(ddev); 410 } 411 412 platform_set_drvdata(pdev, ddev); 413 414 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 415 if (!priv) { 416 ret = -ENOMEM; 417 goto err_put_drm_dev; 418 } 419 420 ddev->dev_private = priv; 421 priv->dev = ddev; 422 423 switch (get_mdp_ver(pdev)) { 424 case KMS_MDP5: 425 ret = mdp5_mdss_init(ddev); 426 break; 427 case KMS_DPU: 428 ret = dpu_mdss_init(ddev); 429 break; 430 default: 431 ret = 0; 432 break; 433 } 434 if (ret) 435 goto err_free_priv; 436 437 mdss = priv->mdss; 438 439 priv->wq = alloc_ordered_workqueue("msm", 0); 440 441 INIT_WORK(&priv->free_work, msm_gem_free_work); 442 init_llist_head(&priv->free_list); 443 444 INIT_LIST_HEAD(&priv->inactive_list); 445 446 drm_mode_config_init(ddev); 447 448 ret = msm_init_vram(ddev); 449 if (ret) 450 goto err_destroy_mdss; 451 452 /* Bind all our sub-components: */ 453 ret = component_bind_all(dev, ddev); 454 if (ret) 455 goto err_destroy_mdss; 456 457 dma_set_max_seg_size(dev, UINT_MAX); 458 459 msm_gem_shrinker_init(ddev); 460 461 switch (get_mdp_ver(pdev)) { 462 case KMS_MDP4: 463 kms = mdp4_kms_init(ddev); 464 priv->kms = kms; 465 break; 466 case KMS_MDP5: 467 kms = mdp5_kms_init(ddev); 468 break; 469 case KMS_DPU: 470 kms = dpu_kms_init(ddev); 471 priv->kms = kms; 472 break; 473 default: 474 /* valid only for the dummy headless case, where of_node=NULL */ 475 WARN_ON(dev->of_node); 476 kms = NULL; 477 break; 478 } 479 480 if (IS_ERR(kms)) { 481 DRM_DEV_ERROR(dev, "failed to load kms\n"); 482 ret = PTR_ERR(kms); 483 priv->kms = NULL; 484 goto err_msm_uninit; 485 } 486 487 /* Enable normalization of plane zpos */ 488 ddev->mode_config.normalize_zpos = true; 489 490 if (kms) { 491 kms->dev = ddev; 492 ret = kms->funcs->hw_init(kms); 493 if (ret) { 494 DRM_DEV_ERROR(dev, "kms hw init failed: %d\n", ret); 495 goto err_msm_uninit; 496 } 497 } 498 499 ddev->mode_config.funcs = &mode_config_funcs; 500 ddev->mode_config.helper_private = &mode_config_helper_funcs; 501 502 for (i = 0; i < priv->num_crtcs; i++) { 503 /* initialize event thread */ 504 priv->event_thread[i].crtc_id = priv->crtcs[i]->base.id; 505 priv->event_thread[i].dev = ddev; 506 priv->event_thread[i].worker = kthread_create_worker(0, 507 "crtc_event:%d", priv->event_thread[i].crtc_id); 508 if (IS_ERR(priv->event_thread[i].worker)) { 509 ret = PTR_ERR(priv->event_thread[i].worker); 510 DRM_DEV_ERROR(dev, "failed to create crtc_event kthread\n"); 511 goto err_msm_uninit; 512 } 513 514 sched_set_fifo(priv->event_thread[i].worker->task); 515 } 516 517 ret = drm_vblank_init(ddev, priv->num_crtcs); 518 if (ret < 0) { 519 DRM_DEV_ERROR(dev, "failed to initialize vblank\n"); 520 goto err_msm_uninit; 521 } 522 523 if (kms) { 524 pm_runtime_get_sync(dev); 525 ret = drm_irq_install(ddev, kms->irq); 526 pm_runtime_put_sync(dev); 527 if (ret < 0) { 528 DRM_DEV_ERROR(dev, "failed to install IRQ handler\n"); 529 goto err_msm_uninit; 530 } 531 } 532 533 ret = drm_dev_register(ddev, 0); 534 if (ret) 535 goto err_msm_uninit; 536 537 drm_mode_config_reset(ddev); 538 539#ifdef CONFIG_DRM_FBDEV_EMULATION 540 if (kms && fbdev) 541 priv->fbdev = msm_fbdev_init(ddev); 542#endif 543 544 ret = msm_debugfs_late_init(ddev); 545 if (ret) 546 goto err_msm_uninit; 547 548 drm_kms_helper_poll_init(ddev); 549 550 return 0; 551 552err_msm_uninit: 553 msm_drm_uninit(dev); 554 return ret; 555err_destroy_mdss: 556 if (mdss && mdss->funcs) 557 mdss->funcs->destroy(ddev); 558err_free_priv: 559 kfree(priv); 560err_put_drm_dev: 561 drm_dev_put(ddev); 562 platform_set_drvdata(pdev, NULL); 563 return ret; 564} 565 566/* 567 * DRM operations: 568 */ 569 570static void load_gpu(struct drm_device *dev) 571{ 572 static DEFINE_MUTEX(init_lock); 573 struct msm_drm_private *priv = dev->dev_private; 574 575 mutex_lock(&init_lock); 576 577 if (!priv->gpu) 578 priv->gpu = adreno_load_gpu(dev); 579 580 mutex_unlock(&init_lock); 581} 582 583static int context_init(struct drm_device *dev, struct drm_file *file) 584{ 585 static atomic_t ident = ATOMIC_INIT(0); 586 struct msm_drm_private *priv = dev->dev_private; 587 struct msm_file_private *ctx; 588 589 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); 590 if (!ctx) 591 return -ENOMEM; 592 593 kref_init(&ctx->ref); 594 msm_submitqueue_init(dev, ctx); 595 596 ctx->aspace = msm_gpu_create_private_address_space(priv->gpu, current); 597 file->driver_priv = ctx; 598 599 ctx->seqno = atomic_inc_return(&ident); 600 601 return 0; 602} 603 604static int msm_open(struct drm_device *dev, struct drm_file *file) 605{ 606 /* For now, load gpu on open.. to avoid the requirement of having 607 * firmware in the initrd. 608 */ 609 load_gpu(dev); 610 611 return context_init(dev, file); 612} 613 614static void context_close(struct msm_file_private *ctx) 615{ 616 msm_submitqueue_close(ctx); 617 msm_file_private_put(ctx); 618} 619 620static void msm_postclose(struct drm_device *dev, struct drm_file *file) 621{ 622 struct msm_drm_private *priv = dev->dev_private; 623 struct msm_file_private *ctx = file->driver_priv; 624 625 mutex_lock(&dev->struct_mutex); 626 if (ctx == priv->lastctx) 627 priv->lastctx = NULL; 628 mutex_unlock(&dev->struct_mutex); 629 630 context_close(ctx); 631} 632 633static irqreturn_t msm_irq(int irq, void *arg) 634{ 635 struct drm_device *dev = arg; 636 struct msm_drm_private *priv = dev->dev_private; 637 struct msm_kms *kms = priv->kms; 638 BUG_ON(!kms); 639 return kms->funcs->irq(kms); 640} 641 642static void msm_irq_preinstall(struct drm_device *dev) 643{ 644 struct msm_drm_private *priv = dev->dev_private; 645 struct msm_kms *kms = priv->kms; 646 BUG_ON(!kms); 647 kms->funcs->irq_preinstall(kms); 648} 649 650static int msm_irq_postinstall(struct drm_device *dev) 651{ 652 struct msm_drm_private *priv = dev->dev_private; 653 struct msm_kms *kms = priv->kms; 654 BUG_ON(!kms); 655 656 if (kms->funcs->irq_postinstall) 657 return kms->funcs->irq_postinstall(kms); 658 659 return 0; 660} 661 662static void msm_irq_uninstall(struct drm_device *dev) 663{ 664 struct msm_drm_private *priv = dev->dev_private; 665 struct msm_kms *kms = priv->kms; 666 BUG_ON(!kms); 667 kms->funcs->irq_uninstall(kms); 668} 669 670int msm_crtc_enable_vblank(struct drm_crtc *crtc) 671{ 672 struct drm_device *dev = crtc->dev; 673 unsigned int pipe = crtc->index; 674 struct msm_drm_private *priv = dev->dev_private; 675 struct msm_kms *kms = priv->kms; 676 if (!kms) 677 return -ENXIO; 678 DBG("dev=%p, crtc=%u", dev, pipe); 679 return vblank_ctrl_queue_work(priv, pipe, true); 680} 681 682void msm_crtc_disable_vblank(struct drm_crtc *crtc) 683{ 684 struct drm_device *dev = crtc->dev; 685 unsigned int pipe = crtc->index; 686 struct msm_drm_private *priv = dev->dev_private; 687 struct msm_kms *kms = priv->kms; 688 if (!kms) 689 return; 690 DBG("dev=%p, crtc=%u", dev, pipe); 691 vblank_ctrl_queue_work(priv, pipe, false); 692} 693 694/* 695 * DRM ioctls: 696 */ 697 698static int msm_ioctl_get_param(struct drm_device *dev, void *data, 699 struct drm_file *file) 700{ 701 struct msm_drm_private *priv = dev->dev_private; 702 struct drm_msm_param *args = data; 703 struct msm_gpu *gpu; 704 705 /* for now, we just have 3d pipe.. eventually this would need to 706 * be more clever to dispatch to appropriate gpu module: 707 */ 708 if (args->pipe != MSM_PIPE_3D0) 709 return -EINVAL; 710 711 gpu = priv->gpu; 712 713 if (!gpu) 714 return -ENXIO; 715 716 return gpu->funcs->get_param(gpu, args->param, &args->value); 717} 718 719static int msm_ioctl_gem_new(struct drm_device *dev, void *data, 720 struct drm_file *file) 721{ 722 struct drm_msm_gem_new *args = data; 723 724 if (args->flags & ~MSM_BO_FLAGS) { 725 DRM_ERROR("invalid flags: %08x\n", args->flags); 726 return -EINVAL; 727 } 728 729 return msm_gem_new_handle(dev, file, args->size, 730 args->flags, &args->handle, NULL); 731} 732 733static inline ktime_t to_ktime(struct drm_msm_timespec timeout) 734{ 735 return ktime_set(timeout.tv_sec, timeout.tv_nsec); 736} 737 738static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data, 739 struct drm_file *file) 740{ 741 struct drm_msm_gem_cpu_prep *args = data; 742 struct drm_gem_object *obj; 743 ktime_t timeout = to_ktime(args->timeout); 744 int ret; 745 746 if (args->op & ~MSM_PREP_FLAGS) { 747 DRM_ERROR("invalid op: %08x\n", args->op); 748 return -EINVAL; 749 } 750 751 obj = drm_gem_object_lookup(file, args->handle); 752 if (!obj) 753 return -ENOENT; 754 755 ret = msm_gem_cpu_prep(obj, args->op, &timeout); 756 757 drm_gem_object_put(obj); 758 759 return ret; 760} 761 762static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data, 763 struct drm_file *file) 764{ 765 struct drm_msm_gem_cpu_fini *args = data; 766 struct drm_gem_object *obj; 767 int ret; 768 769 obj = drm_gem_object_lookup(file, args->handle); 770 if (!obj) 771 return -ENOENT; 772 773 ret = msm_gem_cpu_fini(obj); 774 775 drm_gem_object_put(obj); 776 777 return ret; 778} 779 780static int msm_ioctl_gem_info_iova(struct drm_device *dev, 781 struct drm_file *file, struct drm_gem_object *obj, 782 uint64_t *iova) 783{ 784 struct msm_drm_private *priv = dev->dev_private; 785 struct msm_file_private *ctx = file->driver_priv; 786 787 if (!priv->gpu) 788 return -EINVAL; 789 790 /* 791 * Don't pin the memory here - just get an address so that userspace can 792 * be productive 793 */ 794 return msm_gem_get_iova(obj, ctx->aspace, iova); 795} 796 797static int msm_ioctl_gem_info(struct drm_device *dev, void *data, 798 struct drm_file *file) 799{ 800 struct drm_msm_gem_info *args = data; 801 struct drm_gem_object *obj; 802 struct msm_gem_object *msm_obj; 803 int i, ret = 0; 804 805 if (args->pad) 806 return -EINVAL; 807 808 switch (args->info) { 809 case MSM_INFO_GET_OFFSET: 810 case MSM_INFO_GET_IOVA: 811 /* value returned as immediate, not pointer, so len==0: */ 812 if (args->len) 813 return -EINVAL; 814 break; 815 case MSM_INFO_SET_NAME: 816 case MSM_INFO_GET_NAME: 817 break; 818 default: 819 return -EINVAL; 820 } 821 822 obj = drm_gem_object_lookup(file, args->handle); 823 if (!obj) 824 return -ENOENT; 825 826 msm_obj = to_msm_bo(obj); 827 828 switch (args->info) { 829 case MSM_INFO_GET_OFFSET: 830 args->value = msm_gem_mmap_offset(obj); 831 break; 832 case MSM_INFO_GET_IOVA: 833 ret = msm_ioctl_gem_info_iova(dev, file, obj, &args->value); 834 break; 835 case MSM_INFO_SET_NAME: 836 /* length check should leave room for terminating null: */ 837 if (args->len >= sizeof(msm_obj->name)) { 838 ret = -EINVAL; 839 break; 840 } 841 if (copy_from_user(msm_obj->name, u64_to_user_ptr(args->value), 842 args->len)) { 843 msm_obj->name[0] = '\0'; 844 ret = -EFAULT; 845 break; 846 } 847 msm_obj->name[args->len] = '\0'; 848 for (i = 0; i < args->len; i++) { 849 if (!isprint(msm_obj->name[i])) { 850 msm_obj->name[i] = '\0'; 851 break; 852 } 853 } 854 break; 855 case MSM_INFO_GET_NAME: 856 if (args->value && (args->len < strlen(msm_obj->name))) { 857 ret = -EINVAL; 858 break; 859 } 860 args->len = strlen(msm_obj->name); 861 if (args->value) { 862 if (copy_to_user(u64_to_user_ptr(args->value), 863 msm_obj->name, args->len)) 864 ret = -EFAULT; 865 } 866 break; 867 } 868 869 drm_gem_object_put(obj); 870 871 return ret; 872} 873 874static int msm_ioctl_wait_fence(struct drm_device *dev, void *data, 875 struct drm_file *file) 876{ 877 struct msm_drm_private *priv = dev->dev_private; 878 struct drm_msm_wait_fence *args = data; 879 ktime_t timeout = to_ktime(args->timeout); 880 struct msm_gpu_submitqueue *queue; 881 struct msm_gpu *gpu = priv->gpu; 882 int ret; 883 884 if (args->pad) { 885 DRM_ERROR("invalid pad: %08x\n", args->pad); 886 return -EINVAL; 887 } 888 889 if (!gpu) 890 return 0; 891 892 queue = msm_submitqueue_get(file->driver_priv, args->queueid); 893 if (!queue) 894 return -ENOENT; 895 896 ret = msm_wait_fence(gpu->rb[queue->prio]->fctx, args->fence, &timeout, 897 true); 898 899 msm_submitqueue_put(queue); 900 return ret; 901} 902 903static int msm_ioctl_gem_madvise(struct drm_device *dev, void *data, 904 struct drm_file *file) 905{ 906 struct drm_msm_gem_madvise *args = data; 907 struct drm_gem_object *obj; 908 int ret; 909 910 switch (args->madv) { 911 case MSM_MADV_DONTNEED: 912 case MSM_MADV_WILLNEED: 913 break; 914 default: 915 return -EINVAL; 916 } 917 918 ret = mutex_lock_interruptible(&dev->struct_mutex); 919 if (ret) 920 return ret; 921 922 obj = drm_gem_object_lookup(file, args->handle); 923 if (!obj) { 924 ret = -ENOENT; 925 goto unlock; 926 } 927 928 ret = msm_gem_madvise(obj, args->madv); 929 if (ret >= 0) { 930 args->retained = ret; 931 ret = 0; 932 } 933 934 drm_gem_object_put_locked(obj); 935 936unlock: 937 mutex_unlock(&dev->struct_mutex); 938 return ret; 939} 940 941 942static int msm_ioctl_submitqueue_new(struct drm_device *dev, void *data, 943 struct drm_file *file) 944{ 945 struct drm_msm_submitqueue *args = data; 946 947 if (args->flags & ~MSM_SUBMITQUEUE_FLAGS) 948 return -EINVAL; 949 950 return msm_submitqueue_create(dev, file->driver_priv, args->prio, 951 args->flags, &args->id); 952} 953 954static int msm_ioctl_submitqueue_query(struct drm_device *dev, void *data, 955 struct drm_file *file) 956{ 957 return msm_submitqueue_query(dev, file->driver_priv, data); 958} 959 960static int msm_ioctl_submitqueue_close(struct drm_device *dev, void *data, 961 struct drm_file *file) 962{ 963 u32 id = *(u32 *) data; 964 965 return msm_submitqueue_remove(file->driver_priv, id); 966} 967 968static const struct drm_ioctl_desc msm_ioctls[] = { 969 DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_RENDER_ALLOW), 970 DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_RENDER_ALLOW), 971 DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_RENDER_ALLOW), 972 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_RENDER_ALLOW), 973 DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_RENDER_ALLOW), 974 DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_RENDER_ALLOW), 975 DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_RENDER_ALLOW), 976 DRM_IOCTL_DEF_DRV(MSM_GEM_MADVISE, msm_ioctl_gem_madvise, DRM_RENDER_ALLOW), 977 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new, DRM_RENDER_ALLOW), 978 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close, DRM_RENDER_ALLOW), 979 DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query, DRM_RENDER_ALLOW), 980}; 981 982static const struct vm_operations_struct vm_ops = { 983 .fault = msm_gem_fault, 984 .open = drm_gem_vm_open, 985 .close = drm_gem_vm_close, 986}; 987 988static const struct file_operations fops = { 989 .owner = THIS_MODULE, 990 .open = drm_open, 991 .release = drm_release, 992 .unlocked_ioctl = drm_ioctl, 993 .compat_ioctl = drm_compat_ioctl, 994 .poll = drm_poll, 995 .read = drm_read, 996 .llseek = no_llseek, 997 .mmap = msm_gem_mmap, 998}; 999 1000static struct drm_driver msm_driver = { 1001 .driver_features = DRIVER_GEM | 1002 DRIVER_RENDER | 1003 DRIVER_ATOMIC | 1004 DRIVER_MODESET | 1005 DRIVER_SYNCOBJ, 1006 .open = msm_open, 1007 .postclose = msm_postclose, 1008 .lastclose = drm_fb_helper_lastclose, 1009 .irq_handler = msm_irq, 1010 .irq_preinstall = msm_irq_preinstall, 1011 .irq_postinstall = msm_irq_postinstall, 1012 .irq_uninstall = msm_irq_uninstall, 1013 .gem_free_object_unlocked = msm_gem_free_object, 1014 .gem_vm_ops = &vm_ops, 1015 .dumb_create = msm_gem_dumb_create, 1016 .dumb_map_offset = msm_gem_dumb_map_offset, 1017 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 1018 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 1019 .gem_prime_pin = msm_gem_prime_pin, 1020 .gem_prime_unpin = msm_gem_prime_unpin, 1021 .gem_prime_get_sg_table = msm_gem_prime_get_sg_table, 1022 .gem_prime_import_sg_table = msm_gem_prime_import_sg_table, 1023 .gem_prime_vmap = msm_gem_prime_vmap, 1024 .gem_prime_vunmap = msm_gem_prime_vunmap, 1025 .gem_prime_mmap = msm_gem_prime_mmap, 1026#ifdef CONFIG_DEBUG_FS 1027 .debugfs_init = msm_debugfs_init, 1028#endif 1029 .ioctls = msm_ioctls, 1030 .num_ioctls = ARRAY_SIZE(msm_ioctls), 1031 .fops = &fops, 1032 .name = "msm", 1033 .desc = "MSM Snapdragon DRM", 1034 .date = "20130625", 1035 .major = MSM_VERSION_MAJOR, 1036 .minor = MSM_VERSION_MINOR, 1037 .patchlevel = MSM_VERSION_PATCHLEVEL, 1038}; 1039 1040static int __maybe_unused msm_runtime_suspend(struct device *dev) 1041{ 1042 struct drm_device *ddev = dev_get_drvdata(dev); 1043 struct msm_drm_private *priv = ddev->dev_private; 1044 struct msm_mdss *mdss = priv->mdss; 1045 1046 DBG(""); 1047 1048 if (mdss && mdss->funcs) 1049 return mdss->funcs->disable(mdss); 1050 1051 return 0; 1052} 1053 1054static int __maybe_unused msm_runtime_resume(struct device *dev) 1055{ 1056 struct drm_device *ddev = dev_get_drvdata(dev); 1057 struct msm_drm_private *priv = ddev->dev_private; 1058 struct msm_mdss *mdss = priv->mdss; 1059 1060 DBG(""); 1061 1062 if (mdss && mdss->funcs) 1063 return mdss->funcs->enable(mdss); 1064 1065 return 0; 1066} 1067 1068static int __maybe_unused msm_pm_suspend(struct device *dev) 1069{ 1070 1071 if (pm_runtime_suspended(dev)) 1072 return 0; 1073 1074 return msm_runtime_suspend(dev); 1075} 1076 1077static int __maybe_unused msm_pm_resume(struct device *dev) 1078{ 1079 if (pm_runtime_suspended(dev)) 1080 return 0; 1081 1082 return msm_runtime_resume(dev); 1083} 1084 1085static int __maybe_unused msm_pm_prepare(struct device *dev) 1086{ 1087 struct drm_device *ddev = dev_get_drvdata(dev); 1088 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1089 1090 if (!priv || !priv->kms) 1091 return 0; 1092 1093 return drm_mode_config_helper_suspend(ddev); 1094} 1095 1096static void __maybe_unused msm_pm_complete(struct device *dev) 1097{ 1098 struct drm_device *ddev = dev_get_drvdata(dev); 1099 struct msm_drm_private *priv = ddev ? ddev->dev_private : NULL; 1100 1101 if (!priv || !priv->kms) 1102 return; 1103 1104 drm_mode_config_helper_resume(ddev); 1105} 1106 1107static const struct dev_pm_ops msm_pm_ops = { 1108 SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume) 1109 SET_RUNTIME_PM_OPS(msm_runtime_suspend, msm_runtime_resume, NULL) 1110 .prepare = msm_pm_prepare, 1111 .complete = msm_pm_complete, 1112}; 1113 1114/* 1115 * Componentized driver support: 1116 */ 1117 1118/* 1119 * NOTE: duplication of the same code as exynos or imx (or probably any other). 1120 * so probably some room for some helpers 1121 */ 1122static int compare_of(struct device *dev, void *data) 1123{ 1124 return dev->of_node == data; 1125} 1126 1127/* 1128 * Identify what components need to be added by parsing what remote-endpoints 1129 * our MDP output ports are connected to. In the case of LVDS on MDP4, there 1130 * is no external component that we need to add since LVDS is within MDP4 1131 * itself. 1132 */ 1133static int add_components_mdp(struct device *mdp_dev, 1134 struct component_match **matchptr) 1135{ 1136 struct device_node *np = mdp_dev->of_node; 1137 struct device_node *ep_node; 1138 struct device *master_dev; 1139 1140 /* 1141 * on MDP4 based platforms, the MDP platform device is the component 1142 * master that adds other display interface components to itself. 1143 * 1144 * on MDP5 based platforms, the MDSS platform device is the component 1145 * master that adds MDP5 and other display interface components to 1146 * itself. 1147 */ 1148 if (of_device_is_compatible(np, "qcom,mdp4")) 1149 master_dev = mdp_dev; 1150 else 1151 master_dev = mdp_dev->parent; 1152 1153 for_each_endpoint_of_node(np, ep_node) { 1154 struct device_node *intf; 1155 struct of_endpoint ep; 1156 int ret; 1157 1158 ret = of_graph_parse_endpoint(ep_node, &ep); 1159 if (ret) { 1160 DRM_DEV_ERROR(mdp_dev, "unable to parse port endpoint\n"); 1161 of_node_put(ep_node); 1162 return ret; 1163 } 1164 1165 /* 1166 * The LCDC/LVDS port on MDP4 is a speacial case where the 1167 * remote-endpoint isn't a component that we need to add 1168 */ 1169 if (of_device_is_compatible(np, "qcom,mdp4") && 1170 ep.port == 0) 1171 continue; 1172 1173 /* 1174 * It's okay if some of the ports don't have a remote endpoint 1175 * specified. It just means that the port isn't connected to 1176 * any external interface. 1177 */ 1178 intf = of_graph_get_remote_port_parent(ep_node); 1179 if (!intf) 1180 continue; 1181 1182 if (of_device_is_available(intf)) 1183 drm_of_component_match_add(master_dev, matchptr, 1184 compare_of, intf); 1185 1186 of_node_put(intf); 1187 } 1188 1189 return 0; 1190} 1191 1192static int compare_name_mdp(struct device *dev, void *data) 1193{ 1194 return (strstr(dev_name(dev), "mdp") != NULL); 1195} 1196 1197static int add_display_components(struct device *dev, 1198 struct component_match **matchptr) 1199{ 1200 struct device *mdp_dev; 1201 int ret; 1202 1203 /* 1204 * MDP5/DPU based devices don't have a flat hierarchy. There is a top 1205 * level parent: MDSS, and children: MDP5/DPU, DSI, HDMI, eDP etc. 1206 * Populate the children devices, find the MDP5/DPU node, and then add 1207 * the interfaces to our components list. 1208 */ 1209 if (of_device_is_compatible(dev->of_node, "qcom,mdss") || 1210 of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") || 1211 of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) { 1212 ret = of_platform_populate(dev->of_node, NULL, NULL, dev); 1213 if (ret) { 1214 DRM_DEV_ERROR(dev, "failed to populate children devices\n"); 1215 return ret; 1216 } 1217 1218 mdp_dev = device_find_child(dev, NULL, compare_name_mdp); 1219 if (!mdp_dev) { 1220 DRM_DEV_ERROR(dev, "failed to find MDSS MDP node\n"); 1221 of_platform_depopulate(dev); 1222 return -ENODEV; 1223 } 1224 1225 put_device(mdp_dev); 1226 1227 /* add the MDP component itself */ 1228 drm_of_component_match_add(dev, matchptr, compare_of, 1229 mdp_dev->of_node); 1230 } else { 1231 /* MDP4 */ 1232 mdp_dev = dev; 1233 } 1234 1235 ret = add_components_mdp(mdp_dev, matchptr); 1236 if (ret) 1237 of_platform_depopulate(dev); 1238 1239 return ret; 1240} 1241 1242/* 1243 * We don't know what's the best binding to link the gpu with the drm device. 1244 * Fow now, we just hunt for all the possible gpus that we support, and add them 1245 * as components. 1246 */ 1247static const struct of_device_id msm_gpu_match[] = { 1248 { .compatible = "qcom,adreno" }, 1249 { .compatible = "qcom,adreno-3xx" }, 1250 { .compatible = "amd,imageon" }, 1251 { .compatible = "qcom,kgsl-3d0" }, 1252 { }, 1253}; 1254 1255static int add_gpu_components(struct device *dev, 1256 struct component_match **matchptr) 1257{ 1258 struct device_node *np; 1259 1260 np = of_find_matching_node(NULL, msm_gpu_match); 1261 if (!np) 1262 return 0; 1263 1264 if (of_device_is_available(np)) 1265 drm_of_component_match_add(dev, matchptr, compare_of, np); 1266 1267 of_node_put(np); 1268 1269 return 0; 1270} 1271 1272static int msm_drm_bind(struct device *dev) 1273{ 1274 return msm_drm_init(dev, &msm_driver); 1275} 1276 1277static void msm_drm_unbind(struct device *dev) 1278{ 1279 msm_drm_uninit(dev); 1280} 1281 1282static const struct component_master_ops msm_drm_ops = { 1283 .bind = msm_drm_bind, 1284 .unbind = msm_drm_unbind, 1285}; 1286 1287/* 1288 * Platform driver: 1289 */ 1290 1291static int msm_pdev_probe(struct platform_device *pdev) 1292{ 1293 struct component_match *match = NULL; 1294 int ret; 1295 1296 if (get_mdp_ver(pdev)) { 1297 ret = add_display_components(&pdev->dev, &match); 1298 if (ret) 1299 return ret; 1300 } 1301 1302 ret = add_gpu_components(&pdev->dev, &match); 1303 if (ret) 1304 goto fail; 1305 1306 /* on all devices that I am aware of, iommu's which can map 1307 * any address the cpu can see are used: 1308 */ 1309 ret = dma_set_mask_and_coherent(&pdev->dev, ~0); 1310 if (ret) 1311 goto fail; 1312 1313 ret = component_master_add_with_match(&pdev->dev, &msm_drm_ops, match); 1314 if (ret) 1315 goto fail; 1316 1317 return 0; 1318 1319fail: 1320 of_platform_depopulate(&pdev->dev); 1321 return ret; 1322} 1323 1324static int msm_pdev_remove(struct platform_device *pdev) 1325{ 1326 component_master_del(&pdev->dev, &msm_drm_ops); 1327 of_platform_depopulate(&pdev->dev); 1328 1329 return 0; 1330} 1331 1332static void msm_pdev_shutdown(struct platform_device *pdev) 1333{ 1334 struct drm_device *drm = platform_get_drvdata(pdev); 1335 struct msm_drm_private *priv = drm ? drm->dev_private : NULL; 1336 1337 if (!priv || !priv->kms) 1338 return; 1339 1340 drm_atomic_helper_shutdown(drm); 1341} 1342 1343static const struct of_device_id dt_match[] = { 1344 { .compatible = "qcom,mdp4", .data = (void *)KMS_MDP4 }, 1345 { .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 }, 1346 { .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU }, 1347 { .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU }, 1348 {} 1349}; 1350MODULE_DEVICE_TABLE(of, dt_match); 1351 1352static struct platform_driver msm_platform_driver = { 1353 .probe = msm_pdev_probe, 1354 .remove = msm_pdev_remove, 1355 .shutdown = msm_pdev_shutdown, 1356 .driver = { 1357 .name = "msm", 1358 .of_match_table = dt_match, 1359 .pm = &msm_pm_ops, 1360 }, 1361}; 1362 1363static int __init msm_drm_register(void) 1364{ 1365 if (!modeset) 1366 return -EINVAL; 1367 1368 DBG("init"); 1369 msm_mdp_register(); 1370 msm_dpu_register(); 1371 msm_dsi_register(); 1372 msm_edp_register(); 1373 msm_hdmi_register(); 1374 msm_dp_register(); 1375 adreno_register(); 1376 return platform_driver_register(&msm_platform_driver); 1377} 1378 1379static void __exit msm_drm_unregister(void) 1380{ 1381 DBG("fini"); 1382 platform_driver_unregister(&msm_platform_driver); 1383 msm_dp_unregister(); 1384 msm_hdmi_unregister(); 1385 adreno_unregister(); 1386 msm_edp_unregister(); 1387 msm_dsi_unregister(); 1388 msm_mdp_unregister(); 1389 msm_dpu_unregister(); 1390} 1391 1392module_init(msm_drm_register); 1393module_exit(msm_drm_unregister); 1394 1395MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 1396MODULE_DESCRIPTION("MSM DRM Driver"); 1397MODULE_LICENSE("GPL"); 1398