1// SPDX-License-Identifier: GPL-2.0-only 2/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved. 3 */ 4 5#include "hdmi.h" 6#include <linux/qcom_scm.h> 7 8#define HDCP_REG_ENABLE 0x01 9#define HDCP_REG_DISABLE 0x00 10#define HDCP_PORT_ADDR 0x74 11 12#define HDCP_INT_STATUS_MASK ( \ 13 HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT | \ 14 HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT | \ 15 HDMI_HDCP_INT_CTRL_AUTH_XFER_REQ_INT | \ 16 HDMI_HDCP_INT_CTRL_AUTH_XFER_DONE_INT) 17 18#define AUTH_WORK_RETRIES_TIME 100 19#define AUTH_RETRIES_TIME 30 20 21/* QFPROM Registers for HDMI/HDCP */ 22#define QFPROM_RAW_FEAT_CONFIG_ROW0_LSB 0x000000F8 23#define QFPROM_RAW_FEAT_CONFIG_ROW0_MSB 0x000000FC 24#define HDCP_KSV_LSB 0x000060D8 25#define HDCP_KSV_MSB 0x000060DC 26 27enum DS_TYPE { /* type of downstream device */ 28 DS_UNKNOWN, 29 DS_RECEIVER, 30 DS_REPEATER, 31}; 32 33enum hdmi_hdcp_state { 34 HDCP_STATE_NO_AKSV, 35 HDCP_STATE_INACTIVE, 36 HDCP_STATE_AUTHENTICATING, 37 HDCP_STATE_AUTHENTICATED, 38 HDCP_STATE_AUTH_FAILED 39}; 40 41struct hdmi_hdcp_reg_data { 42 u32 reg_id; 43 u32 off; 44 char *name; 45 u32 reg_val; 46}; 47 48struct hdmi_hdcp_ctrl { 49 struct hdmi *hdmi; 50 u32 auth_retries; 51 bool tz_hdcp; 52 enum hdmi_hdcp_state hdcp_state; 53 struct work_struct hdcp_auth_work; 54 struct work_struct hdcp_reauth_work; 55 56#define AUTH_ABORT_EV 1 57#define AUTH_RESULT_RDY_EV 2 58 unsigned long auth_event; 59 wait_queue_head_t auth_event_queue; 60 61 u32 ksv_fifo_w_index; 62 /* 63 * store aksv from qfprom 64 */ 65 u32 aksv_lsb; 66 u32 aksv_msb; 67 bool aksv_valid; 68 u32 ds_type; 69 u32 bksv_lsb; 70 u32 bksv_msb; 71 u8 dev_count; 72 u8 depth; 73 u8 ksv_list[5 * 127]; 74 bool max_cascade_exceeded; 75 bool max_dev_exceeded; 76}; 77 78static int msm_hdmi_ddc_read(struct hdmi *hdmi, u16 addr, u8 offset, 79 u8 *data, u16 data_len) 80{ 81 int rc; 82 int retry = 5; 83 struct i2c_msg msgs[] = { 84 { 85 .addr = addr >> 1, 86 .flags = 0, 87 .len = 1, 88 .buf = &offset, 89 }, { 90 .addr = addr >> 1, 91 .flags = I2C_M_RD, 92 .len = data_len, 93 .buf = data, 94 } 95 }; 96 97 DBG("Start DDC read"); 98retry: 99 rc = i2c_transfer(hdmi->i2c, msgs, 2); 100 101 retry--; 102 if (rc == 2) 103 rc = 0; 104 else if (retry > 0) 105 goto retry; 106 else 107 rc = -EIO; 108 109 DBG("End DDC read %d", rc); 110 111 return rc; 112} 113 114#define HDCP_DDC_WRITE_MAX_BYTE_NUM 32 115 116static int msm_hdmi_ddc_write(struct hdmi *hdmi, u16 addr, u8 offset, 117 u8 *data, u16 data_len) 118{ 119 int rc; 120 int retry = 10; 121 u8 buf[HDCP_DDC_WRITE_MAX_BYTE_NUM]; 122 struct i2c_msg msgs[] = { 123 { 124 .addr = addr >> 1, 125 .flags = 0, 126 .len = 1, 127 } 128 }; 129 130 DBG("Start DDC write"); 131 if (data_len > (HDCP_DDC_WRITE_MAX_BYTE_NUM - 1)) { 132 pr_err("%s: write size too big\n", __func__); 133 return -ERANGE; 134 } 135 136 buf[0] = offset; 137 memcpy(&buf[1], data, data_len); 138 msgs[0].buf = buf; 139 msgs[0].len = data_len + 1; 140retry: 141 rc = i2c_transfer(hdmi->i2c, msgs, 1); 142 143 retry--; 144 if (rc == 1) 145 rc = 0; 146 else if (retry > 0) 147 goto retry; 148 else 149 rc = -EIO; 150 151 DBG("End DDC write %d", rc); 152 153 return rc; 154} 155 156static int msm_hdmi_hdcp_scm_wr(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 *preg, 157 u32 *pdata, u32 count) 158{ 159 struct hdmi *hdmi = hdcp_ctrl->hdmi; 160 struct qcom_scm_hdcp_req scm_buf[QCOM_SCM_HDCP_MAX_REQ_CNT]; 161 u32 resp, phy_addr, idx = 0; 162 int i, ret = 0; 163 164 WARN_ON(!pdata || !preg || (count == 0)); 165 166 if (hdcp_ctrl->tz_hdcp) { 167 phy_addr = (u32)hdmi->mmio_phy_addr; 168 169 while (count) { 170 memset(scm_buf, 0, sizeof(scm_buf)); 171 for (i = 0; i < count && i < QCOM_SCM_HDCP_MAX_REQ_CNT; 172 i++) { 173 scm_buf[i].addr = phy_addr + preg[idx]; 174 scm_buf[i].val = pdata[idx]; 175 idx++; 176 } 177 ret = qcom_scm_hdcp_req(scm_buf, i, &resp); 178 179 if (ret || resp) { 180 pr_err("%s: error: scm_call ret=%d resp=%u\n", 181 __func__, ret, resp); 182 ret = -EINVAL; 183 break; 184 } 185 186 count -= i; 187 } 188 } else { 189 for (i = 0; i < count; i++) 190 hdmi_write(hdmi, preg[i], pdata[i]); 191 } 192 193 return ret; 194} 195 196void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) 197{ 198 struct hdmi *hdmi = hdcp_ctrl->hdmi; 199 u32 reg_val, hdcp_int_status; 200 unsigned long flags; 201 202 spin_lock_irqsave(&hdmi->reg_lock, flags); 203 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_INT_CTRL); 204 hdcp_int_status = reg_val & HDCP_INT_STATUS_MASK; 205 if (!hdcp_int_status) { 206 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 207 return; 208 } 209 /* Clear Interrupts */ 210 reg_val |= hdcp_int_status << 1; 211 /* Clear AUTH_FAIL_INFO as well */ 212 if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT) 213 reg_val |= HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK; 214 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, reg_val); 215 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 216 217 DBG("hdcp irq %x", hdcp_int_status); 218 219 if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_INT) { 220 pr_info("%s:AUTH_SUCCESS_INT received\n", __func__); 221 if (HDCP_STATE_AUTHENTICATING == hdcp_ctrl->hdcp_state) { 222 set_bit(AUTH_RESULT_RDY_EV, &hdcp_ctrl->auth_event); 223 wake_up_all(&hdcp_ctrl->auth_event_queue); 224 } 225 } 226 227 if (hdcp_int_status & HDMI_HDCP_INT_CTRL_AUTH_FAIL_INT) { 228 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 229 pr_info("%s: AUTH_FAIL_INT rcvd, LINK0_STATUS=0x%08x\n", 230 __func__, reg_val); 231 if (HDCP_STATE_AUTHENTICATED == hdcp_ctrl->hdcp_state) 232 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_reauth_work); 233 else if (HDCP_STATE_AUTHENTICATING == 234 hdcp_ctrl->hdcp_state) { 235 set_bit(AUTH_RESULT_RDY_EV, &hdcp_ctrl->auth_event); 236 wake_up_all(&hdcp_ctrl->auth_event_queue); 237 } 238 } 239} 240 241static int msm_hdmi_hdcp_msleep(struct hdmi_hdcp_ctrl *hdcp_ctrl, u32 ms, u32 ev) 242{ 243 int rc; 244 245 rc = wait_event_timeout(hdcp_ctrl->auth_event_queue, 246 !!test_bit(ev, &hdcp_ctrl->auth_event), 247 msecs_to_jiffies(ms)); 248 if (rc) { 249 pr_info("%s: msleep is canceled by event %d\n", 250 __func__, ev); 251 clear_bit(ev, &hdcp_ctrl->auth_event); 252 return -ECANCELED; 253 } 254 255 return 0; 256} 257 258static int msm_hdmi_hdcp_read_validate_aksv(struct hdmi_hdcp_ctrl *hdcp_ctrl) 259{ 260 struct hdmi *hdmi = hdcp_ctrl->hdmi; 261 262 /* Fetch aksv from QFPROM, this info should be public. */ 263 hdcp_ctrl->aksv_lsb = hdmi_qfprom_read(hdmi, HDCP_KSV_LSB); 264 hdcp_ctrl->aksv_msb = hdmi_qfprom_read(hdmi, HDCP_KSV_MSB); 265 266 /* check there are 20 ones in AKSV */ 267 if ((hweight32(hdcp_ctrl->aksv_lsb) + hweight32(hdcp_ctrl->aksv_msb)) 268 != 20) { 269 pr_err("%s: AKSV QFPROM doesn't have 20 1's, 20 0's\n", 270 __func__); 271 pr_err("%s: QFPROM AKSV chk failed (AKSV=%02x%08x)\n", 272 __func__, hdcp_ctrl->aksv_msb, 273 hdcp_ctrl->aksv_lsb); 274 return -EINVAL; 275 } 276 DBG("AKSV=%02x%08x", hdcp_ctrl->aksv_msb, hdcp_ctrl->aksv_lsb); 277 278 return 0; 279} 280 281static int msm_reset_hdcp_ddc_failures(struct hdmi_hdcp_ctrl *hdcp_ctrl) 282{ 283 struct hdmi *hdmi = hdcp_ctrl->hdmi; 284 u32 reg_val, failure, nack0; 285 int rc = 0; 286 287 /* Check for any DDC transfer failures */ 288 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); 289 failure = reg_val & HDMI_HDCP_DDC_STATUS_FAILED; 290 nack0 = reg_val & HDMI_HDCP_DDC_STATUS_NACK0; 291 DBG("HDCP_DDC_STATUS=0x%x, FAIL=%d, NACK0=%d", 292 reg_val, failure, nack0); 293 294 if (failure) { 295 /* 296 * Indicates that the last HDCP HW DDC transfer failed. 297 * This occurs when a transfer is attempted with HDCP DDC 298 * disabled (HDCP_DDC_DISABLE=1) or the number of retries 299 * matches HDCP_DDC_RETRY_CNT. 300 * Failure occurred, let's clear it. 301 */ 302 DBG("DDC failure detected"); 303 304 /* First, Disable DDC */ 305 hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_0, 306 HDMI_HDCP_DDC_CTRL_0_DISABLE); 307 308 /* ACK the Failure to Clear it */ 309 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_CTRL_1); 310 reg_val |= HDMI_HDCP_DDC_CTRL_1_FAILED_ACK; 311 hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_1, reg_val); 312 313 /* Check if the FAILURE got Cleared */ 314 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); 315 if (reg_val & HDMI_HDCP_DDC_STATUS_FAILED) 316 pr_info("%s: Unable to clear HDCP DDC Failure\n", 317 __func__); 318 319 /* Re-Enable HDCP DDC */ 320 hdmi_write(hdmi, REG_HDMI_HDCP_DDC_CTRL_0, 0); 321 } 322 323 if (nack0) { 324 DBG("Before: HDMI_DDC_SW_STATUS=0x%08x", 325 hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS)); 326 /* Reset HDMI DDC software status */ 327 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); 328 reg_val |= HDMI_DDC_CTRL_SW_STATUS_RESET; 329 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); 330 331 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 332 333 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); 334 reg_val &= ~HDMI_DDC_CTRL_SW_STATUS_RESET; 335 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); 336 337 /* Reset HDMI DDC Controller */ 338 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); 339 reg_val |= HDMI_DDC_CTRL_SOFT_RESET; 340 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); 341 342 /* If previous msleep is aborted, skip this msleep */ 343 if (!rc) 344 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 345 346 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_CTRL); 347 reg_val &= ~HDMI_DDC_CTRL_SOFT_RESET; 348 hdmi_write(hdmi, REG_HDMI_DDC_CTRL, reg_val); 349 DBG("After: HDMI_DDC_SW_STATUS=0x%08x", 350 hdmi_read(hdmi, REG_HDMI_DDC_SW_STATUS)); 351 } 352 353 return rc; 354} 355 356static int msm_hdmi_hdcp_hw_ddc_clean(struct hdmi_hdcp_ctrl *hdcp_ctrl) 357{ 358 int rc; 359 u32 hdcp_ddc_status, ddc_hw_status; 360 u32 xfer_done, xfer_req, hw_done; 361 bool hw_not_ready; 362 u32 timeout_count; 363 struct hdmi *hdmi = hdcp_ctrl->hdmi; 364 365 if (hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS) == 0) 366 return 0; 367 368 /* Wait to be clean on DDC HW engine */ 369 timeout_count = 100; 370 do { 371 hdcp_ddc_status = hdmi_read(hdmi, REG_HDMI_HDCP_DDC_STATUS); 372 ddc_hw_status = hdmi_read(hdmi, REG_HDMI_DDC_HW_STATUS); 373 374 xfer_done = hdcp_ddc_status & HDMI_HDCP_DDC_STATUS_XFER_DONE; 375 xfer_req = hdcp_ddc_status & HDMI_HDCP_DDC_STATUS_XFER_REQ; 376 hw_done = ddc_hw_status & HDMI_DDC_HW_STATUS_DONE; 377 hw_not_ready = !xfer_done || xfer_req || !hw_done; 378 379 if (hw_not_ready) 380 break; 381 382 timeout_count--; 383 if (!timeout_count) { 384 pr_warn("%s: hw_ddc_clean failed\n", __func__); 385 return -ETIMEDOUT; 386 } 387 388 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 389 if (rc) 390 return rc; 391 } while (1); 392 393 return 0; 394} 395 396static void msm_hdmi_hdcp_reauth_work(struct work_struct *work) 397{ 398 struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work, 399 struct hdmi_hdcp_ctrl, hdcp_reauth_work); 400 struct hdmi *hdmi = hdcp_ctrl->hdmi; 401 unsigned long flags; 402 u32 reg_val; 403 404 DBG("HDCP REAUTH WORK"); 405 /* 406 * Disable HPD circuitry. 407 * This is needed to reset the HDCP cipher engine so that when we 408 * attempt a re-authentication, HW would clear the AN0_READY and 409 * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register 410 */ 411 spin_lock_irqsave(&hdmi->reg_lock, flags); 412 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); 413 reg_val &= ~HDMI_HPD_CTRL_ENABLE; 414 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); 415 416 /* Disable HDCP interrupts */ 417 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 0); 418 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 419 420 hdmi_write(hdmi, REG_HDMI_HDCP_RESET, 421 HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE); 422 423 /* Wait to be clean on DDC HW engine */ 424 if (msm_hdmi_hdcp_hw_ddc_clean(hdcp_ctrl)) { 425 pr_info("%s: reauth work aborted\n", __func__); 426 return; 427 } 428 429 /* Disable encryption and disable the HDCP block */ 430 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 0); 431 432 /* Enable HPD circuitry */ 433 spin_lock_irqsave(&hdmi->reg_lock, flags); 434 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); 435 reg_val |= HDMI_HPD_CTRL_ENABLE; 436 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); 437 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 438 439 /* 440 * Only retry defined times then abort current authenticating process 441 */ 442 if (++hdcp_ctrl->auth_retries == AUTH_RETRIES_TIME) { 443 hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; 444 hdcp_ctrl->auth_retries = 0; 445 pr_info("%s: abort reauthentication!\n", __func__); 446 447 return; 448 } 449 450 DBG("Queue AUTH WORK"); 451 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATING; 452 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work); 453} 454 455static int msm_hdmi_hdcp_auth_prepare(struct hdmi_hdcp_ctrl *hdcp_ctrl) 456{ 457 struct hdmi *hdmi = hdcp_ctrl->hdmi; 458 u32 link0_status; 459 u32 reg_val; 460 unsigned long flags; 461 int rc; 462 463 if (!hdcp_ctrl->aksv_valid) { 464 rc = msm_hdmi_hdcp_read_validate_aksv(hdcp_ctrl); 465 if (rc) { 466 pr_err("%s: ASKV validation failed\n", __func__); 467 hdcp_ctrl->hdcp_state = HDCP_STATE_NO_AKSV; 468 return -ENOTSUPP; 469 } 470 hdcp_ctrl->aksv_valid = true; 471 } 472 473 spin_lock_irqsave(&hdmi->reg_lock, flags); 474 /* disable HDMI Encrypt */ 475 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); 476 reg_val &= ~HDMI_CTRL_ENCRYPTED; 477 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); 478 479 /* Enabling Software DDC */ 480 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); 481 reg_val &= ~HDMI_DDC_ARBITRATION_HW_ARBITRATION; 482 hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); 483 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 484 485 /* 486 * Write AKSV read from QFPROM to the HDCP registers. 487 * This step is needed for HDCP authentication and must be 488 * written before enabling HDCP. 489 */ 490 hdmi_write(hdmi, REG_HDMI_HDCP_SW_LOWER_AKSV, hdcp_ctrl->aksv_lsb); 491 hdmi_write(hdmi, REG_HDMI_HDCP_SW_UPPER_AKSV, hdcp_ctrl->aksv_msb); 492 493 /* 494 * HDCP setup prior to enabling HDCP_CTRL. 495 * Setup seed values for random number An. 496 */ 497 hdmi_write(hdmi, REG_HDMI_HDCP_ENTROPY_CTRL0, 0xB1FFB0FF); 498 hdmi_write(hdmi, REG_HDMI_HDCP_ENTROPY_CTRL1, 0xF00DFACE); 499 500 /* Disable the RngCipher state */ 501 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL); 502 reg_val &= ~HDMI_HDCP_DEBUG_CTRL_RNG_CIPHER; 503 hdmi_write(hdmi, REG_HDMI_HDCP_DEBUG_CTRL, reg_val); 504 DBG("HDCP_DEBUG_CTRL=0x%08x", 505 hdmi_read(hdmi, REG_HDMI_HDCP_DEBUG_CTRL)); 506 507 /* 508 * Ensure that all register writes are completed before 509 * enabling HDCP cipher 510 */ 511 wmb(); 512 513 /* 514 * Enable HDCP 515 * This needs to be done as early as possible in order for the 516 * hardware to make An available to read 517 */ 518 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, HDMI_HDCP_CTRL_ENABLE); 519 520 /* 521 * If we had stale values for the An ready bit, it should most 522 * likely be cleared now after enabling HDCP cipher 523 */ 524 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 525 DBG("After enabling HDCP Link0_Status=0x%08x", link0_status); 526 if (!(link0_status & 527 (HDMI_HDCP_LINK0_STATUS_AN_0_READY | 528 HDMI_HDCP_LINK0_STATUS_AN_1_READY))) 529 DBG("An not ready after enabling HDCP"); 530 531 /* Clear any DDC failures from previous tries before enable HDCP*/ 532 rc = msm_reset_hdcp_ddc_failures(hdcp_ctrl); 533 534 return rc; 535} 536 537static void msm_hdmi_hdcp_auth_fail(struct hdmi_hdcp_ctrl *hdcp_ctrl) 538{ 539 struct hdmi *hdmi = hdcp_ctrl->hdmi; 540 u32 reg_val; 541 unsigned long flags; 542 543 DBG("hdcp auth failed, queue reauth work"); 544 /* clear HDMI Encrypt */ 545 spin_lock_irqsave(&hdmi->reg_lock, flags); 546 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); 547 reg_val &= ~HDMI_CTRL_ENCRYPTED; 548 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); 549 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 550 551 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTH_FAILED; 552 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_reauth_work); 553} 554 555static void msm_hdmi_hdcp_auth_done(struct hdmi_hdcp_ctrl *hdcp_ctrl) 556{ 557 struct hdmi *hdmi = hdcp_ctrl->hdmi; 558 u32 reg_val; 559 unsigned long flags; 560 561 /* 562 * Disable software DDC before going into part3 to make sure 563 * there is no Arbitration between software and hardware for DDC 564 */ 565 spin_lock_irqsave(&hdmi->reg_lock, flags); 566 reg_val = hdmi_read(hdmi, REG_HDMI_DDC_ARBITRATION); 567 reg_val |= HDMI_DDC_ARBITRATION_HW_ARBITRATION; 568 hdmi_write(hdmi, REG_HDMI_DDC_ARBITRATION, reg_val); 569 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 570 571 /* enable HDMI Encrypt */ 572 spin_lock_irqsave(&hdmi->reg_lock, flags); 573 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); 574 reg_val |= HDMI_CTRL_ENCRYPTED; 575 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); 576 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 577 578 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATED; 579 hdcp_ctrl->auth_retries = 0; 580} 581 582/* 583 * hdcp authenticating part 1 584 * Wait Key/An ready 585 * Read BCAPS from sink 586 * Write BCAPS and AKSV into HDCP engine 587 * Write An and AKSV to sink 588 * Read BKSV from sink and write into HDCP engine 589 */ 590static int msm_hdmi_hdcp_wait_key_an_ready(struct hdmi_hdcp_ctrl *hdcp_ctrl) 591{ 592 int rc; 593 struct hdmi *hdmi = hdcp_ctrl->hdmi; 594 u32 link0_status, keys_state; 595 u32 timeout_count; 596 bool an_ready; 597 598 /* Wait for HDCP keys to be checked and validated */ 599 timeout_count = 100; 600 do { 601 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 602 keys_state = (link0_status >> 28) & 0x7; 603 if (keys_state == HDCP_KEYS_STATE_VALID) 604 break; 605 606 DBG("Keys not ready(%d). s=%d, l0=%0x08x", 607 timeout_count, keys_state, link0_status); 608 609 timeout_count--; 610 if (!timeout_count) { 611 pr_err("%s: Wait key state timedout", __func__); 612 return -ETIMEDOUT; 613 } 614 615 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 616 if (rc) 617 return rc; 618 } while (1); 619 620 timeout_count = 100; 621 do { 622 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 623 an_ready = (link0_status & HDMI_HDCP_LINK0_STATUS_AN_0_READY) 624 && (link0_status & HDMI_HDCP_LINK0_STATUS_AN_1_READY); 625 if (an_ready) 626 break; 627 628 DBG("An not ready(%d). l0_status=0x%08x", 629 timeout_count, link0_status); 630 631 timeout_count--; 632 if (!timeout_count) { 633 pr_err("%s: Wait An timedout", __func__); 634 return -ETIMEDOUT; 635 } 636 637 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 638 if (rc) 639 return rc; 640 } while (1); 641 642 return 0; 643} 644 645static int msm_hdmi_hdcp_send_aksv_an(struct hdmi_hdcp_ctrl *hdcp_ctrl) 646{ 647 int rc = 0; 648 struct hdmi *hdmi = hdcp_ctrl->hdmi; 649 u32 link0_aksv_0, link0_aksv_1; 650 u32 link0_an[2]; 651 u8 aksv[5]; 652 653 /* Read An0 and An1 */ 654 link0_an[0] = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA5); 655 link0_an[1] = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA6); 656 657 /* Read AKSV */ 658 link0_aksv_0 = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA3); 659 link0_aksv_1 = hdmi_read(hdmi, REG_HDMI_HDCP_RCVPORT_DATA4); 660 661 DBG("Link ASKV=%08x%08x", link0_aksv_0, link0_aksv_1); 662 /* Copy An and AKSV to byte arrays for transmission */ 663 aksv[0] = link0_aksv_0 & 0xFF; 664 aksv[1] = (link0_aksv_0 >> 8) & 0xFF; 665 aksv[2] = (link0_aksv_0 >> 16) & 0xFF; 666 aksv[3] = (link0_aksv_0 >> 24) & 0xFF; 667 aksv[4] = link0_aksv_1 & 0xFF; 668 669 /* Write An to offset 0x18 */ 670 rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x18, (u8 *)link0_an, 671 (u16)sizeof(link0_an)); 672 if (rc) { 673 pr_err("%s:An write failed\n", __func__); 674 return rc; 675 } 676 DBG("Link0-An=%08x%08x", link0_an[0], link0_an[1]); 677 678 /* Write AKSV to offset 0x10 */ 679 rc = msm_hdmi_ddc_write(hdmi, HDCP_PORT_ADDR, 0x10, aksv, 5); 680 if (rc) { 681 pr_err("%s:AKSV write failed\n", __func__); 682 return rc; 683 } 684 DBG("Link0-AKSV=%02x%08x", link0_aksv_1 & 0xFF, link0_aksv_0); 685 686 return 0; 687} 688 689static int msm_hdmi_hdcp_recv_bksv(struct hdmi_hdcp_ctrl *hdcp_ctrl) 690{ 691 int rc = 0; 692 struct hdmi *hdmi = hdcp_ctrl->hdmi; 693 u8 bksv[5]; 694 u32 reg[2], data[2]; 695 696 /* Read BKSV at offset 0x00 */ 697 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x00, bksv, 5); 698 if (rc) { 699 pr_err("%s:BKSV read failed\n", __func__); 700 return rc; 701 } 702 703 hdcp_ctrl->bksv_lsb = bksv[0] | (bksv[1] << 8) | 704 (bksv[2] << 16) | (bksv[3] << 24); 705 hdcp_ctrl->bksv_msb = bksv[4]; 706 DBG(":BKSV=%02x%08x", hdcp_ctrl->bksv_msb, hdcp_ctrl->bksv_lsb); 707 708 /* check there are 20 ones in BKSV */ 709 if ((hweight32(hdcp_ctrl->bksv_lsb) + hweight32(hdcp_ctrl->bksv_msb)) 710 != 20) { 711 pr_err(": BKSV doesn't have 20 1's and 20 0's\n"); 712 pr_err(": BKSV chk fail. BKSV=%02x%02x%02x%02x%02x\n", 713 bksv[4], bksv[3], bksv[2], bksv[1], bksv[0]); 714 return -EINVAL; 715 } 716 717 /* Write BKSV read from sink to HDCP registers */ 718 reg[0] = REG_HDMI_HDCP_RCVPORT_DATA0; 719 data[0] = hdcp_ctrl->bksv_lsb; 720 reg[1] = REG_HDMI_HDCP_RCVPORT_DATA1; 721 data[1] = hdcp_ctrl->bksv_msb; 722 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2); 723 724 return rc; 725} 726 727static int msm_hdmi_hdcp_recv_bcaps(struct hdmi_hdcp_ctrl *hdcp_ctrl) 728{ 729 int rc = 0; 730 struct hdmi *hdmi = hdcp_ctrl->hdmi; 731 u32 reg, data; 732 u8 bcaps; 733 734 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1); 735 if (rc) { 736 pr_err("%s:BCAPS read failed\n", __func__); 737 return rc; 738 } 739 DBG("BCAPS=%02x", bcaps); 740 741 /* receiver (0), repeater (1) */ 742 hdcp_ctrl->ds_type = (bcaps & BIT(6)) ? DS_REPEATER : DS_RECEIVER; 743 744 /* Write BCAPS to the hardware */ 745 reg = REG_HDMI_HDCP_RCVPORT_DATA12; 746 data = (u32)bcaps; 747 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); 748 749 return rc; 750} 751 752static int msm_hdmi_hdcp_auth_part1_key_exchange(struct hdmi_hdcp_ctrl *hdcp_ctrl) 753{ 754 struct hdmi *hdmi = hdcp_ctrl->hdmi; 755 unsigned long flags; 756 int rc; 757 758 /* Wait for AKSV key and An ready */ 759 rc = msm_hdmi_hdcp_wait_key_an_ready(hdcp_ctrl); 760 if (rc) { 761 pr_err("%s: wait key and an ready failed\n", __func__); 762 return rc; 763 } 764 765 /* Read BCAPS and send to HDCP engine */ 766 rc = msm_hdmi_hdcp_recv_bcaps(hdcp_ctrl); 767 if (rc) { 768 pr_err("%s: read bcaps error, abort\n", __func__); 769 return rc; 770 } 771 772 /* 773 * 1.1_Features turned off by default. 774 * No need to write AInfo since 1.1_Features is disabled. 775 */ 776 hdmi_write(hdmi, REG_HDMI_HDCP_RCVPORT_DATA4, 0); 777 778 /* Send AKSV and An to sink */ 779 rc = msm_hdmi_hdcp_send_aksv_an(hdcp_ctrl); 780 if (rc) { 781 pr_err("%s:An/Aksv write failed\n", __func__); 782 return rc; 783 } 784 785 /* Read BKSV and send to HDCP engine*/ 786 rc = msm_hdmi_hdcp_recv_bksv(hdcp_ctrl); 787 if (rc) { 788 pr_err("%s:BKSV Process failed\n", __func__); 789 return rc; 790 } 791 792 /* Enable HDCP interrupts and ack/clear any stale interrupts */ 793 spin_lock_irqsave(&hdmi->reg_lock, flags); 794 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 795 HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_ACK | 796 HDMI_HDCP_INT_CTRL_AUTH_SUCCESS_MASK | 797 HDMI_HDCP_INT_CTRL_AUTH_FAIL_ACK | 798 HDMI_HDCP_INT_CTRL_AUTH_FAIL_MASK | 799 HDMI_HDCP_INT_CTRL_AUTH_FAIL_INFO_ACK); 800 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 801 802 return 0; 803} 804 805/* read R0' from sink and pass it to HDCP engine */ 806static int msm_hdmi_hdcp_auth_part1_recv_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl) 807{ 808 struct hdmi *hdmi = hdcp_ctrl->hdmi; 809 int rc = 0; 810 u8 buf[2]; 811 812 /* 813 * HDCP Compliance Test case 1A-01: 814 * Wait here at least 100ms before reading R0' 815 */ 816 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 125, AUTH_ABORT_EV); 817 if (rc) 818 return rc; 819 820 /* Read R0' at offset 0x08 */ 821 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x08, buf, 2); 822 if (rc) { 823 pr_err("%s:R0' read failed\n", __func__); 824 return rc; 825 } 826 DBG("R0'=%02x%02x", buf[1], buf[0]); 827 828 /* Write R0' to HDCP registers and check to see if it is a match */ 829 hdmi_write(hdmi, REG_HDMI_HDCP_RCVPORT_DATA2_0, 830 (((u32)buf[1]) << 8) | buf[0]); 831 832 return 0; 833} 834 835/* Wait for authenticating result: R0/R0' are matched or not */ 836static int msm_hdmi_hdcp_auth_part1_verify_r0(struct hdmi_hdcp_ctrl *hdcp_ctrl) 837{ 838 struct hdmi *hdmi = hdcp_ctrl->hdmi; 839 u32 link0_status; 840 int rc; 841 842 /* wait for hdcp irq, 10 sec should be long enough */ 843 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 10000, AUTH_RESULT_RDY_EV); 844 if (!rc) { 845 pr_err("%s: Wait Auth IRQ timeout\n", __func__); 846 return -ETIMEDOUT; 847 } 848 849 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 850 if (!(link0_status & HDMI_HDCP_LINK0_STATUS_RI_MATCHES)) { 851 pr_err("%s: Authentication Part I failed\n", __func__); 852 return -EINVAL; 853 } 854 855 /* Enable HDCP Encryption */ 856 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 857 HDMI_HDCP_CTRL_ENABLE | 858 HDMI_HDCP_CTRL_ENCRYPTION_ENABLE); 859 860 return 0; 861} 862 863static int msm_hdmi_hdcp_recv_check_bstatus(struct hdmi_hdcp_ctrl *hdcp_ctrl, 864 u16 *pbstatus) 865{ 866 int rc; 867 struct hdmi *hdmi = hdcp_ctrl->hdmi; 868 bool max_devs_exceeded = false, max_cascade_exceeded = false; 869 u32 repeater_cascade_depth = 0, down_stream_devices = 0; 870 u16 bstatus; 871 u8 buf[2]; 872 873 /* Read BSTATUS at offset 0x41 */ 874 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x41, buf, 2); 875 if (rc) { 876 pr_err("%s: BSTATUS read failed\n", __func__); 877 goto error; 878 } 879 *pbstatus = bstatus = (buf[1] << 8) | buf[0]; 880 881 882 down_stream_devices = bstatus & 0x7F; 883 repeater_cascade_depth = (bstatus >> 8) & 0x7; 884 max_devs_exceeded = (bstatus & BIT(7)) ? true : false; 885 max_cascade_exceeded = (bstatus & BIT(11)) ? true : false; 886 887 if (down_stream_devices == 0) { 888 /* 889 * If no downstream devices are attached to the repeater 890 * then part II fails. 891 * todo: The other approach would be to continue PART II. 892 */ 893 pr_err("%s: No downstream devices\n", __func__); 894 rc = -EINVAL; 895 goto error; 896 } 897 898 /* 899 * HDCP Compliance 1B-05: 900 * Check if no. of devices connected to repeater 901 * exceed max_devices_connected from bit 7 of Bstatus. 902 */ 903 if (max_devs_exceeded) { 904 pr_err("%s: no. of devs connected exceeds max allowed", 905 __func__); 906 rc = -EINVAL; 907 goto error; 908 } 909 910 /* 911 * HDCP Compliance 1B-06: 912 * Check if no. of cascade connected to repeater 913 * exceed max_cascade_connected from bit 11 of Bstatus. 914 */ 915 if (max_cascade_exceeded) { 916 pr_err("%s: no. of cascade conn exceeds max allowed", 917 __func__); 918 rc = -EINVAL; 919 goto error; 920 } 921 922error: 923 hdcp_ctrl->dev_count = down_stream_devices; 924 hdcp_ctrl->max_cascade_exceeded = max_cascade_exceeded; 925 hdcp_ctrl->max_dev_exceeded = max_devs_exceeded; 926 hdcp_ctrl->depth = repeater_cascade_depth; 927 return rc; 928} 929 930static int msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready( 931 struct hdmi_hdcp_ctrl *hdcp_ctrl) 932{ 933 int rc; 934 struct hdmi *hdmi = hdcp_ctrl->hdmi; 935 u32 reg, data; 936 u32 timeout_count; 937 u16 bstatus; 938 u8 bcaps; 939 940 /* 941 * Wait until READY bit is set in BCAPS, as per HDCP specifications 942 * maximum permitted time to check for READY bit is five seconds. 943 */ 944 timeout_count = 100; 945 do { 946 /* Read BCAPS at offset 0x40 */ 947 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x40, &bcaps, 1); 948 if (rc) { 949 pr_err("%s: BCAPS read failed\n", __func__); 950 return rc; 951 } 952 953 if (bcaps & BIT(5)) 954 break; 955 956 timeout_count--; 957 if (!timeout_count) { 958 pr_err("%s: Wait KSV fifo ready timedout", __func__); 959 return -ETIMEDOUT; 960 } 961 962 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 963 if (rc) 964 return rc; 965 } while (1); 966 967 rc = msm_hdmi_hdcp_recv_check_bstatus(hdcp_ctrl, &bstatus); 968 if (rc) { 969 pr_err("%s: bstatus error\n", __func__); 970 return rc; 971 } 972 973 /* Write BSTATUS and BCAPS to HDCP registers */ 974 reg = REG_HDMI_HDCP_RCVPORT_DATA12; 975 data = bcaps | (bstatus << 8); 976 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); 977 if (rc) { 978 pr_err("%s: BSTATUS write failed\n", __func__); 979 return rc; 980 } 981 982 return 0; 983} 984 985/* 986 * hdcp authenticating part 2: 2nd 987 * read ksv fifo from sink 988 * transfer V' from sink to HDCP engine 989 * reset SHA engine 990 */ 991static int msm_hdmi_hdcp_transfer_v_h(struct hdmi_hdcp_ctrl *hdcp_ctrl) 992{ 993 struct hdmi *hdmi = hdcp_ctrl->hdmi; 994 int rc = 0; 995 struct hdmi_hdcp_reg_data reg_data[] = { 996 {REG_HDMI_HDCP_RCVPORT_DATA7, 0x20, "V' H0"}, 997 {REG_HDMI_HDCP_RCVPORT_DATA8, 0x24, "V' H1"}, 998 {REG_HDMI_HDCP_RCVPORT_DATA9, 0x28, "V' H2"}, 999 {REG_HDMI_HDCP_RCVPORT_DATA10, 0x2C, "V' H3"}, 1000 {REG_HDMI_HDCP_RCVPORT_DATA11, 0x30, "V' H4"}, 1001 }; 1002 struct hdmi_hdcp_reg_data *rd; 1003 u32 size = ARRAY_SIZE(reg_data); 1004 u32 reg[ARRAY_SIZE(reg_data)]; 1005 u32 data[ARRAY_SIZE(reg_data)]; 1006 int i; 1007 1008 for (i = 0; i < size; i++) { 1009 rd = ®_data[i]; 1010 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 1011 rd->off, (u8 *)&data[i], (u16)sizeof(data[i])); 1012 if (rc) { 1013 pr_err("%s: Read %s failed\n", __func__, rd->name); 1014 goto error; 1015 } 1016 1017 DBG("%s =%x", rd->name, data[i]); 1018 reg[i] = reg_data[i].reg_id; 1019 } 1020 1021 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, size); 1022 1023error: 1024 return rc; 1025} 1026 1027static int msm_hdmi_hdcp_recv_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1028{ 1029 int rc; 1030 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1031 u32 ksv_bytes; 1032 1033 ksv_bytes = 5 * hdcp_ctrl->dev_count; 1034 1035 rc = msm_hdmi_ddc_read(hdmi, HDCP_PORT_ADDR, 0x43, 1036 hdcp_ctrl->ksv_list, ksv_bytes); 1037 if (rc) 1038 pr_err("%s: KSV FIFO read failed\n", __func__); 1039 1040 return rc; 1041} 1042 1043static int msm_hdmi_hdcp_reset_sha_engine(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1044{ 1045 u32 reg[2], data[2]; 1046 u32 rc = 0; 1047 1048 reg[0] = REG_HDMI_HDCP_SHA_CTRL; 1049 data[0] = HDCP_REG_ENABLE; 1050 reg[1] = REG_HDMI_HDCP_SHA_CTRL; 1051 data[1] = HDCP_REG_DISABLE; 1052 1053 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, reg, data, 2); 1054 1055 return rc; 1056} 1057 1058static int msm_hdmi_hdcp_auth_part2_recv_ksv_fifo( 1059 struct hdmi_hdcp_ctrl *hdcp_ctrl) 1060{ 1061 int rc; 1062 u32 timeout_count; 1063 1064 /* 1065 * Read KSV FIFO over DDC 1066 * Key Selection vector FIFO Used to pull downstream KSVs 1067 * from HDCP Repeaters. 1068 * All bytes (DEVICE_COUNT * 5) must be read in a single, 1069 * auto incrementing access. 1070 * All bytes read as 0x00 for HDCP Receivers that are not 1071 * HDCP Repeaters (REPEATER == 0). 1072 */ 1073 timeout_count = 100; 1074 do { 1075 rc = msm_hdmi_hdcp_recv_ksv_fifo(hdcp_ctrl); 1076 if (!rc) 1077 break; 1078 1079 timeout_count--; 1080 if (!timeout_count) { 1081 pr_err("%s: Recv ksv fifo timedout", __func__); 1082 return -ETIMEDOUT; 1083 } 1084 1085 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 25, AUTH_ABORT_EV); 1086 if (rc) 1087 return rc; 1088 } while (1); 1089 1090 rc = msm_hdmi_hdcp_transfer_v_h(hdcp_ctrl); 1091 if (rc) { 1092 pr_err("%s: transfer V failed\n", __func__); 1093 return rc; 1094 } 1095 1096 /* reset SHA engine before write ksv fifo */ 1097 rc = msm_hdmi_hdcp_reset_sha_engine(hdcp_ctrl); 1098 if (rc) { 1099 pr_err("%s: fail to reset sha engine\n", __func__); 1100 return rc; 1101 } 1102 1103 return 0; 1104} 1105 1106/* 1107 * Write KSV FIFO to HDCP_SHA_DATA. 1108 * This is done 1 byte at time starting with the LSB. 1109 * Once 64 bytes have been written, we need to poll for 1110 * HDCP_SHA_BLOCK_DONE before writing any further 1111 * If the last byte is written, we need to poll for 1112 * HDCP_SHA_COMP_DONE to wait until HW finish 1113 */ 1114static int msm_hdmi_hdcp_write_ksv_fifo(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1115{ 1116 int i; 1117 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1118 u32 ksv_bytes, last_byte = 0; 1119 u8 *ksv_fifo = NULL; 1120 u32 reg_val, data, reg; 1121 u32 rc = 0; 1122 1123 ksv_bytes = 5 * hdcp_ctrl->dev_count; 1124 1125 /* Check if need to wait for HW completion */ 1126 if (hdcp_ctrl->ksv_fifo_w_index) { 1127 reg_val = hdmi_read(hdmi, REG_HDMI_HDCP_SHA_STATUS); 1128 DBG("HDCP_SHA_STATUS=%08x", reg_val); 1129 if (hdcp_ctrl->ksv_fifo_w_index == ksv_bytes) { 1130 /* check COMP_DONE if last write */ 1131 if (reg_val & HDMI_HDCP_SHA_STATUS_COMP_DONE) { 1132 DBG("COMP_DONE"); 1133 return 0; 1134 } else { 1135 return -EAGAIN; 1136 } 1137 } else { 1138 /* check BLOCK_DONE if not last write */ 1139 if (!(reg_val & HDMI_HDCP_SHA_STATUS_BLOCK_DONE)) 1140 return -EAGAIN; 1141 1142 DBG("BLOCK_DONE"); 1143 } 1144 } 1145 1146 ksv_bytes -= hdcp_ctrl->ksv_fifo_w_index; 1147 if (ksv_bytes <= 64) 1148 last_byte = 1; 1149 else 1150 ksv_bytes = 64; 1151 1152 ksv_fifo = hdcp_ctrl->ksv_list; 1153 ksv_fifo += hdcp_ctrl->ksv_fifo_w_index; 1154 1155 for (i = 0; i < ksv_bytes; i++) { 1156 /* Write KSV byte and set DONE bit[0] for last byte*/ 1157 reg_val = ksv_fifo[i] << 16; 1158 if ((i == (ksv_bytes - 1)) && last_byte) 1159 reg_val |= HDMI_HDCP_SHA_DATA_DONE; 1160 1161 reg = REG_HDMI_HDCP_SHA_DATA; 1162 data = reg_val; 1163 rc = msm_hdmi_hdcp_scm_wr(hdcp_ctrl, ®, &data, 1); 1164 1165 if (rc) 1166 return rc; 1167 } 1168 1169 hdcp_ctrl->ksv_fifo_w_index += ksv_bytes; 1170 1171 /* 1172 *return -EAGAIN to notify caller to wait for COMP_DONE or BLOCK_DONE 1173 */ 1174 return -EAGAIN; 1175} 1176 1177/* write ksv fifo into HDCP engine */ 1178static int msm_hdmi_hdcp_auth_part2_write_ksv_fifo( 1179 struct hdmi_hdcp_ctrl *hdcp_ctrl) 1180{ 1181 int rc; 1182 u32 timeout_count; 1183 1184 hdcp_ctrl->ksv_fifo_w_index = 0; 1185 timeout_count = 100; 1186 do { 1187 rc = msm_hdmi_hdcp_write_ksv_fifo(hdcp_ctrl); 1188 if (!rc) 1189 break; 1190 1191 if (rc != -EAGAIN) 1192 return rc; 1193 1194 timeout_count--; 1195 if (!timeout_count) { 1196 pr_err("%s: Write KSV fifo timedout", __func__); 1197 return -ETIMEDOUT; 1198 } 1199 1200 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 1201 if (rc) 1202 return rc; 1203 } while (1); 1204 1205 return 0; 1206} 1207 1208static int msm_hdmi_hdcp_auth_part2_check_v_match(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1209{ 1210 int rc = 0; 1211 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1212 u32 link0_status; 1213 u32 timeout_count = 100; 1214 1215 do { 1216 link0_status = hdmi_read(hdmi, REG_HDMI_HDCP_LINK0_STATUS); 1217 if (link0_status & HDMI_HDCP_LINK0_STATUS_V_MATCHES) 1218 break; 1219 1220 timeout_count--; 1221 if (!timeout_count) { 1222 pr_err("%s: HDCP V Match timedout", __func__); 1223 return -ETIMEDOUT; 1224 } 1225 1226 rc = msm_hdmi_hdcp_msleep(hdcp_ctrl, 20, AUTH_ABORT_EV); 1227 if (rc) 1228 return rc; 1229 } while (1); 1230 1231 return 0; 1232} 1233 1234static void msm_hdmi_hdcp_auth_work(struct work_struct *work) 1235{ 1236 struct hdmi_hdcp_ctrl *hdcp_ctrl = container_of(work, 1237 struct hdmi_hdcp_ctrl, hdcp_auth_work); 1238 int rc; 1239 1240 rc = msm_hdmi_hdcp_auth_prepare(hdcp_ctrl); 1241 if (rc) { 1242 pr_err("%s: auth prepare failed %d\n", __func__, rc); 1243 goto end; 1244 } 1245 1246 /* HDCP PartI */ 1247 rc = msm_hdmi_hdcp_auth_part1_key_exchange(hdcp_ctrl); 1248 if (rc) { 1249 pr_err("%s: key exchange failed %d\n", __func__, rc); 1250 goto end; 1251 } 1252 1253 rc = msm_hdmi_hdcp_auth_part1_recv_r0(hdcp_ctrl); 1254 if (rc) { 1255 pr_err("%s: receive r0 failed %d\n", __func__, rc); 1256 goto end; 1257 } 1258 1259 rc = msm_hdmi_hdcp_auth_part1_verify_r0(hdcp_ctrl); 1260 if (rc) { 1261 pr_err("%s: verify r0 failed %d\n", __func__, rc); 1262 goto end; 1263 } 1264 pr_info("%s: Authentication Part I successful\n", __func__); 1265 if (hdcp_ctrl->ds_type == DS_RECEIVER) 1266 goto end; 1267 1268 /* HDCP PartII */ 1269 rc = msm_hdmi_hdcp_auth_part2_wait_ksv_fifo_ready(hdcp_ctrl); 1270 if (rc) { 1271 pr_err("%s: wait ksv fifo ready failed %d\n", __func__, rc); 1272 goto end; 1273 } 1274 1275 rc = msm_hdmi_hdcp_auth_part2_recv_ksv_fifo(hdcp_ctrl); 1276 if (rc) { 1277 pr_err("%s: recv ksv fifo failed %d\n", __func__, rc); 1278 goto end; 1279 } 1280 1281 rc = msm_hdmi_hdcp_auth_part2_write_ksv_fifo(hdcp_ctrl); 1282 if (rc) { 1283 pr_err("%s: write ksv fifo failed %d\n", __func__, rc); 1284 goto end; 1285 } 1286 1287 rc = msm_hdmi_hdcp_auth_part2_check_v_match(hdcp_ctrl); 1288 if (rc) 1289 pr_err("%s: check v match failed %d\n", __func__, rc); 1290 1291end: 1292 if (rc == -ECANCELED) { 1293 pr_info("%s: hdcp authentication canceled\n", __func__); 1294 } else if (rc == -ENOTSUPP) { 1295 pr_info("%s: hdcp is not supported\n", __func__); 1296 } else if (rc) { 1297 pr_err("%s: hdcp authentication failed\n", __func__); 1298 msm_hdmi_hdcp_auth_fail(hdcp_ctrl); 1299 } else { 1300 msm_hdmi_hdcp_auth_done(hdcp_ctrl); 1301 } 1302} 1303 1304void msm_hdmi_hdcp_on(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1305{ 1306 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1307 u32 reg_val; 1308 unsigned long flags; 1309 1310 if ((HDCP_STATE_INACTIVE != hdcp_ctrl->hdcp_state) || 1311 (HDCP_STATE_NO_AKSV == hdcp_ctrl->hdcp_state)) { 1312 DBG("still active or activating or no askv. returning"); 1313 return; 1314 } 1315 1316 /* clear HDMI Encrypt */ 1317 spin_lock_irqsave(&hdmi->reg_lock, flags); 1318 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); 1319 reg_val &= ~HDMI_CTRL_ENCRYPTED; 1320 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); 1321 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 1322 1323 hdcp_ctrl->auth_event = 0; 1324 hdcp_ctrl->hdcp_state = HDCP_STATE_AUTHENTICATING; 1325 hdcp_ctrl->auth_retries = 0; 1326 queue_work(hdmi->workq, &hdcp_ctrl->hdcp_auth_work); 1327} 1328 1329void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) 1330{ 1331 struct hdmi *hdmi = hdcp_ctrl->hdmi; 1332 unsigned long flags; 1333 u32 reg_val; 1334 1335 if ((HDCP_STATE_INACTIVE == hdcp_ctrl->hdcp_state) || 1336 (HDCP_STATE_NO_AKSV == hdcp_ctrl->hdcp_state)) { 1337 DBG("hdcp inactive or no aksv. returning"); 1338 return; 1339 } 1340 1341 /* 1342 * Disable HPD circuitry. 1343 * This is needed to reset the HDCP cipher engine so that when we 1344 * attempt a re-authentication, HW would clear the AN0_READY and 1345 * AN1_READY bits in HDMI_HDCP_LINK0_STATUS register 1346 */ 1347 spin_lock_irqsave(&hdmi->reg_lock, flags); 1348 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); 1349 reg_val &= ~HDMI_HPD_CTRL_ENABLE; 1350 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); 1351 1352 /* 1353 * Disable HDCP interrupts. 1354 * Also, need to set the state to inactive here so that any ongoing 1355 * reauth works will know that the HDCP session has been turned off. 1356 */ 1357 hdmi_write(hdmi, REG_HDMI_HDCP_INT_CTRL, 0); 1358 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 1359 1360 /* 1361 * Cancel any pending auth/reauth attempts. 1362 * If one is ongoing, this will wait for it to finish. 1363 * No more reauthentication attempts will be scheduled since we 1364 * set the current state to inactive. 1365 */ 1366 set_bit(AUTH_ABORT_EV, &hdcp_ctrl->auth_event); 1367 wake_up_all(&hdcp_ctrl->auth_event_queue); 1368 cancel_work_sync(&hdcp_ctrl->hdcp_auth_work); 1369 cancel_work_sync(&hdcp_ctrl->hdcp_reauth_work); 1370 1371 hdmi_write(hdmi, REG_HDMI_HDCP_RESET, 1372 HDMI_HDCP_RESET_LINK0_DEAUTHENTICATE); 1373 1374 /* Disable encryption and disable the HDCP block */ 1375 hdmi_write(hdmi, REG_HDMI_HDCP_CTRL, 0); 1376 1377 spin_lock_irqsave(&hdmi->reg_lock, flags); 1378 reg_val = hdmi_read(hdmi, REG_HDMI_CTRL); 1379 reg_val &= ~HDMI_CTRL_ENCRYPTED; 1380 hdmi_write(hdmi, REG_HDMI_CTRL, reg_val); 1381 1382 /* Enable HPD circuitry */ 1383 reg_val = hdmi_read(hdmi, REG_HDMI_HPD_CTRL); 1384 reg_val |= HDMI_HPD_CTRL_ENABLE; 1385 hdmi_write(hdmi, REG_HDMI_HPD_CTRL, reg_val); 1386 spin_unlock_irqrestore(&hdmi->reg_lock, flags); 1387 1388 hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; 1389 1390 DBG("HDCP: Off"); 1391} 1392 1393struct hdmi_hdcp_ctrl *msm_hdmi_hdcp_init(struct hdmi *hdmi) 1394{ 1395 struct hdmi_hdcp_ctrl *hdcp_ctrl = NULL; 1396 1397 if (!hdmi->qfprom_mmio) { 1398 pr_err("%s: HDCP is not supported without qfprom\n", 1399 __func__); 1400 return ERR_PTR(-EINVAL); 1401 } 1402 1403 hdcp_ctrl = kzalloc(sizeof(*hdcp_ctrl), GFP_KERNEL); 1404 if (!hdcp_ctrl) 1405 return ERR_PTR(-ENOMEM); 1406 1407 INIT_WORK(&hdcp_ctrl->hdcp_auth_work, msm_hdmi_hdcp_auth_work); 1408 INIT_WORK(&hdcp_ctrl->hdcp_reauth_work, msm_hdmi_hdcp_reauth_work); 1409 init_waitqueue_head(&hdcp_ctrl->auth_event_queue); 1410 hdcp_ctrl->hdmi = hdmi; 1411 hdcp_ctrl->hdcp_state = HDCP_STATE_INACTIVE; 1412 hdcp_ctrl->aksv_valid = false; 1413 1414 if (qcom_scm_hdcp_available()) 1415 hdcp_ctrl->tz_hdcp = true; 1416 else 1417 hdcp_ctrl->tz_hdcp = false; 1418 1419 return hdcp_ctrl; 1420} 1421 1422void msm_hdmi_hdcp_destroy(struct hdmi *hdmi) 1423{ 1424 if (hdmi) { 1425 kfree(hdmi->hdcp_ctrl); 1426 hdmi->hdcp_ctrl = NULL; 1427 } 1428} 1429