1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/delay.h> 8#include <linux/dma-mapping.h> 9#include <linux/err.h> 10#include <linux/gpio/consumer.h> 11#include <linux/interrupt.h> 12#include <linux/mfd/syscon.h> 13#include <linux/of_device.h> 14#include <linux/of_graph.h> 15#include <linux/of_irq.h> 16#include <linux/pinctrl/consumer.h> 17#include <linux/pm_opp.h> 18#include <linux/regmap.h> 19#include <linux/regulator/consumer.h> 20#include <linux/spinlock.h> 21 22#include <video/mipi_display.h> 23 24#include "dsi.h" 25#include "dsi.xml.h" 26#include "sfpb.xml.h" 27#include "dsi_cfg.h" 28#include "msm_kms.h" 29 30#define DSI_RESET_TOGGLE_DELAY_MS 20 31 32static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor) 33{ 34 u32 ver; 35 36 if (!major || !minor) 37 return -EINVAL; 38 39 /* 40 * From DSI6G(v3), addition of a 6G_HW_VERSION register at offset 0 41 * makes all other registers 4-byte shifted down. 42 * 43 * In order to identify between DSI6G(v3) and beyond, and DSIv2 and 44 * older, we read the DSI_VERSION register without any shift(offset 45 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In 46 * the case of DSI6G, this has to be zero (the offset points to a 47 * scratch register which we never touch) 48 */ 49 50 ver = msm_readl(base + REG_DSI_VERSION); 51 if (ver) { 52 /* older dsi host, there is no register shift */ 53 ver = FIELD(ver, DSI_VERSION_MAJOR); 54 if (ver <= MSM_DSI_VER_MAJOR_V2) { 55 /* old versions */ 56 *major = ver; 57 *minor = 0; 58 return 0; 59 } else { 60 return -EINVAL; 61 } 62 } else { 63 /* 64 * newer host, offset 0 has 6G_HW_VERSION, the rest of the 65 * registers are shifted down, read DSI_VERSION again with 66 * the shifted offset 67 */ 68 ver = msm_readl(base + DSI_6G_REG_SHIFT + REG_DSI_VERSION); 69 ver = FIELD(ver, DSI_VERSION_MAJOR); 70 if (ver == MSM_DSI_VER_MAJOR_6G) { 71 /* 6G version */ 72 *major = ver; 73 *minor = msm_readl(base + REG_DSI_6G_HW_VERSION); 74 return 0; 75 } else { 76 return -EINVAL; 77 } 78 } 79} 80 81#define DSI_ERR_STATE_ACK 0x0000 82#define DSI_ERR_STATE_TIMEOUT 0x0001 83#define DSI_ERR_STATE_DLN0_PHY 0x0002 84#define DSI_ERR_STATE_FIFO 0x0004 85#define DSI_ERR_STATE_MDP_FIFO_UNDERFLOW 0x0008 86#define DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION 0x0010 87#define DSI_ERR_STATE_PLL_UNLOCKED 0x0020 88 89#define DSI_CLK_CTRL_ENABLE_CLKS \ 90 (DSI_CLK_CTRL_AHBS_HCLK_ON | DSI_CLK_CTRL_AHBM_SCLK_ON | \ 91 DSI_CLK_CTRL_PCLK_ON | DSI_CLK_CTRL_DSICLK_ON | \ 92 DSI_CLK_CTRL_BYTECLK_ON | DSI_CLK_CTRL_ESCCLK_ON | \ 93 DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK) 94 95struct msm_dsi_host { 96 struct mipi_dsi_host base; 97 98 struct platform_device *pdev; 99 struct drm_device *dev; 100 101 int id; 102 103 void __iomem *ctrl_base; 104 struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX]; 105 106 struct clk *bus_clks[DSI_BUS_CLK_MAX]; 107 108 struct clk *byte_clk; 109 struct clk *esc_clk; 110 struct clk *pixel_clk; 111 struct clk *byte_clk_src; 112 struct clk *pixel_clk_src; 113 struct clk *byte_intf_clk; 114 115 struct opp_table *opp_table; 116 bool has_opp_table; 117 118 u32 byte_clk_rate; 119 u32 pixel_clk_rate; 120 u32 esc_clk_rate; 121 122 /* DSI v2 specific clocks */ 123 struct clk *src_clk; 124 struct clk *esc_clk_src; 125 struct clk *dsi_clk_src; 126 127 u32 src_clk_rate; 128 129 struct gpio_desc *disp_en_gpio; 130 struct gpio_desc *te_gpio; 131 132 const struct msm_dsi_cfg_handler *cfg_hnd; 133 134 struct completion dma_comp; 135 struct completion video_comp; 136 struct mutex dev_mutex; 137 struct mutex cmd_mutex; 138 spinlock_t intr_lock; /* Protect interrupt ctrl register */ 139 140 u32 err_work_state; 141 struct work_struct err_work; 142 struct work_struct hpd_work; 143 struct workqueue_struct *workqueue; 144 145 /* DSI 6G TX buffer*/ 146 struct drm_gem_object *tx_gem_obj; 147 148 /* DSI v2 TX buffer */ 149 void *tx_buf; 150 dma_addr_t tx_buf_paddr; 151 152 int tx_size; 153 154 u8 *rx_buf; 155 156 struct regmap *sfpb; 157 158 struct drm_display_mode *mode; 159 160 /* connected device info */ 161 struct device_node *device_node; 162 unsigned int channel; 163 unsigned int lanes; 164 enum mipi_dsi_pixel_format format; 165 unsigned long mode_flags; 166 167 /* lane data parsed via DT */ 168 int dlane_swap; 169 int num_data_lanes; 170 171 u32 dma_cmd_ctrl_restore; 172 173 bool registered; 174 bool power_on; 175 bool enabled; 176 int irq; 177}; 178 179static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) 180{ 181 switch (fmt) { 182 case MIPI_DSI_FMT_RGB565: return 16; 183 case MIPI_DSI_FMT_RGB666_PACKED: return 18; 184 case MIPI_DSI_FMT_RGB666: 185 case MIPI_DSI_FMT_RGB888: 186 default: return 24; 187 } 188} 189 190static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) 191{ 192 return msm_readl(msm_host->ctrl_base + reg); 193} 194static inline void dsi_write(struct msm_dsi_host *msm_host, u32 reg, u32 data) 195{ 196 msm_writel(data, msm_host->ctrl_base + reg); 197} 198 199static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host); 200static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host); 201 202static const struct msm_dsi_cfg_handler *dsi_get_config( 203 struct msm_dsi_host *msm_host) 204{ 205 const struct msm_dsi_cfg_handler *cfg_hnd = NULL; 206 struct device *dev = &msm_host->pdev->dev; 207 struct regulator *gdsc_reg; 208 struct clk *ahb_clk; 209 int ret; 210 u32 major = 0, minor = 0; 211 212 gdsc_reg = regulator_get(dev, "gdsc"); 213 if (IS_ERR(gdsc_reg)) { 214 pr_err("%s: cannot get gdsc\n", __func__); 215 goto exit; 216 } 217 218 ahb_clk = msm_clk_get(msm_host->pdev, "iface"); 219 if (IS_ERR(ahb_clk)) { 220 pr_err("%s: cannot get interface clock\n", __func__); 221 goto put_gdsc; 222 } 223 224 pm_runtime_get_sync(dev); 225 226 ret = regulator_enable(gdsc_reg); 227 if (ret) { 228 pr_err("%s: unable to enable gdsc\n", __func__); 229 goto put_gdsc; 230 } 231 232 ret = clk_prepare_enable(ahb_clk); 233 if (ret) { 234 pr_err("%s: unable to enable ahb_clk\n", __func__); 235 goto disable_gdsc; 236 } 237 238 ret = dsi_get_version(msm_host->ctrl_base, &major, &minor); 239 if (ret) { 240 pr_err("%s: Invalid version\n", __func__); 241 goto disable_clks; 242 } 243 244 cfg_hnd = msm_dsi_cfg_get(major, minor); 245 246 DBG("%s: Version %x:%x\n", __func__, major, minor); 247 248disable_clks: 249 clk_disable_unprepare(ahb_clk); 250disable_gdsc: 251 regulator_disable(gdsc_reg); 252 pm_runtime_put_sync(dev); 253put_gdsc: 254 regulator_put(gdsc_reg); 255exit: 256 return cfg_hnd; 257} 258 259static inline struct msm_dsi_host *to_msm_dsi_host(struct mipi_dsi_host *host) 260{ 261 return container_of(host, struct msm_dsi_host, base); 262} 263 264static void dsi_host_regulator_disable(struct msm_dsi_host *msm_host) 265{ 266 struct regulator_bulk_data *s = msm_host->supplies; 267 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 268 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 269 int i; 270 271 DBG(""); 272 for (i = num - 1; i >= 0; i--) 273 if (regs[i].disable_load >= 0) 274 regulator_set_load(s[i].consumer, 275 regs[i].disable_load); 276 277 regulator_bulk_disable(num, s); 278} 279 280static int dsi_host_regulator_enable(struct msm_dsi_host *msm_host) 281{ 282 struct regulator_bulk_data *s = msm_host->supplies; 283 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 284 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 285 int ret, i; 286 287 DBG(""); 288 for (i = 0; i < num; i++) { 289 if (regs[i].enable_load >= 0) { 290 ret = regulator_set_load(s[i].consumer, 291 regs[i].enable_load); 292 if (ret < 0) { 293 pr_err("regulator %d set op mode failed, %d\n", 294 i, ret); 295 goto fail; 296 } 297 } 298 } 299 300 ret = regulator_bulk_enable(num, s); 301 if (ret < 0) { 302 pr_err("regulator enable failed, %d\n", ret); 303 goto fail; 304 } 305 306 return 0; 307 308fail: 309 for (i--; i >= 0; i--) 310 regulator_set_load(s[i].consumer, regs[i].disable_load); 311 return ret; 312} 313 314static int dsi_regulator_init(struct msm_dsi_host *msm_host) 315{ 316 struct regulator_bulk_data *s = msm_host->supplies; 317 const struct dsi_reg_entry *regs = msm_host->cfg_hnd->cfg->reg_cfg.regs; 318 int num = msm_host->cfg_hnd->cfg->reg_cfg.num; 319 int i, ret; 320 321 for (i = 0; i < num; i++) 322 s[i].supply = regs[i].name; 323 324 ret = devm_regulator_bulk_get(&msm_host->pdev->dev, num, s); 325 if (ret < 0) { 326 pr_err("%s: failed to init regulator, ret=%d\n", 327 __func__, ret); 328 return ret; 329 } 330 331 return 0; 332} 333 334int dsi_clk_init_v2(struct msm_dsi_host *msm_host) 335{ 336 struct platform_device *pdev = msm_host->pdev; 337 int ret = 0; 338 339 msm_host->src_clk = msm_clk_get(pdev, "src"); 340 341 if (IS_ERR(msm_host->src_clk)) { 342 ret = PTR_ERR(msm_host->src_clk); 343 pr_err("%s: can't find src clock. ret=%d\n", 344 __func__, ret); 345 msm_host->src_clk = NULL; 346 return ret; 347 } 348 349 msm_host->esc_clk_src = clk_get_parent(msm_host->esc_clk); 350 if (!msm_host->esc_clk_src) { 351 ret = -ENODEV; 352 pr_err("%s: can't get esc clock parent. ret=%d\n", 353 __func__, ret); 354 return ret; 355 } 356 357 msm_host->dsi_clk_src = clk_get_parent(msm_host->src_clk); 358 if (!msm_host->dsi_clk_src) { 359 ret = -ENODEV; 360 pr_err("%s: can't get src clock parent. ret=%d\n", 361 __func__, ret); 362 } 363 364 return ret; 365} 366 367int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) 368{ 369 struct platform_device *pdev = msm_host->pdev; 370 int ret = 0; 371 372 msm_host->byte_intf_clk = msm_clk_get(pdev, "byte_intf"); 373 if (IS_ERR(msm_host->byte_intf_clk)) { 374 ret = PTR_ERR(msm_host->byte_intf_clk); 375 pr_err("%s: can't find byte_intf clock. ret=%d\n", 376 __func__, ret); 377 } 378 379 return ret; 380} 381 382static int dsi_clk_init(struct msm_dsi_host *msm_host) 383{ 384 struct platform_device *pdev = msm_host->pdev; 385 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 386 const struct msm_dsi_config *cfg = cfg_hnd->cfg; 387 int i, ret = 0; 388 389 /* get bus clocks */ 390 for (i = 0; i < cfg->num_bus_clks; i++) { 391 msm_host->bus_clks[i] = msm_clk_get(pdev, 392 cfg->bus_clk_names[i]); 393 if (IS_ERR(msm_host->bus_clks[i])) { 394 ret = PTR_ERR(msm_host->bus_clks[i]); 395 pr_err("%s: Unable to get %s clock, ret = %d\n", 396 __func__, cfg->bus_clk_names[i], ret); 397 goto exit; 398 } 399 } 400 401 /* get link and source clocks */ 402 msm_host->byte_clk = msm_clk_get(pdev, "byte"); 403 if (IS_ERR(msm_host->byte_clk)) { 404 ret = PTR_ERR(msm_host->byte_clk); 405 pr_err("%s: can't find dsi_byte clock. ret=%d\n", 406 __func__, ret); 407 msm_host->byte_clk = NULL; 408 goto exit; 409 } 410 411 msm_host->pixel_clk = msm_clk_get(pdev, "pixel"); 412 if (IS_ERR(msm_host->pixel_clk)) { 413 ret = PTR_ERR(msm_host->pixel_clk); 414 pr_err("%s: can't find dsi_pixel clock. ret=%d\n", 415 __func__, ret); 416 msm_host->pixel_clk = NULL; 417 goto exit; 418 } 419 420 msm_host->esc_clk = msm_clk_get(pdev, "core"); 421 if (IS_ERR(msm_host->esc_clk)) { 422 ret = PTR_ERR(msm_host->esc_clk); 423 pr_err("%s: can't find dsi_esc clock. ret=%d\n", 424 __func__, ret); 425 msm_host->esc_clk = NULL; 426 goto exit; 427 } 428 429 msm_host->byte_clk_src = clk_get_parent(msm_host->byte_clk); 430 if (IS_ERR(msm_host->byte_clk_src)) { 431 ret = PTR_ERR(msm_host->byte_clk_src); 432 pr_err("%s: can't find byte_clk clock. ret=%d\n", __func__, ret); 433 goto exit; 434 } 435 436 msm_host->pixel_clk_src = clk_get_parent(msm_host->pixel_clk); 437 if (IS_ERR(msm_host->pixel_clk_src)) { 438 ret = PTR_ERR(msm_host->pixel_clk_src); 439 pr_err("%s: can't find pixel_clk clock. ret=%d\n", __func__, ret); 440 goto exit; 441 } 442 443 if (cfg_hnd->ops->clk_init_ver) 444 ret = cfg_hnd->ops->clk_init_ver(msm_host); 445exit: 446 return ret; 447} 448 449static int dsi_bus_clk_enable(struct msm_dsi_host *msm_host) 450{ 451 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 452 int i, ret; 453 454 DBG("id=%d", msm_host->id); 455 456 for (i = 0; i < cfg->num_bus_clks; i++) { 457 ret = clk_prepare_enable(msm_host->bus_clks[i]); 458 if (ret) { 459 pr_err("%s: failed to enable bus clock %d ret %d\n", 460 __func__, i, ret); 461 goto err; 462 } 463 } 464 465 return 0; 466err: 467 while (--i >= 0) 468 clk_disable_unprepare(msm_host->bus_clks[i]); 469 470 return ret; 471} 472 473static void dsi_bus_clk_disable(struct msm_dsi_host *msm_host) 474{ 475 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 476 int i; 477 478 DBG(""); 479 480 for (i = cfg->num_bus_clks - 1; i >= 0; i--) 481 clk_disable_unprepare(msm_host->bus_clks[i]); 482} 483 484int msm_dsi_runtime_suspend(struct device *dev) 485{ 486 struct platform_device *pdev = to_platform_device(dev); 487 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 488 struct mipi_dsi_host *host = msm_dsi->host; 489 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 490 491 if (!msm_host->cfg_hnd) 492 return 0; 493 494 dsi_bus_clk_disable(msm_host); 495 496 return 0; 497} 498 499int msm_dsi_runtime_resume(struct device *dev) 500{ 501 struct platform_device *pdev = to_platform_device(dev); 502 struct msm_dsi *msm_dsi = platform_get_drvdata(pdev); 503 struct mipi_dsi_host *host = msm_dsi->host; 504 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 505 506 if (!msm_host->cfg_hnd) 507 return 0; 508 509 return dsi_bus_clk_enable(msm_host); 510} 511 512int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host) 513{ 514 int ret; 515 516 DBG("Set clk rates: pclk=%d, byteclk=%d", 517 msm_host->mode->clock, msm_host->byte_clk_rate); 518 519 ret = dev_pm_opp_set_rate(&msm_host->pdev->dev, 520 msm_host->byte_clk_rate); 521 if (ret) { 522 pr_err("%s: dev_pm_opp_set_rate failed %d\n", __func__, ret); 523 return ret; 524 } 525 526 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 527 if (ret) { 528 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 529 return ret; 530 } 531 532 if (msm_host->byte_intf_clk) { 533 ret = clk_set_rate(msm_host->byte_intf_clk, 534 msm_host->byte_clk_rate / 2); 535 if (ret) { 536 pr_err("%s: Failed to set rate byte intf clk, %d\n", 537 __func__, ret); 538 return ret; 539 } 540 } 541 542 return 0; 543} 544 545 546int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) 547{ 548 int ret; 549 550 ret = clk_prepare_enable(msm_host->esc_clk); 551 if (ret) { 552 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 553 goto error; 554 } 555 556 ret = clk_prepare_enable(msm_host->byte_clk); 557 if (ret) { 558 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 559 goto byte_clk_err; 560 } 561 562 ret = clk_prepare_enable(msm_host->pixel_clk); 563 if (ret) { 564 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 565 goto pixel_clk_err; 566 } 567 568 if (msm_host->byte_intf_clk) { 569 ret = clk_prepare_enable(msm_host->byte_intf_clk); 570 if (ret) { 571 pr_err("%s: Failed to enable byte intf clk\n", 572 __func__); 573 goto byte_intf_clk_err; 574 } 575 } 576 577 return 0; 578 579byte_intf_clk_err: 580 clk_disable_unprepare(msm_host->pixel_clk); 581pixel_clk_err: 582 clk_disable_unprepare(msm_host->byte_clk); 583byte_clk_err: 584 clk_disable_unprepare(msm_host->esc_clk); 585error: 586 return ret; 587} 588 589int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host) 590{ 591 int ret; 592 593 DBG("Set clk rates: pclk=%d, byteclk=%d, esc_clk=%d, dsi_src_clk=%d", 594 msm_host->mode->clock, msm_host->byte_clk_rate, 595 msm_host->esc_clk_rate, msm_host->src_clk_rate); 596 597 ret = clk_set_rate(msm_host->byte_clk, msm_host->byte_clk_rate); 598 if (ret) { 599 pr_err("%s: Failed to set rate byte clk, %d\n", __func__, ret); 600 return ret; 601 } 602 603 ret = clk_set_rate(msm_host->esc_clk, msm_host->esc_clk_rate); 604 if (ret) { 605 pr_err("%s: Failed to set rate esc clk, %d\n", __func__, ret); 606 return ret; 607 } 608 609 ret = clk_set_rate(msm_host->src_clk, msm_host->src_clk_rate); 610 if (ret) { 611 pr_err("%s: Failed to set rate src clk, %d\n", __func__, ret); 612 return ret; 613 } 614 615 ret = clk_set_rate(msm_host->pixel_clk, msm_host->pixel_clk_rate); 616 if (ret) { 617 pr_err("%s: Failed to set rate pixel clk, %d\n", __func__, ret); 618 return ret; 619 } 620 621 return 0; 622} 623 624int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host) 625{ 626 int ret; 627 628 ret = clk_prepare_enable(msm_host->byte_clk); 629 if (ret) { 630 pr_err("%s: Failed to enable dsi byte clk\n", __func__); 631 goto error; 632 } 633 634 ret = clk_prepare_enable(msm_host->esc_clk); 635 if (ret) { 636 pr_err("%s: Failed to enable dsi esc clk\n", __func__); 637 goto esc_clk_err; 638 } 639 640 ret = clk_prepare_enable(msm_host->src_clk); 641 if (ret) { 642 pr_err("%s: Failed to enable dsi src clk\n", __func__); 643 goto src_clk_err; 644 } 645 646 ret = clk_prepare_enable(msm_host->pixel_clk); 647 if (ret) { 648 pr_err("%s: Failed to enable dsi pixel clk\n", __func__); 649 goto pixel_clk_err; 650 } 651 652 return 0; 653 654pixel_clk_err: 655 clk_disable_unprepare(msm_host->src_clk); 656src_clk_err: 657 clk_disable_unprepare(msm_host->esc_clk); 658esc_clk_err: 659 clk_disable_unprepare(msm_host->byte_clk); 660error: 661 return ret; 662} 663 664void dsi_link_clk_disable_6g(struct msm_dsi_host *msm_host) 665{ 666 /* Drop the performance state vote */ 667 dev_pm_opp_set_rate(&msm_host->pdev->dev, 0); 668 clk_disable_unprepare(msm_host->esc_clk); 669 clk_disable_unprepare(msm_host->pixel_clk); 670 if (msm_host->byte_intf_clk) 671 clk_disable_unprepare(msm_host->byte_intf_clk); 672 clk_disable_unprepare(msm_host->byte_clk); 673} 674 675void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) 676{ 677 clk_disable_unprepare(msm_host->pixel_clk); 678 clk_disable_unprepare(msm_host->src_clk); 679 clk_disable_unprepare(msm_host->esc_clk); 680 clk_disable_unprepare(msm_host->byte_clk); 681} 682 683static u32 dsi_get_pclk_rate(struct msm_dsi_host *msm_host, bool is_dual_dsi) 684{ 685 struct drm_display_mode *mode = msm_host->mode; 686 u32 pclk_rate; 687 688 pclk_rate = mode->clock * 1000; 689 690 /* 691 * For dual DSI mode, the current DRM mode has the complete width of the 692 * panel. Since, the complete panel is driven by two DSI controllers, 693 * the clock rates have to be split between the two dsi controllers. 694 * Adjust the byte and pixel clock rates for each dsi host accordingly. 695 */ 696 if (is_dual_dsi) 697 pclk_rate /= 2; 698 699 return pclk_rate; 700} 701 702static void dsi_calc_pclk(struct msm_dsi_host *msm_host, bool is_dual_dsi) 703{ 704 u8 lanes = msm_host->lanes; 705 u32 bpp = dsi_get_bpp(msm_host->format); 706 u32 pclk_rate = dsi_get_pclk_rate(msm_host, is_dual_dsi); 707 u64 pclk_bpp = (u64)pclk_rate * bpp; 708 709 if (lanes == 0) { 710 pr_err("%s: forcing mdss_dsi lanes to 1\n", __func__); 711 lanes = 1; 712 } 713 714 do_div(pclk_bpp, (8 * lanes)); 715 716 msm_host->pixel_clk_rate = pclk_rate; 717 msm_host->byte_clk_rate = pclk_bpp; 718 719 DBG("pclk=%d, bclk=%d", msm_host->pixel_clk_rate, 720 msm_host->byte_clk_rate); 721 722} 723 724int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_dual_dsi) 725{ 726 if (!msm_host->mode) { 727 pr_err("%s: mode not set\n", __func__); 728 return -EINVAL; 729 } 730 731 dsi_calc_pclk(msm_host, is_dual_dsi); 732 msm_host->esc_clk_rate = clk_get_rate(msm_host->esc_clk); 733 return 0; 734} 735 736int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_dual_dsi) 737{ 738 u32 bpp = dsi_get_bpp(msm_host->format); 739 u64 pclk_bpp; 740 unsigned int esc_mhz, esc_div; 741 unsigned long byte_mhz; 742 743 dsi_calc_pclk(msm_host, is_dual_dsi); 744 745 pclk_bpp = (u64)dsi_get_pclk_rate(msm_host, is_dual_dsi) * bpp; 746 do_div(pclk_bpp, 8); 747 msm_host->src_clk_rate = pclk_bpp; 748 749 /* 750 * esc clock is byte clock followed by a 4 bit divider, 751 * we need to find an escape clock frequency within the 752 * mipi DSI spec range within the maximum divider limit 753 * We iterate here between an escape clock frequencey 754 * between 20 Mhz to 5 Mhz and pick up the first one 755 * that can be supported by our divider 756 */ 757 758 byte_mhz = msm_host->byte_clk_rate / 1000000; 759 760 for (esc_mhz = 20; esc_mhz >= 5; esc_mhz--) { 761 esc_div = DIV_ROUND_UP(byte_mhz, esc_mhz); 762 763 /* 764 * TODO: Ideally, we shouldn't know what sort of divider 765 * is available in mmss_cc, we're just assuming that 766 * it'll always be a 4 bit divider. Need to come up with 767 * a better way here. 768 */ 769 if (esc_div >= 1 && esc_div <= 16) 770 break; 771 } 772 773 if (esc_mhz < 5) 774 return -EINVAL; 775 776 msm_host->esc_clk_rate = msm_host->byte_clk_rate / esc_div; 777 778 DBG("esc=%d, src=%d", msm_host->esc_clk_rate, 779 msm_host->src_clk_rate); 780 781 return 0; 782} 783 784static void dsi_intr_ctrl(struct msm_dsi_host *msm_host, u32 mask, int enable) 785{ 786 u32 intr; 787 unsigned long flags; 788 789 spin_lock_irqsave(&msm_host->intr_lock, flags); 790 intr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 791 792 if (enable) 793 intr |= mask; 794 else 795 intr &= ~mask; 796 797 DBG("intr=%x enable=%d", intr, enable); 798 799 dsi_write(msm_host, REG_DSI_INTR_CTRL, intr); 800 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 801} 802 803static inline enum dsi_traffic_mode dsi_get_traffic_mode(const u32 mode_flags) 804{ 805 if (mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 806 return BURST_MODE; 807 else if (mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 808 return NON_BURST_SYNCH_PULSE; 809 810 return NON_BURST_SYNCH_EVENT; 811} 812 813static inline enum dsi_vid_dst_format dsi_get_vid_fmt( 814 const enum mipi_dsi_pixel_format mipi_fmt) 815{ 816 switch (mipi_fmt) { 817 case MIPI_DSI_FMT_RGB888: return VID_DST_FORMAT_RGB888; 818 case MIPI_DSI_FMT_RGB666: return VID_DST_FORMAT_RGB666_LOOSE; 819 case MIPI_DSI_FMT_RGB666_PACKED: return VID_DST_FORMAT_RGB666; 820 case MIPI_DSI_FMT_RGB565: return VID_DST_FORMAT_RGB565; 821 default: return VID_DST_FORMAT_RGB888; 822 } 823} 824 825static inline enum dsi_cmd_dst_format dsi_get_cmd_fmt( 826 const enum mipi_dsi_pixel_format mipi_fmt) 827{ 828 switch (mipi_fmt) { 829 case MIPI_DSI_FMT_RGB888: return CMD_DST_FORMAT_RGB888; 830 case MIPI_DSI_FMT_RGB666_PACKED: 831 case MIPI_DSI_FMT_RGB666: return CMD_DST_FORMAT_RGB666; 832 case MIPI_DSI_FMT_RGB565: return CMD_DST_FORMAT_RGB565; 833 default: return CMD_DST_FORMAT_RGB888; 834 } 835} 836 837static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable, 838 struct msm_dsi_phy_shared_timings *phy_shared_timings) 839{ 840 u32 flags = msm_host->mode_flags; 841 enum mipi_dsi_pixel_format mipi_fmt = msm_host->format; 842 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 843 u32 data = 0, lane_ctrl = 0; 844 845 if (!enable) { 846 dsi_write(msm_host, REG_DSI_CTRL, 0); 847 return; 848 } 849 850 if (flags & MIPI_DSI_MODE_VIDEO) { 851 if (flags & MIPI_DSI_MODE_VIDEO_HSE) 852 data |= DSI_VID_CFG0_PULSE_MODE_HSA_HE; 853 if (flags & MIPI_DSI_MODE_VIDEO_HFP) 854 data |= DSI_VID_CFG0_HFP_POWER_STOP; 855 if (flags & MIPI_DSI_MODE_VIDEO_HBP) 856 data |= DSI_VID_CFG0_HBP_POWER_STOP; 857 if (flags & MIPI_DSI_MODE_VIDEO_HSA) 858 data |= DSI_VID_CFG0_HSA_POWER_STOP; 859 /* Always set low power stop mode for BLLP 860 * to let command engine send packets 861 */ 862 data |= DSI_VID_CFG0_EOF_BLLP_POWER_STOP | 863 DSI_VID_CFG0_BLLP_POWER_STOP; 864 data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); 865 data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); 866 data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); 867 dsi_write(msm_host, REG_DSI_VID_CFG0, data); 868 869 /* Do not swap RGB colors */ 870 data = DSI_VID_CFG1_RGB_SWAP(SWAP_RGB); 871 dsi_write(msm_host, REG_DSI_VID_CFG1, 0); 872 } else { 873 /* Do not swap RGB colors */ 874 data = DSI_CMD_CFG0_RGB_SWAP(SWAP_RGB); 875 data |= DSI_CMD_CFG0_DST_FORMAT(dsi_get_cmd_fmt(mipi_fmt)); 876 dsi_write(msm_host, REG_DSI_CMD_CFG0, data); 877 878 data = DSI_CMD_CFG1_WR_MEM_START(MIPI_DCS_WRITE_MEMORY_START) | 879 DSI_CMD_CFG1_WR_MEM_CONTINUE( 880 MIPI_DCS_WRITE_MEMORY_CONTINUE); 881 /* Always insert DCS command */ 882 data |= DSI_CMD_CFG1_INSERT_DCS_COMMAND; 883 dsi_write(msm_host, REG_DSI_CMD_CFG1, data); 884 } 885 886 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, 887 DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER | 888 DSI_CMD_DMA_CTRL_LOW_POWER); 889 890 data = 0; 891 /* Always assume dedicated TE pin */ 892 data |= DSI_TRIG_CTRL_TE; 893 data |= DSI_TRIG_CTRL_MDP_TRIGGER(TRIGGER_NONE); 894 data |= DSI_TRIG_CTRL_DMA_TRIGGER(TRIGGER_SW); 895 data |= DSI_TRIG_CTRL_STREAM(msm_host->channel); 896 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 897 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_2)) 898 data |= DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME; 899 dsi_write(msm_host, REG_DSI_TRIG_CTRL, data); 900 901 data = DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(phy_shared_timings->clk_post) | 902 DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(phy_shared_timings->clk_pre); 903 dsi_write(msm_host, REG_DSI_CLKOUT_TIMING_CTRL, data); 904 905 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 906 (cfg_hnd->minor > MSM_DSI_6G_VER_MINOR_V1_0) && 907 phy_shared_timings->clk_pre_inc_by_2) 908 dsi_write(msm_host, REG_DSI_T_CLK_PRE_EXTEND, 909 DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK); 910 911 data = 0; 912 if (!(flags & MIPI_DSI_MODE_EOT_PACKET)) 913 data |= DSI_EOT_PACKET_CTRL_TX_EOT_APPEND; 914 dsi_write(msm_host, REG_DSI_EOT_PACKET_CTRL, data); 915 916 /* allow only ack-err-status to generate interrupt */ 917 dsi_write(msm_host, REG_DSI_ERR_INT_MASK0, 0x13ff3fe0); 918 919 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 920 921 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 922 923 data = DSI_CTRL_CLK_EN; 924 925 DBG("lane number=%d", msm_host->lanes); 926 data |= ((DSI_CTRL_LANE0 << msm_host->lanes) - DSI_CTRL_LANE0); 927 928 dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL, 929 DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap)); 930 931 if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) { 932 lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL); 933 dsi_write(msm_host, REG_DSI_LANE_CTRL, 934 lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST); 935 } 936 937 data |= DSI_CTRL_ENABLE; 938 939 dsi_write(msm_host, REG_DSI_CTRL, data); 940} 941 942static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_dual_dsi) 943{ 944 struct drm_display_mode *mode = msm_host->mode; 945 u32 hs_start = 0, vs_start = 0; /* take sync start as 0 */ 946 u32 h_total = mode->htotal; 947 u32 v_total = mode->vtotal; 948 u32 hs_end = mode->hsync_end - mode->hsync_start; 949 u32 vs_end = mode->vsync_end - mode->vsync_start; 950 u32 ha_start = h_total - mode->hsync_start; 951 u32 ha_end = ha_start + mode->hdisplay; 952 u32 va_start = v_total - mode->vsync_start; 953 u32 va_end = va_start + mode->vdisplay; 954 u32 hdisplay = mode->hdisplay; 955 u32 wc; 956 957 DBG(""); 958 959 /* 960 * For dual DSI mode, the current DRM mode has 961 * the complete width of the panel. Since, the complete 962 * panel is driven by two DSI controllers, the horizontal 963 * timings have to be split between the two dsi controllers. 964 * Adjust the DSI host timing values accordingly. 965 */ 966 if (is_dual_dsi) { 967 h_total /= 2; 968 hs_end /= 2; 969 ha_start /= 2; 970 ha_end /= 2; 971 hdisplay /= 2; 972 } 973 974 if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { 975 dsi_write(msm_host, REG_DSI_ACTIVE_H, 976 DSI_ACTIVE_H_START(ha_start) | 977 DSI_ACTIVE_H_END(ha_end)); 978 dsi_write(msm_host, REG_DSI_ACTIVE_V, 979 DSI_ACTIVE_V_START(va_start) | 980 DSI_ACTIVE_V_END(va_end)); 981 dsi_write(msm_host, REG_DSI_TOTAL, 982 DSI_TOTAL_H_TOTAL(h_total - 1) | 983 DSI_TOTAL_V_TOTAL(v_total - 1)); 984 985 dsi_write(msm_host, REG_DSI_ACTIVE_HSYNC, 986 DSI_ACTIVE_HSYNC_START(hs_start) | 987 DSI_ACTIVE_HSYNC_END(hs_end)); 988 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_HPOS, 0); 989 dsi_write(msm_host, REG_DSI_ACTIVE_VSYNC_VPOS, 990 DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | 991 DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); 992 } else { /* command mode */ 993 /* image data and 1 byte write_memory_start cmd */ 994 wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; 995 996 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, 997 DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | 998 DSI_CMD_MDP_STREAM0_CTRL_VIRTUAL_CHANNEL( 999 msm_host->channel) | 1000 DSI_CMD_MDP_STREAM0_CTRL_DATA_TYPE( 1001 MIPI_DSI_DCS_LONG_WRITE)); 1002 1003 dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, 1004 DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | 1005 DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); 1006 } 1007} 1008 1009static void dsi_sw_reset(struct msm_dsi_host *msm_host) 1010{ 1011 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1012 wmb(); /* clocks need to be enabled before reset */ 1013 1014 dsi_write(msm_host, REG_DSI_RESET, 1); 1015 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1016 dsi_write(msm_host, REG_DSI_RESET, 0); 1017} 1018 1019static void dsi_op_mode_config(struct msm_dsi_host *msm_host, 1020 bool video_mode, bool enable) 1021{ 1022 u32 dsi_ctrl; 1023 1024 dsi_ctrl = dsi_read(msm_host, REG_DSI_CTRL); 1025 1026 if (!enable) { 1027 dsi_ctrl &= ~(DSI_CTRL_ENABLE | DSI_CTRL_VID_MODE_EN | 1028 DSI_CTRL_CMD_MODE_EN); 1029 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE | 1030 DSI_IRQ_MASK_VIDEO_DONE, 0); 1031 } else { 1032 if (video_mode) { 1033 dsi_ctrl |= DSI_CTRL_VID_MODE_EN; 1034 } else { /* command mode */ 1035 dsi_ctrl |= DSI_CTRL_CMD_MODE_EN; 1036 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_MDP_DONE, 1); 1037 } 1038 dsi_ctrl |= DSI_CTRL_ENABLE; 1039 } 1040 1041 dsi_write(msm_host, REG_DSI_CTRL, dsi_ctrl); 1042} 1043 1044static void dsi_set_tx_power_mode(int mode, struct msm_dsi_host *msm_host) 1045{ 1046 u32 data; 1047 1048 data = dsi_read(msm_host, REG_DSI_CMD_DMA_CTRL); 1049 1050 if (mode == 0) 1051 data &= ~DSI_CMD_DMA_CTRL_LOW_POWER; 1052 else 1053 data |= DSI_CMD_DMA_CTRL_LOW_POWER; 1054 1055 dsi_write(msm_host, REG_DSI_CMD_DMA_CTRL, data); 1056} 1057 1058static void dsi_wait4video_done(struct msm_dsi_host *msm_host) 1059{ 1060 u32 ret = 0; 1061 struct device *dev = &msm_host->pdev->dev; 1062 1063 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 1); 1064 1065 reinit_completion(&msm_host->video_comp); 1066 1067 ret = wait_for_completion_timeout(&msm_host->video_comp, 1068 msecs_to_jiffies(70)); 1069 1070 if (ret == 0) 1071 DRM_DEV_ERROR(dev, "wait for video done timed out\n"); 1072 1073 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_VIDEO_DONE, 0); 1074} 1075 1076static void dsi_wait4video_eng_busy(struct msm_dsi_host *msm_host) 1077{ 1078 u32 data; 1079 1080 if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) 1081 return; 1082 1083 data = dsi_read(msm_host, REG_DSI_STATUS0); 1084 1085 /* if video mode engine is not busy, its because 1086 * either timing engine was not turned on or the 1087 * DSI controller has finished transmitting the video 1088 * data already, so no need to wait in those cases 1089 */ 1090 if (!(data & DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY)) 1091 return; 1092 1093 if (msm_host->power_on && msm_host->enabled) { 1094 dsi_wait4video_done(msm_host); 1095 /* delay 4 ms to skip BLLP */ 1096 usleep_range(2000, 4000); 1097 } 1098} 1099 1100int dsi_tx_buf_alloc_6g(struct msm_dsi_host *msm_host, int size) 1101{ 1102 struct drm_device *dev = msm_host->dev; 1103 struct msm_drm_private *priv = dev->dev_private; 1104 uint64_t iova; 1105 u8 *data; 1106 1107 data = msm_gem_kernel_new(dev, size, MSM_BO_UNCACHED, 1108 priv->kms->aspace, 1109 &msm_host->tx_gem_obj, &iova); 1110 1111 if (IS_ERR(data)) { 1112 msm_host->tx_gem_obj = NULL; 1113 return PTR_ERR(data); 1114 } 1115 1116 msm_gem_object_set_name(msm_host->tx_gem_obj, "tx_gem"); 1117 1118 msm_host->tx_size = msm_host->tx_gem_obj->size; 1119 1120 return 0; 1121} 1122 1123int dsi_tx_buf_alloc_v2(struct msm_dsi_host *msm_host, int size) 1124{ 1125 struct drm_device *dev = msm_host->dev; 1126 1127 msm_host->tx_buf = dma_alloc_coherent(dev->dev, size, 1128 &msm_host->tx_buf_paddr, GFP_KERNEL); 1129 if (!msm_host->tx_buf) 1130 return -ENOMEM; 1131 1132 msm_host->tx_size = size; 1133 1134 return 0; 1135} 1136 1137static void dsi_tx_buf_free(struct msm_dsi_host *msm_host) 1138{ 1139 struct drm_device *dev = msm_host->dev; 1140 struct msm_drm_private *priv; 1141 1142 /* 1143 * This is possible if we're tearing down before we've had a chance to 1144 * fully initialize. A very real possibility if our probe is deferred, 1145 * in which case we'll hit msm_dsi_host_destroy() without having run 1146 * through the dsi_tx_buf_alloc(). 1147 */ 1148 if (!dev) 1149 return; 1150 1151 priv = dev->dev_private; 1152 if (msm_host->tx_gem_obj) { 1153 msm_gem_unpin_iova(msm_host->tx_gem_obj, priv->kms->aspace); 1154 drm_gem_object_put(msm_host->tx_gem_obj); 1155 msm_host->tx_gem_obj = NULL; 1156 } 1157 1158 if (msm_host->tx_buf) 1159 dma_free_coherent(dev->dev, msm_host->tx_size, msm_host->tx_buf, 1160 msm_host->tx_buf_paddr); 1161} 1162 1163void *dsi_tx_buf_get_6g(struct msm_dsi_host *msm_host) 1164{ 1165 return msm_gem_get_vaddr(msm_host->tx_gem_obj); 1166} 1167 1168void *dsi_tx_buf_get_v2(struct msm_dsi_host *msm_host) 1169{ 1170 return msm_host->tx_buf; 1171} 1172 1173void dsi_tx_buf_put_6g(struct msm_dsi_host *msm_host) 1174{ 1175 msm_gem_put_vaddr(msm_host->tx_gem_obj); 1176} 1177 1178/* 1179 * prepare cmd buffer to be txed 1180 */ 1181static int dsi_cmd_dma_add(struct msm_dsi_host *msm_host, 1182 const struct mipi_dsi_msg *msg) 1183{ 1184 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1185 struct mipi_dsi_packet packet; 1186 int len; 1187 int ret; 1188 u8 *data; 1189 1190 ret = mipi_dsi_create_packet(&packet, msg); 1191 if (ret) { 1192 pr_err("%s: create packet failed, %d\n", __func__, ret); 1193 return ret; 1194 } 1195 len = (packet.size + 3) & (~0x3); 1196 1197 if (len > msm_host->tx_size) { 1198 pr_err("%s: packet size is too big\n", __func__); 1199 return -EINVAL; 1200 } 1201 1202 data = cfg_hnd->ops->tx_buf_get(msm_host); 1203 if (IS_ERR(data)) { 1204 ret = PTR_ERR(data); 1205 pr_err("%s: get vaddr failed, %d\n", __func__, ret); 1206 return ret; 1207 } 1208 1209 /* MSM specific command format in memory */ 1210 data[0] = packet.header[1]; 1211 data[1] = packet.header[2]; 1212 data[2] = packet.header[0]; 1213 data[3] = BIT(7); /* Last packet */ 1214 if (mipi_dsi_packet_format_is_long(msg->type)) 1215 data[3] |= BIT(6); 1216 if (msg->rx_buf && msg->rx_len) 1217 data[3] |= BIT(5); 1218 1219 /* Long packet */ 1220 if (packet.payload && packet.payload_length) 1221 memcpy(data + 4, packet.payload, packet.payload_length); 1222 1223 /* Append 0xff to the end */ 1224 if (packet.size < len) 1225 memset(data + packet.size, 0xff, len - packet.size); 1226 1227 if (cfg_hnd->ops->tx_buf_put) 1228 cfg_hnd->ops->tx_buf_put(msm_host); 1229 1230 return len; 1231} 1232 1233/* 1234 * dsi_short_read1_resp: 1 parameter 1235 */ 1236static int dsi_short_read1_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1237{ 1238 u8 *data = msg->rx_buf; 1239 if (data && (msg->rx_len >= 1)) { 1240 *data = buf[1]; /* strip out dcs type */ 1241 return 1; 1242 } else { 1243 pr_err("%s: read data does not match with rx_buf len %zu\n", 1244 __func__, msg->rx_len); 1245 return -EINVAL; 1246 } 1247} 1248 1249/* 1250 * dsi_short_read2_resp: 2 parameter 1251 */ 1252static int dsi_short_read2_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1253{ 1254 u8 *data = msg->rx_buf; 1255 if (data && (msg->rx_len >= 2)) { 1256 data[0] = buf[1]; /* strip out dcs type */ 1257 data[1] = buf[2]; 1258 return 2; 1259 } else { 1260 pr_err("%s: read data does not match with rx_buf len %zu\n", 1261 __func__, msg->rx_len); 1262 return -EINVAL; 1263 } 1264} 1265 1266static int dsi_long_read_resp(u8 *buf, const struct mipi_dsi_msg *msg) 1267{ 1268 /* strip out 4 byte dcs header */ 1269 if (msg->rx_buf && msg->rx_len) 1270 memcpy(msg->rx_buf, buf + 4, msg->rx_len); 1271 1272 return msg->rx_len; 1273} 1274 1275int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1276{ 1277 struct drm_device *dev = msm_host->dev; 1278 struct msm_drm_private *priv = dev->dev_private; 1279 1280 if (!dma_base) 1281 return -EINVAL; 1282 1283 return msm_gem_get_and_pin_iova(msm_host->tx_gem_obj, 1284 priv->kms->aspace, dma_base); 1285} 1286 1287int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *dma_base) 1288{ 1289 if (!dma_base) 1290 return -EINVAL; 1291 1292 *dma_base = msm_host->tx_buf_paddr; 1293 return 0; 1294} 1295 1296static int dsi_cmd_dma_tx(struct msm_dsi_host *msm_host, int len) 1297{ 1298 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1299 int ret; 1300 uint64_t dma_base; 1301 bool triggered; 1302 1303 ret = cfg_hnd->ops->dma_base_get(msm_host, &dma_base); 1304 if (ret) { 1305 pr_err("%s: failed to get iova: %d\n", __func__, ret); 1306 return ret; 1307 } 1308 1309 reinit_completion(&msm_host->dma_comp); 1310 1311 dsi_wait4video_eng_busy(msm_host); 1312 1313 triggered = msm_dsi_manager_cmd_xfer_trigger( 1314 msm_host->id, dma_base, len); 1315 if (triggered) { 1316 ret = wait_for_completion_timeout(&msm_host->dma_comp, 1317 msecs_to_jiffies(200)); 1318 DBG("ret=%d", ret); 1319 if (ret == 0) 1320 ret = -ETIMEDOUT; 1321 else 1322 ret = len; 1323 } else 1324 ret = len; 1325 1326 return ret; 1327} 1328 1329static int dsi_cmd_dma_rx(struct msm_dsi_host *msm_host, 1330 u8 *buf, int rx_byte, int pkt_size) 1331{ 1332 u32 *temp, data; 1333 int i, j = 0, cnt; 1334 u32 read_cnt; 1335 u8 reg[16]; 1336 int repeated_bytes = 0; 1337 int buf_offset = buf - msm_host->rx_buf; 1338 1339 temp = (u32 *)reg; 1340 cnt = (rx_byte + 3) >> 2; 1341 if (cnt > 4) 1342 cnt = 4; /* 4 x 32 bits registers only */ 1343 1344 if (rx_byte == 4) 1345 read_cnt = 4; 1346 else 1347 read_cnt = pkt_size + 6; 1348 1349 /* 1350 * In case of multiple reads from the panel, after the first read, there 1351 * is possibility that there are some bytes in the payload repeating in 1352 * the RDBK_DATA registers. Since we read all the parameters from the 1353 * panel right from the first byte for every pass. We need to skip the 1354 * repeating bytes and then append the new parameters to the rx buffer. 1355 */ 1356 if (read_cnt > 16) { 1357 int bytes_shifted; 1358 /* Any data more than 16 bytes will be shifted out. 1359 * The temp read buffer should already contain these bytes. 1360 * The remaining bytes in read buffer are the repeated bytes. 1361 */ 1362 bytes_shifted = read_cnt - 16; 1363 repeated_bytes = buf_offset - bytes_shifted; 1364 } 1365 1366 for (i = cnt - 1; i >= 0; i--) { 1367 data = dsi_read(msm_host, REG_DSI_RDBK_DATA(i)); 1368 *temp++ = ntohl(data); /* to host byte order */ 1369 DBG("data = 0x%x and ntohl(data) = 0x%x", data, ntohl(data)); 1370 } 1371 1372 for (i = repeated_bytes; i < 16; i++) 1373 buf[j++] = reg[i]; 1374 1375 return j; 1376} 1377 1378static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, 1379 const struct mipi_dsi_msg *msg) 1380{ 1381 int len, ret; 1382 int bllp_len = msm_host->mode->hdisplay * 1383 dsi_get_bpp(msm_host->format) / 8; 1384 1385 len = dsi_cmd_dma_add(msm_host, msg); 1386 if (len < 0) { 1387 pr_err("%s: failed to add cmd type = 0x%x\n", 1388 __func__, msg->type); 1389 return len; 1390 } 1391 1392 /* for video mode, do not send cmds more than 1393 * one pixel line, since it only transmit it 1394 * during BLLP. 1395 */ 1396 /* TODO: if the command is sent in LP mode, the bit rate is only 1397 * half of esc clk rate. In this case, if the video is already 1398 * actively streaming, we need to check more carefully if the 1399 * command can be fit into one BLLP. 1400 */ 1401 if ((msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && (len > bllp_len)) { 1402 pr_err("%s: cmd cannot fit into BLLP period, len=%d\n", 1403 __func__, len); 1404 return -EINVAL; 1405 } 1406 1407 ret = dsi_cmd_dma_tx(msm_host, len); 1408 if (ret < 0) { 1409 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, len=%d, ret=%d\n", 1410 __func__, msg->type, (*(u8 *)(msg->tx_buf)), len, ret); 1411 return ret; 1412 } else if (ret < len) { 1413 pr_err("%s: cmd dma tx failed, type=0x%x, data0=0x%x, ret=%d len=%d\n", 1414 __func__, msg->type, (*(u8 *)(msg->tx_buf)), ret, len); 1415 return -EIO; 1416 } 1417 1418 return len; 1419} 1420 1421static void dsi_sw_reset_restore(struct msm_dsi_host *msm_host) 1422{ 1423 u32 data0, data1; 1424 1425 data0 = dsi_read(msm_host, REG_DSI_CTRL); 1426 data1 = data0; 1427 data1 &= ~DSI_CTRL_ENABLE; 1428 dsi_write(msm_host, REG_DSI_CTRL, data1); 1429 /* 1430 * dsi controller need to be disabled before 1431 * clocks turned on 1432 */ 1433 wmb(); 1434 1435 dsi_write(msm_host, REG_DSI_CLK_CTRL, DSI_CLK_CTRL_ENABLE_CLKS); 1436 wmb(); /* make sure clocks enabled */ 1437 1438 /* dsi controller can only be reset while clocks are running */ 1439 dsi_write(msm_host, REG_DSI_RESET, 1); 1440 msleep(DSI_RESET_TOGGLE_DELAY_MS); /* make sure reset happen */ 1441 dsi_write(msm_host, REG_DSI_RESET, 0); 1442 wmb(); /* controller out of reset */ 1443 dsi_write(msm_host, REG_DSI_CTRL, data0); 1444 wmb(); /* make sure dsi controller enabled again */ 1445} 1446 1447static void dsi_hpd_worker(struct work_struct *work) 1448{ 1449 struct msm_dsi_host *msm_host = 1450 container_of(work, struct msm_dsi_host, hpd_work); 1451 1452 drm_helper_hpd_irq_event(msm_host->dev); 1453} 1454 1455static void dsi_err_worker(struct work_struct *work) 1456{ 1457 struct msm_dsi_host *msm_host = 1458 container_of(work, struct msm_dsi_host, err_work); 1459 u32 status = msm_host->err_work_state; 1460 1461 pr_err_ratelimited("%s: status=%x\n", __func__, status); 1462 if (status & DSI_ERR_STATE_MDP_FIFO_UNDERFLOW) 1463 dsi_sw_reset_restore(msm_host); 1464 1465 /* It is safe to clear here because error irq is disabled. */ 1466 msm_host->err_work_state = 0; 1467 1468 /* enable dsi error interrupt */ 1469 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 1); 1470} 1471 1472static void dsi_ack_err_status(struct msm_dsi_host *msm_host) 1473{ 1474 u32 status; 1475 1476 status = dsi_read(msm_host, REG_DSI_ACK_ERR_STATUS); 1477 1478 if (status) { 1479 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, status); 1480 /* Writing of an extra 0 needed to clear error bits */ 1481 dsi_write(msm_host, REG_DSI_ACK_ERR_STATUS, 0); 1482 msm_host->err_work_state |= DSI_ERR_STATE_ACK; 1483 } 1484} 1485 1486static void dsi_timeout_status(struct msm_dsi_host *msm_host) 1487{ 1488 u32 status; 1489 1490 status = dsi_read(msm_host, REG_DSI_TIMEOUT_STATUS); 1491 1492 if (status) { 1493 dsi_write(msm_host, REG_DSI_TIMEOUT_STATUS, status); 1494 msm_host->err_work_state |= DSI_ERR_STATE_TIMEOUT; 1495 } 1496} 1497 1498static void dsi_dln0_phy_err(struct msm_dsi_host *msm_host) 1499{ 1500 u32 status; 1501 1502 status = dsi_read(msm_host, REG_DSI_DLN0_PHY_ERR); 1503 1504 if (status & (DSI_DLN0_PHY_ERR_DLN0_ERR_ESC | 1505 DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC | 1506 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL | 1507 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 | 1508 DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1)) { 1509 dsi_write(msm_host, REG_DSI_DLN0_PHY_ERR, status); 1510 msm_host->err_work_state |= DSI_ERR_STATE_DLN0_PHY; 1511 } 1512} 1513 1514static void dsi_fifo_status(struct msm_dsi_host *msm_host) 1515{ 1516 u32 status; 1517 1518 status = dsi_read(msm_host, REG_DSI_FIFO_STATUS); 1519 1520 /* fifo underflow, overflow */ 1521 if (status) { 1522 dsi_write(msm_host, REG_DSI_FIFO_STATUS, status); 1523 msm_host->err_work_state |= DSI_ERR_STATE_FIFO; 1524 if (status & DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW) 1525 msm_host->err_work_state |= 1526 DSI_ERR_STATE_MDP_FIFO_UNDERFLOW; 1527 } 1528} 1529 1530static void dsi_status(struct msm_dsi_host *msm_host) 1531{ 1532 u32 status; 1533 1534 status = dsi_read(msm_host, REG_DSI_STATUS0); 1535 1536 if (status & DSI_STATUS0_INTERLEAVE_OP_CONTENTION) { 1537 dsi_write(msm_host, REG_DSI_STATUS0, status); 1538 msm_host->err_work_state |= 1539 DSI_ERR_STATE_INTERLEAVE_OP_CONTENTION; 1540 } 1541} 1542 1543static void dsi_clk_status(struct msm_dsi_host *msm_host) 1544{ 1545 u32 status; 1546 1547 status = dsi_read(msm_host, REG_DSI_CLK_STATUS); 1548 1549 if (status & DSI_CLK_STATUS_PLL_UNLOCKED) { 1550 dsi_write(msm_host, REG_DSI_CLK_STATUS, status); 1551 msm_host->err_work_state |= DSI_ERR_STATE_PLL_UNLOCKED; 1552 } 1553} 1554 1555static void dsi_error(struct msm_dsi_host *msm_host) 1556{ 1557 /* disable dsi error interrupt */ 1558 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_ERROR, 0); 1559 1560 dsi_clk_status(msm_host); 1561 dsi_fifo_status(msm_host); 1562 dsi_ack_err_status(msm_host); 1563 dsi_timeout_status(msm_host); 1564 dsi_status(msm_host); 1565 dsi_dln0_phy_err(msm_host); 1566 1567 queue_work(msm_host->workqueue, &msm_host->err_work); 1568} 1569 1570static irqreturn_t dsi_host_irq(int irq, void *ptr) 1571{ 1572 struct msm_dsi_host *msm_host = ptr; 1573 u32 isr; 1574 unsigned long flags; 1575 1576 if (!msm_host->ctrl_base) 1577 return IRQ_HANDLED; 1578 1579 spin_lock_irqsave(&msm_host->intr_lock, flags); 1580 isr = dsi_read(msm_host, REG_DSI_INTR_CTRL); 1581 dsi_write(msm_host, REG_DSI_INTR_CTRL, isr); 1582 spin_unlock_irqrestore(&msm_host->intr_lock, flags); 1583 1584 DBG("isr=0x%x, id=%d", isr, msm_host->id); 1585 1586 if (isr & DSI_IRQ_ERROR) 1587 dsi_error(msm_host); 1588 1589 if (isr & DSI_IRQ_VIDEO_DONE) 1590 complete(&msm_host->video_comp); 1591 1592 if (isr & DSI_IRQ_CMD_DMA_DONE) 1593 complete(&msm_host->dma_comp); 1594 1595 return IRQ_HANDLED; 1596} 1597 1598static int dsi_host_init_panel_gpios(struct msm_dsi_host *msm_host, 1599 struct device *panel_device) 1600{ 1601 msm_host->disp_en_gpio = devm_gpiod_get_optional(panel_device, 1602 "disp-enable", 1603 GPIOD_OUT_LOW); 1604 if (IS_ERR(msm_host->disp_en_gpio)) { 1605 DBG("cannot get disp-enable-gpios %ld", 1606 PTR_ERR(msm_host->disp_en_gpio)); 1607 return PTR_ERR(msm_host->disp_en_gpio); 1608 } 1609 1610 msm_host->te_gpio = devm_gpiod_get_optional(panel_device, "disp-te", 1611 GPIOD_IN); 1612 if (IS_ERR(msm_host->te_gpio)) { 1613 DBG("cannot get disp-te-gpios %ld", PTR_ERR(msm_host->te_gpio)); 1614 return PTR_ERR(msm_host->te_gpio); 1615 } 1616 1617 return 0; 1618} 1619 1620static int dsi_host_attach(struct mipi_dsi_host *host, 1621 struct mipi_dsi_device *dsi) 1622{ 1623 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1624 int ret; 1625 1626 if (dsi->lanes > msm_host->num_data_lanes) 1627 return -EINVAL; 1628 1629 msm_host->channel = dsi->channel; 1630 msm_host->lanes = dsi->lanes; 1631 msm_host->format = dsi->format; 1632 msm_host->mode_flags = dsi->mode_flags; 1633 1634 /* Some gpios defined in panel DT need to be controlled by host */ 1635 ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); 1636 if (ret) 1637 return ret; 1638 1639 DBG("id=%d", msm_host->id); 1640 if (msm_host->dev) 1641 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1642 1643 return 0; 1644} 1645 1646static int dsi_host_detach(struct mipi_dsi_host *host, 1647 struct mipi_dsi_device *dsi) 1648{ 1649 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1650 1651 msm_host->device_node = NULL; 1652 1653 DBG("id=%d", msm_host->id); 1654 if (msm_host->dev) 1655 queue_work(msm_host->workqueue, &msm_host->hpd_work); 1656 1657 return 0; 1658} 1659 1660static ssize_t dsi_host_transfer(struct mipi_dsi_host *host, 1661 const struct mipi_dsi_msg *msg) 1662{ 1663 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1664 int ret; 1665 1666 if (!msg || !msm_host->power_on) 1667 return -EINVAL; 1668 1669 mutex_lock(&msm_host->cmd_mutex); 1670 ret = msm_dsi_manager_cmd_xfer(msm_host->id, msg); 1671 mutex_unlock(&msm_host->cmd_mutex); 1672 1673 return ret; 1674} 1675 1676static struct mipi_dsi_host_ops dsi_host_ops = { 1677 .attach = dsi_host_attach, 1678 .detach = dsi_host_detach, 1679 .transfer = dsi_host_transfer, 1680}; 1681 1682/* 1683 * List of supported physical to logical lane mappings. 1684 * For example, the 2nd entry represents the following mapping: 1685 * 1686 * "3012": Logic 3->Phys 0; Logic 0->Phys 1; Logic 1->Phys 2; Logic 2->Phys 3; 1687 */ 1688static const int supported_data_lane_swaps[][4] = { 1689 { 0, 1, 2, 3 }, 1690 { 3, 0, 1, 2 }, 1691 { 2, 3, 0, 1 }, 1692 { 1, 2, 3, 0 }, 1693 { 0, 3, 2, 1 }, 1694 { 1, 0, 3, 2 }, 1695 { 2, 1, 0, 3 }, 1696 { 3, 2, 1, 0 }, 1697}; 1698 1699static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, 1700 struct device_node *ep) 1701{ 1702 struct device *dev = &msm_host->pdev->dev; 1703 struct property *prop; 1704 u32 lane_map[4]; 1705 int ret, i, len, num_lanes; 1706 1707 prop = of_find_property(ep, "data-lanes", &len); 1708 if (!prop) { 1709 DRM_DEV_DEBUG(dev, 1710 "failed to find data lane mapping, using default\n"); 1711 /* Set the number of date lanes to 4 by default. */ 1712 msm_host->num_data_lanes = 4; 1713 return 0; 1714 } 1715 1716 num_lanes = len / sizeof(u32); 1717 1718 if (num_lanes < 1 || num_lanes > 4) { 1719 DRM_DEV_ERROR(dev, "bad number of data lanes\n"); 1720 return -EINVAL; 1721 } 1722 1723 msm_host->num_data_lanes = num_lanes; 1724 1725 ret = of_property_read_u32_array(ep, "data-lanes", lane_map, 1726 num_lanes); 1727 if (ret) { 1728 DRM_DEV_ERROR(dev, "failed to read lane data\n"); 1729 return ret; 1730 } 1731 1732 /* 1733 * compare DT specified physical-logical lane mappings with the ones 1734 * supported by hardware 1735 */ 1736 for (i = 0; i < ARRAY_SIZE(supported_data_lane_swaps); i++) { 1737 const int *swap = supported_data_lane_swaps[i]; 1738 int j; 1739 1740 /* 1741 * the data-lanes array we get from DT has a logical->physical 1742 * mapping. The "data lane swap" register field represents 1743 * supported configurations in a physical->logical mapping. 1744 * Translate the DT mapping to what we understand and find a 1745 * configuration that works. 1746 */ 1747 for (j = 0; j < num_lanes; j++) { 1748 if (lane_map[j] < 0 || lane_map[j] > 3) 1749 DRM_DEV_ERROR(dev, "bad physical lane entry %u\n", 1750 lane_map[j]); 1751 1752 if (swap[lane_map[j]] != j) 1753 break; 1754 } 1755 1756 if (j == num_lanes) { 1757 msm_host->dlane_swap = i; 1758 return 0; 1759 } 1760 } 1761 1762 return -EINVAL; 1763} 1764 1765static int dsi_host_parse_dt(struct msm_dsi_host *msm_host) 1766{ 1767 struct device *dev = &msm_host->pdev->dev; 1768 struct device_node *np = dev->of_node; 1769 struct device_node *endpoint, *device_node; 1770 int ret = 0; 1771 1772 /* 1773 * Get the endpoint of the output port of the DSI host. In our case, 1774 * this is mapped to port number with reg = 1. Don't return an error if 1775 * the remote endpoint isn't defined. It's possible that there is 1776 * nothing connected to the dsi output. 1777 */ 1778 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1779 if (!endpoint) { 1780 DRM_DEV_DEBUG(dev, "%s: no endpoint\n", __func__); 1781 return 0; 1782 } 1783 1784 ret = dsi_host_parse_lane_data(msm_host, endpoint); 1785 if (ret) { 1786 DRM_DEV_ERROR(dev, "%s: invalid lane configuration %d\n", 1787 __func__, ret); 1788 ret = -EINVAL; 1789 goto err; 1790 } 1791 1792 /* Get panel node from the output port's endpoint data */ 1793 device_node = of_graph_get_remote_node(np, 1, 0); 1794 if (!device_node) { 1795 DRM_DEV_DEBUG(dev, "%s: no valid device\n", __func__); 1796 ret = -ENODEV; 1797 goto err; 1798 } 1799 1800 msm_host->device_node = device_node; 1801 1802 if (of_property_read_bool(np, "syscon-sfpb")) { 1803 msm_host->sfpb = syscon_regmap_lookup_by_phandle(np, 1804 "syscon-sfpb"); 1805 if (IS_ERR(msm_host->sfpb)) { 1806 DRM_DEV_ERROR(dev, "%s: failed to get sfpb regmap\n", 1807 __func__); 1808 ret = PTR_ERR(msm_host->sfpb); 1809 } 1810 } 1811 1812 of_node_put(device_node); 1813 1814err: 1815 of_node_put(endpoint); 1816 1817 return ret; 1818} 1819 1820static int dsi_host_get_id(struct msm_dsi_host *msm_host) 1821{ 1822 struct platform_device *pdev = msm_host->pdev; 1823 const struct msm_dsi_config *cfg = msm_host->cfg_hnd->cfg; 1824 struct resource *res; 1825 int i; 1826 1827 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dsi_ctrl"); 1828 if (!res) 1829 return -EINVAL; 1830 1831 for (i = 0; i < cfg->num_dsi; i++) { 1832 if (cfg->io_start[i] == res->start) 1833 return i; 1834 } 1835 1836 return -EINVAL; 1837} 1838 1839int msm_dsi_host_init(struct msm_dsi *msm_dsi) 1840{ 1841 struct msm_dsi_host *msm_host = NULL; 1842 struct platform_device *pdev = msm_dsi->pdev; 1843 int ret; 1844 1845 msm_host = devm_kzalloc(&pdev->dev, sizeof(*msm_host), GFP_KERNEL); 1846 if (!msm_host) { 1847 pr_err("%s: FAILED: cannot alloc dsi host\n", 1848 __func__); 1849 ret = -ENOMEM; 1850 goto fail; 1851 } 1852 1853 msm_host->pdev = pdev; 1854 msm_dsi->host = &msm_host->base; 1855 1856 ret = dsi_host_parse_dt(msm_host); 1857 if (ret) { 1858 pr_err("%s: failed to parse dt\n", __func__); 1859 goto fail; 1860 } 1861 1862 msm_host->ctrl_base = msm_ioremap(pdev, "dsi_ctrl", "DSI CTRL"); 1863 if (IS_ERR(msm_host->ctrl_base)) { 1864 pr_err("%s: unable to map Dsi ctrl base\n", __func__); 1865 ret = PTR_ERR(msm_host->ctrl_base); 1866 goto fail; 1867 } 1868 1869 pm_runtime_enable(&pdev->dev); 1870 1871 msm_host->cfg_hnd = dsi_get_config(msm_host); 1872 if (!msm_host->cfg_hnd) { 1873 ret = -EINVAL; 1874 pr_err("%s: get config failed\n", __func__); 1875 goto fail; 1876 } 1877 1878 msm_host->id = dsi_host_get_id(msm_host); 1879 if (msm_host->id < 0) { 1880 ret = msm_host->id; 1881 pr_err("%s: unable to identify DSI host index\n", __func__); 1882 goto fail; 1883 } 1884 1885 /* fixup base address by io offset */ 1886 msm_host->ctrl_base += msm_host->cfg_hnd->cfg->io_offset; 1887 1888 ret = dsi_regulator_init(msm_host); 1889 if (ret) { 1890 pr_err("%s: regulator init failed\n", __func__); 1891 goto fail; 1892 } 1893 1894 ret = dsi_clk_init(msm_host); 1895 if (ret) { 1896 pr_err("%s: unable to initialize dsi clks\n", __func__); 1897 goto fail; 1898 } 1899 1900 msm_host->rx_buf = devm_kzalloc(&pdev->dev, SZ_4K, GFP_KERNEL); 1901 if (!msm_host->rx_buf) { 1902 ret = -ENOMEM; 1903 pr_err("%s: alloc rx temp buf failed\n", __func__); 1904 goto fail; 1905 } 1906 1907 msm_host->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "byte"); 1908 if (IS_ERR(msm_host->opp_table)) 1909 return PTR_ERR(msm_host->opp_table); 1910 /* OPP table is optional */ 1911 ret = dev_pm_opp_of_add_table(&pdev->dev); 1912 if (!ret) { 1913 msm_host->has_opp_table = true; 1914 } else if (ret != -ENODEV) { 1915 dev_err(&pdev->dev, "invalid OPP table in device tree\n"); 1916 dev_pm_opp_put_clkname(msm_host->opp_table); 1917 return ret; 1918 } 1919 1920 init_completion(&msm_host->dma_comp); 1921 init_completion(&msm_host->video_comp); 1922 mutex_init(&msm_host->dev_mutex); 1923 mutex_init(&msm_host->cmd_mutex); 1924 spin_lock_init(&msm_host->intr_lock); 1925 1926 /* setup workqueue */ 1927 msm_host->workqueue = alloc_ordered_workqueue("dsi_drm_work", 0); 1928 if (!msm_host->workqueue) 1929 return -ENOMEM; 1930 1931 INIT_WORK(&msm_host->err_work, dsi_err_worker); 1932 INIT_WORK(&msm_host->hpd_work, dsi_hpd_worker); 1933 1934 msm_dsi->id = msm_host->id; 1935 1936 DBG("Dsi Host %d initialized", msm_host->id); 1937 return 0; 1938 1939fail: 1940 return ret; 1941} 1942 1943void msm_dsi_host_destroy(struct mipi_dsi_host *host) 1944{ 1945 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1946 1947 DBG(""); 1948 dsi_tx_buf_free(msm_host); 1949 if (msm_host->workqueue) { 1950 flush_workqueue(msm_host->workqueue); 1951 destroy_workqueue(msm_host->workqueue); 1952 msm_host->workqueue = NULL; 1953 } 1954 1955 mutex_destroy(&msm_host->cmd_mutex); 1956 mutex_destroy(&msm_host->dev_mutex); 1957 1958 if (msm_host->has_opp_table) 1959 dev_pm_opp_of_remove_table(&msm_host->pdev->dev); 1960 dev_pm_opp_put_clkname(msm_host->opp_table); 1961 pm_runtime_disable(&msm_host->pdev->dev); 1962} 1963 1964int msm_dsi_host_modeset_init(struct mipi_dsi_host *host, 1965 struct drm_device *dev) 1966{ 1967 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 1968 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 1969 struct platform_device *pdev = msm_host->pdev; 1970 int ret; 1971 1972 msm_host->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1973 if (msm_host->irq < 0) { 1974 ret = msm_host->irq; 1975 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); 1976 return ret; 1977 } 1978 1979 ret = devm_request_irq(&pdev->dev, msm_host->irq, 1980 dsi_host_irq, IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 1981 "dsi_isr", msm_host); 1982 if (ret < 0) { 1983 DRM_DEV_ERROR(&pdev->dev, "failed to request IRQ%u: %d\n", 1984 msm_host->irq, ret); 1985 return ret; 1986 } 1987 1988 msm_host->dev = dev; 1989 ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K); 1990 if (ret) { 1991 pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret); 1992 return ret; 1993 } 1994 1995 return 0; 1996} 1997 1998int msm_dsi_host_register(struct mipi_dsi_host *host, bool check_defer) 1999{ 2000 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2001 int ret; 2002 2003 /* Register mipi dsi host */ 2004 if (!msm_host->registered) { 2005 host->dev = &msm_host->pdev->dev; 2006 host->ops = &dsi_host_ops; 2007 ret = mipi_dsi_host_register(host); 2008 if (ret) 2009 return ret; 2010 2011 msm_host->registered = true; 2012 2013 /* If the panel driver has not been probed after host register, 2014 * we should defer the host's probe. 2015 * It makes sure panel is connected when fbcon detects 2016 * connector status and gets the proper display mode to 2017 * create framebuffer. 2018 * Don't try to defer if there is nothing connected to the dsi 2019 * output 2020 */ 2021 if (check_defer && msm_host->device_node) { 2022 if (IS_ERR(of_drm_find_panel(msm_host->device_node))) 2023 if (!of_drm_find_bridge(msm_host->device_node)) 2024 return -EPROBE_DEFER; 2025 } 2026 } 2027 2028 return 0; 2029} 2030 2031void msm_dsi_host_unregister(struct mipi_dsi_host *host) 2032{ 2033 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2034 2035 if (msm_host->registered) { 2036 mipi_dsi_host_unregister(host); 2037 host->dev = NULL; 2038 host->ops = NULL; 2039 msm_host->registered = false; 2040 } 2041} 2042 2043int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, 2044 const struct mipi_dsi_msg *msg) 2045{ 2046 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2047 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2048 2049 /* TODO: make sure dsi_cmd_mdp is idle. 2050 * Since DSI6G v1.2.0, we can set DSI_TRIG_CTRL.BLOCK_DMA_WITHIN_FRAME 2051 * to ask H/W to wait until cmd mdp is idle. S/W wait is not needed. 2052 * How to handle the old versions? Wait for mdp cmd done? 2053 */ 2054 2055 /* 2056 * mdss interrupt is generated in mdp core clock domain 2057 * mdp clock need to be enabled to receive dsi interrupt 2058 */ 2059 pm_runtime_get_sync(&msm_host->pdev->dev); 2060 cfg_hnd->ops->link_clk_set_rate(msm_host); 2061 cfg_hnd->ops->link_clk_enable(msm_host); 2062 2063 /* TODO: vote for bus bandwidth */ 2064 2065 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2066 dsi_set_tx_power_mode(0, msm_host); 2067 2068 msm_host->dma_cmd_ctrl_restore = dsi_read(msm_host, REG_DSI_CTRL); 2069 dsi_write(msm_host, REG_DSI_CTRL, 2070 msm_host->dma_cmd_ctrl_restore | 2071 DSI_CTRL_CMD_MODE_EN | 2072 DSI_CTRL_ENABLE); 2073 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 1); 2074 2075 return 0; 2076} 2077 2078void msm_dsi_host_xfer_restore(struct mipi_dsi_host *host, 2079 const struct mipi_dsi_msg *msg) 2080{ 2081 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2082 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2083 2084 dsi_intr_ctrl(msm_host, DSI_IRQ_MASK_CMD_DMA_DONE, 0); 2085 dsi_write(msm_host, REG_DSI_CTRL, msm_host->dma_cmd_ctrl_restore); 2086 2087 if (!(msg->flags & MIPI_DSI_MSG_USE_LPM)) 2088 dsi_set_tx_power_mode(1, msm_host); 2089 2090 /* TODO: unvote for bus bandwidth */ 2091 2092 cfg_hnd->ops->link_clk_disable(msm_host); 2093 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2094} 2095 2096int msm_dsi_host_cmd_tx(struct mipi_dsi_host *host, 2097 const struct mipi_dsi_msg *msg) 2098{ 2099 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2100 2101 return dsi_cmds2buf_tx(msm_host, msg); 2102} 2103 2104int msm_dsi_host_cmd_rx(struct mipi_dsi_host *host, 2105 const struct mipi_dsi_msg *msg) 2106{ 2107 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2108 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2109 int data_byte, rx_byte, dlen, end; 2110 int short_response, diff, pkt_size, ret = 0; 2111 char cmd; 2112 int rlen = msg->rx_len; 2113 u8 *buf; 2114 2115 if (rlen <= 2) { 2116 short_response = 1; 2117 pkt_size = rlen; 2118 rx_byte = 4; 2119 } else { 2120 short_response = 0; 2121 data_byte = 10; /* first read */ 2122 if (rlen < data_byte) 2123 pkt_size = rlen; 2124 else 2125 pkt_size = data_byte; 2126 rx_byte = data_byte + 6; /* 4 header + 2 crc */ 2127 } 2128 2129 buf = msm_host->rx_buf; 2130 end = 0; 2131 while (!end) { 2132 u8 tx[2] = {pkt_size & 0xff, pkt_size >> 8}; 2133 struct mipi_dsi_msg max_pkt_size_msg = { 2134 .channel = msg->channel, 2135 .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, 2136 .tx_len = 2, 2137 .tx_buf = tx, 2138 }; 2139 2140 DBG("rlen=%d pkt_size=%d rx_byte=%d", 2141 rlen, pkt_size, rx_byte); 2142 2143 ret = dsi_cmds2buf_tx(msm_host, &max_pkt_size_msg); 2144 if (ret < 2) { 2145 pr_err("%s: Set max pkt size failed, %d\n", 2146 __func__, ret); 2147 return -EINVAL; 2148 } 2149 2150 if ((cfg_hnd->major == MSM_DSI_VER_MAJOR_6G) && 2151 (cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V1_1)) { 2152 /* Clear the RDBK_DATA registers */ 2153 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 2154 DSI_RDBK_DATA_CTRL_CLR); 2155 wmb(); /* make sure the RDBK registers are cleared */ 2156 dsi_write(msm_host, REG_DSI_RDBK_DATA_CTRL, 0); 2157 wmb(); /* release cleared status before transfer */ 2158 } 2159 2160 ret = dsi_cmds2buf_tx(msm_host, msg); 2161 if (ret < 0) { 2162 pr_err("%s: Read cmd Tx failed, %d\n", __func__, ret); 2163 return ret; 2164 } else if (ret < msg->tx_len) { 2165 pr_err("%s: Read cmd Tx failed, too short: %d\n", __func__, ret); 2166 return -ECOMM; 2167 } 2168 2169 /* 2170 * once cmd_dma_done interrupt received, 2171 * return data from client is ready and stored 2172 * at RDBK_DATA register already 2173 * since rx fifo is 16 bytes, dcs header is kept at first loop, 2174 * after that dcs header lost during shift into registers 2175 */ 2176 dlen = dsi_cmd_dma_rx(msm_host, buf, rx_byte, pkt_size); 2177 2178 if (dlen <= 0) 2179 return 0; 2180 2181 if (short_response) 2182 break; 2183 2184 if (rlen <= data_byte) { 2185 diff = data_byte - rlen; 2186 end = 1; 2187 } else { 2188 diff = 0; 2189 rlen -= data_byte; 2190 } 2191 2192 if (!end) { 2193 dlen -= 2; /* 2 crc */ 2194 dlen -= diff; 2195 buf += dlen; /* next start position */ 2196 data_byte = 14; /* NOT first read */ 2197 if (rlen < data_byte) 2198 pkt_size += rlen; 2199 else 2200 pkt_size += data_byte; 2201 DBG("buf=%p dlen=%d diff=%d", buf, dlen, diff); 2202 } 2203 } 2204 2205 /* 2206 * For single Long read, if the requested rlen < 10, 2207 * we need to shift the start position of rx 2208 * data buffer to skip the bytes which are not 2209 * updated. 2210 */ 2211 if (pkt_size < 10 && !short_response) 2212 buf = msm_host->rx_buf + (10 - rlen); 2213 else 2214 buf = msm_host->rx_buf; 2215 2216 cmd = buf[0]; 2217 switch (cmd) { 2218 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 2219 pr_err("%s: rx ACK_ERR_PACLAGE\n", __func__); 2220 ret = 0; 2221 break; 2222 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 2223 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 2224 ret = dsi_short_read1_resp(buf, msg); 2225 break; 2226 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 2227 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 2228 ret = dsi_short_read2_resp(buf, msg); 2229 break; 2230 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 2231 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 2232 ret = dsi_long_read_resp(buf, msg); 2233 break; 2234 default: 2235 pr_warn("%s:Invalid response cmd\n", __func__); 2236 ret = 0; 2237 } 2238 2239 return ret; 2240} 2241 2242void msm_dsi_host_cmd_xfer_commit(struct mipi_dsi_host *host, u32 dma_base, 2243 u32 len) 2244{ 2245 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2246 2247 dsi_write(msm_host, REG_DSI_DMA_BASE, dma_base); 2248 dsi_write(msm_host, REG_DSI_DMA_LEN, len); 2249 dsi_write(msm_host, REG_DSI_TRIG_DMA, 1); 2250 2251 /* Make sure trigger happens */ 2252 wmb(); 2253} 2254 2255int msm_dsi_host_set_src_pll(struct mipi_dsi_host *host, 2256 struct msm_dsi_pll *src_pll) 2257{ 2258 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2259 struct clk *byte_clk_provider, *pixel_clk_provider; 2260 int ret; 2261 2262 ret = msm_dsi_pll_get_clk_provider(src_pll, 2263 &byte_clk_provider, &pixel_clk_provider); 2264 if (ret) { 2265 pr_info("%s: can't get provider from pll, don't set parent\n", 2266 __func__); 2267 return 0; 2268 } 2269 2270 ret = clk_set_parent(msm_host->byte_clk_src, byte_clk_provider); 2271 if (ret) { 2272 pr_err("%s: can't set parent to byte_clk_src. ret=%d\n", 2273 __func__, ret); 2274 goto exit; 2275 } 2276 2277 ret = clk_set_parent(msm_host->pixel_clk_src, pixel_clk_provider); 2278 if (ret) { 2279 pr_err("%s: can't set parent to pixel_clk_src. ret=%d\n", 2280 __func__, ret); 2281 goto exit; 2282 } 2283 2284 if (msm_host->dsi_clk_src) { 2285 ret = clk_set_parent(msm_host->dsi_clk_src, pixel_clk_provider); 2286 if (ret) { 2287 pr_err("%s: can't set parent to dsi_clk_src. ret=%d\n", 2288 __func__, ret); 2289 goto exit; 2290 } 2291 } 2292 2293 if (msm_host->esc_clk_src) { 2294 ret = clk_set_parent(msm_host->esc_clk_src, byte_clk_provider); 2295 if (ret) { 2296 pr_err("%s: can't set parent to esc_clk_src. ret=%d\n", 2297 __func__, ret); 2298 goto exit; 2299 } 2300 } 2301 2302exit: 2303 return ret; 2304} 2305 2306void msm_dsi_host_reset_phy(struct mipi_dsi_host *host) 2307{ 2308 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2309 2310 DBG(""); 2311 dsi_write(msm_host, REG_DSI_PHY_RESET, DSI_PHY_RESET_RESET); 2312 /* Make sure fully reset */ 2313 wmb(); 2314 udelay(1000); 2315 dsi_write(msm_host, REG_DSI_PHY_RESET, 0); 2316 udelay(100); 2317} 2318 2319void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host *host, 2320 struct msm_dsi_phy_clk_request *clk_req, 2321 bool is_dual_dsi) 2322{ 2323 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2324 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2325 int ret; 2326 2327 ret = cfg_hnd->ops->calc_clk_rate(msm_host, is_dual_dsi); 2328 if (ret) { 2329 pr_err("%s: unable to calc clk rate, %d\n", __func__, ret); 2330 return; 2331 } 2332 2333 clk_req->bitclk_rate = msm_host->byte_clk_rate * 8; 2334 clk_req->escclk_rate = msm_host->esc_clk_rate; 2335} 2336 2337int msm_dsi_host_enable(struct mipi_dsi_host *host) 2338{ 2339 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2340 2341 dsi_op_mode_config(msm_host, 2342 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), true); 2343 2344 /* TODO: clock should be turned off for command mode, 2345 * and only turned on before MDP START. 2346 * This part of code should be enabled once mdp driver support it. 2347 */ 2348 /* if (msm_panel->mode == MSM_DSI_CMD_MODE) { 2349 * dsi_link_clk_disable(msm_host); 2350 * pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2351 * } 2352 */ 2353 msm_host->enabled = true; 2354 return 0; 2355} 2356 2357int msm_dsi_host_disable(struct mipi_dsi_host *host) 2358{ 2359 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2360 2361 msm_host->enabled = false; 2362 dsi_op_mode_config(msm_host, 2363 !!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO), false); 2364 2365 /* Since we have disabled INTF, the video engine won't stop so that 2366 * the cmd engine will be blocked. 2367 * Reset to disable video engine so that we can send off cmd. 2368 */ 2369 dsi_sw_reset(msm_host); 2370 2371 return 0; 2372} 2373 2374static void msm_dsi_sfpb_config(struct msm_dsi_host *msm_host, bool enable) 2375{ 2376 enum sfpb_ahb_arb_master_port_en en; 2377 2378 if (!msm_host->sfpb) 2379 return; 2380 2381 en = enable ? SFPB_MASTER_PORT_ENABLE : SFPB_MASTER_PORT_DISABLE; 2382 2383 regmap_update_bits(msm_host->sfpb, REG_SFPB_GPREG, 2384 SFPB_GPREG_MASTER_PORT_EN__MASK, 2385 SFPB_GPREG_MASTER_PORT_EN(en)); 2386} 2387 2388int msm_dsi_host_power_on(struct mipi_dsi_host *host, 2389 struct msm_dsi_phy_shared_timings *phy_shared_timings, 2390 bool is_dual_dsi) 2391{ 2392 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2393 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2394 int ret = 0; 2395 2396 mutex_lock(&msm_host->dev_mutex); 2397 if (msm_host->power_on) { 2398 DBG("dsi host already on"); 2399 goto unlock_ret; 2400 } 2401 2402 msm_dsi_sfpb_config(msm_host, true); 2403 2404 ret = dsi_host_regulator_enable(msm_host); 2405 if (ret) { 2406 pr_err("%s:Failed to enable vregs.ret=%d\n", 2407 __func__, ret); 2408 goto unlock_ret; 2409 } 2410 2411 pm_runtime_get_sync(&msm_host->pdev->dev); 2412 ret = cfg_hnd->ops->link_clk_set_rate(msm_host); 2413 if (!ret) 2414 ret = cfg_hnd->ops->link_clk_enable(msm_host); 2415 if (ret) { 2416 pr_err("%s: failed to enable link clocks. ret=%d\n", 2417 __func__, ret); 2418 goto fail_disable_reg; 2419 } 2420 2421 ret = pinctrl_pm_select_default_state(&msm_host->pdev->dev); 2422 if (ret) { 2423 pr_err("%s: failed to set pinctrl default state, %d\n", 2424 __func__, ret); 2425 goto fail_disable_clk; 2426 } 2427 2428 dsi_timing_setup(msm_host, is_dual_dsi); 2429 dsi_sw_reset(msm_host); 2430 dsi_ctrl_config(msm_host, true, phy_shared_timings); 2431 2432 if (msm_host->disp_en_gpio) 2433 gpiod_set_value(msm_host->disp_en_gpio, 1); 2434 2435 msm_host->power_on = true; 2436 mutex_unlock(&msm_host->dev_mutex); 2437 2438 return 0; 2439 2440fail_disable_clk: 2441 cfg_hnd->ops->link_clk_disable(msm_host); 2442 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2443fail_disable_reg: 2444 dsi_host_regulator_disable(msm_host); 2445unlock_ret: 2446 mutex_unlock(&msm_host->dev_mutex); 2447 return ret; 2448} 2449 2450int msm_dsi_host_power_off(struct mipi_dsi_host *host) 2451{ 2452 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2453 const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd; 2454 2455 mutex_lock(&msm_host->dev_mutex); 2456 if (!msm_host->power_on) { 2457 DBG("dsi host already off"); 2458 goto unlock_ret; 2459 } 2460 2461 dsi_ctrl_config(msm_host, false, NULL); 2462 2463 if (msm_host->disp_en_gpio) 2464 gpiod_set_value(msm_host->disp_en_gpio, 0); 2465 2466 pinctrl_pm_select_sleep_state(&msm_host->pdev->dev); 2467 2468 cfg_hnd->ops->link_clk_disable(msm_host); 2469 pm_runtime_put_autosuspend(&msm_host->pdev->dev); 2470 2471 dsi_host_regulator_disable(msm_host); 2472 2473 msm_dsi_sfpb_config(msm_host, false); 2474 2475 DBG("-"); 2476 2477 msm_host->power_on = false; 2478 2479unlock_ret: 2480 mutex_unlock(&msm_host->dev_mutex); 2481 return 0; 2482} 2483 2484int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, 2485 const struct drm_display_mode *mode) 2486{ 2487 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2488 2489 if (msm_host->mode) { 2490 drm_mode_destroy(msm_host->dev, msm_host->mode); 2491 msm_host->mode = NULL; 2492 } 2493 2494 msm_host->mode = drm_mode_duplicate(msm_host->dev, mode); 2495 if (!msm_host->mode) { 2496 pr_err("%s: cannot duplicate mode\n", __func__); 2497 return -ENOMEM; 2498 } 2499 2500 return 0; 2501} 2502 2503struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host) 2504{ 2505 return of_drm_find_panel(to_msm_dsi_host(host)->device_node); 2506} 2507 2508unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host) 2509{ 2510 return to_msm_dsi_host(host)->mode_flags; 2511} 2512 2513struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host) 2514{ 2515 struct msm_dsi_host *msm_host = to_msm_dsi_host(host); 2516 2517 return of_drm_find_bridge(msm_host->device_node); 2518} 2519