1/* SPDX-License-Identifier: GPL-2.0-only */ 2/* 3 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. 4 */ 5 6#ifndef _DP_REG_H_ 7#define _DP_REG_H_ 8 9/* DP_TX Registers */ 10#define REG_DP_HW_VERSION (0x00000000) 11 12#define REG_DP_SW_RESET (0x00000010) 13#define DP_SW_RESET (0x00000001) 14 15#define REG_DP_PHY_CTRL (0x00000014) 16#define DP_PHY_CTRL_SW_RESET_PLL (0x00000001) 17#define DP_PHY_CTRL_SW_RESET (0x00000004) 18 19#define REG_DP_CLK_CTRL (0x00000018) 20#define REG_DP_CLK_ACTIVE (0x0000001C) 21#define REG_DP_INTR_STATUS (0x00000020) 22#define REG_DP_INTR_STATUS2 (0x00000024) 23#define REG_DP_INTR_STATUS3 (0x00000028) 24 25#define REG_DP_DP_HPD_CTRL (0x00000000) 26#define DP_DP_HPD_CTRL_HPD_EN (0x00000001) 27 28#define REG_DP_DP_HPD_INT_STATUS (0x00000004) 29 30#define REG_DP_DP_HPD_INT_ACK (0x00000008) 31#define DP_DP_HPD_PLUG_INT_ACK (0x00000001) 32#define DP_DP_IRQ_HPD_INT_ACK (0x00000002) 33#define DP_DP_HPD_REPLUG_INT_ACK (0x00000004) 34#define DP_DP_HPD_UNPLUG_INT_ACK (0x00000008) 35#define DP_DP_HPD_STATE_STATUS_BITS_MASK (0x0000000F) 36#define DP_DP_HPD_STATE_STATUS_BITS_SHIFT (0x1C) 37 38#define REG_DP_DP_HPD_INT_MASK (0x0000000C) 39#define DP_DP_HPD_PLUG_INT_MASK (0x00000001) 40#define DP_DP_IRQ_HPD_INT_MASK (0x00000002) 41#define DP_DP_HPD_REPLUG_INT_MASK (0x00000004) 42#define DP_DP_HPD_UNPLUG_INT_MASK (0x00000008) 43#define DP_DP_HPD_INT_MASK (DP_DP_HPD_PLUG_INT_MASK | \ 44 DP_DP_IRQ_HPD_INT_MASK | \ 45 DP_DP_HPD_REPLUG_INT_MASK | \ 46 DP_DP_HPD_UNPLUG_INT_MASK) 47#define DP_DP_HPD_STATE_STATUS_CONNECTED (0x40000000) 48#define DP_DP_HPD_STATE_STATUS_PENDING (0x20000000) 49#define DP_DP_HPD_STATE_STATUS_DISCONNECTED (0x00000000) 50#define DP_DP_HPD_STATE_STATUS_MASK (0xE0000000) 51 52#define REG_DP_DP_HPD_REFTIMER (0x00000018) 53#define DP_DP_HPD_REFTIMER_ENABLE (1 << 16) 54 55#define REG_DP_DP_HPD_EVENT_TIME_0 (0x0000001C) 56#define REG_DP_DP_HPD_EVENT_TIME_1 (0x00000020) 57#define DP_DP_HPD_EVENT_TIME_0_VAL (0x3E800FA) 58#define DP_DP_HPD_EVENT_TIME_1_VAL (0x1F407D0) 59 60#define REG_DP_AUX_CTRL (0x00000030) 61#define DP_AUX_CTRL_ENABLE (0x00000001) 62#define DP_AUX_CTRL_RESET (0x00000002) 63 64#define REG_DP_AUX_DATA (0x00000034) 65#define DP_AUX_DATA_READ (0x00000001) 66#define DP_AUX_DATA_WRITE (0x00000000) 67#define DP_AUX_DATA_OFFSET (0x00000008) 68#define DP_AUX_DATA_INDEX_OFFSET (0x00000010) 69#define DP_AUX_DATA_MASK (0x0000ff00) 70#define DP_AUX_DATA_INDEX_WRITE (0x80000000) 71 72#define REG_DP_AUX_TRANS_CTRL (0x00000038) 73#define DP_AUX_TRANS_CTRL_I2C (0x00000100) 74#define DP_AUX_TRANS_CTRL_GO (0x00000200) 75#define DP_AUX_TRANS_CTRL_NO_SEND_ADDR (0x00000400) 76#define DP_AUX_TRANS_CTRL_NO_SEND_STOP (0x00000800) 77 78#define REG_DP_TIMEOUT_COUNT (0x0000003C) 79#define REG_DP_AUX_LIMITS (0x00000040) 80#define REG_DP_AUX_STATUS (0x00000044) 81 82#define DP_DPCD_CP_IRQ (0x201) 83#define DP_DPCD_RXSTATUS (0x69493) 84 85#define DP_INTERRUPT_TRANS_NUM (0x000000A0) 86 87#define REG_DP_MAINLINK_CTRL (0x00000000) 88#define DP_MAINLINK_CTRL_ENABLE (0x00000001) 89#define DP_MAINLINK_CTRL_RESET (0x00000002) 90#define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) 91#define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) 92 93#define REG_DP_STATE_CTRL (0x00000004) 94#define DP_STATE_CTRL_LINK_TRAINING_PATTERN1 (0x00000001) 95#define DP_STATE_CTRL_LINK_TRAINING_PATTERN2 (0x00000002) 96#define DP_STATE_CTRL_LINK_TRAINING_PATTERN3 (0x00000004) 97#define DP_STATE_CTRL_LINK_TRAINING_PATTERN4 (0x00000008) 98#define DP_STATE_CTRL_LINK_SYMBOL_ERR_MEASURE (0x00000010) 99#define DP_STATE_CTRL_LINK_PRBS7 (0x00000020) 100#define DP_STATE_CTRL_LINK_TEST_CUSTOM_PATTERN (0x00000040) 101#define DP_STATE_CTRL_SEND_VIDEO (0x00000080) 102#define DP_STATE_CTRL_PUSH_IDLE (0x00000100) 103 104#define REG_DP_CONFIGURATION_CTRL (0x00000008) 105#define DP_CONFIGURATION_CTRL_SYNC_ASYNC_CLK (0x00000001) 106#define DP_CONFIGURATION_CTRL_STATIC_DYNAMIC_CN (0x00000002) 107#define DP_CONFIGURATION_CTRL_P_INTERLACED (0x00000004) 108#define DP_CONFIGURATION_CTRL_INTERLACED_BTF (0x00000008) 109#define DP_CONFIGURATION_CTRL_NUM_OF_LANES (0x00000010) 110#define DP_CONFIGURATION_CTRL_ENHANCED_FRAMING (0x00000040) 111#define DP_CONFIGURATION_CTRL_SEND_VSC (0x00000080) 112#define DP_CONFIGURATION_CTRL_BPC (0x00000100) 113#define DP_CONFIGURATION_CTRL_ASSR (0x00000400) 114#define DP_CONFIGURATION_CTRL_RGB_YUV (0x00000800) 115#define DP_CONFIGURATION_CTRL_LSCLK_DIV (0x00002000) 116#define DP_CONFIGURATION_CTRL_NUM_OF_LANES_SHIFT (0x04) 117#define DP_CONFIGURATION_CTRL_BPC_SHIFT (0x08) 118#define DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT (0x0D) 119 120#define REG_DP_SOFTWARE_MVID (0x00000010) 121#define REG_DP_SOFTWARE_NVID (0x00000018) 122#define REG_DP_TOTAL_HOR_VER (0x0000001C) 123#define REG_DP_START_HOR_VER_FROM_SYNC (0x00000020) 124#define REG_DP_HSYNC_VSYNC_WIDTH_POLARITY (0x00000024) 125#define REG_DP_ACTIVE_HOR_VER (0x00000028) 126 127#define REG_DP_MISC1_MISC0 (0x0000002C) 128#define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) 129#define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) 130#define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) 131 132#define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB (0) 133#define DP_MISC0_COLORIMERY_CFG_CEA_RGB (0x04) 134 135#define REG_DP_VALID_BOUNDARY (0x00000030) 136#define REG_DP_VALID_BOUNDARY_2 (0x00000034) 137 138#define REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING (0x00000038) 139#define LANE0_MAPPING_SHIFT (0x00000000) 140#define LANE1_MAPPING_SHIFT (0x00000002) 141#define LANE2_MAPPING_SHIFT (0x00000004) 142#define LANE3_MAPPING_SHIFT (0x00000006) 143 144#define REG_DP_MAINLINK_READY (0x00000040) 145#define DP_MAINLINK_READY_FOR_VIDEO (0x00000001) 146#define DP_MAINLINK_READY_LINK_TRAINING_SHIFT (0x00000003) 147 148#define REG_DP_MAINLINK_LEVELS (0x00000044) 149#define DP_MAINLINK_SAFE_TO_EXIT_LEVEL_2 (0x00000002) 150 151 152#define REG_DP_TU (0x0000004C) 153 154#define REG_DP_HBR2_COMPLIANCE_SCRAMBLER_RESET (0x00000054) 155#define DP_HBR2_ERM_PATTERN (0x00010000) 156 157#define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG0 (0x000000C0) 158#define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG1 (0x000000C4) 159#define REG_DP_TEST_80BIT_CUSTOM_PATTERN_REG2 (0x000000C8) 160 161#define MMSS_DP_MISC1_MISC0 (0x0000002C) 162#define MMSS_DP_AUDIO_TIMING_GEN (0x00000080) 163#define MMSS_DP_AUDIO_TIMING_RBR_32 (0x00000084) 164#define MMSS_DP_AUDIO_TIMING_HBR_32 (0x00000088) 165#define MMSS_DP_AUDIO_TIMING_RBR_44 (0x0000008C) 166#define MMSS_DP_AUDIO_TIMING_HBR_44 (0x00000090) 167#define MMSS_DP_AUDIO_TIMING_RBR_48 (0x00000094) 168#define MMSS_DP_AUDIO_TIMING_HBR_48 (0x00000098) 169 170#define MMSS_DP_PSR_CRC_RG (0x00000154) 171#define MMSS_DP_PSR_CRC_B (0x00000158) 172 173#define REG_DP_COMPRESSION_MODE_CTRL (0x00000180) 174 175#define MMSS_DP_AUDIO_CFG (0x00000200) 176#define MMSS_DP_AUDIO_STATUS (0x00000204) 177#define MMSS_DP_AUDIO_PKT_CTRL (0x00000208) 178#define MMSS_DP_AUDIO_PKT_CTRL2 (0x0000020C) 179#define MMSS_DP_AUDIO_ACR_CTRL (0x00000210) 180#define MMSS_DP_AUDIO_CTRL_RESET (0x00000214) 181 182#define MMSS_DP_SDP_CFG (0x00000228) 183#define MMSS_DP_SDP_CFG2 (0x0000022C) 184#define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) 185#define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234) 186 187#define MMSS_DP_AUDIO_STREAM_0 (0x00000240) 188#define MMSS_DP_AUDIO_STREAM_1 (0x00000244) 189 190#define MMSS_DP_EXTENSION_0 (0x00000250) 191#define MMSS_DP_EXTENSION_1 (0x00000254) 192#define MMSS_DP_EXTENSION_2 (0x00000258) 193#define MMSS_DP_EXTENSION_3 (0x0000025C) 194#define MMSS_DP_EXTENSION_4 (0x00000260) 195#define MMSS_DP_EXTENSION_5 (0x00000264) 196#define MMSS_DP_EXTENSION_6 (0x00000268) 197#define MMSS_DP_EXTENSION_7 (0x0000026C) 198#define MMSS_DP_EXTENSION_8 (0x00000270) 199#define MMSS_DP_EXTENSION_9 (0x00000274) 200#define MMSS_DP_AUDIO_COPYMANAGEMENT_0 (0x00000278) 201#define MMSS_DP_AUDIO_COPYMANAGEMENT_1 (0x0000027C) 202#define MMSS_DP_AUDIO_COPYMANAGEMENT_2 (0x00000280) 203#define MMSS_DP_AUDIO_COPYMANAGEMENT_3 (0x00000284) 204#define MMSS_DP_AUDIO_COPYMANAGEMENT_4 (0x00000288) 205#define MMSS_DP_AUDIO_COPYMANAGEMENT_5 (0x0000028C) 206#define MMSS_DP_AUDIO_ISRC_0 (0x00000290) 207#define MMSS_DP_AUDIO_ISRC_1 (0x00000294) 208#define MMSS_DP_AUDIO_ISRC_2 (0x00000298) 209#define MMSS_DP_AUDIO_ISRC_3 (0x0000029C) 210#define MMSS_DP_AUDIO_ISRC_4 (0x000002A0) 211#define MMSS_DP_AUDIO_ISRC_5 (0x000002A4) 212#define MMSS_DP_AUDIO_INFOFRAME_0 (0x000002A8) 213#define MMSS_DP_AUDIO_INFOFRAME_1 (0x000002AC) 214#define MMSS_DP_AUDIO_INFOFRAME_2 (0x000002B0) 215 216#define MMSS_DP_GENERIC0_0 (0x00000300) 217#define MMSS_DP_GENERIC0_1 (0x00000304) 218#define MMSS_DP_GENERIC0_2 (0x00000308) 219#define MMSS_DP_GENERIC0_3 (0x0000030C) 220#define MMSS_DP_GENERIC0_4 (0x00000310) 221#define MMSS_DP_GENERIC0_5 (0x00000314) 222#define MMSS_DP_GENERIC0_6 (0x00000318) 223#define MMSS_DP_GENERIC0_7 (0x0000031C) 224#define MMSS_DP_GENERIC0_8 (0x00000320) 225#define MMSS_DP_GENERIC0_9 (0x00000324) 226#define MMSS_DP_GENERIC1_0 (0x00000328) 227#define MMSS_DP_GENERIC1_1 (0x0000032C) 228#define MMSS_DP_GENERIC1_2 (0x00000330) 229#define MMSS_DP_GENERIC1_3 (0x00000334) 230#define MMSS_DP_GENERIC1_4 (0x00000338) 231#define MMSS_DP_GENERIC1_5 (0x0000033C) 232#define MMSS_DP_GENERIC1_6 (0x00000340) 233#define MMSS_DP_GENERIC1_7 (0x00000344) 234#define MMSS_DP_GENERIC1_8 (0x00000348) 235#define MMSS_DP_GENERIC1_9 (0x0000034C) 236 237#define MMSS_DP_VSCEXT_0 (0x000002D0) 238#define MMSS_DP_VSCEXT_1 (0x000002D4) 239#define MMSS_DP_VSCEXT_2 (0x000002D8) 240#define MMSS_DP_VSCEXT_3 (0x000002DC) 241#define MMSS_DP_VSCEXT_4 (0x000002E0) 242#define MMSS_DP_VSCEXT_5 (0x000002E4) 243#define MMSS_DP_VSCEXT_6 (0x000002E8) 244#define MMSS_DP_VSCEXT_7 (0x000002EC) 245#define MMSS_DP_VSCEXT_8 (0x000002F0) 246#define MMSS_DP_VSCEXT_9 (0x000002F4) 247 248#define MMSS_DP_BIST_ENABLE (0x00000000) 249#define DP_BIST_ENABLE_DPBIST_EN (0x00000001) 250 251#define MMSS_DP_TIMING_ENGINE_EN (0x00000010) 252#define DP_TIMING_ENGINE_EN_EN (0x00000001) 253 254#define MMSS_DP_INTF_CONFIG (0x00000014) 255#define MMSS_DP_INTF_HSYNC_CTL (0x00000018) 256#define MMSS_DP_INTF_VSYNC_PERIOD_F0 (0x0000001C) 257#define MMSS_DP_INTF_VSYNC_PERIOD_F1 (0x00000020) 258#define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F0 (0x00000024) 259#define MMSS_DP_INTF_VSYNC_PULSE_WIDTH_F1 (0x00000028) 260#define MMSS_INTF_DISPLAY_V_START_F0 (0x0000002C) 261#define MMSS_INTF_DISPLAY_V_START_F1 (0x00000030) 262#define MMSS_DP_INTF_DISPLAY_V_END_F0 (0x00000034) 263#define MMSS_DP_INTF_DISPLAY_V_END_F1 (0x00000038) 264#define MMSS_DP_INTF_ACTIVE_V_START_F0 (0x0000003C) 265#define MMSS_DP_INTF_ACTIVE_V_START_F1 (0x00000040) 266#define MMSS_DP_INTF_ACTIVE_V_END_F0 (0x00000044) 267#define MMSS_DP_INTF_ACTIVE_V_END_F1 (0x00000048) 268#define MMSS_DP_INTF_DISPLAY_HCTL (0x0000004C) 269#define MMSS_DP_INTF_ACTIVE_HCTL (0x00000050) 270#define MMSS_DP_INTF_POLARITY_CTL (0x00000058) 271 272#define MMSS_DP_TPG_MAIN_CONTROL (0x00000060) 273#define MMSS_DP_DSC_DTO (0x0000007C) 274#define DP_TPG_CHECKERED_RECT_PATTERN (0x00000100) 275 276#define MMSS_DP_TPG_VIDEO_CONFIG (0x00000064) 277#define DP_TPG_VIDEO_CONFIG_BPP_8BIT (0x00000001) 278#define DP_TPG_VIDEO_CONFIG_RGB (0x00000004) 279 280#define MMSS_DP_ASYNC_FIFO_CONFIG (0x00000088) 281 282#define REG_DP_PHY_AUX_INTERRUPT_CLEAR (0x0000004C) 283#define REG_DP_PHY_AUX_BIST_CFG (0x00000050) 284#define REG_DP_PHY_AUX_INTERRUPT_STATUS (0x000000BC) 285 286/* DP HDCP 1.3 registers */ 287#define DP_HDCP_CTRL (0x0A0) 288#define DP_HDCP_STATUS (0x0A4) 289#define DP_HDCP_SW_UPPER_AKSV (0x098) 290#define DP_HDCP_SW_LOWER_AKSV (0x09C) 291#define DP_HDCP_ENTROPY_CTRL0 (0x350) 292#define DP_HDCP_ENTROPY_CTRL1 (0x35C) 293#define DP_HDCP_SHA_STATUS (0x0C8) 294#define DP_HDCP_RCVPORT_DATA2_0 (0x0B0) 295#define DP_HDCP_RCVPORT_DATA3 (0x0A4) 296#define DP_HDCP_RCVPORT_DATA4 (0x0A8) 297#define DP_HDCP_RCVPORT_DATA5 (0x0C0) 298#define DP_HDCP_RCVPORT_DATA6 (0x0C4) 299 300#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_CTRL (0x024) 301#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_SHA_DATA (0x028) 302#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA0 (0x004) 303#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA1 (0x008) 304#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA7 (0x00C) 305#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA8 (0x010) 306#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA9 (0x014) 307#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA10 (0x018) 308#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA11 (0x01C) 309#define HDCP_SEC_DP_TZ_HV_HLOS_HDCP_RCVPORT_DATA12 (0x020) 310 311#endif /* _DP_REG_H_ */ 312