1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 *
6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
7 */
8
9#ifndef __ADRENO_GPU_H__
10#define __ADRENO_GPU_H__
11
12#include <linux/firmware.h>
13#include <linux/iopoll.h>
14
15#include "msm_gpu.h"
16
17#include "adreno_common.xml.h"
18#include "adreno_pm4.xml.h"
19
20extern bool snapshot_debugbus;
21
22enum {
23	ADRENO_FW_PM4 = 0,
24	ADRENO_FW_SQE = 0, /* a6xx */
25	ADRENO_FW_PFP = 1,
26	ADRENO_FW_GMU = 1, /* a6xx */
27	ADRENO_FW_GPMU = 2,
28	ADRENO_FW_MAX,
29};
30
31#define ADRENO_QUIRK_TWO_PASS_USE_WFI		BIT(0)
32#define ADRENO_QUIRK_FAULT_DETECT_MASK		BIT(1)
33#define ADRENO_QUIRK_LMLOADKILL_DISABLE		BIT(2)
34
35struct adreno_rev {
36	uint8_t  core;
37	uint8_t  major;
38	uint8_t  minor;
39	uint8_t  patchid;
40};
41
42#define ADRENO_REV(core, major, minor, patchid) \
43	((struct adreno_rev){ core, major, minor, patchid })
44
45struct adreno_gpu_funcs {
46	struct msm_gpu_funcs base;
47	int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
48};
49
50struct adreno_reglist {
51	u32 offset;
52	u32 value;
53};
54
55extern const struct adreno_reglist a630_hwcg[], a640_hwcg[], a650_hwcg[];
56
57struct adreno_info {
58	struct adreno_rev rev;
59	uint32_t revn;
60	const char *name;
61	const char *fw[ADRENO_FW_MAX];
62	uint32_t gmem;
63	u64 quirks;
64	struct msm_gpu *(*init)(struct drm_device *dev);
65	const char *zapfw;
66	u32 inactive_period;
67	const struct adreno_reglist *hwcg;
68};
69
70const struct adreno_info *adreno_info(struct adreno_rev rev);
71
72struct adreno_gpu {
73	struct msm_gpu base;
74	struct adreno_rev rev;
75	const struct adreno_info *info;
76	uint32_t gmem;  /* actual gmem size */
77	uint32_t revn;  /* numeric revision name */
78	const struct adreno_gpu_funcs *funcs;
79
80	/* interesting register offsets to dump: */
81	const unsigned int *registers;
82
83	/*
84	 * Are we loading fw from legacy path?  Prior to addition
85	 * of gpu firmware to linux-firmware, the fw files were
86	 * placed in toplevel firmware directory, following qcom's
87	 * android kernel.  But linux-firmware preferred they be
88	 * placed in a 'qcom' subdirectory.
89	 *
90	 * For backwards compatibility, we try first to load from
91	 * the new path, using request_firmware_direct() to avoid
92	 * any potential timeout waiting for usermode helper, then
93	 * fall back to the old path (with direct load).  And
94	 * finally fall back to request_firmware() with the new
95	 * path to allow the usermode helper.
96	 */
97	enum {
98		FW_LOCATION_UNKNOWN = 0,
99		FW_LOCATION_NEW,       /* /lib/firmware/qcom/$fwfile */
100		FW_LOCATION_LEGACY,    /* /lib/firmware/$fwfile */
101		FW_LOCATION_HELPER,
102	} fwloc;
103
104	/* firmware: */
105	const struct firmware *fw[ADRENO_FW_MAX];
106
107	/*
108	 * Register offsets are different between some GPUs.
109	 * GPU specific offsets will be exported by GPU specific
110	 * code (a3xx_gpu.c) and stored in this common location.
111	 */
112	const unsigned int *reg_offsets;
113};
114#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
115
116struct adreno_ocmem {
117	struct ocmem *ocmem;
118	unsigned long base;
119	void *hdl;
120};
121
122/* platform config data (ie. from DT, or pdata) */
123struct adreno_platform_config {
124	struct adreno_rev rev;
125};
126
127#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
128
129#define spin_until(X) ({                                   \
130	int __ret = -ETIMEDOUT;                            \
131	unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
132	do {                                               \
133		if (X) {                                   \
134			__ret = 0;                         \
135			break;                             \
136		}                                          \
137	} while (time_before(jiffies, __t));               \
138	__ret;                                             \
139})
140
141static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
142{
143	return (gpu->revn < 300);
144}
145
146static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
147{
148	return (gpu->revn < 210);
149}
150
151static inline bool adreno_is_a225(struct adreno_gpu *gpu)
152{
153	return gpu->revn == 225;
154}
155
156static inline bool adreno_is_a305(struct adreno_gpu *gpu)
157{
158	return gpu->revn == 305;
159}
160
161static inline bool adreno_is_a306(struct adreno_gpu *gpu)
162{
163	/* yes, 307, because a305c is 306 */
164	return gpu->revn == 307;
165}
166
167static inline bool adreno_is_a320(struct adreno_gpu *gpu)
168{
169	return gpu->revn == 320;
170}
171
172static inline bool adreno_is_a330(struct adreno_gpu *gpu)
173{
174	return gpu->revn == 330;
175}
176
177static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
178{
179	return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
180}
181
182static inline int adreno_is_a405(struct adreno_gpu *gpu)
183{
184	return gpu->revn == 405;
185}
186
187static inline int adreno_is_a420(struct adreno_gpu *gpu)
188{
189	return gpu->revn == 420;
190}
191
192static inline int adreno_is_a430(struct adreno_gpu *gpu)
193{
194       return gpu->revn == 430;
195}
196
197static inline int adreno_is_a510(struct adreno_gpu *gpu)
198{
199	return gpu->revn == 510;
200}
201
202static inline int adreno_is_a530(struct adreno_gpu *gpu)
203{
204	return gpu->revn == 530;
205}
206
207static inline int adreno_is_a540(struct adreno_gpu *gpu)
208{
209	return gpu->revn == 540;
210}
211
212static inline int adreno_is_a618(struct adreno_gpu *gpu)
213{
214       return gpu->revn == 618;
215}
216
217static inline int adreno_is_a630(struct adreno_gpu *gpu)
218{
219       return gpu->revn == 630;
220}
221
222static inline int adreno_is_a640(struct adreno_gpu *gpu)
223{
224       return gpu->revn == 640;
225}
226
227static inline int adreno_is_a650(struct adreno_gpu *gpu)
228{
229       return gpu->revn == 650;
230}
231
232int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
233const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
234		const char *fwname);
235struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
236		const struct firmware *fw, u64 *iova);
237int adreno_hw_init(struct msm_gpu *gpu);
238void adreno_recover(struct msm_gpu *gpu);
239void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
240bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
241#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
242void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
243		struct drm_printer *p);
244#endif
245void adreno_dump_info(struct msm_gpu *gpu);
246void adreno_dump(struct msm_gpu *gpu);
247void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
248struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
249
250int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
251			  struct adreno_ocmem *ocmem);
252void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
253
254int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
255		struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
256		int nr_rings);
257void adreno_gpu_cleanup(struct adreno_gpu *gpu);
258int adreno_load_fw(struct adreno_gpu *adreno_gpu);
259
260void adreno_gpu_state_destroy(struct msm_gpu_state *state);
261
262int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
263int adreno_gpu_state_put(struct msm_gpu_state *state);
264
265/*
266 * Common helper function to initialize the default address space for arm-smmu
267 * attached targets
268 */
269struct msm_gem_address_space *
270adreno_iommu_create_address_space(struct msm_gpu *gpu,
271		struct platform_device *pdev);
272
273/*
274 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
275 * out of secure mode
276 */
277int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
278
279/* ringbuffer helpers (the parts that are adreno specific) */
280
281static inline void
282OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
283{
284	adreno_wait_ring(ring, cnt+1);
285	OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
286}
287
288/* no-op packet: */
289static inline void
290OUT_PKT2(struct msm_ringbuffer *ring)
291{
292	adreno_wait_ring(ring, 1);
293	OUT_RING(ring, CP_TYPE2_PKT);
294}
295
296static inline void
297OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
298{
299	adreno_wait_ring(ring, cnt+1);
300	OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
301}
302
303static inline u32 PM4_PARITY(u32 val)
304{
305	return (0x9669 >> (0xF & (val ^
306		(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
307		(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
308		(val >> 28)))) & 1;
309}
310
311/* Maximum number of values that can be executed for one opcode */
312#define TYPE4_MAX_PAYLOAD 127
313
314#define PKT4(_reg, _cnt) \
315	(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
316	 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
317
318static inline void
319OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
320{
321	adreno_wait_ring(ring, cnt + 1);
322	OUT_RING(ring, PKT4(regindx, cnt));
323}
324
325static inline void
326OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
327{
328	adreno_wait_ring(ring, cnt + 1);
329	OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
330		((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
331}
332
333struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
334struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
335struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
336struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
337struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
338
339static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
340{
341	return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
342}
343
344/*
345 * Given a register and a count, return a value to program into
346 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
347 * registers starting at _reg.
348 *
349 * The register base needs to be a multiple of the length. If it is not, the
350 * hardware will quietly mask off the bits for you and shift the size. For
351 * example, if you intend the protection to start at 0x07 for a length of 4
352 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
353 * expose registers you intended to protect!
354 */
355#define ADRENO_PROTECT_RW(_reg, _len) \
356	((1 << 30) | (1 << 29) | \
357	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
358
359/*
360 * Same as above, but allow reads over the range. For areas of mixed use (such
361 * as performance counters) this allows us to protect a much larger range with a
362 * single register
363 */
364#define ADRENO_PROTECT_RDONLY(_reg, _len) \
365	((1 << 29) \
366	((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
367
368
369#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
370	readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
371		interval, timeout)
372
373#endif /* __ADRENO_GPU_H__ */
374