1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 * 6 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 7 */ 8 9#include <linux/ascii85.h> 10#include <linux/interconnect.h> 11#include <linux/qcom_scm.h> 12#include <linux/kernel.h> 13#include <linux/of_address.h> 14#include <linux/pm_opp.h> 15#include <linux/slab.h> 16#include <linux/soc/qcom/mdt_loader.h> 17#include <soc/qcom/ocmem.h> 18#include "adreno_gpu.h" 19#include "msm_gem.h" 20#include "msm_mmu.h" 21 22static bool zap_available = true; 23 24static int zap_shader_load_mdt(struct msm_gpu *gpu, const char *fwname, 25 u32 pasid) 26{ 27 struct device *dev = &gpu->pdev->dev; 28 const struct firmware *fw; 29 const char *signed_fwname = NULL; 30 struct device_node *np, *mem_np; 31 struct resource r; 32 phys_addr_t mem_phys; 33 ssize_t mem_size; 34 void *mem_region = NULL; 35 int ret; 36 37 if (!IS_ENABLED(CONFIG_ARCH_QCOM)) { 38 zap_available = false; 39 return -EINVAL; 40 } 41 42 np = of_get_child_by_name(dev->of_node, "zap-shader"); 43 if (!np) { 44 zap_available = false; 45 return -ENODEV; 46 } 47 48 mem_np = of_parse_phandle(np, "memory-region", 0); 49 of_node_put(np); 50 if (!mem_np) { 51 zap_available = false; 52 return -EINVAL; 53 } 54 55 ret = of_address_to_resource(mem_np, 0, &r); 56 of_node_put(mem_np); 57 if (ret) 58 return ret; 59 60 mem_phys = r.start; 61 62 /* 63 * Check for a firmware-name property. This is the new scheme 64 * to handle firmware that may be signed with device specific 65 * keys, allowing us to have a different zap fw path for different 66 * devices. 67 * 68 * If the firmware-name property is found, we bypass the 69 * adreno_request_fw() mechanism, because we don't need to handle 70 * the /lib/firmware/qcom/... vs /lib/firmware/... case. 71 * 72 * If the firmware-name property is not found, for backwards 73 * compatibility we fall back to the fwname from the gpulist 74 * table. 75 */ 76 of_property_read_string_index(np, "firmware-name", 0, &signed_fwname); 77 if (signed_fwname) { 78 fwname = signed_fwname; 79 ret = request_firmware_direct(&fw, fwname, gpu->dev->dev); 80 if (ret) 81 fw = ERR_PTR(ret); 82 } else if (fwname) { 83 /* Request the MDT file from the default location: */ 84 fw = adreno_request_fw(to_adreno_gpu(gpu), fwname); 85 } else { 86 /* 87 * For new targets, we require the firmware-name property, 88 * if a zap-shader is required, rather than falling back 89 * to a firmware name specified in gpulist. 90 * 91 * Because the firmware is signed with a (potentially) 92 * device specific key, having the name come from gpulist 93 * was a bad idea, and is only provided for backwards 94 * compatibility for older targets. 95 */ 96 return -ENODEV; 97 } 98 99 if (IS_ERR(fw)) { 100 DRM_DEV_ERROR(dev, "Unable to load %s\n", fwname); 101 return PTR_ERR(fw); 102 } 103 104 /* Figure out how much memory we need */ 105 mem_size = qcom_mdt_get_size(fw); 106 if (mem_size < 0) { 107 ret = mem_size; 108 goto out; 109 } 110 111 if (mem_size > resource_size(&r)) { 112 DRM_DEV_ERROR(dev, 113 "memory region is too small to load the MDT\n"); 114 ret = -E2BIG; 115 goto out; 116 } 117 118 /* Allocate memory for the firmware image */ 119 mem_region = memremap(mem_phys, mem_size, MEMREMAP_WC); 120 if (!mem_region) { 121 ret = -ENOMEM; 122 goto out; 123 } 124 125 /* 126 * Load the rest of the MDT 127 * 128 * Note that we could be dealing with two different paths, since 129 * with upstream linux-firmware it would be in a qcom/ subdir.. 130 * adreno_request_fw() handles this, but qcom_mdt_load() does 131 * not. But since we've already gotten through adreno_request_fw() 132 * we know which of the two cases it is: 133 */ 134 if (signed_fwname || (to_adreno_gpu(gpu)->fwloc == FW_LOCATION_LEGACY)) { 135 ret = qcom_mdt_load(dev, fw, fwname, pasid, 136 mem_region, mem_phys, mem_size, NULL); 137 } else { 138 char *newname; 139 140 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 141 142 ret = qcom_mdt_load(dev, fw, newname, pasid, 143 mem_region, mem_phys, mem_size, NULL); 144 kfree(newname); 145 } 146 if (ret) 147 goto out; 148 149 /* Send the image to the secure world */ 150 ret = qcom_scm_pas_auth_and_reset(pasid); 151 152 /* 153 * If the scm call returns -EOPNOTSUPP we assume that this target 154 * doesn't need/support the zap shader so quietly fail 155 */ 156 if (ret == -EOPNOTSUPP) 157 zap_available = false; 158 else if (ret) 159 DRM_DEV_ERROR(dev, "Unable to authorize the image\n"); 160 161out: 162 if (mem_region) 163 memunmap(mem_region); 164 165 release_firmware(fw); 166 167 return ret; 168} 169 170int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid) 171{ 172 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 173 struct platform_device *pdev = gpu->pdev; 174 175 /* Short cut if we determine the zap shader isn't available/needed */ 176 if (!zap_available) 177 return -ENODEV; 178 179 /* We need SCM to be able to load the firmware */ 180 if (!qcom_scm_is_available()) { 181 DRM_DEV_ERROR(&pdev->dev, "SCM is not available\n"); 182 return -EPROBE_DEFER; 183 } 184 185 return zap_shader_load_mdt(gpu, adreno_gpu->info->zapfw, pasid); 186} 187 188struct msm_gem_address_space * 189adreno_iommu_create_address_space(struct msm_gpu *gpu, 190 struct platform_device *pdev) 191{ 192 struct iommu_domain *iommu; 193 struct msm_mmu *mmu; 194 struct msm_gem_address_space *aspace; 195 u64 start, size; 196 197 iommu = iommu_domain_alloc(&platform_bus_type); 198 if (!iommu) 199 return NULL; 200 201 mmu = msm_iommu_new(&pdev->dev, iommu); 202 203 /* 204 * Use the aperture start or SZ_16M, whichever is greater. This will 205 * ensure that we align with the allocated pagetable range while still 206 * allowing room in the lower 32 bits for GMEM and whatnot 207 */ 208 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start); 209 size = iommu->geometry.aperture_end - start + 1; 210 211 aspace = msm_gem_address_space_create(mmu, "gpu", 212 start & GENMASK_ULL(48, 0), size); 213 214 if (IS_ERR(aspace) && !IS_ERR(mmu)) 215 mmu->funcs->destroy(mmu); 216 217 return aspace; 218} 219 220int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value) 221{ 222 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 223 224 switch (param) { 225 case MSM_PARAM_GPU_ID: 226 *value = adreno_gpu->info->revn; 227 return 0; 228 case MSM_PARAM_GMEM_SIZE: 229 *value = adreno_gpu->gmem; 230 return 0; 231 case MSM_PARAM_GMEM_BASE: 232 *value = !adreno_is_a650(adreno_gpu) ? 0x100000 : 0; 233 return 0; 234 case MSM_PARAM_CHIP_ID: 235 *value = adreno_gpu->rev.patchid | 236 (adreno_gpu->rev.minor << 8) | 237 (adreno_gpu->rev.major << 16) | 238 (adreno_gpu->rev.core << 24); 239 return 0; 240 case MSM_PARAM_MAX_FREQ: 241 *value = adreno_gpu->base.fast_rate; 242 return 0; 243 case MSM_PARAM_TIMESTAMP: 244 if (adreno_gpu->funcs->get_timestamp) { 245 int ret; 246 247 pm_runtime_get_sync(&gpu->pdev->dev); 248 ret = adreno_gpu->funcs->get_timestamp(gpu, value); 249 pm_runtime_put_autosuspend(&gpu->pdev->dev); 250 251 return ret; 252 } 253 return -EINVAL; 254 case MSM_PARAM_NR_RINGS: 255 *value = gpu->nr_rings; 256 return 0; 257 case MSM_PARAM_PP_PGTABLE: 258 *value = 0; 259 return 0; 260 case MSM_PARAM_FAULTS: 261 *value = gpu->global_faults; 262 return 0; 263 default: 264 DBG("%s: invalid param: %u", gpu->name, param); 265 return -EINVAL; 266 } 267} 268 269const struct firmware * 270adreno_request_fw(struct adreno_gpu *adreno_gpu, const char *fwname) 271{ 272 struct drm_device *drm = adreno_gpu->base.dev; 273 const struct firmware *fw = NULL; 274 char *newname; 275 int ret; 276 277 newname = kasprintf(GFP_KERNEL, "qcom/%s", fwname); 278 if (!newname) 279 return ERR_PTR(-ENOMEM); 280 281 /* 282 * Try first to load from qcom/$fwfile using a direct load (to avoid 283 * a potential timeout waiting for usermode helper) 284 */ 285 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 286 (adreno_gpu->fwloc == FW_LOCATION_NEW)) { 287 288 ret = request_firmware_direct(&fw, newname, drm->dev); 289 if (!ret) { 290 DRM_DEV_INFO(drm->dev, "loaded %s from new location\n", 291 newname); 292 adreno_gpu->fwloc = FW_LOCATION_NEW; 293 goto out; 294 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 295 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 296 newname, ret); 297 fw = ERR_PTR(ret); 298 goto out; 299 } 300 } 301 302 /* 303 * Then try the legacy location without qcom/ prefix 304 */ 305 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 306 (adreno_gpu->fwloc == FW_LOCATION_LEGACY)) { 307 308 ret = request_firmware_direct(&fw, fwname, drm->dev); 309 if (!ret) { 310 DRM_DEV_INFO(drm->dev, "loaded %s from legacy location\n", 311 newname); 312 adreno_gpu->fwloc = FW_LOCATION_LEGACY; 313 goto out; 314 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 315 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 316 fwname, ret); 317 fw = ERR_PTR(ret); 318 goto out; 319 } 320 } 321 322 /* 323 * Finally fall back to request_firmware() for cases where the 324 * usermode helper is needed (I think mainly android) 325 */ 326 if ((adreno_gpu->fwloc == FW_LOCATION_UNKNOWN) || 327 (adreno_gpu->fwloc == FW_LOCATION_HELPER)) { 328 329 ret = request_firmware(&fw, newname, drm->dev); 330 if (!ret) { 331 DRM_DEV_INFO(drm->dev, "loaded %s with helper\n", 332 newname); 333 adreno_gpu->fwloc = FW_LOCATION_HELPER; 334 goto out; 335 } else if (adreno_gpu->fwloc != FW_LOCATION_UNKNOWN) { 336 DRM_DEV_ERROR(drm->dev, "failed to load %s: %d\n", 337 newname, ret); 338 fw = ERR_PTR(ret); 339 goto out; 340 } 341 } 342 343 DRM_DEV_ERROR(drm->dev, "failed to load %s\n", fwname); 344 fw = ERR_PTR(-ENOENT); 345out: 346 kfree(newname); 347 return fw; 348} 349 350int adreno_load_fw(struct adreno_gpu *adreno_gpu) 351{ 352 int i; 353 354 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) { 355 const struct firmware *fw; 356 357 if (!adreno_gpu->info->fw[i]) 358 continue; 359 360 /* Skip if the firmware has already been loaded */ 361 if (adreno_gpu->fw[i]) 362 continue; 363 364 fw = adreno_request_fw(adreno_gpu, adreno_gpu->info->fw[i]); 365 if (IS_ERR(fw)) 366 return PTR_ERR(fw); 367 368 adreno_gpu->fw[i] = fw; 369 } 370 371 return 0; 372} 373 374struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu, 375 const struct firmware *fw, u64 *iova) 376{ 377 struct drm_gem_object *bo; 378 void *ptr; 379 380 ptr = msm_gem_kernel_new_locked(gpu->dev, fw->size - 4, 381 MSM_BO_UNCACHED | MSM_BO_GPU_READONLY, gpu->aspace, &bo, iova); 382 383 if (IS_ERR(ptr)) 384 return ERR_CAST(ptr); 385 386 memcpy(ptr, &fw->data[4], fw->size - 4); 387 388 msm_gem_put_vaddr(bo); 389 390 return bo; 391} 392 393int adreno_hw_init(struct msm_gpu *gpu) 394{ 395 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 396 int ret, i; 397 398 DBG("%s", gpu->name); 399 400 ret = adreno_load_fw(adreno_gpu); 401 if (ret) 402 return ret; 403 404 for (i = 0; i < gpu->nr_rings; i++) { 405 struct msm_ringbuffer *ring = gpu->rb[i]; 406 407 if (!ring) 408 continue; 409 410 ring->cur = ring->start; 411 ring->next = ring->start; 412 413 /* reset completed fence seqno: */ 414 ring->memptrs->fence = ring->fctx->completed_fence; 415 ring->memptrs->rptr = 0; 416 } 417 418 return 0; 419} 420 421/* Use this helper to read rptr, since a430 doesn't update rptr in memory */ 422static uint32_t get_rptr(struct adreno_gpu *adreno_gpu, 423 struct msm_ringbuffer *ring) 424{ 425 struct msm_gpu *gpu = &adreno_gpu->base; 426 427 return gpu->funcs->get_rptr(gpu, ring); 428} 429 430struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu) 431{ 432 return gpu->rb[0]; 433} 434 435void adreno_recover(struct msm_gpu *gpu) 436{ 437 struct drm_device *dev = gpu->dev; 438 int ret; 439 440 // XXX pm-runtime?? we *need* the device to be off after this 441 // so maybe continuing to call ->pm_suspend/resume() is better? 442 443 gpu->funcs->pm_suspend(gpu); 444 gpu->funcs->pm_resume(gpu); 445 446 ret = msm_gpu_hw_init(gpu); 447 if (ret) { 448 DRM_DEV_ERROR(dev->dev, "gpu hw init failed: %d\n", ret); 449 /* hmm, oh well? */ 450 } 451} 452 453void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg) 454{ 455 uint32_t wptr; 456 457 /* Copy the shadow to the actual register */ 458 ring->cur = ring->next; 459 460 /* 461 * Mask wptr value that we calculate to fit in the HW range. This is 462 * to account for the possibility that the last command fit exactly into 463 * the ringbuffer and rb->next hasn't wrapped to zero yet 464 */ 465 wptr = get_wptr(ring); 466 467 /* ensure writes to ringbuffer have hit system memory: */ 468 mb(); 469 470 gpu_write(gpu, reg, wptr); 471} 472 473bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring) 474{ 475 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 476 uint32_t wptr = get_wptr(ring); 477 478 /* wait for CP to drain ringbuffer: */ 479 if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) 480 return true; 481 482 /* TODO maybe we need to reset GPU here to recover from hang? */ 483 DRM_ERROR("%s: timeout waiting to drain ringbuffer %d rptr/wptr = %X/%X\n", 484 gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); 485 486 return false; 487} 488 489int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state) 490{ 491 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 492 int i, count = 0; 493 494 kref_init(&state->ref); 495 496 ktime_get_real_ts64(&state->time); 497 498 for (i = 0; i < gpu->nr_rings; i++) { 499 int size = 0, j; 500 501 state->ring[i].fence = gpu->rb[i]->memptrs->fence; 502 state->ring[i].iova = gpu->rb[i]->iova; 503 state->ring[i].seqno = gpu->rb[i]->seqno; 504 state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); 505 state->ring[i].wptr = get_wptr(gpu->rb[i]); 506 507 /* Copy at least 'wptr' dwords of the data */ 508 size = state->ring[i].wptr; 509 510 /* After wptr find the last non zero dword to save space */ 511 for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) 512 if (gpu->rb[i]->start[j]) 513 size = j + 1; 514 515 if (size) { 516 state->ring[i].data = kvmalloc(size << 2, GFP_KERNEL); 517 if (state->ring[i].data) { 518 memcpy(state->ring[i].data, gpu->rb[i]->start, size << 2); 519 state->ring[i].data_size = size << 2; 520 } 521 } 522 } 523 524 /* Some targets prefer to collect their own registers */ 525 if (!adreno_gpu->registers) 526 return 0; 527 528 /* Count the number of registers */ 529 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) 530 count += adreno_gpu->registers[i + 1] - 531 adreno_gpu->registers[i] + 1; 532 533 state->registers = kcalloc(count * 2, sizeof(u32), GFP_KERNEL); 534 if (state->registers) { 535 int pos = 0; 536 537 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 538 u32 start = adreno_gpu->registers[i]; 539 u32 end = adreno_gpu->registers[i + 1]; 540 u32 addr; 541 542 for (addr = start; addr <= end; addr++) { 543 state->registers[pos++] = addr; 544 state->registers[pos++] = gpu_read(gpu, addr); 545 } 546 } 547 548 state->nr_registers = count; 549 } 550 551 return 0; 552} 553 554void adreno_gpu_state_destroy(struct msm_gpu_state *state) 555{ 556 int i; 557 558 for (i = 0; i < ARRAY_SIZE(state->ring); i++) 559 kvfree(state->ring[i].data); 560 561 for (i = 0; state->bos && i < state->nr_bos; i++) 562 kvfree(state->bos[i].data); 563 564 kfree(state->bos); 565 kfree(state->comm); 566 kfree(state->cmd); 567 kfree(state->registers); 568} 569 570static void adreno_gpu_state_kref_destroy(struct kref *kref) 571{ 572 struct msm_gpu_state *state = container_of(kref, 573 struct msm_gpu_state, ref); 574 575 adreno_gpu_state_destroy(state); 576 kfree(state); 577} 578 579int adreno_gpu_state_put(struct msm_gpu_state *state) 580{ 581 if (IS_ERR_OR_NULL(state)) 582 return 1; 583 584 return kref_put(&state->ref, adreno_gpu_state_kref_destroy); 585} 586 587#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP) 588 589static char *adreno_gpu_ascii85_encode(u32 *src, size_t len) 590{ 591 void *buf; 592 size_t buf_itr = 0, buffer_size; 593 char out[ASCII85_BUFSZ]; 594 long l; 595 int i; 596 597 if (!src || !len) 598 return NULL; 599 600 l = ascii85_encode_len(len); 601 602 /* 603 * Ascii85 outputs either a 5 byte string or a 1 byte string. So we 604 * account for the worst case of 5 bytes per dword plus the 1 for '\0' 605 */ 606 buffer_size = (l * 5) + 1; 607 608 buf = kvmalloc(buffer_size, GFP_KERNEL); 609 if (!buf) 610 return NULL; 611 612 for (i = 0; i < l; i++) 613 buf_itr += scnprintf(buf + buf_itr, buffer_size - buf_itr, "%s", 614 ascii85_encode(src[i], out)); 615 616 return buf; 617} 618 619/* len is expected to be in bytes */ 620static void adreno_show_object(struct drm_printer *p, void **ptr, int len, 621 bool *encoded) 622{ 623 if (!*ptr || !len) 624 return; 625 626 if (!*encoded) { 627 long datalen, i; 628 u32 *buf = *ptr; 629 630 /* 631 * Only dump the non-zero part of the buffer - rarely will 632 * any data completely fill the entire allocated size of 633 * the buffer. 634 */ 635 for (datalen = 0, i = 0; i < len >> 2; i++) 636 if (buf[i]) 637 datalen = ((i + 1) << 2); 638 639 /* 640 * If we reach here, then the originally captured binary buffer 641 * will be replaced with the ascii85 encoded string 642 */ 643 *ptr = adreno_gpu_ascii85_encode(buf, datalen); 644 645 kvfree(buf); 646 647 *encoded = true; 648 } 649 650 if (!*ptr) 651 return; 652 653 drm_puts(p, " data: !!ascii85 |\n"); 654 drm_puts(p, " "); 655 656 drm_puts(p, *ptr); 657 658 drm_puts(p, "\n"); 659} 660 661void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, 662 struct drm_printer *p) 663{ 664 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 665 int i; 666 667 if (IS_ERR_OR_NULL(state)) 668 return; 669 670 drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", 671 adreno_gpu->info->revn, adreno_gpu->rev.core, 672 adreno_gpu->rev.major, adreno_gpu->rev.minor, 673 adreno_gpu->rev.patchid); 674 675 drm_printf(p, "rbbm-status: 0x%08x\n", state->rbbm_status); 676 677 drm_puts(p, "ringbuffer:\n"); 678 679 for (i = 0; i < gpu->nr_rings; i++) { 680 drm_printf(p, " - id: %d\n", i); 681 drm_printf(p, " iova: 0x%016llx\n", state->ring[i].iova); 682 drm_printf(p, " last-fence: %d\n", state->ring[i].seqno); 683 drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); 684 drm_printf(p, " rptr: %d\n", state->ring[i].rptr); 685 drm_printf(p, " wptr: %d\n", state->ring[i].wptr); 686 drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); 687 688 adreno_show_object(p, &state->ring[i].data, 689 state->ring[i].data_size, &state->ring[i].encoded); 690 } 691 692 if (state->bos) { 693 drm_puts(p, "bos:\n"); 694 695 for (i = 0; i < state->nr_bos; i++) { 696 drm_printf(p, " - iova: 0x%016llx\n", 697 state->bos[i].iova); 698 drm_printf(p, " size: %zd\n", state->bos[i].size); 699 700 adreno_show_object(p, &state->bos[i].data, 701 state->bos[i].size, &state->bos[i].encoded); 702 } 703 } 704 705 if (state->nr_registers) { 706 drm_puts(p, "registers:\n"); 707 708 for (i = 0; i < state->nr_registers; i++) { 709 drm_printf(p, " - { offset: 0x%04x, value: 0x%08x }\n", 710 state->registers[i * 2] << 2, 711 state->registers[(i * 2) + 1]); 712 } 713 } 714} 715#endif 716 717/* Dump common gpu status and scratch registers on any hang, to make 718 * the hangcheck logs more useful. The scratch registers seem always 719 * safe to read when GPU has hung (unlike some other regs, depending 720 * on how the GPU hung), and they are useful to match up to cmdstream 721 * dumps when debugging hangs: 722 */ 723void adreno_dump_info(struct msm_gpu *gpu) 724{ 725 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 726 int i; 727 728 printk("revision: %d (%d.%d.%d.%d)\n", 729 adreno_gpu->info->revn, adreno_gpu->rev.core, 730 adreno_gpu->rev.major, adreno_gpu->rev.minor, 731 adreno_gpu->rev.patchid); 732 733 for (i = 0; i < gpu->nr_rings; i++) { 734 struct msm_ringbuffer *ring = gpu->rb[i]; 735 736 printk("rb %d: fence: %d/%d\n", i, 737 ring->memptrs->fence, 738 ring->seqno); 739 740 printk("rptr: %d\n", get_rptr(adreno_gpu, ring)); 741 printk("rb wptr: %d\n", get_wptr(ring)); 742 } 743} 744 745/* would be nice to not have to duplicate the _show() stuff with printk(): */ 746void adreno_dump(struct msm_gpu *gpu) 747{ 748 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); 749 int i; 750 751 if (!adreno_gpu->registers) 752 return; 753 754 /* dump these out in a form that can be parsed by demsm: */ 755 printk("IO:region %s 00000000 00020000\n", gpu->name); 756 for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { 757 uint32_t start = adreno_gpu->registers[i]; 758 uint32_t end = adreno_gpu->registers[i+1]; 759 uint32_t addr; 760 761 for (addr = start; addr <= end; addr++) { 762 uint32_t val = gpu_read(gpu, addr); 763 printk("IO:R %08x %08x\n", addr<<2, val); 764 } 765 } 766} 767 768static uint32_t ring_freewords(struct msm_ringbuffer *ring) 769{ 770 struct adreno_gpu *adreno_gpu = to_adreno_gpu(ring->gpu); 771 uint32_t size = MSM_GPU_RINGBUFFER_SZ >> 2; 772 /* Use ring->next to calculate free size */ 773 uint32_t wptr = ring->next - ring->start; 774 uint32_t rptr = get_rptr(adreno_gpu, ring); 775 return (rptr + (size - 1) - wptr) % size; 776} 777 778void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords) 779{ 780 if (spin_until(ring_freewords(ring) >= ndwords)) 781 DRM_DEV_ERROR(ring->gpu->dev->dev, 782 "timeout waiting for space in ringbuffer %d\n", 783 ring->id); 784} 785 786/* Get legacy powerlevels from qcom,gpu-pwrlevels and populate the opp table */ 787static int adreno_get_legacy_pwrlevels(struct device *dev) 788{ 789 struct device_node *child, *node; 790 int ret; 791 792 node = of_get_compatible_child(dev->of_node, "qcom,gpu-pwrlevels"); 793 if (!node) { 794 DRM_DEV_DEBUG(dev, "Could not find the GPU powerlevels\n"); 795 return -ENXIO; 796 } 797 798 for_each_child_of_node(node, child) { 799 unsigned int val; 800 801 ret = of_property_read_u32(child, "qcom,gpu-freq", &val); 802 if (ret) 803 continue; 804 805 /* 806 * Skip the intentionally bogus clock value found at the bottom 807 * of most legacy frequency tables 808 */ 809 if (val != 27000000) 810 dev_pm_opp_add(dev, val, 0); 811 } 812 813 of_node_put(node); 814 815 return 0; 816} 817 818static void adreno_get_pwrlevels(struct device *dev, 819 struct msm_gpu *gpu) 820{ 821 unsigned long freq = ULONG_MAX; 822 struct dev_pm_opp *opp; 823 int ret; 824 825 gpu->fast_rate = 0; 826 827 /* You down with OPP? */ 828 if (!of_find_property(dev->of_node, "operating-points-v2", NULL)) 829 ret = adreno_get_legacy_pwrlevels(dev); 830 else { 831 ret = dev_pm_opp_of_add_table(dev); 832 if (ret) 833 DRM_DEV_ERROR(dev, "Unable to set the OPP table\n"); 834 } 835 836 if (!ret) { 837 /* Find the fastest defined rate */ 838 opp = dev_pm_opp_find_freq_floor(dev, &freq); 839 if (!IS_ERR(opp)) { 840 gpu->fast_rate = freq; 841 dev_pm_opp_put(opp); 842 } 843 } 844 845 if (!gpu->fast_rate) { 846 dev_warn(dev, 847 "Could not find a clock rate. Using a reasonable default\n"); 848 /* Pick a suitably safe clock speed for any target */ 849 gpu->fast_rate = 200000000; 850 } 851 852 DBG("fast_rate=%u, slow_rate=27000000", gpu->fast_rate); 853} 854 855int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, 856 struct adreno_ocmem *adreno_ocmem) 857{ 858 struct ocmem_buf *ocmem_hdl; 859 struct ocmem *ocmem; 860 861 ocmem = of_get_ocmem(dev); 862 if (IS_ERR(ocmem)) { 863 if (PTR_ERR(ocmem) == -ENODEV) { 864 /* 865 * Return success since either the ocmem property was 866 * not specified in device tree, or ocmem support is 867 * not compiled into the kernel. 868 */ 869 return 0; 870 } 871 872 return PTR_ERR(ocmem); 873 } 874 875 ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem); 876 if (IS_ERR(ocmem_hdl)) 877 return PTR_ERR(ocmem_hdl); 878 879 adreno_ocmem->ocmem = ocmem; 880 adreno_ocmem->base = ocmem_hdl->addr; 881 adreno_ocmem->hdl = ocmem_hdl; 882 adreno_gpu->gmem = ocmem_hdl->len; 883 884 return 0; 885} 886 887void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *adreno_ocmem) 888{ 889 if (adreno_ocmem && adreno_ocmem->base) 890 ocmem_free(adreno_ocmem->ocmem, OCMEM_GRAPHICS, 891 adreno_ocmem->hdl); 892} 893 894int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, 895 struct adreno_gpu *adreno_gpu, 896 const struct adreno_gpu_funcs *funcs, int nr_rings) 897{ 898 struct device *dev = &pdev->dev; 899 struct adreno_platform_config *config = dev->platform_data; 900 struct msm_gpu_config adreno_gpu_config = { 0 }; 901 struct msm_gpu *gpu = &adreno_gpu->base; 902 int ret; 903 904 adreno_gpu->funcs = funcs; 905 adreno_gpu->info = adreno_info(config->rev); 906 adreno_gpu->gmem = adreno_gpu->info->gmem; 907 adreno_gpu->revn = adreno_gpu->info->revn; 908 adreno_gpu->rev = config->rev; 909 910 adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; 911 912 adreno_gpu_config.nr_rings = nr_rings; 913 914 adreno_get_pwrlevels(dev, gpu); 915 916 pm_runtime_set_autosuspend_delay(dev, 917 adreno_gpu->info->inactive_period); 918 pm_runtime_use_autosuspend(dev); 919 920 ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base, 921 adreno_gpu->info->name, &adreno_gpu_config); 922 if (ret) 923 return ret; 924 925 /* 926 * The legacy case, before "interconnect-names", only has a 927 * single interconnect path which is equivalent to "gfx-mem" 928 */ 929 if (!of_find_property(dev->of_node, "interconnect-names", NULL)) { 930 gpu->icc_path = of_icc_get(dev, NULL); 931 } else { 932 gpu->icc_path = of_icc_get(dev, "gfx-mem"); 933 gpu->ocmem_icc_path = of_icc_get(dev, "ocmem"); 934 } 935 936 if (IS_ERR(gpu->icc_path)) { 937 ret = PTR_ERR(gpu->icc_path); 938 gpu->icc_path = NULL; 939 return ret; 940 } 941 942 if (IS_ERR(gpu->ocmem_icc_path)) { 943 ret = PTR_ERR(gpu->ocmem_icc_path); 944 gpu->ocmem_icc_path = NULL; 945 /* allow -ENODATA, ocmem icc is optional */ 946 if (ret != -ENODATA) 947 return ret; 948 } 949 950 return 0; 951} 952 953void adreno_gpu_cleanup(struct adreno_gpu *adreno_gpu) 954{ 955 struct msm_gpu *gpu = &adreno_gpu->base; 956 struct msm_drm_private *priv = gpu->dev ? gpu->dev->dev_private : NULL; 957 unsigned int i; 958 959 for (i = 0; i < ARRAY_SIZE(adreno_gpu->info->fw); i++) 960 release_firmware(adreno_gpu->fw[i]); 961 962 if (priv && pm_runtime_enabled(&priv->gpu_pdev->dev)) 963 pm_runtime_disable(&priv->gpu_pdev->dev); 964 965 msm_gpu_cleanup(&adreno_gpu->base); 966 967 icc_put(gpu->icc_path); 968 icc_put(gpu->ocmem_icc_path); 969} 970