1#ifndef ADRENO_COMMON_XML 2#define ADRENO_COMMON_XML 3 4/* Autogenerated file, DO NOT EDIT manually! 5 6This file was generated by the rules-ng-ng headergen tool in this git repository: 7http://github.com/freedreno/envytools/ 8git clone https://github.com/freedreno/envytools.git 9 10The rules-ng-ng source files this header was generated from are: 11- /home/robclark/src/envytools/rnndb/adreno.xml ( 594 bytes, from 2020-07-23 21:58:14) 12- /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2020-07-23 21:58:14) 13- /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 90159 bytes, from 2020-07-23 21:58:14) 14- /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14386 bytes, from 2020-07-23 21:58:14) 15- /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 65048 bytes, from 2020-07-23 21:58:14) 16- /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84226 bytes, from 2020-07-23 21:58:14) 17- /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112556 bytes, from 2020-07-23 21:58:14) 18- /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 149461 bytes, from 2020-07-23 21:58:14) 19- /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 184695 bytes, from 2020-07-23 21:58:14) 20- /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 11218 bytes, from 2020-07-23 21:58:14) 21- /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2020-07-23 21:58:14) 22- /home/robclark/src/envytools/rnndb/adreno/adreno_control_regs.xml ( 4559 bytes, from 2020-07-23 21:58:14) 23- /home/robclark/src/envytools/rnndb/adreno/adreno_pipe_regs.xml ( 2872 bytes, from 2020-07-23 21:58:14) 24 25Copyright (C) 2013-2020 by the following authors: 26- Rob Clark <robdclark@gmail.com> (robclark) 27- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) 28 29Permission is hereby granted, free of charge, to any person obtaining 30a copy of this software and associated documentation files (the 31"Software"), to deal in the Software without restriction, including 32without limitation the rights to use, copy, modify, merge, publish, 33distribute, sublicense, and/or sell copies of the Software, and to 34permit persons to whom the Software is furnished to do so, subject to 35the following conditions: 36 37The above copyright notice and this permission notice (including the 38next paragraph) shall be included in all copies or substantial 39portions of the Software. 40 41THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 42EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 43MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 44IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 45LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 46OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 47WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 48*/ 49 50 51enum chip { 52 A2XX = 0, 53 A3XX = 0, 54 A4XX = 0, 55 A5XX = 0, 56 A6XX = 0, 57}; 58 59enum adreno_pa_su_sc_draw { 60 PC_DRAW_POINTS = 0, 61 PC_DRAW_LINES = 1, 62 PC_DRAW_TRIANGLES = 2, 63}; 64 65enum adreno_compare_func { 66 FUNC_NEVER = 0, 67 FUNC_LESS = 1, 68 FUNC_EQUAL = 2, 69 FUNC_LEQUAL = 3, 70 FUNC_GREATER = 4, 71 FUNC_NOTEQUAL = 5, 72 FUNC_GEQUAL = 6, 73 FUNC_ALWAYS = 7, 74}; 75 76enum adreno_stencil_op { 77 STENCIL_KEEP = 0, 78 STENCIL_ZERO = 1, 79 STENCIL_REPLACE = 2, 80 STENCIL_INCR_CLAMP = 3, 81 STENCIL_DECR_CLAMP = 4, 82 STENCIL_INVERT = 5, 83 STENCIL_INCR_WRAP = 6, 84 STENCIL_DECR_WRAP = 7, 85}; 86 87enum adreno_rb_blend_factor { 88 FACTOR_ZERO = 0, 89 FACTOR_ONE = 1, 90 FACTOR_SRC_COLOR = 4, 91 FACTOR_ONE_MINUS_SRC_COLOR = 5, 92 FACTOR_SRC_ALPHA = 6, 93 FACTOR_ONE_MINUS_SRC_ALPHA = 7, 94 FACTOR_DST_COLOR = 8, 95 FACTOR_ONE_MINUS_DST_COLOR = 9, 96 FACTOR_DST_ALPHA = 10, 97 FACTOR_ONE_MINUS_DST_ALPHA = 11, 98 FACTOR_CONSTANT_COLOR = 12, 99 FACTOR_ONE_MINUS_CONSTANT_COLOR = 13, 100 FACTOR_CONSTANT_ALPHA = 14, 101 FACTOR_ONE_MINUS_CONSTANT_ALPHA = 15, 102 FACTOR_SRC_ALPHA_SATURATE = 16, 103 FACTOR_SRC1_COLOR = 20, 104 FACTOR_ONE_MINUS_SRC1_COLOR = 21, 105 FACTOR_SRC1_ALPHA = 22, 106 FACTOR_ONE_MINUS_SRC1_ALPHA = 23, 107}; 108 109enum adreno_rb_surface_endian { 110 ENDIAN_NONE = 0, 111 ENDIAN_8IN16 = 1, 112 ENDIAN_8IN32 = 2, 113 ENDIAN_16IN32 = 3, 114 ENDIAN_8IN64 = 4, 115 ENDIAN_8IN128 = 5, 116}; 117 118enum adreno_rb_dither_mode { 119 DITHER_DISABLE = 0, 120 DITHER_ALWAYS = 1, 121 DITHER_IF_ALPHA_OFF = 2, 122}; 123 124enum adreno_rb_depth_format { 125 DEPTHX_16 = 0, 126 DEPTHX_24_8 = 1, 127 DEPTHX_32 = 2, 128}; 129 130enum adreno_rb_copy_control_mode { 131 RB_COPY_RESOLVE = 1, 132 RB_COPY_CLEAR = 2, 133 RB_COPY_DEPTH_STENCIL = 5, 134}; 135 136enum a3xx_rop_code { 137 ROP_CLEAR = 0, 138 ROP_NOR = 1, 139 ROP_AND_INVERTED = 2, 140 ROP_COPY_INVERTED = 3, 141 ROP_AND_REVERSE = 4, 142 ROP_INVERT = 5, 143 ROP_NAND = 7, 144 ROP_AND = 8, 145 ROP_EQUIV = 9, 146 ROP_NOOP = 10, 147 ROP_OR_INVERTED = 11, 148 ROP_OR_REVERSE = 13, 149 ROP_OR = 14, 150 ROP_SET = 15, 151}; 152 153enum a3xx_render_mode { 154 RB_RENDERING_PASS = 0, 155 RB_TILING_PASS = 1, 156 RB_RESOLVE_PASS = 2, 157 RB_COMPUTE_PASS = 3, 158}; 159 160enum a3xx_msaa_samples { 161 MSAA_ONE = 0, 162 MSAA_TWO = 1, 163 MSAA_FOUR = 2, 164 MSAA_EIGHT = 3, 165}; 166 167enum a3xx_threadmode { 168 MULTI = 0, 169 SINGLE = 1, 170}; 171 172enum a3xx_instrbuffermode { 173 CACHE = 0, 174 BUFFER = 1, 175}; 176 177enum a3xx_threadsize { 178 TWO_QUADS = 0, 179 FOUR_QUADS = 1, 180}; 181 182enum a3xx_color_swap { 183 WZYX = 0, 184 WXYZ = 1, 185 ZYXW = 2, 186 XYZW = 3, 187}; 188 189enum a3xx_rb_blend_opcode { 190 BLEND_DST_PLUS_SRC = 0, 191 BLEND_SRC_MINUS_DST = 1, 192 BLEND_DST_MINUS_SRC = 2, 193 BLEND_MIN_DST_SRC = 3, 194 BLEND_MAX_DST_SRC = 4, 195}; 196 197enum a4xx_tess_spacing { 198 EQUAL_SPACING = 0, 199 ODD_SPACING = 2, 200 EVEN_SPACING = 3, 201}; 202 203enum a5xx_address_mode { 204 ADDR_32B = 0, 205 ADDR_64B = 1, 206}; 207 208#define REG_AXXX_CP_RB_BASE 0x000001c0 209 210#define REG_AXXX_CP_RB_CNTL 0x000001c1 211#define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f 212#define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0 213static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val) 214{ 215 return ((val) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT) & AXXX_CP_RB_CNTL_BUFSZ__MASK; 216} 217#define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00 218#define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8 219static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val) 220{ 221 return ((val) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT) & AXXX_CP_RB_CNTL_BLKSZ__MASK; 222} 223#define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000 224#define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16 225static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val) 226{ 227 return ((val) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK; 228} 229#define AXXX_CP_RB_CNTL_POLL_EN 0x00100000 230#define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000 231#define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000 232 233#define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3 234#define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003 235#define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0 236static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) 237{ 238 return ((val) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK; 239} 240#define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc 241#define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 242static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) 243{ 244 return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; 245} 246 247#define REG_AXXX_CP_RB_RPTR 0x000001c4 248 249#define REG_AXXX_CP_RB_WPTR 0x000001c5 250 251#define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6 252 253#define REG_AXXX_CP_RB_RPTR_WR 0x000001c7 254 255#define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8 256 257#define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5 258#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f 259#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0 260static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val) 261{ 262 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK; 263} 264#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00 265#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8 266static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val) 267{ 268 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK; 269} 270#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000 271#define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16 272static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val) 273{ 274 return ((val) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK; 275} 276 277#define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6 278#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000 279#define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16 280static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val) 281{ 282 return ((val) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK; 283} 284#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000 285#define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24 286static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val) 287{ 288 return ((val) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK; 289} 290 291#define REG_AXXX_CP_CSQ_AVAIL 0x000001d7 292#define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f 293#define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0 294static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val) 295{ 296 return ((val) << AXXX_CP_CSQ_AVAIL_RING__SHIFT) & AXXX_CP_CSQ_AVAIL_RING__MASK; 297} 298#define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00 299#define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8 300static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val) 301{ 302 return ((val) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT) & AXXX_CP_CSQ_AVAIL_IB1__MASK; 303} 304#define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000 305#define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16 306static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val) 307{ 308 return ((val) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT) & AXXX_CP_CSQ_AVAIL_IB2__MASK; 309} 310 311#define REG_AXXX_CP_STQ_AVAIL 0x000001d8 312#define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f 313#define AXXX_CP_STQ_AVAIL_ST__SHIFT 0 314static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val) 315{ 316 return ((val) << AXXX_CP_STQ_AVAIL_ST__SHIFT) & AXXX_CP_STQ_AVAIL_ST__MASK; 317} 318 319#define REG_AXXX_CP_MEQ_AVAIL 0x000001d9 320#define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f 321#define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0 322static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val) 323{ 324 return ((val) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT) & AXXX_CP_MEQ_AVAIL_MEQ__MASK; 325} 326 327#define REG_AXXX_SCRATCH_UMSK 0x000001dc 328#define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff 329#define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0 330static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val) 331{ 332 return ((val) << AXXX_SCRATCH_UMSK_UMSK__SHIFT) & AXXX_SCRATCH_UMSK_UMSK__MASK; 333} 334#define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000 335#define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16 336static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val) 337{ 338 return ((val) << AXXX_SCRATCH_UMSK_SWAP__SHIFT) & AXXX_SCRATCH_UMSK_SWAP__MASK; 339} 340 341#define REG_AXXX_SCRATCH_ADDR 0x000001dd 342 343#define REG_AXXX_CP_ME_RDADDR 0x000001ea 344 345#define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec 346 347#define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed 348 349#define REG_AXXX_CP_INT_CNTL 0x000001f2 350#define AXXX_CP_INT_CNTL_SW_INT_MASK 0x00080000 351#define AXXX_CP_INT_CNTL_T0_PACKET_IN_IB_MASK 0x00800000 352#define AXXX_CP_INT_CNTL_OPCODE_ERROR_MASK 0x01000000 353#define AXXX_CP_INT_CNTL_PROTECTED_MODE_ERROR_MASK 0x02000000 354#define AXXX_CP_INT_CNTL_RESERVED_BIT_ERROR_MASK 0x04000000 355#define AXXX_CP_INT_CNTL_IB_ERROR_MASK 0x08000000 356#define AXXX_CP_INT_CNTL_IB2_INT_MASK 0x20000000 357#define AXXX_CP_INT_CNTL_IB1_INT_MASK 0x40000000 358#define AXXX_CP_INT_CNTL_RB_INT_MASK 0x80000000 359 360#define REG_AXXX_CP_INT_STATUS 0x000001f3 361 362#define REG_AXXX_CP_INT_ACK 0x000001f4 363 364#define REG_AXXX_CP_ME_CNTL 0x000001f6 365#define AXXX_CP_ME_CNTL_BUSY 0x20000000 366#define AXXX_CP_ME_CNTL_HALT 0x10000000 367 368#define REG_AXXX_CP_ME_STATUS 0x000001f7 369 370#define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8 371 372#define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9 373 374#define REG_AXXX_CP_ME_RAM_DATA 0x000001fa 375 376#define REG_AXXX_CP_DEBUG 0x000001fc 377#define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000 378#define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000 379#define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000 380#define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000 381#define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000 382#define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000 383#define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000 384#define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000 385 386#define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd 387#define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f 388#define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0 389static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val) 390{ 391 return ((val) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK; 392} 393#define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000 394#define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16 395static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val) 396{ 397 return ((val) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK; 398} 399 400#define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe 401#define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f 402#define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0 403static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val) 404{ 405 return ((val) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK; 406} 407#define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000 408#define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16 409static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val) 410{ 411 return ((val) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK; 412} 413 414#define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff 415#define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f 416#define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0 417static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val) 418{ 419 return ((val) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK; 420} 421#define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000 422#define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16 423static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) 424{ 425 return ((val) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK; 426} 427 428#define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440 429 430#define REG_AXXX_CP_STQ_ST_STAT 0x00000443 431 432#define REG_AXXX_CP_ST_BASE 0x0000044d 433 434#define REG_AXXX_CP_ST_BUFSZ 0x0000044e 435 436#define REG_AXXX_CP_MEQ_STAT 0x0000044f 437 438#define REG_AXXX_CP_MIU_TAG_STAT 0x00000452 439 440#define REG_AXXX_CP_BIN_MASK_LO 0x00000454 441 442#define REG_AXXX_CP_BIN_MASK_HI 0x00000455 443 444#define REG_AXXX_CP_BIN_SELECT_LO 0x00000456 445 446#define REG_AXXX_CP_BIN_SELECT_HI 0x00000457 447 448#define REG_AXXX_CP_IB1_BASE 0x00000458 449 450#define REG_AXXX_CP_IB1_BUFSZ 0x00000459 451 452#define REG_AXXX_CP_IB2_BASE 0x0000045a 453 454#define REG_AXXX_CP_IB2_BUFSZ 0x0000045b 455 456#define REG_AXXX_CP_STAT 0x0000047f 457#define AXXX_CP_STAT_CP_BUSY__MASK 0x80000000 458#define AXXX_CP_STAT_CP_BUSY__SHIFT 31 459static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val) 460{ 461 return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK; 462} 463#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK 0x40000000 464#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT 30 465static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val) 466{ 467 return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK; 468} 469#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK 0x20000000 470#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT 29 471static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val) 472{ 473 return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK; 474} 475#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK 0x10000000 476#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT 28 477static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val) 478{ 479 return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK; 480} 481#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK 0x08000000 482#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT 27 483static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val) 484{ 485 return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK; 486} 487#define AXXX_CP_STAT_ME_BUSY__MASK 0x04000000 488#define AXXX_CP_STAT_ME_BUSY__SHIFT 26 489static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val) 490{ 491 return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK; 492} 493#define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK 0x02000000 494#define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT 25 495static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val) 496{ 497 return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK; 498} 499#define AXXX_CP_STAT_CP_3D_BUSY__MASK 0x00800000 500#define AXXX_CP_STAT_CP_3D_BUSY__SHIFT 23 501static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val) 502{ 503 return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK; 504} 505#define AXXX_CP_STAT_CP_NRT_BUSY__MASK 0x00400000 506#define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT 22 507static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val) 508{ 509 return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK; 510} 511#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK 0x00200000 512#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT 21 513static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val) 514{ 515 return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK; 516} 517#define AXXX_CP_STAT_RCIU_ME_BUSY__MASK 0x00100000 518#define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT 20 519static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val) 520{ 521 return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK; 522} 523#define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK 0x00080000 524#define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT 19 525static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val) 526{ 527 return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK; 528} 529#define AXXX_CP_STAT_MEQ_RING_BUSY__MASK 0x00040000 530#define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT 18 531static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val) 532{ 533 return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK; 534} 535#define AXXX_CP_STAT_PFP_BUSY__MASK 0x00020000 536#define AXXX_CP_STAT_PFP_BUSY__SHIFT 17 537static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val) 538{ 539 return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK; 540} 541#define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK 0x00010000 542#define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT 16 543static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val) 544{ 545 return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK; 546} 547#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK 0x00002000 548#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT 13 549static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val) 550{ 551 return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK; 552} 553#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK 0x00001000 554#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT 12 555static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val) 556{ 557 return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK; 558} 559#define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK 0x00000800 560#define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT 11 561static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val) 562{ 563 return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK; 564} 565#define AXXX_CP_STAT_CSF_BUSY__MASK 0x00000400 566#define AXXX_CP_STAT_CSF_BUSY__SHIFT 10 567static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val) 568{ 569 return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK; 570} 571#define AXXX_CP_STAT_CSF_ST_BUSY__MASK 0x00000200 572#define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT 9 573static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val) 574{ 575 return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK; 576} 577#define AXXX_CP_STAT_EVENT_BUSY__MASK 0x00000100 578#define AXXX_CP_STAT_EVENT_BUSY__SHIFT 8 579static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val) 580{ 581 return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK; 582} 583#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK 0x00000080 584#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT 7 585static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val) 586{ 587 return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK; 588} 589#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK 0x00000040 590#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT 6 591static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val) 592{ 593 return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK; 594} 595#define AXXX_CP_STAT_CSF_RING_BUSY__MASK 0x00000020 596#define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT 5 597static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val) 598{ 599 return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK; 600} 601#define AXXX_CP_STAT_RCIU_BUSY__MASK 0x00000010 602#define AXXX_CP_STAT_RCIU_BUSY__SHIFT 4 603static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val) 604{ 605 return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK; 606} 607#define AXXX_CP_STAT_RBIU_BUSY__MASK 0x00000008 608#define AXXX_CP_STAT_RBIU_BUSY__SHIFT 3 609static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val) 610{ 611 return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK; 612} 613#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK 0x00000004 614#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT 2 615static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val) 616{ 617 return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK; 618} 619#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK 0x00000002 620#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT 1 621static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val) 622{ 623 return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK; 624} 625#define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 626 627#define REG_AXXX_CP_SCRATCH_REG0 0x00000578 628 629#define REG_AXXX_CP_SCRATCH_REG1 0x00000579 630 631#define REG_AXXX_CP_SCRATCH_REG2 0x0000057a 632 633#define REG_AXXX_CP_SCRATCH_REG3 0x0000057b 634 635#define REG_AXXX_CP_SCRATCH_REG4 0x0000057c 636 637#define REG_AXXX_CP_SCRATCH_REG5 0x0000057d 638 639#define REG_AXXX_CP_SCRATCH_REG6 0x0000057e 640 641#define REG_AXXX_CP_SCRATCH_REG7 0x0000057f 642 643#define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600 644 645#define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601 646 647#define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602 648 649#define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603 650 651#define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604 652 653#define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605 654 655#define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606 656 657#define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607 658 659#define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608 660 661#define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609 662 663#define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a 664 665#define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b 666 667#define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c 668 669#define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d 670 671#define REG_AXXX_CP_ME_NRT_DATA 0x0000060e 672 673#define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612 674 675#define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613 676 677#define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 678 679 680#endif /* ADRENO_COMMON_XML */ 681